TCXO device board-level wiring structure, wiring method and circuit board

Abstract

The invention provides a TCXO device board-level wiring structure, a TCXO device board-level wiring method and a circuit board. The wiring structure comprises a PCB substrate, a TCXO and an external chip. The TCXO is arranged on any outermost copper sheet layer of the PCB substrate; the outermost copper sheet layer where the TCXO is located comprises a bonding pad area and a grounding copper sheet area; a heat insulation gap is formed between the two areas; a pin of the TCXO is connected with a bonding pad, the bonding pad is connected with an external chip through a connecting line, and a grounding pin of the external chip is connected with the grounding copper sheet area; the length of a wire in the connecting circuit is greater than the minimum linear distance between the bonding pad area and the external chip; in at least two copper sheet layers which are arranged in sequence with the outermost copper sheet layer where the TCXO is located, a region which is located in a range jointly covered by projection regions of the heat insulation gap and the bonding pad region is not provided with a grounding copper sheet; the projection area of the heat insulation gap and the bonding pad area is the area formed by projection of the heat insulation gap and the bonding pad area in the thickness direction of the PCB substrate.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit design and manufacturing, and in particular to a board-level wiring structure, wiring method and circuit board for a TCXO device. Background Technology

[0002] In fields such as communication equipment, navigation systems, and precision instruments where clock frequency accuracy is critical, TCXOs (Temperature Compensated Crystal Oscillators) are core electronic clock devices and key components ensuring the timing stability of equipment. By incorporating temperature sensing and compensation circuits into a standard crystal oscillator, TCXOs form a closed-loop control system, providing a stable frequency output with a frequency stability of ±0.5ppm to ±2.5ppm over a wide temperature range of -40℃ to 105℃. This effectively counteracts frequency drift caused by temperature changes in the quartz crystal, ensuring normal equipment operation.

[0003] The frequency stability of a TCXO depends on its compensation accuracy, which is itself constrained by multiple internal and external factors. Internally, the temperature lag caused by the thermistor layout in the temperature sensing circuit, and the nonlinearity of the temperature compensation circuit itself, directly affect the frequency regulation accuracy of the TCXO. Externally, thermal shocks caused by sudden changes in ambient temperature can compromise the effectiveness of the preset compensation model in the temperature compensation circuit.

[0004] In board-level applications, it is necessary to minimize the impact of ambient temperature changes on the TCXO compensation accuracy. When the ambient temperature changes slowly, the temperature drift of the TCXO is within the required range; however, when the ambient temperature changes drastically, the instantaneous temperature difference between the temperature sensing circuit and the crystal can disrupt the synchronization of compensation, causing the temperature drift to exceed the required range, resulting in excessive frequency deviation, which seriously affects the stable operation of related equipment. Summary of the Invention

[0005] Based on the above situation, the main objective of this invention is to provide a TCXO device board-level wiring structure, wiring method, and circuit board, so that when the ambient temperature changes drastically, the internal closed-loop compensation system of the TCXO can promptly offset the frequency drift of the crystal oscillator caused by temperature changes, thereby improving the stability of the related equipment.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: This invention provides a board-level wiring structure for a TCXO device, which includes a PCB substrate and a TCXO device and an external chip disposed on the PCB substrate. The PCB substrate includes a copper layer and a dielectric layer, which are arranged alternately along the thickness direction of the PCB substrate; the TCXO device has a temperature sensing circuit and a temperature compensation circuit inside; the external chip generates heat at a rate greater than the TCXO device ... The TCXO device is disposed on any outermost copper layer of the PCB substrate, and the outermost copper layer is either the top copper layer or the bottom copper layer of the PCB substrate; the outermost copper layer where the TCXO device is located includes a pad area and a ground copper area of ​​the PCB substrate; a heat insulation gap is formed between the pad area and the ground copper area; a device pad is disposed in the pad area. The pins of the TCXO device are connected to the device pads, and the device pads are connected to the external chip via connection lines. The ground pin of the external chip is connected to the ground copper area. The length of the conductor in the connection line is greater than the minimum straight-line distance between the pad area and the external chip. In at least two copper layers arranged sequentially with the outermost copper layer containing the TCXO device, the area within the range jointly covered by the projection area of ​​the thermal insulation gap and the projection area of ​​the pad area is not provided with a grounding copper layer; wherein, the projection area of ​​the thermal insulation gap is the area formed by the thermal insulation gap projected along the thickness direction of the PCB substrate, and the projection area of ​​the pad area is the area formed by the pad area projected along the thickness direction of the PCB substrate.

[0007] Preferably, the minimum distance between the outer boundary of one side of the TCXO device and the grounding copper area on the same side is greater than or equal to three times the wire width in the connection line.

[0008] Preferably, when the PCB substrate includes two or more copper layers and their corresponding dielectric layers, and some of the conductors in the connection lines are located in different copper layers, the conductors with the same function located in different copper layers in the connection lines are connected through vias.

[0009] Preferably, the connection line includes a ground wire and a clock wire. One end of the ground wire is connected to the ground pin of the TCXO device, and the other end is connected to the ground pin of the external chip. One end of the clock wire is connected to the clock output pin of the TCXO device, and the other end is connected to the clock input pin of the external chip. The length of the grounding conductor is greater than the straight-line distance between the device pad connected to the ground pin of the TCXO device and the ground pin of the external chip; the length of the clock conductor is greater than the straight-line distance between the device pad connected to the clock output pin of the TCXO device and the clock input pin of the external chip.

[0010] Preferably, both the grounding wire and the clock wire extend along a first direction and are arranged with multiple back-and-forth bends; the first direction is from the pad area to the external chip.

[0011] Preferably, the grounding conductor includes multiple grounding extension sections and grounding bend transition sections. The grounding extension sections extend along a second direction and are parallel to each other. Adjacent grounding extension sections are connected by the grounding bend transition sections. The second direction is perpendicular to the first direction.

[0012] Preferably, the clock conductor includes multiple clock extension segments and clock bend transition segments, the clock extension segments extend along a second direction and are parallel to each other, and adjacent clock extension segments are connected by the clock bend transition segments.

[0013] Preferably, the ground extension segment is parallel to the clock extension segment, each segment of the ground bending transition segment is parallel to the corresponding segment of the clock bending transition segment, and the distance between the ground extension segment and the clock extension segment is equal to the distance between the ground bending transition segment and the clock bending transition segment.

[0014] Preferably, the line width of the grounding conductor is equal to the line width of the clock conductor, and the ratio of the spacing between adjacent grounding extensions and clock extensions to the line width of the grounding conductor in the same round trip is 1 to 2.

[0015] Preferably, an insulating gap is formed between the grounding conductor and the grounding copper area on the side away from the clock conductor, and between the clock conductor and the grounding copper area on the side away from the grounding conductor, wherein the ratio of the width of the insulating gap along the second direction to the linewidth of the grounding conductor is greater than or equal to 2.

[0016] Preferably, the power supply pin of the TCXO device is connected to an external power supply via a power supply wire, and the ratio of the line width of the power supply wire to the line width of the ground wire is 1.5 to 3.

[0017] Preferably, the PCB substrate further includes a solder resist layer, and the solder resist layer is provided on the side of the ground copper area away from the dielectric layer and the pad area; wherein the solder resist layer in the pad area is disposed around the device pad.

[0018] This invention also provides a board-level routing method for TCXO devices, which includes the following steps: A pad area and a ground copper area are set on the outermost copper layer of the TCXO device on the PCB substrate, and a heat insulation gap is formed between the pad area and the ground copper area. Set up device pads within the pad area, connect the pins of the TCXO device to the device pads, connect the device pads to the external chip via connection lines, and connect the ground pins of the external chip to the ground copper area; wherein, the length of the conductor in the connection line is greater than the minimum straight-line distance between the pad area and the external chip; For at least two copper layers arranged sequentially with the outermost copper layer where the TCXO device is located, the ground copper layer within the area covered by the projection area of ​​the thermal insulation gap and the projection area of ​​the pad area is removed; wherein, the projection area of ​​the thermal insulation gap is the area formed by the thermal insulation gap projected along the thickness direction of the PCB substrate, and the projection area of ​​the pad area is the area formed by the pad area projected along the thickness direction of the PCB substrate.

[0019] The present invention also provides a circuit board comprising the TCXO device board-level wiring structure described in any of the preceding claims, or the TCXO device disposed on the PCB substrate is wired using the TCXO device board-level wiring method described in any of the preceding claims.

[0020] This invention directly cuts off the surface lateral heat conduction path between the ground copper and the TCXO device pads by forming a thermal insulation gap between the pad area and the ground copper area. Furthermore, by removing the ground copper within the area covered by the projection areas of the thermal insulation gap and the pad area in at least two copper layers arranged sequentially with the outermost copper layer containing the TCXO device, the vertical heat conduction path from the inner layers of the PCB to the TCXO device is blocked. This reduces the heat transferred to the TCXO device from external high-heat components via copper conduction at the copper conduction level of the PCB. The bent traces connecting the TCXO device to external chips are not simply signal routing; they increase the physical length of the traces, increasing the thermal resistance and slowing down the heat transfer efficiency from external chips to the TCXO device. This complements the thermal insulation gap and copper removal design, achieving full-dimensional thermal isolation of the TCXO device from the main heat conduction path, thus significantly reducing the impact of external thermal fluctuations on the TCXO device's operating temperature. When the external temperature changes, this multi-dimensional thermal resistance design significantly slows down the transmission of external temperature changes to the internal quartz crystal resonator of the TCXO device. The rate of temperature change is greatly reduced, and the closed-loop compensation system inside the TCXO device no longer needs to deal with drastic temperature fluctuations. It has more time to detect the frequency drift of the crystal oscillator caused by temperature changes and to accurately adjust the compensation parameters through the temperature compensation circuit to offset the drift. This effectively avoids frequency deviation caused by untimely response of the compensation system, and ultimately improves the output frequency stability of the TCXO device, ensuring the overall stability of systems such as GNSS positioning and communication synchronization that rely on high-precision clock signals.

[0021] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0022] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram of the TCXO device board-level wiring structure according to a preferred embodiment of the present invention, viewed from a side-top view. Figure 2 This is a schematic diagram of the TCXO device board-level wiring structure according to a preferred embodiment of the present invention, viewed from a side-bottom perspective. Figure 3 This is a schematic diagram of the connection relationship between the TCXO device and the external chip in a preferred embodiment of the TCXO device board-level wiring structure of the present invention. Figure 4 This is a schematic diagram of the PCB substrate in a preferred embodiment of the TCXO device board-level wiring structure of the present invention.

[0024] In the picture: 10. PCB substrate; 11. Copper layer; 111. Pad area; 1111. Component pad; 112. Grounding copper area; 113. Thermal insulation gap; 114. Grounding wire; 115. Clock wire; 116. Insulation gap; 12. Dielectric layer; 13. Solder mask layer; 20. TCXO devices; 30. External chip. Detailed Implementation

[0025] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail, but well-known methods, processes, procedures, and elements are not described in detail in order to avoid obscuring the essence of the present invention.

[0026] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0027] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0028] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0029] TCXO devices typically have four pads. The signal definitions for the first, second, third, and fourth pads are EN / GND, GND, CLK_OUT, and VCC, respectively. EN represents the enable signal, GND represents the ground signal, CLK_OUT represents the output reference clock signal, and VCC represents the power supply. The signal definition for the first pad varies between different TCXO models; some define it as EN, while others define it as GND. The following description assumes the first pad is defined as GND.

[0030] Typically, the first and second pads of a TCXO device are directly connected to the GND copper layer of the PCB via a large copper area, while the third and fourth pads are connected to the corresponding pads of external chips via copper traces. Because the GND copper layer is not only large in area but also extensively connected to other components on the PCB and often shares a common ground with other external PCBs, it is the primary heat transfer path for the entire PCB.

[0031] Heat transfer between TCXO devices and the external environment occurs primarily through two paths: the device casing, which is in direct contact with the air, and the metal pads soldered to the PCB board. For the casing path, a shield can be added to the outside of the TCXO device to slow down the surrounding airflow and thus reduce the rate of temperature change. For the metal pad path, this invention mitigates the temperature changes caused by adjusting the PCB board-level wiring structure of the TCXO device.

[0032] The board-level wiring structure of the TCXO device provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0033] like Figures 1-3 As shown, the TCXO device board-level wiring structure provided by the present invention includes a PCB substrate 10 and a TCXO device 20 and an external chip 30 disposed on the PCB substrate 10. The PCB substrate 10 includes a copper layer 11 and a dielectric layer 12, which are alternately arranged along the thickness direction of the PCB substrate 10. The TCXO device 20 has a temperature sensing circuit and a temperature compensation circuit inside. The external chip 30 generates heat at a rate greater than the rate at which the TCXO device 20 generates heat during operation.

[0034] The TCXO device 20 is disposed on any of the outermost copper layers 11 of the PCB substrate 10. The outermost copper layer 11 is either the top copper layer 11 or the bottom copper layer 11 of the PCB substrate 10. The outermost copper layer 11 where the TCXO device 20 is located includes a pad area 111 and a ground copper area 112 of the PCB substrate 10. A heat insulation gap 113 is formed between the pad area 111 and the ground copper area 112. The pad area 111 contains a device pad 1111.

[0035] The pins of TCXO device 20 are connected to device pad 1111. Device pad 1111 is connected to external chip 30 through connection lines. The ground pin of external chip 30 is connected to ground copper area 112. The length of the conductor in the connection line is greater than the minimum straight-line distance between pad area 111 and external chip 30.

[0036] Along the thickness direction of the PCB substrate 10, in at least two copper layers 11 arranged sequentially with the outermost copper layer 11 where the TCXO device 20 is located, the area within the overall range covered by the superimposed projection area of ​​the thermal insulation gap 113 and the projection area of ​​the pad area 111 is not provided with a grounding copper layer; wherein, the projection area of ​​the thermal insulation gap 113 is the area formed by the thermal insulation gap 113 projected along the thickness direction of the PCB substrate 10, and the projection area of ​​the pad area 111 is the area formed by the pad area 111 projected along the thickness direction of the PCB substrate 10.

[0037] It should be noted that the PCB substrate 10 can be a single-layer board, a double-layer board, or a multi-layer board.

[0038] When the PCB substrate 10 is a single-layer board, there is only one copper layer 11. At this time, the TCXO device 20 is disposed on the copper layer 11. A heat insulation gap 113 is formed between the pad area 111 of the copper layer 11 and the ground copper area 112. The pad area 111 is provided with device pads 1111.

[0039] The pins of TCXO device 20 are connected to device pad 1111. Device pad 1111 is connected to external chip 30 through connection lines. The ground pin of external chip 30 is connected to ground copper area 112. The length of the conductor in the connection line is greater than the minimum straight-line distance between pad area 111 and external chip 30.

[0040] When the PCB substrate 10 is a double-layer board, it has two copper layers 11: a top copper layer 11 and a bottom copper layer 11, with a dielectric layer 12 disposed between the two copper layers 11. This dielectric layer 12 isolates the top and bottom copper layers 11 to prevent short circuits and provides support for the PCB substrate 10, ensuring the board's rigidity and stability. Electrical connection between the top and bottom copper layers 11 can be achieved through metallized vias. The inner walls of the vias are plated with copper, thus enabling the circuitry between the two copper layers 11. Specifically, for example, a TCXO device 20 is disposed on the top copper layer 11, which has a pad area 111 and a ground copper area 112, with a thermal insulation gap 113 formed between the pad area 111 and the ground copper area 112.

[0041] The area within the superimposed area of ​​the thermal insulation gap 113 on the bottom copper layer 11 and the pad area 111 on the bottom copper layer 11 is not provided with a grounding copper pad.

[0042] Furthermore, the pins of the TCXO device 20 are connected to the device pad 1111, the device pad 1111 is connected to the external chip 30 through the connection line, and the ground pin of the external chip 30 is connected to the ground copper area 112; the length of the conductor in the connection line is greater than the minimum straight distance between the pad area 111 and the external chip 30.

[0043] When the PCB substrate 10 is a multilayer board, it has three or more copper layers 11. Along the thickness direction of the PCB substrate 10, the PCB substrate 10 includes a top copper layer 11, an intermediate copper layer 11, and a bottom copper layer 11, with a dielectric layer 12 disposed between adjacent copper layers 11. For example, the TCXO device 20 is disposed on the top copper layer 11. Along the thickness direction of the PCB substrate 10, at least two copper layers 11 arranged sequentially may include a first intermediate copper layer, a second intermediate copper layer, a third intermediate copper layer, ..., a bottom copper layer 11 below the top copper layer 11. No grounding copper is disposed in the area covered by the superimposed projection areas of the thermal insulation gap 113 and the pad area 111 on these copper layers 11.

[0044] Furthermore, the pins of the TCXO device 20 are connected to the device pad 1111, the device pad 1111 is connected to the external chip 30 through the connection line, and the ground pin of the external chip 30 is connected to the ground copper area 112; the length of the conductor in the connection line is greater than the minimum straight distance between the pad area 111 and the external chip 30.

[0045] Understandably, the wires connecting the device pad 1111 and the external chip 30 are not directly connected, but rather through bending, winding, or other methods to ensure that the actual length of the wire is greater than the geometric shortest straight-line distance between them. This wire length is not infinitely extended and still needs to meet electrical performance requirements (such as impedance matching and signal transmission delay).

[0046] In addition, the thermal insulation gap 113 can be understood as a gap strip without copper or other conductive medium set on the copper layer 11 where the TCXO device 20 is located, between the pad area 111 and the ground copper area 112. The width of this gap strip can be reasonably designed according to the size of the PCB substrate 10, the heat dissipation characteristics of the TCXO device 20, and the heat generation of the external chip 30.

[0047] The rates at which external chip 30 and TCXO device 20 generate heat during operation refer to the heat generated per unit time by external chip 30 and TCXO device 20, respectively. The rate at which external chip 30 generates heat is greater than the rate at which TCXO device 20 generates heat; this is a premise of the board-level wiring structure design of the TCXO device in this invention. This indicates that the external device generates more heat per unit time than the TCXO device 20.

[0048] It should be noted that the connection lines include wires connecting the TCXO device 20 and the external chip 30, as well as vias for connecting wires in different copper layers 11.

[0049] The heat generated by the external chip 30 during operation is conducted through the copper layer 11 of the PCB substrate 10 (copper is a good conductor of heat). By setting a thermal insulation gap 113 between the pad area 111 and the ground copper area 112 of the copper layer 11 where the TCXO device 20 is located, the heat conduction path from the ground pin of the external chip 30 → ground copper area 112 → pad area 111 → surface of the TCXO device 20 can be cut off. Because the thermal insulation gap 113 has no copper dielectric, heat conduction can only occur through air or the PCB substrate (such as FR-4, whose thermal conductivity is much lower than that of copper), which can significantly reduce the efficiency of heat transfer from the surface to the pad area 111 of the TCXO device 20, and reduce the local temperature rise of the TCXO device 20 caused by heat conduction from the external chip 30.

[0050] In a multilayer PCB, heat is transferred to the TCXO device 20 via vertical heat conduction (the thickness direction of the PCB substrate 10) and lateral heat conduction through the copper layer 11. Within the entire area covered by the superimposed projection areas of the thermal insulation gap 113 and the pad area 111 on the lower copper layer 11, at least two copper layers 11 do not have grounded copper pads. This results in the absence of copper pads, an efficient heat-conducting medium, in the vertical direction on at least two copper layers 11 corresponding to the thermal insulation gap 113 and the pad area 111. This further blocks the vertical heat conduction from the lower copper layer 11 to the TCXO device 20, preventing heat from accumulating below the pad area 111 and being transferred to the TCXO device 20. This maintains the stability of the operating temperature of the TCXO device 20 and reduces frequency drift caused by temperature fluctuations.

[0051] In addition, the length of the conductor in the connection line is greater than the minimum straight-line distance between the pad area 111 and the external chip 30. That is, a non-direct wiring method is adopted. The use of a bent wiring method can increase the physical length of the conductor. The thermal resistance increases with the increase of the conductor. The resistance encountered by the heat flow during the conduction process is increased. The amount of heat transferred from the external chip 30 to the TCXO device 20 per unit time is reduced, and the heat transfer rate is slowed down. This makes the temperature change rate of the TCXO device 20 much lower than that of the external chip 30. The TCXO device 20 can maintain a stable operating temperature for a longer period of time, ensuring the accuracy of the output frequency.

[0052] In the above embodiments, such as Figure 3 As shown, the minimum distance between the outer boundary of one side of the TCXO device 20 and the grounded copper area 112 on the same side is greater than or equal to 3 times the width of the conductor in the connection line.

[0053] For example, when the conductors in the connection line are thin conductors with a line width of 4mil (1mil equals 0.0254mm), for a TCXO device 20 with a package size of 2mm*1.6mm, the front, back, left and right sides of the TCXO device 20 are extended outward by at least 0.3mm respectively, forming a rectangular space of 2.6mm*22.2mm in the pad area 111, in which the TCXO device 20 can be placed.

[0054] This spacing significantly slows down the heat transfer rate between the copper foil in the grounded copper area 112 and the TCXO device 20. Specifically, this spacing replaces the high-density heat conduction path of close contact between the copper foil and the TCXO device 20 with air or a dielectric layer 12. This not only extends the heat transfer path, allowing heat to dissipate and decay during transfer, but also significantly weakens the thermal coupling between the two. Furthermore, it allows the heat radiated from the copper foil to decrease rapidly before reaching the TCXO device 20, thereby effectively preventing temperature fluctuations on the copper foil from being directly and rapidly conducted to the temperature-sensitive TCXO device 20. This significantly reduces the temperature variation around the TCXO device 20, reduces the frequency drift problem of the TCXO device 20 caused by temperature fluctuations, and thus ensures the stability of its oscillation frequency.

[0055] In the above embodiments, when the PCB substrate 10 includes two or more copper layers 11 and their corresponding dielectric layers 12, and some wires in the connection lines are located in different copper layers 11, the wires with the same function located in different copper layers 11 in the connection lines are connected through vias.

[0056] By distributing functionally identical wires across different copper layers 11 and connecting them vias, the heat conducted from the external chip 30 to the wires can be dispersed across multiple copper layers 11, breaking the concentrated accumulation of heat in a single copper layer 11. This allows heat to form a dispersed transfer path along multiple copper layers 11, reducing the heat density in the local area surrounding the TCXO and reducing the concentrated conduction of heat to the TCXO device 20 from the source.

[0057] Furthermore, the absence of a grounding copper layer within the superimposed area of ​​the thermal insulation gap 113 and the pad area 111 further cuts off the heat conduction path from the grounding copper layer to the TCXO device 20. Due to the lack of a highly thermally conductive grounding copper layer in these areas, the thermal resistance is significantly increased, making it difficult for heat to dissipate to the TCXO device 20 through this path. Therefore, by dispersing the heat path and increasing the thermal resistance in key areas, the rate of external heat transfer to the TCXO can be doubly slowed, ensuring a stable operating temperature and effectively avoiding frequency stability issues caused by sudden temperature changes.

[0058] For complex PCB design scenarios with high thermal interference on the top layer and the need to disperse heat, the via-layer connection method provided in this embodiment can be used. This connection method relies on multi-layer buffering and flexible paths to buffer temperature changes.

[0059] In the above embodiments, such as Figure 3As shown, the connection line includes a ground wire 114 and a clock wire 115. One end of the ground wire 114 is connected to the ground pin of the TCXO device 20, and the other end is connected to the ground pin of the external chip 30. One end of the clock wire 115 is connected to the clock output pin of the TCXO device 20, and the other end is connected to the clock input pin of the external chip 30.

[0060] The length of the grounding wire 114 is greater than the straight-line distance between the device pad 1111 connected to the ground pin of the TCXO device 20 and the ground pin of the external chip 30; the length of the clock wire 115 is greater than the straight-line distance between the device pad 1111 connected to the clock output pin of the TCXO device 20 and the clock input pin of the external chip 30. Compared to the connection between the device pad 1111 and the external chip 30 via a straight wire, connecting them by bending or winding increases the length of the wire, thereby increasing the thermal resistance of the wire and slowing down the heat transfer rate.

[0061] Furthermore, both the grounding wire 114 and the clock wire 115 extend along the first direction and are arranged with multiple back-and-forth bends. The first direction can be from the pad area 111 to the external chip 30.

[0062] In a specific embodiment, such as Figure 3 As shown, the grounding conductor 114 includes multiple grounding extension sections and grounding bend transition sections. The grounding extension sections extend back and forth along the second direction, and each grounding extension section is parallel to the others. Adjacent grounding extension sections are connected by the grounding bend transition sections. The second direction is perpendicular to the first direction.

[0063] The clock conductor 115 includes multiple clock extensions and clock bend transitions. The clock extensions extend back and forth along a second direction and are parallel to each other. Adjacent clock extensions are connected by clock bend transitions.

[0064] By bending the ground wire 114 and the clock wire 115, the wire length can be increased, thereby increasing the thermal resistance of the wire. This slows down the heat transfer rate between the PCB GND copper and the TCXO device 20, and also slows down the heat transfer rate between other chips and the TCXO device 20 through the CLK_OUT signal line.

[0065] Specifically, both the grounding wire 114 and the clock wire 115 can be made of 4mil wide thin copper wire using a serpentine routing method. Since the time T taken for heat to transfer from one end of the copper wire to the other is proportional to the square of the copper wire length L, i.e., T∝L... 2Therefore, the longer the copper wire, the longer the heat transfer time. For example, if the grounding wire 114 and the clock wire 115 are both straight traces of length L, and the time it takes for heat to transfer from one end of the straight trace to the other is T, then when the trace length becomes 2L, the transfer time becomes 4T. When the serpentine trace length is 5 times the straight trace length, the transfer time is extended to 25T, giving the negative feedback compensation system inside the TCXO device 20 more time to perform compensation and adjustment.

[0066] In the above embodiments, such as Figure 3 As shown, the ground extension segment is parallel to the clock extension segment, each segment in the ground bending transition segment is parallel to the corresponding segment in the clock bending transition segment, and the distance between the ground extension segment and the clock extension segment is equal to the distance between the ground bending transition segment and the clock bending transition segment.

[0067] On the one hand, the bent routing and parallel, equally spaced arrangement of the grounding conductor 114 and clock conductor 115 precisely control the length of the clock conductor 115 and the grounding conductor 114 to ensure timing synchronization. Simultaneously, they form a uniform transmission line structure to stabilize impedance, reduce signal transmission and distortion, and maintain the integrity of the clock signal. On the other hand, the parallel, equally spaced grounding conductor 114 shields the clock conductor 115, significantly reducing its electromagnetic radiation and external interference. The uniform heat capacity distribution also helps buffer temperature fluctuations and avoid localized potential differences. Furthermore, the neat routing improves PCB manufacturing consistency and facilitates later signal simulation and troubleshooting.

[0068] Furthermore, the line width of the grounding conductor 114 is equal to the line width of the clock conductor 115, and the ratio of the spacing between adjacent grounding extensions and clock extensions to the line width of the grounding conductor 114 in the same round trip is 1 to 2.

[0069] The grounding conductor 114 and the clock conductor 115 are designed with equal line widths, and the ratio of the spacing between adjacent grounding extensions and clock extensions in the same round trip to the line width of the grounding conductor 114 is 1 to 2. This design is a precise optimization that balances signal quality, anti-interference capability, and production feasibility. This design allows the stripline structure formed by the grounding conductor 114 and the clock conductor 115 to accurately match the target characteristic impedance, avoiding clock signal reflection caused by impedance abrupt changes and ensuring the integrity of the clock signal of the TCXO device 20. It is also located in the optimal range of signal and ground shielding, which can effectively reduce the electromagnetic radiation of the clock conductor 115 with the help of the grounding conductor 114, while reducing the crosstalk of external signals to the clock conductor 115. It also allows the thermal capacities of the grounding conductor 114 and the clock conductor 115 to be closer, making the heat distribution more uniform and slightly buffering temperature fluctuations. It can also avoid manufacturing problems such as etching deviation caused by excessive spacing, thus reducing production risks while ensuring stable circuit operation.

[0070] In the above embodiments, such as Figure 4 As shown, an insulating gap 116 is formed between the grounding conductor 114 and the grounding copper area 112 on the side away from the clock conductor 115, and between the clock conductor 115 and the grounding copper area 112 on the side away from the grounding conductor 114. The ratio of the width of the insulating gap 116 along the second direction to the line width of the grounding conductor 114 is greater than or equal to 2.

[0071] The insulation gap 116 reduces thermal conduction interference and buffers temperature fluctuations. Because the PCB GND copper layer has a large area and high heat capacity, heat is easily transferred rapidly through close-range conductors when temperatures change. A sufficient insulation gap 116 weakens the thermal conduction efficiency between the conductors and the GND copper layer, preventing rapid temperature changes in the GND copper layer from being conducted to the clock conductor 115 and the ground conductor 114. This reduces temperature shocks to the connected TCXO device 20, helps buffer the rate of temperature change in the TCXO device 20, and reduces frequency drift caused by temperature fluctuations.

[0072] In the above embodiment, the power supply pin of the TCXO device 20 is connected to an external power supply through a power supply wire, and the ratio of the line width of the power supply wire to the line width of the ground wire 114 is 1.5 to 3.

[0073] By using wider power supply leads, the DC resistance of the power supply leads can be significantly reduced, thereby reducing voltage drop and power loss during current transmission and preventing TCXO device 20 from malfunctioning due to insufficient or fluctuating supply voltage. Furthermore, the wider power supply leads have a larger cross-sectional area and stronger current carrying capacity, effectively dispersing Joule heat generated during current flow and preventing localized overheating due to overload or prolonged operation. Simultaneously, the larger cross-sectional area increases the thermal capacity of the power supply leads, preventing sudden temperature rises and falls even during transient current fluctuations in the external power supply. This reduces the transmission of such temperature changes to TCXO device 20 through the pins, helping to buffer temperature fluctuations in TCXO device 20 and indirectly ensuring its frequency stability.

[0074] In the above embodiments, such as Figure 1 and Figure 2 As shown, the PCB substrate 10 also includes a solder mask layer 13. The side of the ground copper area 112 away from the dielectric layer 12 and the pad area 111 are both provided with the solder mask layer 13; wherein, the solder mask layer 13 in the pad area 111 surrounds the device pad 1111. The solder mask layer 13 is used to avoid the risk of short circuits during soldering. By fully covering non-soldering areas such as traces, it suppresses solder flow and prevents bridging, ensuring the reliability of the soldering process. Additionally, it is used to delay circuit aging failure by isolating the copper foil from air, thus blocking the oxidation and corrosion path of the metal traces.

[0075] In other embodiments, the present invention also provides a board-level routing method for a TCXO device, comprising the following steps: S100. A pad area 111 and a ground copper area 112 are provided on the outermost copper layer 11 of the TCXO device 20 on the PCB substrate 10. A heat insulation gap 113 is formed between the pad area 111 and the ground copper area 112.

[0076] S200. Set device pad 1111 in pad area 111, connect the pins of TCXO device 20 to device pad 1111, connect device pad 1111 to external chip 30 through connection line, and connect the ground pin of external chip 30 to ground copper area 112; wherein, the length of the wire in the connection line is greater than the minimum straight distance between pad area 111 and external chip 30.

[0077] S300. For at least two copper layers 11 arranged sequentially with the outermost copper layer 11 where the TCXO device 20 is located, the ground copper layer in the area covered by the projection area of ​​the thermal insulation gap 113 and the projection area of ​​the pad area 111 is removed; wherein, the projection area of ​​the thermal insulation gap 113 is the area formed by the thermal insulation gap 113 projected along the thickness direction of the PCB substrate 10, and the projection area of ​​the pad area 111 is the area formed by the pad area 111 projected along the thickness direction of the PCB substrate 10.

[0078] By forming a thermal insulation gap 113 between the pad area 111 and the ground copper area 112, the heat conduction path of the copper layer on the surface of the circuit board can be cut off. By removing the ground copper area within the area covered by the projection area of ​​the thermal insulation gap 113 and the projection area of ​​the pad area 111 in at least two copper layers 11 arranged sequentially with the outermost copper layer 11 where the TCXO device 20 is located, the heat conduction path in the thickness direction of the PCB substrate 10 can be blocked. This results in a thermal island state around the TCXO device 20, where the heat from external high-heat components cannot be conducted to the TCXO device 20, and the area is dominated only by the working heat of the TCXO device 20 itself. The temperature fluctuation amplitude and rate are greatly reduced, and the temperature compensation circuit in the TCXO device 20 can more accurately compensate for its own thermal drift, thus solving the problem of accuracy reduction caused by external thermal disturbances from the root.

[0079] It should be noted that the size of the device pads 1111 in pad area 111 should be the minimum necessary size in the industry to ensure the reliability of the TCXO device 20 pin soldering. For example, for a TCXO device 20 with a package size of 2.0mm*1.6mm, the size of a single device pad 1111 can be 0.35mm~0.45mm. Excessively large device pads 1111 will increase the heat conduction area, causing heat from the TCXO device 20 to be rapidly conducted to the PCB substrate 10 through the device pads 1111, or external heat to enter the TCXO device 20 through the device pads 1111. Smaller device pads 1111 can reduce the contact area for heat conduction, thereby slowing down the heat transfer rate.

[0080] In the TCXO device board-level routing method provided by this invention, the minimum spacing between the outer boundary of one side of the TCXO device 20 and the ground copper area 112 on the same side is greater than or equal to three times the wire width in the connection line. In this invention, this minimum spacing can be greater than or equal to 0.3 mm. This spacing setting can significantly slow down the heat transfer rate between the copper of the ground copper area 112 and the TCXO device 20.

[0081] In the TCXO device board-level routing method provided by the present invention, when the PCB substrate 10 includes two or more copper layers 11 and their corresponding dielectric layers 12, and some conductors in the connection lines are located in different copper layers 11, the conductors with the same function located in different copper layers 11 in the connection lines are connected through vias.

[0082] In other embodiments, the present invention also provides a circuit board including the above-described TCXO device board-level wiring structure, or uses the above-described TCXO device board-level wiring method to wire the TCXO device 20 disposed on the PCB substrate 10.

[0083] It should be noted that the use of step numbers (letters or numbers) to refer to certain specific method steps in this invention is merely for the purpose of convenience and brevity in description, and is by no means intended to restrict the order of these method steps. Those skilled in the art will understand that the order of the relevant method steps should be determined by the technology itself and should not be unduly restricted by the existence of step numbers. Those skilled in the art can determine various permissible and reasonable orderings of steps based on the technology itself.

[0084] Those skilled in the art will understand that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0085] It should be understood that the above embodiments are merely exemplary and not restrictive. Various obvious or equivalent modifications or substitutions that can be made by those skilled in the art regarding the above details without departing from the basic principles of the present invention will be included within the scope of the claims of the present invention.

Claims

1. A board-level wiring structure for a TCXO device, characterized in that, Includes a PCB substrate and a TCXO device and external chip disposed on the PCB substrate; The PCB substrate includes a copper layer and a dielectric layer, which are arranged alternately along the thickness direction of the PCB substrate; the TCXO device has a temperature sensing circuit and a temperature compensation circuit inside; the external chip generates heat at a rate greater than the TCXO device ... The TCXO device is disposed on any outermost copper layer of the PCB substrate, and the outermost copper layer is either the top copper layer or the bottom copper layer of the PCB substrate; the outermost copper layer where the TCXO device is located includes a pad area and a ground copper area of ​​the PCB substrate; a heat insulation gap is formed between the pad area and the ground copper area; a device pad is disposed in the pad area. The pins of the TCXO device are connected to the device pads, and the device pads are connected to the external chip via connection lines. The ground pin of the external chip is connected to the ground copper area. The length of the conductor in the connection line is greater than the minimum straight-line distance between the pad area and the external chip. In at least two copper layers arranged sequentially with the outermost copper layer containing the TCXO device, the area within the superimposed area of ​​the projection region of the thermal insulation gap and the projection region of the pad region is not provided with a grounding copper layer; wherein, the projection region of the thermal insulation gap is the area formed by the thermal insulation gap projected along the thickness direction of the PCB substrate, and the projection region of the pad region is the area formed by the pad region projected along the thickness direction of the PCB substrate.

2. The TCXO device board-level wiring structure according to claim 1, characterized in that, The minimum distance between the outer boundary of one side of the TCXO device and the grounding copper area on the same side is greater than or equal to three times the wire width in the connection line.

3. The TCXO device board-level wiring structure according to claim 1, characterized in that, When the PCB substrate includes two or more copper layers and their corresponding dielectric layers, and some of the conductors in the connection lines are located in different copper layers, the conductors with the same function located in different copper layers in the connection lines are connected through vias.

4. The TCXO device board-level wiring structure according to any one of claims 1-3, characterized in that, The connection line includes a ground wire and a clock wire. One end of the ground wire is connected to the ground pin of the TCXO device, and the other end is connected to the ground pin of the external chip. One end of the clock wire is connected to the clock output pin of the TCXO device, and the other end is connected to the clock input pin of the external chip. The length of the grounding conductor is greater than the straight-line distance between the device pad connected to the ground pin of the TCXO device and the ground pin of the external chip; the length of the clock conductor is greater than the straight-line distance between the device pad connected to the clock output pin of the TCXO device and the clock input pin of the external chip.

5. The TCXO device board-level wiring structure according to claim 4, characterized in that, Both the grounding wire and the clock wire extend along a first direction and are arranged with multiple back-and-forth bends; the first direction is from the pad area to the external chip.

6. The TCXO device board-level wiring structure according to claim 5, characterized in that, The grounding conductor includes multiple grounding extension sections and grounding bend transition sections. The grounding extension sections extend along a second direction and are parallel to each other. Adjacent grounding extension sections are connected by the grounding bend transition sections. The second direction is perpendicular to the first direction.

7. The TCXO device board-level wiring structure according to claim 6, characterized in that, The clock conductor includes multiple clock extension segments and clock bend transition segments. The clock extension segments extend along a second direction and are parallel to each other. Adjacent clock extension segments are connected by the clock bend transition segments.

8. The TCXO device board-level wiring structure according to claim 7, characterized in that, The ground extension is parallel to the clock extension, each segment of the ground bend transition is parallel to the corresponding segment of the clock bend transition, and the distance between the ground extension and the clock extension is equal to the distance between the ground bend transition and the clock bend transition.

9. The TCXO device board-level wiring structure according to claim 8, characterized in that, The width of the grounding conductor is equal to the width of the clock conductor, and the ratio of the spacing between adjacent grounding extensions and clock extensions to the width of the grounding conductor in the same round trip is 1 to 2.

10. The TCXO device board-level wiring structure according to claim 9, characterized in that, An insulating gap is formed between the grounding conductor and the grounding copper area on the side away from the clock conductor, and between the clock conductor and the grounding copper area on the side away from the grounding conductor. The ratio of the width of the insulating gap along the second direction to the line width of the grounding conductor is greater than or equal to 2.

11. The TCXO device board-level wiring structure according to any one of claims 1-3, characterized in that, The power supply pin of the TCXO device is connected to an external power supply via a power supply wire, and the ratio of the line width of the power supply wire to the line width of the ground wire is 1.5 to 3.

12. The TCXO device board-level wiring structure according to any one of claims 1-3, characterized in that, The PCB substrate further includes a solder mask layer, and the solder mask layer is provided on the side of the ground copper area away from the dielectric layer and the pad area; wherein, the solder mask layer in the pad area is arranged around the device pad.

13. A board-level routing method for a TCXO device, characterized in that, Includes the following steps: A pad area and a ground copper area are set on the outermost copper layer of the TCXO device on the PCB substrate, and a heat insulation gap is formed between the pad area and the ground copper area. Set up device pads within the pad area, connect the pins of the TCXO device to the device pads, connect the device pads to the external chip via connection lines, and connect the ground pins of the external chip to the ground copper area; wherein, the length of the conductor in the connection line is greater than the minimum straight-line distance between the pad area and the external chip; For at least two copper layers arranged sequentially with the outermost copper layer where the TCXO device is located, the ground copper layer within the area covered by the projection area of ​​the thermal insulation gap and the projection area of ​​the pad area is removed; wherein, the projection area of ​​the thermal insulation gap is the area formed by the thermal insulation gap projected along the thickness direction of the PCB substrate, and the projection area of ​​the pad area is the area formed by the pad area projected along the thickness direction of the PCB substrate.

14. The TCXO device board-level routing method according to claim 13, characterized in that, The minimum spacing between the outer boundary of one side of the TCXO device and the grounding copper area on the same side is set to be greater than or equal to 3 times the wire width in the connection line.

15. The TCXO device board-level routing method according to claim 13, characterized in that, When a PCB substrate includes two or more copper layers and their corresponding dielectric layers, and some conductors in the connection circuit are placed on different copper layers, the conductors with the same function located on different copper layers in the connection circuit are connected through vias.

16. A circuit board, characterized in that, Including the TCXO device board-level wiring structure as described in any one of claims 1-12, or, The TCXO devices disposed on the PCB substrate are routed using the TCXO device board-level routing method as described in any one of claims 13-15.

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