Method of manufacturing semiconductor memory device

Abstract

A method of manufacturing a semiconductor memory device includes the steps of: forming a hole through at least a portion of a stacked structure having first material layers and second material layers alternately stacked; sequentially forming a blocking insulating layer, a charge trapping layer and a tunnel insulating layer along the hole; forming a preliminary channel layer along the tunnel insulating layer; forming a sacrificial layer by oxidizing the exposed inner wall of the preliminary channel layer; forming a first sacrificial layer and a second sacrificial layer separated in a second direction crossing the first direction by patterning the sacrificial layer; and separating the preliminary channel layer in the second direction by performing an etching process, thereby forming a first channel layer and a second channel layer.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to electronic devices, and more specifically, to a method of manufacturing a semiconductor memory device. Background Technology

[0002] Non-volatile memory devices are memory devices that retain stored data even when power is interrupted. As the integration density of two-dimensional (2D) non-volatile memory devices, in which memory cells are formed as a single layer on a substrate, has reached its limit, three-dimensional (3D) non-volatile memory devices, in which memory cells are stacked on a substrate in the vertical direction, have been proposed.

[0003] 3D non-volatile memory devices may include alternately stacked interlayer insulating layers and gate electrodes, as well as channel layers penetrating the interlayer insulating layers and gate electrodes, wherein memory cells are stacked along the channel layers. Various structures and manufacturing methods have been developed to improve the operational reliability of such non-volatile memory devices with 3D structures. Summary of the Invention

[0004] Various embodiments of this disclosure may relate to a semiconductor memory device including a vertical structure and a method of manufacturing the semiconductor memory device, the vertical structure including a plurality of plug patterns.

[0005] According to embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include the following steps: forming a hole through at least a portion of a stacked structure in which a first material layer and a second material layer are alternately stacked in a first direction; forming a barrier insulating layer along the hole; forming a charge trapping layer along the barrier insulating layer; forming a tunnel insulating layer along the charge trapping layer; forming a preliminary channel layer along the tunnel insulating layer; forming a sacrificial layer by oxidizing the exposed inner walls of the preliminary channel layer; forming a first sacrificial layer and a second sacrificial layer separated from each other in a second direction intersecting the first direction by patterning the sacrificial layer; and separating the preliminary channel layer in the second direction by performing an etching process to form the first channel layer and the second channel layer.

[0006] According to embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include the following steps: forming a hole through at least a portion of a stacked structure in which a first material layer and a second material layer are alternately stacked in a first direction; forming a barrier insulating layer along the hole; forming a charge trapping layer along the barrier insulating layer; forming a tunnel insulating layer along the charge trapping layer; forming a preliminary channel layer along the tunnel insulating layer; etching the preliminary channel layer to a reduced thickness; forming a sacrificial layer by oxidizing the inner wall of the preliminary channel layer; forming a first sacrificial layer and a second sacrificial layer separated from each other in a second direction intersecting the first direction by patterning the sacrificial layer; and separating the preliminary channel layer in the second direction by performing an etching process to form the first channel layer and the second channel layer.

[0007] According to embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include the following steps: forming a hole through at least a portion of a stacked structure in which a first material layer and a second material layer are alternately stacked in a first direction; forming a recessed region by etching the second material layer through the hole to a recess depth; forming a barrier insulating layer and a charge trapping layer in each recessed region; forming a tunnel insulating layer along the sidewalls of the charge trapping layer and the first material layer; forming a preliminary channel layer along the tunnel insulating layer; forming a sacrificial layer by oxidizing the inner wall of the preliminary channel layer; forming a first sacrificial layer and a second sacrificial layer separated from each other in a second direction intersecting the first direction by patterning the sacrificial layer; and separating the preliminary channel layer in the second direction by performing an etching process to form the first channel layer and the second channel layer.

[0008] According to embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include the following steps: forming a hole through at least a portion of a stacked structure in which a first material layer and a second material layer are alternately stacked in a first direction; forming a recessed region by etching the second material layer exposed via the hole to a recess depth; forming a barrier insulating layer and a charge trapping layer in each recessed region; forming a tunnel insulating layer along the first material layer and the charge trapping layer; forming a preliminary channel layer along the tunnel insulating layer; etching the preliminary channel layer to reduce the thickness of the preliminary channel layer; forming a sacrificial layer by oxidizing the exposed inner walls of the preliminary channel layer; forming a first sacrificial layer and a second sacrificial layer separated from each other in a second direction orthogonal to the first direction by patterning the sacrificial layer; and separating the preliminary channel layer in the second direction by performing an etching process to form the first channel layer and the second channel layer. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a circuit diagram of a memory cell array according to an embodiment of the present disclosure.

[0011] Figure 3A and Figure 3B This is a diagram showing the vertical arrangement of a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 4A , Figure 4B and Figure 4C These are plan views and cross-sectional views used to describe a semiconductor memory device according to embodiments of the present disclosure.

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B and Figure 11C These are plan views and cross-sectional views used to describe a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0014] Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B and Figure 18C These are plan views and cross-sectional views used to describe a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0015] Figure 19A , Figure 19B and Figure 19C These are plan views and cross-sectional views used to describe a semiconductor memory device according to embodiments of the present disclosure.

[0016] Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22 , Figure 23 , Figure 24 , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B and Figure 26C These are plan views and cross-sectional views used to describe a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0017] Figure 27A , Figure 27B , Figure 27C , Figure 28A , Figure 28B , Figure 28C , Figure 29 , Figure 30 , Figure 31 , Figure 32A , Figure 32B , Figure 32C , Figure 33A , Figure 33B and Figure 33C These are plan views and cross-sectional views used to describe a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0018] Figure 34 This is a block diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure. Detailed Implementation

[0019] The specific structural or functional descriptions of embodiments based on the concepts of this disclosure disclosed in this specification or application are illustrated by example to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure should not be construed as limited to those described in this specification or application, and may be modified and replaced in various ways with other equivalent embodiments.

[0020] In the following text, although terms such as “first” and “second” may be used to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one component from another, and the order or number of components is not limited by the terms.

[0021] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0022] Reference Figure 1 The semiconductor memory device 100 may include peripheral circuitry 120 and a memory cell array 110.

[0023] The peripheral circuitry 120 can perform programming operations to store data in the memory cell array 110, reading operations to output data stored in the memory cell array 110, and erasing operations to erase data stored in the memory cell array 110. In some embodiments, the peripheral circuitry 120 may include an input / output circuitry 121, a control circuitry 123, a voltage generation circuitry 131, a row decoder 133, a column decoder 135, a page buffer 137, and a source line driver 139.

[0024] The peripheral circuit 120 can be connected to the memory cell array 110 via the common source line CSL, bit line BL, drain select line DSL, word line WL and source select line SSL.

[0025] Input / output circuit 121 can transmit commands (CMD) and addresses (ADD) received from an external device (e.g., a memory controller) of semiconductor memory device 100 to control circuit 123. Input / output circuit 121 can exchange data (DATA) with external devices and column decoder 135.

[0026] Control circuit 123 can output operation signal OP_S, row address RADD, source line control signal SL_S, page buffer control signal PB_S and column address CADD in response to command CMD and address ADD.

[0027] The voltage generation circuit 131 can generate various operating voltages Vop for programming, reading and erasing operations in response to the operation signal OP_S.

[0028] The line decoder 133 can transmit the operating voltage Vop to the drain select line DSL, word line WL, and source select line SSL in response to the line address RADD.

[0029] The column decoder 135 can send data DATA input from the input / output circuit 121 to the page buffer 137 or send data DATA stored in the page buffer 137 to the input / output circuit 121 in response to the column address CADD. The column decoder 135 can exchange data DATA with the input / output circuit 121 via the column line CL. The column decoder 135 can exchange data DATA with the page buffer 137 via the data line DL.

[0030] Page buffer 137 can store read data received via bit line BL in response to page buffer control signal PB_S. Page buffer 137 can sense the voltage or current of bit line BL during read operations.

[0031] The source line driver 139 can control the voltage applied to the common source line CSL in response to the source line control signal SL_S.

[0032] The memory cell array 110 may include multiple memory blocks. Each memory block may include multiple memory cells arranged in a three-dimensional (3D) configuration. The multiple memory cells may be divided into multiple memory cell strings. Each memory cell may be a non-volatile memory cell. In this embodiment, each memory cell may be a NAND flash memory cell.

[0033] Figure 2 This is a circuit diagram of a memory cell array according to an embodiment of the present disclosure.

[0034] Reference Figure 2 The memory cell string CS of the memory cell array may include at least one source-select transistor SST, multiple memory cells MC, and at least one drain-select transistor DST. The multiple memory cells MC may be connected in series between the source-select transistor SST and the drain-select transistor DST. The source-select transistor SST, the multiple memory cells MC, and the drain-select transistor DST may be connected in series via a channel pattern or a channel layer. The channel pattern or channel layer may serve as the channel region of the memory cell string CS, and it may be formed of a semiconductor layer.

[0035] The common source region (CSR) and bit line (BL) can be connected to the channel pattern or channel layer of the memory cell string (CS). A voltage used to discharge the potential of the channel region of the memory cell string (CS) can be applied to the common source region (CSR). A voltage used to pre-charge the channel region of the memory cell string (CS) can be applied to the bit line (BL).

[0036] Multiple memory cells MC of the memory cell string CS can be connected to a common source region CSR via source select transistor SST. Multiple memory cells MC of the memory cell string CS can be connected to bit line BL via drain select transistor DST.

[0037] The gate electrodes of the source select transistor (SST), multiple memory cells (MC), and drain select transistor (DST) can form a gate stack structure. The gate stack structure may include a source select line SSL, which serves as the gate electrode of the source select transistor (SST), multiple word lines WL, which serve as the gate electrodes of the multiple memory cells (MC), and a drain select line DSL, which serves as the gate electrode of the drain select transistor (DST).

[0038] The common source region CSR can be electrically connected to Figure 1 The common source line (CSL) is shown. The common source region (CSR) can be formed in a doped semiconductor structure (DPS).

[0039] Figure 3A and Figure 3B This is a diagram showing the vertical arrangement of a semiconductor memory device according to an embodiment of the present disclosure.

[0040] Reference Figure 3A and Figure 3B The semiconductor memory device may include a first structure ST1, a second structure ST2, and a doped semiconductor structure DPS. The first structure ST1 may include a cell array structure CAS and a bit line array structure BAS, and the second structure ST2 may include a peripheral circuit structure PS.

[0041] Bit-line array (BAS) structures may include the above-mentioned references. Figure 1 and Figure 2 The bit line BL is described.

[0042] The cell array structure CAS can be categorized between the bit line array structure BAS and the doped semiconductor structure DPS. The cell array structure CAS may include multiple gate electrodes connected to multiple memory cell strings. These multiple gate electrodes may include... Figure 2 The source select line (SSL), multiple word lines (WL), and drain select line (DSL) are shown, and they may be spaced apart from each other in the vertical direction. The cell array structure (CAS) may include a channel pattern (or channel layer) that penetrates multiple gate electrodes. The multiple gate electrodes and channel pattern (or channel layer) can be formed into various structures to improve the integration density of the memory cell string.

[0043] A doped semiconductor structure (DPS) may include at least one of n-type impurities and p-type impurities. A doped semiconductor structure (DPS) may include components configured as follows: Figure 2 The common source region (CSR) shown is an n-type impurity region. This disclosure is not limited thereto; the doped semiconductor structure (DPS) may also include a p-type impurity region as a well region.

[0044] The peripheral circuit structure PS may include the overlapping region of a doped semiconductor structure (DPS), a cell array structure (CAS), and a bit line array structure (BAS). The peripheral circuit structure PS may include multiple transistors, capacitors, resistors, etc., which constitute... Figure 1 The peripheral circuit 120 shown.

[0045] The peripheral circuit structure PS can be as follows Figure 3A The diagram shows a structure adjacent to the doped semiconductor structure DPS, or it can be shown as... Figure 3B The diagram shows a structure adjacent to the bit line array (BAS).

[0046] Although not shown in the accompanying drawings, each of the first structure ST1 and the second structure ST2 may include at least one of a plurality of interconnects, a plurality of contacts, and a plurality of conductive bonding pads for electrical connection.

[0047] The first structure ST1, the doped semiconductor structure DPS, and the second structure ST2 can be stacked in the vertical direction (Z). In addition, bit lines BL can be arranged sequentially in the first horizontal direction (X), and each bit line BL can extend in the second horizontal direction (Y) orthogonal to the first horizontal direction (X).

[0048] Figure 4A , Figure 4B and Figure 4C These are plan views and cross-sectional views used to describe a semiconductor memory device according to embodiments of the present disclosure.

[0049] Figure 4A , Figure 4B and Figure 4C It is shown Figure 1 A plan view and a cross-sectional view of a portion of the memory cell array 110.

[0050] Reference Figure 4A , Figure 4B and Figure 4C The semiconductor memory device may include a gate stack structure GST and a first plug pattern PP1 and a second plug pattern PP2 extending in the gate stack structure GST in a direction (Z) perpendicular to the substrate SUB.

[0051] A gate stack structure (GST) may include alternately stacked conductive layers (CP) and interlayer insulating layers (ILD). The conductive layers (CP) may be gate electrodes for select transistors, memory cells, etc. The conductive layers (CP) may be select lines connected to select transistors and word lines connected to memory cells. The conductive layers (CP) may contain conductive materials such as polysilicon, tungsten, or metals. The interlayer insulating layers (ILD) are used to insulate the stacked conductive layers (CP) from each other. The interlayer insulating layers (ILD) may contain insulating materials such as oxides or nitrides.

[0052] The first plug pattern PP1 and the second plug pattern PP2 can extend in a direction perpendicular to the substrate SUB by penetrating the gate stack structure GST. That is, the first plug pattern PP1 and the second plug pattern PP2 can extend in the stacking direction of the gate stack structure GST. The stacking direction of the gate stack structure GST can be defined as the stacking direction of the conductive layer CP and the interlayer insulating layer ILD that are alternately stacked and included in the gate stack structure GST. The first plug pattern PP1 and the second plug pattern PP2 can be arranged in a hole through the gate stack structure GST.

[0053] The first plug pattern PP1 and the second plug pattern PP2 may have a symmetrical structure while being opposite each other in a second horizontal direction (Y) B-B' of a hole extending in the vertical direction (Z) through the gate stack structure GST. For example, the first plug pattern PP1 and the second plug pattern PP2 may have mirror symmetry across the A-A' section line. The second horizontal direction B-B' may be horizontal to the substrate SUB. The central portion of the hole may be filled with a core insulating layer CO, and the core insulating layer CO may extend in the vertical direction (Z) to physically and electrically separate the first channel layer CHL1 of the first plug pattern PP1 from the second channel layer CHL2 of the second plug pattern PP2. The core insulating layer CO may contain an insulating material such as an oxide.

[0054] The first plug pattern PP1 may include a barrier insulating layer BI formed along a first sidewall SW1 of the via, a charge trapping layer CTL contacting the inner wall of the barrier insulating layer BI, a tunnel insulating layer TIL contacting the inner wall of the charge trapping layer CTL, and a first channel layer CHL1 contacting the inner wall of the tunnel insulating layer TIL. The first plug pattern PP1 may also include a first sacrificial layer SAC1 contacting the inner wall of the first channel layer CHL1. The sidewall of the via may refer to the inner sidewall of the gate stack structure GST exposed through the via through which the gate stack structure GST is formed.

[0055] The first sacrificial layer SAC1 can contact the sidewall of the core insulating layer CO, the first channel layer CHL1 can contact the outer wall of the first sacrificial layer SAC1, the tunnel insulating layer TIL can contact the outer wall of the first channel layer CHL1, the charge trapping layer CTL can contact the outer wall of the tunnel insulating layer TIL, and the blocking insulating layer BI can contact the outer wall of the charge trapping layer CTL.

[0056] The second plug pattern PP2 may include a barrier insulating layer BI formed along a second sidewall SW2 opposite to the first sidewall SW1 of the hole, a charge trapping layer CTL contacting the inner wall of the barrier insulating layer BI, a tunnel insulating layer TIL contacting the inner wall of the charge trapping layer CTL, and a second channel layer CHL2 contacting the inner wall of the tunnel insulating layer TIL. The second plug pattern PP2 may also include a second sacrificial layer SAC2 contacting the inner wall of the second channel layer CHL2.

[0057] The second sacrificial layer SAC2 can contact the sidewall of the core insulating layer CO, the second channel layer CHL2 can contact the outer wall of the second sacrificial layer SAC2, the tunnel insulating layer TIL can contact the outer wall of the second channel layer CHL2, the charge trapping layer CTL can contact the outer wall of the tunnel insulating layer TIL, and the blocking insulating layer BI can contact the outer wall of the charge trapping layer CTL.

[0058] The first channel layer CHL1 and the second channel layer CHL2 can be regions forming channels such as selection transistors or memory cells. Each of the first channel layer CHL1 and the second channel layer CHL2 may include a semiconductor material such as silicon or germanium, or may include nanostructures such as nanodots, nanotubes, or graphene. The tunnel insulating layer TIL can be a layer that tunnels through the charge via FN tunneling, and it may contain an insulating material such as an oxide or nitride. The charge trapping layer CTL may include a charge trapping material, a nitride, a variable resistance material, a nanostructure, or a combination thereof. The barrier insulating layer BI may include a high-dielectric layer.

[0059] The barrier insulation layer BI, charge trapping layer CTL, and tunnel insulation layer TIL of the first plug pattern PP1 can be physically connected to the barrier insulation layer BI, charge trapping layer CTL, and tunnel insulation layer TIL of the second plug pattern PP2, respectively.

[0060] For example, the barrier insulating layer BI of the first plug pattern PP1 and the barrier insulating layer BI of the second plug pattern PP2 can be formed along the first sidewall SW1 and the second sidewall SW2 of the hole, respectively, and can be connected to each other. Furthermore, the charge trapping layer CTL of the first plug pattern PP1 and the charge trapping layer CTL of the second plug pattern PP2 can be formed along the inner wall of the corresponding barrier insulating layer BI, and they can be connected to each other. Additionally, the tunnel insulating layer TIL of the first plug pattern PP1 and the tunnel insulating layer TIL of the second plug pattern PP2 can be formed along the inner wall of the corresponding charge trapping layer CTL, and they can be connected to each other.

[0061] The first channel layer CHL1 of the first plug pattern PP1 and the second channel layer CHL2 of the second plug pattern PP2 can be separated from each other by the core insulation layer CO, and the first sacrificial layer SAC1 of the first plug pattern PP1 and the second sacrificial layer SAC2 of the second plug pattern PP2 can be separated from each other by the core insulation layer CO.

[0062] Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B and Figure 11C These are plan views and cross-sectional views used to describe a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0063] Reference Figure 5A , Figure 5B and Figure 5C A multilayer structure ST is formed on a substrate SUB. The multilayer structure ST may include alternating layers of a first material layer 11 and a second material layer 12. The first material layer 11 and the second material layer 12 may be stacked in a direction perpendicular to the substrate SUB. The first material layer 11 and the second material layer 12 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0064] The first material layer 11 may contain a material with high etch selectivity relative to the second material layer 12. In an example, the first material layer 11 may contain an insulating material such as an oxide, and the second material layer 12 may contain a sacrificial material such as a nitride. In another example, the first material layer 11 may contain an insulating material such as an oxide, and the second material layer 12 may contain a conductive material such as polysilicon or tungsten.

[0065] Additionally, a hard mask pattern (not shown) can be formed on the stacked structure ST, and an aperture H passing through at least a portion of the stacked structure ST can be formed by performing an etching process using the hard mask pattern. The aperture H can extend partially into the substrate SUB.

[0066] The hole H can be formed such that the width X2 of the hole H in the first horizontal direction A-A' is smaller than the width X1 of the hole H in the second horizontal direction B-B'. For example, the cross-section of the hole H in the XY plane can have an elliptical shape.

[0067] Reference Figure 6A , Figure 6B and Figure 6C A barrier insulating layer 13, a charge trapping layer 14, a tunnel insulating layer 15, and a preliminary channel layer 16 are sequentially formed along the sidewall of the aperture H. For example, the barrier insulating layer 13 is formed along the sidewall of the aperture H. The barrier insulating layer 13 may be a high-dielectric layer. Subsequently, the charge trapping layer 14 may be formed along the inner wall of the barrier insulating layer 13. The charge trapping layer 14 may include a charge trapping material, a nitride, a variable resistance material, a nanostructure, or a combination thereof. Subsequently, the tunnel insulating layer 15 may be formed along the inner wall of the charge trapping layer 14. The tunnel insulating layer 15 may be a layer through which charge tunnels, such as FN tunneling, and it may contain an insulating material such as an oxide or a nitride. Subsequently, the preliminary channel layer 16 may be formed along the inner wall of the tunnel insulating layer 15. The initial channel layer 16 may include semiconductor materials such as silicon or germanium, oxide semiconductor materials such as ZnO, In2O3, InZnO, ZnSnO, InGaZnO, or ZnGaSnO, two-dimensional (2D) semiconductor materials such as MoS2, MoSe2, WS2, WSe2, or SnS2, or nanostructures such as nanodots, nanotubes, or graphene. The initial channel layer 16 may be formed to partially fill the central region of the hole.

[0068] Reference Figure 7 A heat treatment (annealing) process can be performed on the preliminary channel layer 16, and an oxide layer 17 can be formed by oxidizing the exposed inner wall of the preliminary channel layer 16. Therefore, the thickness of the preliminary channel layer 16 can be reduced.

[0069] Reference Figure 8 The oxide layer can be removed by performing a stripping process (e.g., Figure 7 17), and the sacrificial layer 18 can be formed by oxidizing the exposed inner wall of the preliminary channel layer 16. When the sacrificial layer 18 is formed by deposition, the portion of the sacrificial layer 18 corresponding to the uppermost part of the hole can be formed relatively thick, and the portion of the sacrificial layer 18 corresponding to the bottom surface of the hole can be formed relatively thin, thus resulting in an uneven distribution of the thickness of the sacrificial layer 18. When the sacrificial layer 18 is formed by oxidation, the thickness of the sacrificial layer 18 corresponding to the uppermost and bottom surfaces of the hole can be formed uniformly. Furthermore, for some embodiments, the sacrificial layer formed by oxidation can have fewer dangling bonds at the interface with the preliminary channel layer 16 compared to the sacrificial layer formed by deposition, thus exhibiting improved performance in terms of current flow and leakage current. In addition, the sacrificial layer 18 formed by oxidation can have higher etch selectivity than the preliminary channel layer 16 compared to the sacrificial layer formed by deposition.

[0070] Reference Figure 9 A barrier layer 19 is formed along the inner wall of the sacrificial layer 18. The barrier layer 19 may include a polysilicon layer. The thickness d1 of the barrier layer 19 formed on the sidewall of the hole H in the first horizontal direction A-A' and the thickness d2 of the barrier layer 19 formed on the sidewall of the hole H in the second horizontal direction B-B' may be different from each other. For example, the thickness d1 of the barrier layer 19 formed on the sidewall of the hole H in the first horizontal direction A-A' may be smaller than the thickness d2 of the barrier layer 19 formed on the sidewall of the hole H in the second horizontal direction B-B'.

[0071] Reference Figure 10A , Figure 10B and Figure 10C The barrier layer (e.g., can be removed by performing an etching process) Figure 9 (19) Etching to a specific thickness, which can then be partially removed. The etching process can be performed using an isotropic etching process. For example, a barrier layer (e.g., Figure 9 Part of 19), such that the sidewalls of the sacrificial layer 18 in the first horizontal direction A-A' are exposed. During the etching process, a barrier layer (e.g.,) is formed on the sidewalls of the sacrificial layer 18. Figure 9 19) The thickness in the first horizontal direction A-A' is less than that of the barrier layer formed on the sidewall of the sacrificial layer 18 (e.g., Figure 9The thickness of 19) in the second horizontal direction B-B' is such that even the barrier layer (e.g., Figure 9 19) is etched to expose the sidewalls of the sacrificial layer 18 in the first horizontal direction A-A', the barrier layer (e.g., Figure 9 19) can also be retained on the sidewalls of the sacrificial layer 18 in the second horizontal direction B-B'. The remaining barrier layers can be defined as barrier patterns 19A and 19B. Furthermore, during the isotropic etching process, the etching rate in the first horizontal direction A-A' can be higher than the etching rate in the second horizontal direction B-B' due to the difference in surface area and surface angle exposed to the etchant. Therefore, barrier patterns 19A and 19B can be formed on the opposite sidewalls of the aperture H in the second horizontal direction B-B'. The horizontal cross-section of each of the barrier patterns 19A and 19B can have a crescent shape.

[0072] Reference Figure 11A , Figure 11B and Figure 11C Partial etching can be performed by using a barrier pattern (e.g., Figure 10A , Figure 10B and Figure 10C The sacrificial layers exposed by the etching process of 19A and 19B as masks, thus exposing the initial channel layer (e.g., ) in the first horizontal direction A-A'. Figure 10A , Figure 10B and Figure 10C (16). Therefore, the sacrificial layers can be patterned as a first sacrificial layer 18A and a second sacrificial layer 18B separated from each other. Thereafter, the initial channel layer exposed by performing an etching process using the first sacrificial layer 18A and the second sacrificial layer 18B as a mask can be etched (e.g., Figure 10A , Figure 10B and Figure 10C Therefore, the tunnel insulation layer 15 is exposed in the first horizontal direction A-A'. Thus, the initial trench layer can be patterned as a first trench layer 16A and a second trench layer 16B separated from each other. Thereafter, the barrier pattern can be removed.

[0073] Subsequently, a core insulating layer 20 can be formed to fill the holes (e.g., Figure 10B and Figure 10C The central region of H). The core insulation layer 20 may contain an insulating material such as oxides.

[0074] Subsequently, an etching process can be performed to expose the stacked structure (e.g., Figure 10B and Figure 10C The sidewalls of the ST) and the exposed second material layer can be removed (e.g., Figure 10B and Figure 10C(12). Subsequently, a third material layer 21 may be formed in the space where the second material layer has been removed. The third material layer 21 may contain a conductive material such as polysilicon, tungsten, or metal. Thus, a gate stack structure GST including the first material layer 11 and the third material layer 21 can be formed.

[0075] As described above, according to embodiments of the present disclosure, the preliminary channel layer 16 and the sacrificial layer 18 can be formed by a deposition-annealing-oxidation (DAO) scheme including a deposition process, an annealing process and an oxidation process. Therefore, the layer quality of the preliminary channel layer 16 and the sacrificial layer 18 can be improved, resulting in an increase in the channel current of the memory cell string and a decrease in the leakage current.

[0076] Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B and Figure 18C These are plan views and cross-sectional views used to describe a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0077] Reference Figure 12A , Figure 12B and Figure 12C A multilayer structure ST is formed on a substrate SUB. The multilayer structure ST may include alternating layers of a first material layer 31 and a second material layer 32. The first material layer 31 and the second material layer 32 may be stacked in a direction perpendicular to the substrate SUB. The first material layer 31 and the second material layer 32 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0078] The first material layer 31 may contain a material with high etch selectivity relative to the second material layer 32. In an example, the first material layer 31 may contain an insulating material such as an oxide, and the second material layer 32 may contain a sacrificial material such as a nitride. In another example, the first material layer 31 may contain an insulating material such as an oxide, and the second material layer 32 may contain a conductive material such as polysilicon or tungsten.

[0079] Additionally, a hard mask pattern (not shown) can be formed on the stacked structure ST, and an aperture H passing through at least a portion of the stacked structure ST can be formed by performing an etching process using the hard mask pattern. The aperture H can extend partially into the substrate SUB.

[0080] The hole H can be formed such that the width X2 of the hole H in the first horizontal direction A-A' is smaller than the width X1 of the hole H in the second horizontal direction B-B'. For example, the cross-section of the hole H in the XY plane can have an elliptical shape.

[0081] Reference Figure 13A , Figure 13B and Figure 13C A barrier insulating layer 33, a charge trapping layer 34, a tunnel insulating layer 35, and a preliminary channel layer 36 are sequentially formed along the sidewall of the aperture H. For example, the barrier insulating layer 33 is formed along the sidewall of the aperture H. The barrier insulating layer 33 may be a high-dielectric layer. Subsequently, the charge trapping layer 34 may be formed along the inner wall of the barrier insulating layer 33. The charge trapping layer 34 may include a charge trapping material, a nitride, a variable resistance material, a nanostructure, or a combination thereof. Subsequently, the tunnel insulating layer 35 may be formed along the inner wall of the charge trapping layer 34. The tunnel insulating layer 35 may be a layer through which charge tunnels, such as FN tunneling, and it may contain an insulating material such as an oxide or a nitride. Subsequently, the preliminary channel layer 36 may be formed along the inner wall of the tunnel insulating layer 35. The preliminary channel layer 36 may include semiconductor materials such as silicon or germanium, oxide semiconductor materials such as ZnO, In2O3, InZnO, ZnSnO, InGaZnO, or ZnGaSnO, two-dimensional (2D) semiconductor materials such as MoS2, MoSe2, WS2, WSe2, or SnS2, or nanostructures such as nanodots, nanotubes, or graphene. The preliminary channel layer 36 may be formed to partially fill the central region of the hole. The preliminary channel layer 36 may be formed to have a first thickness d11. Subsequently, an annealing process may be performed on the preliminary channel layer 36.

[0082] Reference Figure 14 An etching process can be performed to reduce the thickness of the initial channel layer 36. Therefore, the initial channel layer 36 can be etched down to the second thickness d12.

[0083] Reference Figure 15The sacrificial layer 37 is formed by oxidizing the exposed inner wall of the preliminary channel layer 36. When the sacrificial layer 37 is formed by deposition, the portion of the sacrificial layer 37 corresponding to the uppermost part of the hole can be relatively thick, and the portion of the sacrificial layer 37 corresponding to the bottom surface of the hole can be relatively thin, resulting in an uneven thickness distribution of the sacrificial layer 18. When the sacrificial layer 37 is formed by oxidation, the thickness of the sacrificial layer 37 corresponding to the uppermost and bottom surfaces of the hole can be uniformly formed. Furthermore, in some embodiments, compared with the sacrificial layer formed by deposition, the sacrificial layer formed by oxidation can have fewer dangling bonds at the interface with the preliminary channel layer 36, thus exhibiting improved performance in terms of current flow and leakage current. In addition, the sacrificial layer 37 formed by oxidation can have higher etch selectivity than the preliminary channel layer 36 compared with the sacrificial layer formed by deposition.

[0084] Reference Figure 16 A barrier layer 38 is formed along the inner wall of the sacrificial layer 37. The barrier layer 38 may include a polysilicon layer. The thickness d13 of the barrier layer 38 formed on the sidewall of the hole H in the first horizontal direction A-A' and the thickness d14 of the barrier layer 38 formed on the sidewall of the hole H in the second horizontal direction B-B' may be different from each other. For example, the thickness d13 of the barrier layer 38 formed on the sidewall of the hole H in the first horizontal direction A-A' may be smaller than the thickness d14 of the barrier layer 38 formed on the sidewall of the hole H in the second horizontal direction B-B'.

[0085] Reference Figure 17A , Figure 17B and Figure 17C The barrier layer (e.g., can be removed by performing an etching process) Figure 16 (38) Etching to a specific thickness, which can then be partially removed. The etching process can be performed using an isotropic etching process. For example, a barrier layer (e.g., Figure 16 Part of 38), such that the sidewalls of the sacrificial layer 37 in the first horizontal direction A-A' are exposed. During the etching process, a barrier layer (e.g.,) is formed on the sidewalls of the sacrificial layer 37. Figure 16 38) The thickness in the first horizontal direction A-A' is less than that of the barrier layer formed on the sidewall of the sacrificial layer 37 (e.g., Figure 16 The thickness of the 38) in the second horizontal direction B-B' is such that even the barrier layer (e.g., Figure 16 38) is etched to expose the sidewalls of the sacrificial layer 37 in the first horizontal direction A-A', the barrier layer (e.g., Figure 1638) can also be retained on the sidewalls of the sacrificial layer 37 in the second horizontal direction B-B'. The remaining barrier layers can be defined as barrier patterns 38A and 38B. Furthermore, during the isotropic etching process, the etching rate in the first horizontal direction A-A' can be higher than the etching rate in the second horizontal direction B-B' due to the difference in surface area and surface angle exposed to the etchant. Therefore, barrier patterns 38A and 38B can be formed on the opposite sidewalls of the hole H in the second horizontal direction B-B'. The horizontal cross-section of each of the barrier patterns 38A and 38B can have a crescent shape.

[0086] Reference Figure 18A , Figure 18B and Figure 18C Partial etching can be performed by using a barrier pattern (e.g., Figure 17A , Figure 17B and Figure 17C The 38A and 38B layers are used as a mask in the etching process to expose the sacrificial layer, thus exposing the initial channel layer (e.g., ) in the first horizontal direction A-A'. Figure 17A , Figure 17B and Figure 17C (36). Therefore, the sacrificial layers can be patterned as a first sacrificial layer 37A and a second sacrificial layer 37B separated from each other. Thereafter, the preliminary channel layer exposed by performing an etching process using the first sacrificial layer 37A and the second sacrificial layer 37B as a mask can be etched (e.g., Figure 17A , Figure 17B and Figure 17C Therefore, the tunnel insulation layer 35 is exposed in the first horizontal direction A-A'. Thus, the initial trench layer can be patterned as a first trench layer 36A and a second trench layer 36B separated from each other. Subsequently, the barrier pattern can be removed.

[0087] Subsequently, a core insulating layer 39 can be formed to fill the holes (e.g., Figure 17A , Figure 17B and Figure 17C The central region of H). The core insulation layer 39 may contain an insulating material such as oxides.

[0088] Subsequently, an etching process can be performed to expose the stacked structure (e.g., Figure 17A , Figure 17B and Figure 17C The sidewalls of the ST) and the exposed second material layer can be removed (e.g., Figure 17A , Figure 17B and Figure 17C (32). Subsequently, a third material layer 40 may be formed in the space where the second material layer has been removed. The third material layer 40 may contain a conductive material such as polysilicon, tungsten, or metal. Thus, a gate stack structure GST including the first material layer 31 and the third material layer 40 can be formed.

[0089] As described above, according to embodiments of the present disclosure, the preliminary channel layer 36 and the sacrificial layer 37 can be formed by a DAO scheme including a deposition process, an annealing process and an oxidation process. Therefore, the layer quality of the preliminary channel layer 36 and the sacrificial layer 37 can be improved, resulting in an increase in the channel current of the memory cell string and a decrease in leakage current.

[0090] Figure 19A , Figure 19B and Figure 19C These are plan views and cross-sectional views used to describe a semiconductor memory device according to embodiments of the present disclosure.

[0091] Figure 19A , Figure 19B and Figure 19C It is shown Figure 1 A plan view and a cross-sectional view of a portion of the memory cell array 110.

[0092] Reference Figure 19A , Figure 19B and Figure 19C The semiconductor memory device may include a gate stack structure GST and a first plug pattern PP1 and a second plug pattern PP2 extending in the gate stack structure GST in a direction (Z) perpendicular to the substrate SUB.

[0093] A gate stack structure (GST) may include alternately stacked conductive layers (CP) and interlayer insulating layers (ILD). The conductive layers (CP) may be gate electrodes for select transistors, memory cells, etc. The conductive layers (CP) may be select lines connected to select transistors and word lines connected to memory cells. The conductive layers (CP) may contain conductive materials such as polysilicon, tungsten, or metals. The interlayer insulating layers (ILD) are used to insulate the stacked conductive layers (CP) from each other. The interlayer insulating layers (ILD) may contain insulating materials such as oxides or nitrides.

[0094] The interlayer insulating layer (ILD) can extend further than the conductive layer (CP) in the direction of the first plug pattern (PP1) and the second plug pattern (PP2).

[0095] The first plug pattern PP1 and the second plug pattern PP2 can extend in a direction perpendicular to the substrate SUB by penetrating the gate stack structure GST. That is, the first plug pattern PP1 and the second plug pattern PP2 can extend in the stacking direction of the gate stack structure GST. The stacking direction of the gate stack structure GST can be defined as the stacking direction of the conductive layer CP and the interlayer insulating layer ILD that are alternately stacked and included in the gate stack structure GST. Both the first plug pattern PP1 and the second plug pattern PP2 can be arranged in a hole through the gate stack structure GST.

[0096] The first plug pattern PP1 and the second plug pattern PP2 may have a symmetrical structure while being opposite each other in a second horizontal direction (Y) B-B' of a hole extending in the vertical direction (Z) through the gate stack structure GST. For example, the first plug pattern PP1 and the second plug pattern PP2 may have mirror symmetry across the A-A' section line. The second horizontal direction B-B' may be horizontal to the substrate SUB. The central portion of the hole may be filled with a core insulating layer CO, and the core insulating layer CO may extend in the vertical direction (Z) to physically and electrically separate the first channel layer CHL1 of the first plug pattern PP1 from the second channel layer CHL2 of the second plug pattern PP2. The core insulating layer CO may contain an insulating material such as an oxide.

[0097] The first plug pattern PP1 may include a barrier insulating layer BI, a charge trapping layer CTL, a tunnel insulating layer TIL, and a first channel layer CHL1, sequentially arranged between a conductive layer CP and a core insulating layer CO. The first plug pattern PP1 may also include a first sacrificial layer SAC1. For example, the barrier insulating layer BI may be formed along a first sidewall SW1 of the conductive layer CP, and the charge trapping layer CTL may be formed along an inner wall of the barrier insulating layer BI. The barrier insulating layer BI and the charge trapping layer CTL corresponding to a memory cell may be physically separated from the barrier insulating layer BI and the charge trapping layer CTL of a memory cell adjacent to this memory cell in the vertical direction (Z) by an interlayer insulating layer ILD. The tunnel insulating layer TIL may be formed along the inner wall of the charge trapping layer CTL and may extend vertically along the sidewall of the interlayer insulating layer ILD. The first channel layer CHL1 may extend vertically (Z) along the inner wall of the tunnel insulating layer TIL. The first sacrificial layer SAC1 may extend vertically along the inner wall of the first channel layer CHL1.

[0098] The second plug pattern PP2 may include a barrier insulating layer BI, a charge trapping layer CTL, a tunnel insulating layer TIL, and a second channel layer CHL2, sequentially arranged between a conductive layer CP and a core insulating layer CO. The second plug pattern PP2 may also include a second sacrificial layer SAC2. For example, the barrier insulating layer BI may be formed along the second sidewall SW2 of the conductive layer CP, and the charge trapping layer CTL may be formed along the inner wall of the barrier insulating layer BI. The barrier insulating layer BI and the charge trapping layer CTL corresponding to a memory cell can be physically separated from the barrier insulating layer BI and the charge trapping layer CTL of the memory cell adjacent to this memory cell in the vertical direction (Z) by an interlayer insulating layer ILD. The tunnel insulating layer TIL may be formed along the inner wall of the charge trapping layer CTL and may extend vertically along the sidewall of the interlayer insulating layer ILD. The second channel layer CHL2 may extend vertically (Z) along the inner wall of the tunnel insulating layer TIL. The second sacrificial layer SAC2 may extend vertically along the inner wall of the second channel layer CHL2.

[0099] The first channel layer CHL1 and the second channel layer CHL2 can be regions forming channels such as selection transistors or memory cells. Each of the first channel layer CHL1 and the second channel layer CHL2 may include a semiconductor material such as silicon or germanium, or may include nanostructures such as nanodots, nanotubes, or graphene. The tunnel insulating layer TIL can be a layer that tunnels through the charge via FN tunneling, and it may contain an insulating material such as an oxide or nitride. The charge trapping layer CTL may include a charge trapping material, a nitride, a variable resistance material, a nanostructure, or a combination thereof. The barrier insulating layer BI may include a high-dielectric layer.

[0100] The barrier insulation layer BI, charge trapping layer CTL, and tunnel insulation layer TIL of the first plug pattern PP1 can be physically connected to the barrier insulation layer BI, charge trapping layer CTL, and tunnel insulation layer TIL of the second plug pattern PP2, respectively.

[0101] For example, the barrier insulating layer BI of the first plug pattern PP1 and the barrier insulating layer BI of the second plug pattern PP2 can be formed along the first sidewall SW1 and the second sidewall SW2 of the conductive layer CP, respectively, and they can be connected to each other. Furthermore, the charge trapping layer CTL of the first plug pattern PP1 and the charge trapping layer CTL of the second plug pattern PP2 can be formed along the inner wall of the corresponding barrier insulating layer BI, and they can be connected to each other. Additionally, the tunnel insulating layer TIL of the first plug pattern PP1 and the tunnel insulating layer TIL of the second plug pattern PP2 can be formed along the inner wall of the corresponding charge trapping layer CTL, and they can be connected to each other.

[0102] The first channel layer CHL1 of the first plug pattern PP1 and the second channel layer CHL2 of the second plug pattern PP2 can be separated from each other by the core insulation layer CO, and the first sacrificial layer SAC1 of the first plug pattern PP1 and the second sacrificial layer SAC2 of the second plug pattern PP2 can be separated from each other by the core insulation layer CO.

[0103] Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22 , Figure 23 , Figure 24 , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B and Figure 26C These are plan views and cross-sectional views used to describe a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0104] Reference Figure 20A , Figure 20B and Figure 20C A multilayer structure ST is formed on a substrate SUB. The multilayer structure ST may include alternating layers of a first material layer 41 and a second material layer 42. The first material layer 41 and the second material layer 42 may be stacked in a direction perpendicular to the substrate SUB. The first material layer 41 and the second material layer 42 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0105] The first material layer 41 may comprise a material with high etch selectivity relative to the second material layer 42. In one example, the first material layer 41 may comprise an insulating material such as an oxide, and the second material layer 42 may comprise a sacrificial material such as a nitride. In another example, the first material layer 41 may comprise an insulating material such as an oxide, and the second material layer 42 may comprise a conductive material such as polysilicon or tungsten.

[0106] Additionally, a hard mask pattern (not shown) can be formed on the stacked structure ST, and an aperture H passing through at least a portion of the stacked structure ST can be formed by performing an etching process using the hard mask pattern. The aperture H can extend partially into the substrate SUB.

[0107] The hole H can be formed such that the width X12 of the hole H in the first horizontal direction A-A' is smaller than the width X11 of the hole H in the second horizontal direction B-B'. For example, the cross-section of the hole H in the XY plane can have an elliptical shape.

[0108] Subsequently, the recessed region R can be formed by etching the sidewalls of the second material layer 42 exposed through the hole H to the recessed depth. For example, the sidewalls of the second material layer 42 can be etched to the recessed depth such that the first material layer 41 protrudes beyond the second material layer 42 in the direction of the hole H. Therefore, the sidewalls of the hole H can be formed as a structure in which irregular portions (concave / convex portions) are arranged sequentially in a direction perpendicular to the substrate SUB.

[0109] Reference Figure 21A , Figure 21B and Figure 21C In the various recessed areas of hole H (e.g., Figure 20B and Figure 20C A barrier insulating layer 43 and a charge trapping layer 44 are formed in the R).

[0110] For example, the barrier insulating layer 43 and the charge trapping layer 44 are formed sequentially along the sidewall of the hole H. Alternatively, by performing an etching process to expose the sidewall of the first material layer 41, the barrier insulating layer 43 and the charge trapping layer 44 can be retained only in the recessed area (e.g., Figure 20B and Figure 20C In R).

[0111] Subsequently, a tunnel insulating layer 45 and a preliminary channel layer 46 are sequentially formed along the inner wall of the charge trapping layer 44 and the sidewall of the first material layer 41. The charge trapping layer 44 may include a charge trapping material, a nitride, a variable resistance material, a nanostructure, or a combination thereof. The tunnel insulating layer 45 may then be formed along the inner wall of the charge trapping layer 44. The tunnel insulating layer 45 may be a layer through which charge tunnels, such as FN tunneling, and may contain an insulating material such as an oxide or a nitride. The preliminary channel layer 46 may then be formed along the inner wall of the tunnel insulating layer 45. The preliminary channel layer 46 may include a semiconductor material such as silicon or germanium, an oxide semiconductor material such as ZnO, In2O3, InZnO, ZnSnO, InGaZnO, or ZnGaSnO, a two-dimensional (2D) semiconductor material such as MoS2, MoSe2, WS2, WSe2, or SnS2, or a nanostructure such as nanodots, nanotubes, or graphene. The initial channel layer 46 can be formed as a central region that does not completely fill the hole.

[0112] Reference Figure 22 A heat treatment (annealing) process can be performed on the preliminary channel layer 46, and an oxide layer 47 can be formed by oxidizing the exposed inner wall of the preliminary channel layer 46. Therefore, the thickness of the preliminary channel layer 46 can be reduced.

[0113] Reference Figure 23 The oxide layer can be removed by performing a stripping process (e.g., Figure 22 The sacrificial layer 48 can be formed by oxidizing the exposed inner wall of the preliminary channel layer 46 (47). When the sacrificial layer 48 is formed by deposition, the portion of the sacrificial layer 48 corresponding to the uppermost part of the hole can be formed relatively thick, and the portion of the sacrificial layer 48 corresponding to the bottom surface of the hole can be formed relatively thin, thus resulting in an uneven distribution of the thickness of the sacrificial layer 18. When the sacrificial layer 48 is formed by oxidation, the thickness of the sacrificial layer 48 corresponding to the uppermost and bottom surfaces of the hole can be formed uniformly. Furthermore, in some embodiments, compared with the sacrificial layer formed by deposition, the sacrificial layer formed by oxidation can have fewer dangling bonds at the interface with the preliminary channel layer 46, thus exhibiting improved performance in terms of current flow and leakage current. In addition, the sacrificial layer 48 formed by oxidation can have higher etch selectivity relative to the preliminary channel layer 46 compared with the sacrificial layer formed by deposition.

[0114] Reference Figure 24A barrier layer 49 is formed along the inner wall of the sacrificial layer 48. The barrier layer 49 may include a polysilicon layer. The thickness d1 of the barrier layer 49 formed on the sidewall of the hole H in the first horizontal direction A-A' and the thickness d2 of the barrier layer 49 formed on the sidewall of the hole H in the second horizontal direction B-B' may be different from each other. For example, the thickness d1 of the barrier layer 49 formed on the sidewall of the hole H in the first horizontal direction A-A' may be smaller than the thickness d2 of the barrier layer 49 formed on the sidewall of the hole H in the second horizontal direction B-B'.

[0115] Reference Figure 25A , Figure 25B and Figure 25C The barrier layer (e.g., can be removed by performing an etching process) Figure 24 (49) Etching to a specific thickness, which can then be partially removed. The etching process can be performed using an isotropic etching process. For example, a barrier layer (e.g., Figure 24 Part of 49), such that the sidewalls of the sacrificial layer 48 in the first horizontal direction A-A' are exposed. During the etching process, a barrier layer (e.g., ...) is formed on the sidewalls of the sacrificial layer 48. Figure 24 49) The thickness in the first horizontal direction A-A' is less than that of the barrier layer formed on the sidewall of the sacrificial layer 48 (e.g., Figure 24 The thickness of the 49) in the second horizontal direction B-B' is such that even the barrier layer (e.g., Figure 24 49) is etched to expose the sidewalls of the sacrificial layer 48 in the first horizontal direction A-A', the barrier layer (e.g., Figure 24 49) can also be retained on the sidewalls of the sacrificial layer 37 in the second horizontal direction B-B'. The remaining barrier layers can be defined as barrier patterns 49A and 49B. Furthermore, during the isotropic etching process, the etching rate in the first horizontal direction A-A' can be higher than the etching rate in the second horizontal direction B-B' due to the difference in surface area and surface angle exposed to the etchant. Therefore, barrier patterns 49A and 49B can be formed on the opposite sidewalls of the aperture H in the second horizontal direction B-B'. The horizontal cross-section of each of the barrier patterns 49A and 49B can have a crescent shape.

[0116] Reference Figure 26A , Figure 26B and Figure 26C Partial etching can be performed by using a barrier pattern (e.g., Figure 25A , Figure 25B and Figure 25C The etch process using 49A and 49B as masks exposes sacrificial layers, thus exposing the initial channel layer (e.g., ) in the first horizontal direction A-A'. Figure 25A , Figure 25B and Figure 25C46). Therefore, the sacrificial layers can be patterned as a first sacrificial layer 48A and a second sacrificial layer 48B separated from each other. Thereafter, the initial channel layer exposed by performing an etching process using the first sacrificial layer 48A and the second sacrificial layer 48B as masks (e.g., Figure 25A , Figure 25B and Figure 25C Therefore, the tunnel insulation layer 45 is exposed in the first horizontal direction A-A'. Thus, the initial trench layer can be patterned as a first trench layer 46A and a second trench layer 46B separated from each other. Thereafter, the barrier pattern can be removed.

[0117] Subsequently, a core insulating layer 50 can be formed to fill the holes (e.g., Figure 25B and Figure 25C The central region of H). The core insulation layer 50 may contain an insulating material such as oxides.

[0118] Subsequently, an etching process can be performed to expose the stacked structure (e.g., Figure 25B and Figure 25C The sidewalls of the ST) and the exposed second material layer can be removed (e.g., Figure 25B and Figure 25C (42). Subsequently, a third material layer 51 may be formed in the space where the second material layer has been removed. The third material layer 51 may contain a conductive material such as polysilicon, tungsten, or metal. Thus, a gate stack structure GST including the first material layer 41 and the third material layer 51 can be formed.

[0119] As described above, according to embodiments of the present disclosure, the preliminary channel layer 46 and the sacrificial layer 48 can be formed by a DAO scheme including a deposition process, an annealing process and an oxidation process. Therefore, the layer quality of the preliminary channel layer 46 and the sacrificial layer 48 can be improved, resulting in an increase in the channel current of the memory cell string and a decrease in leakage current.

[0120] Figure 27A , Figure 27B , Figure 27C , Figure 28A , Figure 28B , Figure 28C , Figure 29 , Figure 30 , Figure 31 , Figure 32A , Figure 32B , Figure 32C , Figure 33A , Figure 33B and Figure 33C These are plan views and cross-sectional views used to describe a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0121] Reference Figure 27A , Figure 27B and Figure 27C A multilayer structure ST is formed on a substrate SUB. The multilayer structure ST may include alternating layers of a first material layer 61 and a second material layer 62. The first material layer 61 and the second material layer 62 may be stacked in a direction perpendicular to the substrate SUB. The first material layer 61 and the second material layer 62 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0122] The first material layer 61 may contain a material with high etch selectivity relative to the second material layer 62. In an example, the first material layer 61 may contain an insulating material such as an oxide, and the second material layer 62 may contain a sacrificial material such as a nitride. In another example, the first material layer 61 may contain an insulating material such as an oxide, and the second material layer 62 may contain a conductive material such as polysilicon or tungsten.

[0123] Additionally, a hard mask pattern (not shown) can be formed on the stacked structure ST, and an aperture H passing through at least a portion of the stacked structure ST can be formed by performing an etching process using the hard mask pattern. The aperture H can extend partially into the substrate SUB.

[0124] The hole H can be formed such that the width X12 of the hole H in the first horizontal direction A-A' is smaller than the width X11 of the hole H in the second horizontal direction B-B'. For example, the cross-section of the hole H in the XY plane can have an elliptical shape.

[0125] Subsequently, the recessed region R can be formed by etching the sidewalls of the second material layer 62 exposed through the hole H to the recessed depth. For example, the sidewalls of the second material layer 62 can be etched to the recessed depth such that the first material layer 61 protrudes beyond the second material layer 62 in the direction of the hole H. Therefore, the sidewalls of the hole H can be formed as a structure in which irregular portions (concave / convex portions) are arranged sequentially in a direction perpendicular to the substrate SUB.

[0126] Reference Figure 28A , Figure 28B and Figure 28C In the various recessed areas of hole H (e.g., Figure 27B and Figure 27C A barrier insulating layer 63 and a charge trapping layer 64 are formed in the R).

[0127] For example, a barrier insulating layer 63 and a charge trapping layer 64 are sequentially formed along the sidewall of the hole H. Alternatively, by performing an etching process to expose the sidewalls of the first material layer 61, the barrier insulating layer 63 and the charge trapping layer 64 can be retained only in the recessed area (e.g., Figure 27B and Figure 27C In R).

[0128] Subsequently, a tunnel insulating layer 65 and a preliminary channel layer 66 are sequentially formed along the inner wall of the charge trapping layer 64 and the sidewall of the first material layer 61. The charge trapping layer 64 may include a charge trapping material, a nitride, a variable resistance material, a nanostructure, or a combination thereof. The tunnel insulating layer 65 may then be formed along the inner wall of the charge trapping layer 64. The tunnel insulating layer 65 may be a layer through which charge tunnels, such as FN tunneling, and may contain an insulating material such as an oxide or nitride. The preliminary channel layer 66 may then be formed along the inner wall of the tunnel insulating layer 65. The preliminary channel layer 66 may include a semiconductor material such as silicon or germanium, an oxide semiconductor material such as ZnO, In2O3, InZnO, ZnSnO, InGaZnO, or ZnGaSnO, a two-dimensional (2D) semiconductor material such as MoS2, MoSe2, WS2, WSe2, or SnS2, or a nanostructure such as nanodots, nanotubes, or graphene. The preliminary channel layer 66 can be formed to partially fill the central region of the hole. The preliminary channel layer 66 can be formed to have a first thickness d11. Thereafter, an annealing process can be performed on the preliminary channel layer 66.

[0129] Reference Figure 29 An etching process can be performed to reduce the thickness of the initial channel layer 66. Therefore, the initial channel layer 66 can be etched down to the second thickness d12.

[0130] Reference Figure 30 The sacrificial layer 67 is formed by oxidizing the exposed inner wall of the preliminary channel layer 66. When the sacrificial layer 67 is formed by deposition, the portion of the sacrificial layer 67 corresponding to the uppermost part of the hole can be formed relatively thick, and the portion of the sacrificial layer 67 corresponding to the bottom surface of the hole can be formed relatively thin, thus resulting in an uneven thickness distribution of the sacrificial layer 18. When the sacrificial layer 67 is formed by oxidation, the thickness of the sacrificial layer 67 corresponding to the uppermost and bottom surfaces of the hole can be formed uniformly. Furthermore, in some embodiments, compared with the sacrificial layer formed by deposition, the sacrificial layer formed by oxidation can have fewer dangling bonds at the interface with the preliminary channel layer 66, thus exhibiting improved performance in terms of current flow and leakage current. In addition, the sacrificial layer 67 formed by oxidation can have higher etch selectivity relative to the preliminary channel layer 66 compared with the sacrificial layer formed by deposition.

[0131] Reference Figure 31A barrier layer 68 is formed along the inner wall of the sacrificial layer 67. The barrier layer 68 may include a polysilicon layer. The thickness d13 of the barrier layer 68 formed on the sidewall of the hole H in the first horizontal direction A-A' and the thickness d14 of the barrier layer 68 formed on the sidewall of the hole H in the second horizontal direction B-B' may be different from each other. For example, the thickness d13 of the barrier layer 68 formed on the sidewall of the hole H in the first horizontal direction A-A' may be smaller than the thickness d14 of the barrier layer 68 formed on the sidewall of the hole H in the second horizontal direction B-B'.

[0132] Reference Figure 32A , Figure 32B and Figure 32C The barrier layer (e.g., can be removed by performing an etching process) Figure 31 (68) Etches to a specific thickness, and then it can be partially removed. The etching process can be performed using an isotropic etching process. For example, a barrier layer (e.g., Figure 31 Part of 68), such that the sidewalls of the sacrificial layer 67 in the first horizontal direction A-A' are exposed. During the etching process, a barrier layer (e.g.,) is formed on the sidewalls of the sacrificial layer 67. Figure 31 The thickness of 68) in the first horizontal direction A-A' is less than that of the barrier layer formed on the sidewall of the sacrificial layer 67 (e.g., Figure 31 The thickness of 68) in the second horizontal direction B-B' is such that even the barrier layer (e.g., Figure 31 68) is etched to expose the sidewalls of the sacrificial layer 67 in the first horizontal direction A-A', the barrier layer (e.g., Figure 31 68) can be retained on the sidewalls of the sacrificial layer 67 in the second horizontal direction B-B'. The remaining barrier layers can be defined as barrier patterns 68A and 68B. Furthermore, during the isotropic etching process, the etching rate in the first horizontal direction A-A' can be higher than the etching rate in the second horizontal direction B-B' due to the difference in surface area and surface angle exposed to the etchant. Therefore, barrier patterns 68A and 68B can be formed on the opposing sidewalls of the aperture H in the second horizontal direction B-B'. The horizontal cross-section of each of the barrier patterns 68A and 68B can have a crescent shape.

[0133] Reference Figure 33A , Figure 33B and Figure 33C Partial etching can be performed by using a barrier pattern (e.g., Figure 32A , Figure 32B and Figure 32C The 68A and 68B) are used as a mask for the etching process, which exposes the sacrificial layer, thus exposing the initial channel layer (e.g., ) in the first horizontal direction A-A'. Figure 32A , Figure 32B and Figure 32C(66). Therefore, the sacrificial layers can be patterned as a first sacrificial layer 67A and a second sacrificial layer 67B separated from each other. Thereafter, the initial channel layer exposed by performing an etching process using the first sacrificial layer 67A and the second sacrificial layer 67B as a mask can be etched (e.g., Figure 32A , Figure 32B and Figure 32C Therefore, the tunnel insulation layer 65 is exposed in the first horizontal direction A-A'. Thus, the initial trench layer can be patterned as a first trench layer 66A and a second trench layer 66B separated from each other. Subsequently, the barrier pattern can be removed.

[0134] Subsequently, a core insulating layer 69 can be formed to fill the holes (e.g., Figure 32A , Figure 32B and Figure 32C The central region of H). The core insulation layer 69 may contain an insulating material such as oxides.

[0135] Subsequently, an etching process can be performed to expose the stacked structure (e.g., Figure 32A , Figure 32B and Figure 32C The sidewalls of the ST) and the exposed second material layer can be removed (e.g., Figure 32A , Figure 32B and Figure 32C (62). Subsequently, a third material layer 70 may be formed in the space where the second material layer has been removed. The third material layer 70 may contain a conductive material such as polysilicon, tungsten, or metal. Thus, a gate stack structure GST including the first material layer 61 and the third material layer 70 can be formed.

[0136] As described above, according to embodiments of the present disclosure, the preliminary channel layer 66 and the sacrificial layer 67 can be formed by a DAO scheme including a deposition process, an annealing process and an oxidation process. Therefore, the layer quality of the preliminary channel layer 66 and the sacrificial layer 67 can be improved, resulting in an increase in the channel current of the memory cell string and a decrease in the leakage current.

[0137] Figure 34 This is a block diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0138] Reference Figure 34 The memory system 1000 may include a host 1100 and a storage device 1200.

[0139] The host 1100 can store data in the storage device 1200, or can read data stored in the storage device 1200 based on an interface. The interface may include at least one of the following: Double Data Rate (DDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Peripheral Component Interconnect (PCI) interface, High-Speed ​​PCI (PCI-E) interface, Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, Parallel ATA (PATA) interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE) interface, Firewire interface, Universal Flash Memory (UFS) interface, and High-Speed ​​Non-Volatile Memory (NVMe) interface.

[0140] Storage device 1200 may include storage controller 1210 and semiconductor memory device 1220. In embodiments, storage device 1200 may be a storage medium such as a solid-state drive (SSD) or a universal serial bus (USB) memory device.

[0141] The storage controller 1210 can store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100.

[0142] Semiconductor memory device 1220 may include one or more memory chips. Semiconductor memory device 1220 may store data or output stored data under the control of memory controller 1210.

[0143] The teachings of this disclosure can increase the number of memory cells by separating the channel layer in the plug hole into multiple channel layers. This can be achieved by improving the layer quality of the channel layer by forming a sacrificial layer used as a mask layer during the etching process used to separate the channel layers using a deposition-annealing-oxidation (DAO) method.

[0144] Cross-reference to related applications

[0145] This application claims priority to Korean Patent Application No. 10-2024-0144745, filed with the Korean Intellectual Property Office on October 22, 2024, the full disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A hole is formed through at least a portion of a laminated structure in which the first material layer and the second material layer are alternately stacked in a first direction; A barrier insulating layer is formed along the hole; A charge trapping layer is formed along the barrier insulating layer; A tunnel insulating layer is formed along the charge trapping layer; A preliminary trench layer is formed along the tunnel insulation layer; A sacrificial layer is formed by oxidizing the exposed inner wall of the initial channel layer; A first sacrificial layer and a second sacrificial layer separated from each other in a second direction intersecting the first direction are formed by patterning the sacrificial layer; as well as The initial channel layer is separated in the second direction by performing an etching process, thereby forming a first channel layer and a second channel layer.

2. The method according to claim 1, further comprising the following steps: After forming the preliminary trench layer, the inner wall of the preliminary trench layer is oxidized; and The thickness of the initial channel layer is reduced by stripping off a portion of the oxidized initial channel layer.

3. The method according to claim 1, further comprising the following steps: After the initial trench layer is formed, an annealing process is performed on the initial trench layer.

4. The method according to claim 1, further comprising the following steps: After the sacrificial layer is formed, a barrier layer is formed along the sacrificial layer.

5. The method according to claim 4, wherein, The steps for forming the barrier layer include the following: The barrier layer is formed such that the thickness of the barrier layer in the third direction is less than the thickness of the barrier layer in the second direction, wherein the third direction intersects both the first direction and the second direction.

6. The method according to claim 5, further comprising the following steps: A barrier pattern is formed by partially etching the barrier layer to the opposite ends of the barrier layer in the second direction.

7. The method according to claim 6, wherein, The steps of forming the first sacrificial layer and the second sacrificial layer include the following steps: The exposed portion of the sacrificial layer is etched using the barrier pattern as a mask.

8. The method according to claim 1, further comprising the following steps: After the first trench layer and the second trench layer are formed, the central portion of the hole is filled with a core insulating layer; as well as The second material layer is replaced with a conductive layer.

9. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A hole is formed through at least a portion of a laminated structure in which the first material layer and the second material layer are alternately stacked in a first direction; A barrier insulating layer is formed along the hole; A charge trapping layer is formed along the barrier insulating layer; A tunnel insulating layer is formed along the charge trapping layer; A preliminary trench layer is formed along the tunnel insulation layer; The initial trench layer is etched to a reduced thickness; A sacrificial layer is formed by oxidizing the inner wall of the initial channel layer; A first sacrificial layer and a second sacrificial layer separated from each other in a second direction intersecting the first direction are formed by patterning the sacrificial layer; as well as The initial channel layer is separated in the second direction by performing an etching process, thereby forming a first channel layer and a second channel layer.

10. The method of claim 9, further comprising the step of: After the initial trench layer is formed, an annealing process is performed on the initial trench layer.

11. The method of claim 9, further comprising the step of: After the sacrificial layer is formed, a barrier layer is formed along the sacrificial layer.

12. The method according to claim 11, wherein, The steps for forming the barrier layer include the following: The barrier layer is formed such that the thickness of the barrier layer in the third direction is less than the thickness of the barrier layer in the second direction, wherein the third direction intersects both the first direction and the second direction.

13. The method of claim 12, further comprising the step of: A barrier pattern is formed by partially etching the barrier layer to the opposite ends of the barrier layer in the second direction.

14. The method according to claim 13, wherein, The steps of forming the first sacrificial layer and the second sacrificial layer include the following steps: The exposed portion of the sacrificial layer is etched using the barrier pattern as a mask.

15. The method of claim 9, further comprising the step of: After the first trench layer and the second trench layer are formed, the central portion of the hole is filled with a core insulating layer; as well as The second material layer is replaced with a conductive layer.

16. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A hole is formed through at least a portion of a laminated structure in which the first material layer and the second material layer are alternately stacked in a first direction; The recessed region is formed by etching the second material layer to the recessed depth through the hole; A barrier insulating layer and a charge trapping layer are formed in each of the recessed regions; A tunnel insulation layer is formed along the sidewall of the charge trapping layer and the first material layer; A preliminary trench layer is formed along the tunnel insulation layer; A sacrificial layer is formed by oxidizing the inner wall of the initial channel layer; A first sacrificial layer and a second sacrificial layer separated from each other in a second direction intersecting the first direction are formed by patterning the sacrificial layer; as well as The initial channel layer is separated in the second direction by performing an etching process, thereby forming a first channel layer and a second channel layer.

17. The method of claim 16, further comprising the step of: After the initial channel layer is formed, the inner wall of the initial channel layer is oxidized; as well as A portion of the oxidized initial trench layer is stripped to reduce the thickness of the initial trench layer.

18. The method of claim 16, further comprising the step of: After the initial trench layer is formed, an annealing process is performed on the initial trench layer.

19. The method of claim 16, further comprising the step of: After the sacrificial layer is formed, a barrier layer is formed along the sacrificial layer.

20. The method according to claim 19, wherein, The steps for forming the barrier layer include the following: The barrier layer is formed such that the thickness of the barrier layer in the third direction is less than the thickness of the barrier layer in the second direction, wherein the third direction intersects both the first direction and the second direction.

21. The method of claim 20, further comprising the step of: A barrier pattern is formed by partially etching the barrier layer to the opposite ends of the barrier layer in the second direction.

22. The method according to claim 21, wherein, The steps of forming the first sacrificial layer and the second sacrificial layer include the following steps: A portion of the sacrificial layer is etched using the barrier pattern as a mask.

23. The method of claim 16, further comprising the step of: After the first trench layer and the second trench layer are formed, the central portion of the hole is filled with a core insulating layer; as well as The second material layer is replaced with a conductive layer.

24. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A hole is formed through at least a portion of a laminated structure in which the first material layer and the second material layer are alternately stacked in a first direction; The recessed region is formed by etching the second material layer exposed through the hole to the recessed depth; A barrier insulating layer and a charge trapping layer are formed in each of the recessed regions; A tunnel insulating layer is formed along the first material layer and the charge trapping layer; A preliminary trench layer is formed along the tunnel insulation layer; Etch the initial trench layer to reduce the thickness of the initial trench layer; A sacrificial layer is formed by oxidizing the exposed inner wall of the initial channel layer; A first sacrificial layer and a second sacrificial layer separated from each other in a second direction orthogonal to the first direction are formed by patterning the sacrificial layer; as well as The initial channel layer is separated in the second direction by performing an etching process, thereby forming a first channel layer and a second channel layer.

25. The method of claim 24, further comprising the step of: After the initial trench layer is formed, an annealing process is performed on the initial trench layer.

26. The method of claim 25, further comprising the step of: After the sacrificial layer is formed, a barrier layer is formed along the sacrificial layer.

27. The method according to claim 26, wherein, The steps for forming the barrier layer include the following: The barrier layer is formed such that the thickness of the barrier layer in the third direction is less than the thickness of the barrier layer in the second direction, wherein the third direction intersects both the first direction and the second direction.

28. The method of claim 27, further comprising the step of: A barrier pattern is formed by partially etching the barrier layer to the opposite ends of the barrier layer in the second direction.

29. The method according to claim 28, wherein, The steps of forming the first sacrificial layer and the second sacrificial layer include the following steps: The exposed portion of the sacrificial layer is etched using the barrier pattern as a mask.

30. The method of claim 24, further comprising the step of: After the first trench layer and the second trench layer are formed, the central portion of the hole is filled with a core insulating layer; as well as The second material layer is replaced with a conductive layer.

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