Image sensing device

Abstract

An image sensing apparatus is disclosed. In an embodiment, an image sensing device includes: a substrate including a pixel region and a peripheral region outside the pixel region, the peripheral region including a pad region and a first adhesion enhancing structure between the pixel region and the pad region and including a plurality of protrusions and a plurality of recesses; a plurality of first substrate isolation structures disposed in the substrate and surrounding each of the pad regions; and a light shielding layer disposed over the substrate and configured to cover the first adhesion enhancing structure and the first substrate isolation structure.

Description

Technical Field

[0001] The technology and implementation methods disclosed in this patent document generally relate to an image sensing device. Background Technology

[0002] Image sensors capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With advancements in industries such as computers and communications, the demand for high-performance image sensors is growing across various fields, including digital cameras, camcorders, personal communication systems (PCS), game consoles, surveillance cameras, medical miniature cameras, and robotics.

[0003] To meet the demands for high resolution and high-speed operation, multilayer image sensing devices have been developed. These devices include an upper layer stacked on top of a lower layer, featuring a through-silicon via (TSV) structure that electrically connects the circuitry between the upper and lower layers. Summary of the Invention

[0004] Various embodiments of the disclosed technology relate to an image sensing device capable of preventing the lens layer from peeling off while also preventing damage to the substrate isolation structure surrounding the pad area.

[0005] In one embodiment of the disclosed technology, the image sensing device may include: a substrate, the substrate including: a pixel region configured to include an image sensing pixel; and a peripheral region located outside the pixel region and configured to include a pad region and a first adhesion enhancement structure located between the pixel region and the pad region and including a plurality of protrusions and a plurality of recesses; a plurality of first substrate isolation structures disposed in the substrate and surrounding each of the pad regions; and a light-shielding layer disposed above the substrate and configured to cover the first adhesion enhancement structure and the first substrate isolation structure.

[0006] In another embodiment of the disclosed technology, the image sensing device may include: a first stacked structure, the first stacked structure including a pixel region configured to include an image sensing pixel and a plurality of first pad regions located outside the pixel region; and a second stacked structure, the second stacked structure being stacked below the first stacked structure and electrically connected to the first stacked structure, and configured to include a logic region configured to include logic circuitry and a plurality of second pad regions located outside the logic region, wherein each second pad region includes an electrode pad. The first stacked structure may include: a substrate, the substrate being configured to include a pad opening region formed in the first pad regions and a first adhesion enhancement structure disposed between the pixel region and the pad opening region and including a plurality of protrusions and a plurality of recesses; a substrate isolation structure, the substrate isolation structure being disposed through the substrate and configured to surround each of the first pad regions; and a light-shielding layer, the light-shielding layer being disposed above the substrate and configured to cover the first adhesion enhancement structure and the first substrate isolation structure.

[0007] It should be understood that the above overview and the following detailed description of the disclosed technology are illustrative and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0008] The above and other features and advantages of the disclosed technology will become apparent when considered in conjunction with the accompanying drawings and the following detailed description.

[0009] Figure 1 This is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0010] Figure 2 This is a schematic diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0011] Figure 3 This demonstrates some implementation methods based on the disclosed technology. Figure 2 A plan view of an example of the planar arrangement of the first stacked structure in the image sensing device shown.

[0012] Figure 4 This demonstrates some implementation methods based on the disclosed technology. Figure 2 Along the stacked structure shown Figure 3 An example cross-sectional view of the section intercepted by line X-X'.

[0013] Figures 5A to 5F This illustrates some implementation methods based on the disclosed technology for forming Figure 4 A cross-sectional view of an example of a structural method.

[0014] Figure 6 This is a cross-sectional view illustrating an example structure of an image sensing device based on some other implementations of the disclosed technology.

[0015] Figure 7 This is a cross-sectional view illustrating an example structure of an image sensing device based on some other implementations of the disclosed technology.

[0016] Figure 8 This is a cross-sectional view illustrating an example structure of an image sensing device based on some other implementations of the disclosed technology. Detailed Implementation

[0017] This patent document provides implementations and examples of an image sensing device that can substantially solve one or more technical or engineering problems and mitigate limitations or drawbacks encountered in some other image sensing devices. Some implementations of the disclosed technology provide examples of image sensing devices that can prevent lens layer peeling while also preventing damage to the substrate isolation structure surrounding the pad area. In view of the above-mentioned problems, the disclosed technology provides various implementations of image sensing devices that can prevent damage to the substrate isolation structure and lens layer peeling, thereby improving the operating characteristics of the image sensing device.

[0018] Specific embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. In the following description, detailed descriptions of related known configurations or functions contained herein will be omitted to avoid obscuring the subject matter.

[0019] Various embodiments will be described below with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents, and / or substitutions of the embodiments. Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the disclosed technology.

[0020] Figure 1 This is a block diagram illustrating an example of an image sensing device 100 based on some implementations of the disclosed technology.

[0021] Reference Figure 1 The image sensing device may include a pixel array 10, a row driver 20, a correlated dual sampler (CDS) 30, an analog-to-digital converter (ADC) 40, an output buffer 50, a column driver 60, and a timing controller 70. Figure 1The components of the image sensing device shown are discussed by way of example only, and this patent document includes many other variations, substitutions, modifications, alterations, and alterations. In this patent document, the term "pixel" may be used to refer to an image sensing pixel, which is configured to detect incident light to generate an electrical signal carrying an image in the incident light.

[0022] The pixel array 10 may include a plurality of unit pixels PX arranged along a first direction (e.g., the X-axis direction) and a second direction (e.g., the Y-axis direction). The plurality of unit pixels may convert optical signals into electrical signals on a unit pixel basis or on a pixel group basis. The plurality of unit pixels PX may be arranged in a Bayer pattern.

[0023] The line driver 20 can activate the unit pixel PX based on a control signal received from a controller circuit such as a timing controller 70. The pixel signal generated by the unit pixel can be output to a correlated double sampler (CDS) 30.

[0024] The Correlated Double Sampler (CDS) 30 can use correlated double sampling to remove unwanted offset values ​​per unit pixel. In some implementations, upon receiving a clock signal from the timing controller 70, the CDS 30 can sequentially sample and hold the voltage levels of the reference signal and the pixel signals provided from the pixel array 10 via multiple column lines. In some implementations, the CDS 30 can transmit the reference signal and the pixel signals as correlated double sampled (CDS) signals to the ADC 40 based on control signals from the timing controller 70.

[0025] The ADC 40 can convert the CDS signal received from the correlated dual sampler (CDS) 30 into a digital signal and output the digital signal to the output buffer 50.

[0026] The output buffer 50 can temporarily store column-based data received from the ADC 40 under the control of the timing controller 70.

[0027] The column driver 60 can select the column of the output buffer 50 under the control of the timing controller 70, and can sequentially output the data temporarily stored in the selected column of the output buffer 50.

[0028] The timing controller 70 can generate signals for controlling the row driver 20, ADC 40, output buffer 50, and column driver 60.

[0029] Figure 2 This is a schematic diagram illustrating an example of an image sensing device 100 based on some implementations of the disclosed technology.

[0030] Reference Figure 2The image sensing device may include a first stacked structure 100 and a second stacked structure 200.

[0031] The first stacked structure 100 and the second stacked structure 200 can be stacked to be electrically connected via a hybrid bonding (or direct bonding) structure.

[0032] The first stacked structure 100 may include structures formed with Figure 1 The pixel array 10 has a pixel region PA and a first pad region PAD1 located in a first peripheral region surrounding the pixel region PA. The pixel region PA may be located at the central portion of the first stacked structure 100.

[0033] The second stacked structure 200 may include a logic region LA and a second pad region PAD2. The logic region LA may include circuitry for operating the pixel array 10 of the first stacked structure 100 and processing pixel electrical signals from the pixel array 10, including, for example, a row driver 20, a CDS 30, an ADC 40, an output buffer 50, a column driver 60, and a timing controller 70. The second pad region PAD2 may be located in a second peripheral region surrounding the logic region LA. The logic region LA may be located at the central portion of the second stacked structure 200, corresponding to the pixel region PA.

[0034] The first pad area PAD1 and the second pad area PAD2 can be configured to overlap each other in the vertical direction. The second pad area PAD2 may include electrode pads connected to bonding wires, and the first pad area PAD1 may include pad openings for exposing the electrode pads. In some implementations, the pad areas PAD can be formed as direct pad structures in which bonding wires are directly connected to the metal interconnects of the second stack structure 200, rather than as structures in which electrode pads are formed on the first stack structure 100 and connected to the metal interconnects of the second stack structure 200 through through-silicon vias (TSVs).

[0035] Figure 3 This demonstrates some implementation methods based on the disclosed technology. Figure 2 A plan view of an example of the planar arrangement of the first stacked structure in the image sensing device shown.

[0036] Reference Figure 3 The first stacked structure 100 may include therein forming Figure 1 The pixel array 10 has a pixel region PA and a peripheral region PERI located outside the pixel region PA. The peripheral region PERI can be formed to surround the pixel region PA and can include a first pad region PAD1. The first pad region PAD1 can include a pad opening region for exposing electrode pads.

[0037] A pixel region PA may include multiple unit pixels PX arranged in multiple rows and columns. A pixel region PA may include a photoelectric conversion area, a color filter, a lens layer, and pixel transistors.

[0038] Substrate isolation structures 118a and 118b can be formed in the peripheral region PERI to reduce or minimize signal interference between pad areas and prevent electrical signals from being introduced from the outside. For example, substrate isolation structures 118a and 118b may include: a first substrate isolation structure 118a surrounding each of the first pad areas PAD1 to prevent signal interference between pad areas; and at least one second substrate isolation structure 118b formed at the edge (e.g., the outermost edge) of the peripheral region PERI to surround (e.g., completely surround) both the pixel area PA and the peripheral region PERI to prevent electrical signals from being introduced from the outside. Substrate isolation structures 118a and 118b may be formed to have the same structure and may be formed to penetrate the substrate within the first stacked structure 100. A light-shielding layer including a metal layer may be formed over the substrate isolation structures 118a and 118b.

[0039] In the peripheral region PERI of the first stacked structure 100, adhesion enhancement structures 132a, 132b, and 132c may be formed to provide enhanced adhesion or bonding of different layers in the first stacked structure 100, including, for example, lens layers, and to prevent lens layer peeling. For example, adhesion enhancement structures 132a, 132b, and 132c may include: a first adhesion enhancement structure 132a formed in the peripheral region PERI between the pixel region PA and the first pad region PAD1; a second adhesion enhancement structure 132b formed above the substrate isolation structure 118a to surround the first pad region PAD1; and a third adhesion enhancement structure 132c formed between the first pad regions PAD1. Adhesion enhancement structures 132a, 132b, and 132c may be formed to have the same structure. Furthermore, adhesion enhancement structures may also be formed on the second substrate isolation structure 118b. In some implementations, each of the adhesion enhancement structures may include multiple protrusions and multiple recesses to increase contact force by expanding the contact area with another material layer. In some implementations, each of the adhesion-enhancing structures may include a rough or textured surface that can improve adhesion. Here, a rough or textured surface includes all forms of uneven surfaces.

[0040] All adhesion reinforcement structures 132a, 132b, and 132c may be formed in the first laminated structure 100, or only some of the adhesion reinforcement structures 132a, 132b, and 132c may be selectively formed in the first laminated structure 100. Such adhesion reinforcement structures will be described in more detail later.

[0041] Figure 4This demonstrates some implementation methods based on the disclosed technology. Figure 2 Along the stacked structure shown Figure 3 An example cross-sectional view of the section intercepted by line X-X'.

[0042] Reference Figure 4 The image sensing device may include a first stacked structure 100, a second stacked structure 200, and a pad opening area 300.

[0043] The first substrate layer 110 may include a first substrate 111, a pixel isolation structure 112, a planarization layer 113, a light-shielding layer 114, a color filter 115, a mesh structure 116, a lens layer 117, a substrate isolation structure 118a, and a pixel transistor 119.

[0044] The first substrate 111 may include a pixel region PA and a peripheral region PERI, and the peripheral region PERI may include a pad region PAD and a middle region MA. The middle region MA may represent the area in the peripheral region PERI between the pixel region PA and the pad region PAD.

[0045] The first substrate 111 may include a first front surface and a first rear surface facing or opposite to the first front surface. The first rear surface of the first substrate 111 may be a light-receiving surface on which light is incident, and may be formed having a planarization layer 113, a light-shielding layer 114, a color filter 115, a mesh structure 116, and a lens layer 117. The first front surface of the first substrate 111 may be formed having a pixel transistor 119 and may be in contact with a first interconnect layer 120. That is, the image sensing device may refer to a back-illuminated (BSI) image sensing device.

[0046] The first substrate 111 may include a first adhesion enhancement structure 132a formed in the intermediate region MA and a plurality of second adhesion enhancement structures 132b formed on the substrate isolation structure 118a. In some implementations, the adhesion enhancement structures 132a, 132b may include a plurality of trenches formed by etching the first rear surface of the first substrate 111. In one example, each of the adhesion enhancement structures 132a, 132b has a triangular cross-section to increase the contact force by increasing the contact area with another material layer. The adhesion enhancement structures 132a, 132b can effectively prevent the lens layer 117 from peeling off by increasing the contact area of ​​the bottom surface of the lens layer 117. The first adhesion enhancement structure 132a may be formed in the intermediate region MA between the pixel region PA and the pad region PAD to surround the pixel region PA, such as Figure 3 As shown. The second adhesion reinforcement structure 132b can be formed on the substrate isolation structure 118a. For ease of description, Figure 4Only the first adhesion reinforcement structure and the second adhesion reinforcement structures 132a and 132b are shown in the figure, but as Figure 3 As shown, the first substrate 111 may further include a third adhesion enhancement structure 132c disposed between the pads (PADs).

[0047] In the first substrate 111, the pad area PAD can refer to the pad opening area 300 through which the first substrate 111 passes or extends.

[0048] The first substrate 111 may include a semiconductor substrate. For example, the first substrate 111 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the first substrate 111 may be formed of an epitaxial layer formed over a base substrate.

[0049] Pixel isolation structure 112 can separate (isolate) the photoelectric conversion regions of adjacent unit pixels PX within the first substrate 111. For example, the photoelectric conversion region (e.g., photodiode (PD)) can be formed to correspond to the unit pixel PX in the region defined by the pixel isolation structure 112 within the first substrate 111. Pixel isolation structure 112 can include a trench isolation structure in which insulating material is buried in trenches etched to a predetermined depth in the first substrate 111. For example, pixel isolation structure 112 can have a deep trench isolation (DTI) structure in which oxide layers (e.g., Al2O3, HfO2, and high aspect ratio process (HARP) oxide layers) and nitride layers are buried in the trenches in a stacked manner.

[0050] A planarization layer 113 may be formed on the first rear surface of the first substrate 111. The planarization layer 113 may be formed to completely cover the first rear surface of the first substrate 111. The planarization layer 113 may be formed of the same material as the pixel isolation structure 112. For example, the planarization layer 113 may be formed together with an insulating material formed in the pixel isolation structure 112. The planarization layer 113 may be formed along the surfaces of a plurality of protrusions and recesses of the adhesion reinforcement structures 132a and 132b in the region where the adhesion reinforcement structures 132a and 132b are formed.

[0051] A light-shielding layer 114 may be formed on the planarization layer 113 in the peripheral region PERI to prevent incident light from being introduced into the first substrate 111 of the peripheral region PERI. The light-shielding layer 114 may extend from the boundary region between the pixel region PA and the peripheral region PERI to the edge of the peripheral region PERI (e.g., the outermost edge). The light-shielding layer 114 may not be formed in the pad region PAD. For example, the light-shielding layer 114 may be formed to completely cover the peripheral region PERI except for the pad region PAD and some areas adjacent to the pad region PAD.

[0052] The light-shielding layer 114 may include a metal. For example, the light-shielding layer 114 may include a structure in which a barrier metal layer 114a and an additional metal layer 114b are stacked. The barrier metal layer 114a may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the additional metal layer 114b may include tungsten (W).

[0053] Because each of the substrate isolation structures 118a and 118b is formed as a thin and deep structure, it can be easily damaged by external impacts and can be used as a pathway for moisture penetration. Furthermore, since the substrate isolation structures 118a and 118b are formed to penetrate the first substrate 111, any moisture entering through the damaged substrate isolation structures 118a and 118b can easily reach the interconnect layer where the metal interconnects are formed. In one embodiment of the disclosed technology, a light-shielding layer 114 covers the substrate isolation structures 118a and 118b to protect them from external impacts and more effectively prevent moisture penetration through the substrate isolation structures 118a and 118b.

[0054] The light-shielding layer 114 may be formed to include a plurality of protrusions and a plurality of recesses along the planarization layer 113 in the region where the adhesion reinforcement structures 132a, 132b are formed, such as the adhesion reinforcement structures.

[0055] Color filter 115 can selectively transmit visible light from incident light. Color filter 115 may include a red color filter, a green color filter, or a blue color filter (R, G, B) arranged in a Bayer pattern. Color filter 115 may be formed on a planarization layer 113 in pixel region PA and may be formed on a light-shielding layer 114 in intermediate region MA.

[0056] A mesh structure 116 can be disposed between color filters 115 to prevent crosstalk of incident light between adjacent color filters 115. The mesh structure 116 may include a barrier metal layer and an air layer. The barrier metal layer of the mesh structure 116 can be formed together with the barrier metal layer 114a of the light-shielding layer 114 using the same process.

[0057] Lens layer 117 can focus incident light onto the photoelectric conversion area of ​​a unit pixel. Lens layer 117 may include: an outer coating layer; and a microlens formed on the outer coating layer and shaped as a hemispherical shape. A lens cover layer may be formed on lens layer 117 to protect lens layer 117 and prevent flickering in lens layer 117.

[0058] Lens layer 117 can be formed to extend into the peripheral region PERI. For example, the lens material of lens layer 117 can extend into the peripheral region PERI to completely cover the peripheral region PERI except for the pad area PAD. Lens layer 117 can be formed between light-shielding layer 114 and pad opening area 300 to prevent light-shielding layer 114 from being exposed to the outside.

[0059] The substrate isolation structure 118a can be formed to surround the pad area PAD, thereby isolating the pad areas PAD from each other in the peripheral region PERI. The substrate isolation structure 118a can be formed to surround each of the pad areas PAD in a dual manner. As described above, the substrate isolation structure 118a can be formed to surround each of the pad areas PAD, thereby preventing signal interference between the pad areas PAD.

[0060] Although for the sake of ease of description, Figure 4 Only the first substrate isolation structure 118a surrounding the pad area PAD is shown, but other implementations are possible. It should be noted that the second substrate isolation structure 118b can be formed at the outermost edge of the first substrate 111 to completely surround the pixel area PA and the peripheral area PERI, such as... Figure 3 As shown. The adhesion enhancement structure and the light-shielding layer 114 can also be formed on the second substrate isolation structure 118b.

[0061] The substrate isolation structure 118a can be formed to penetrate the first substrate 111. The substrate isolation structure 118a may include a lower substrate isolation structure 118a1 and an upper substrate isolation structure 118a2 stacked vertically. The lower substrate isolation structure 118a1 may include a shallow trench isolation (STI) structure in which insulating material is embedded in trenches etched from the first front surface of the first substrate 111 to a predetermined depth. The upper substrate isolation structure 118a2 may include a deep trench isolation (DTI) structure in which insulating material is embedded in trenches etched from the second adhesion reinforcement structure 132b into the lower substrate isolation structure 118a1. When forming the insulating material of the pixel isolation structure 112, the insulating material of the upper substrate isolation structure 118a2 may be formed together.

[0062] A pixel transistor 119 may be formed on a first front surface of the first substrate 111 to be electrically connected to a first metal interconnect 124 of the first interconnect layer 120. The pixel transistor 119 may be formed to correspond to a unit pixel PX in the pixel region PA. The pixel transistor 119 may generate a pixel signal corresponding to the magnitude of the photocharge generated by the photoelectric conversion region of the corresponding unit pixel PX, and may output the pixel signal through the first metal interconnect 124. The pixel transistor 119 may include a transfer transistor, a reset transistor, a source follower transistor, and a select transistor.

[0063] The first interconnect layer 120 may be formed below the first front surface to contact the first front surface of the first substrate 111. The first interconnect layer 120 may be formed to contact the second interconnect layer 220 of the second stacked structure 200. The first interconnect layer 120 may include a first interlayer insulating layer 122, a first metal interconnect 124, and a first bonding structure 126.

[0064] The first interlayer insulating layer 122 may include an insulating material formed not only between the pixel transistor 119 and the first metal interconnect 124, but also between the first metal interconnect 124. For example, the first interlayer insulating layer 122 may include at least one of silicon oxide, silicon nitride, and silicon oxide nitride.

[0065] The first metal interconnect 124 may be formed within the first interlayer insulating layer 122 and may be electrically connected to the pixel transistor 119. Some of the metal interconnects included in the lowest layer of the first metal interconnect 124 may be connected to the first bonding structure 126.

[0066] The first bonding structure 126 can be directly connected to the second bonding structure 228 of the second interconnect layer 220. That is, the first stacked structure 100 and the second stacked structure 200 can be electrically connected to each other using the first bonding structure 126 and the second bonding structure 228 through a hybrid bonding method (or a direct bonding method).

[0067] The first pad region PAD1 of the first stacked structure 100 can be formed as a pad opening region 300 for exposing the electrode pads 226 formed in the second stacked structure 200.

[0068] The second stacked structure 200 may include a second substrate layer 210 and a second interconnect layer 220.

[0069] The second substrate layer 210 may include a second substrate 212 and a logic transistor 214.

[0070] The second substrate 212 may include a logic region LA and a second pad region PAD2 located outside the logic region LA. The second substrate 212 may include a second front surface and a second rear surface facing or relative to the second front surface. The second front surface may be a surface that contacts the second interconnect layer 220, and a plurality of logic transistors 214 may be formed on the second front surface. The second substrate 212 may include a semiconductor substrate such as the first substrate 111.

[0071] Logic transistor 214 may be formed on the second front surface of the second substrate 212 to connect to the second metal interconnect 224. Logic transistor 214 can generate control signals for controlling the operation of unit pixel PX, and can generate an image by processing pixel signals output from unit pixel PX. For example, logic transistor 214 may include components constituting... Figure 1 The diagram shows multiple transistors in the row driver 20, CDS 30, ADC 40, output buffer 50, column driver 60, and timing controller 70. Logic transistor 214 can be formed in the logic region LA of the second substrate 212. Logic transistor 214 can be electrically connected to external devices via electrode pads 226.

[0072] The second interconnect layer 220 may be formed on the second front surface to contact the second front surface of the second substrate 212, and may contact the first interconnect layer 120 of the first stacked structure 100. The second interconnect layer 220 may include a second interlayer insulating layer 222, a second metal interconnect 224, an electrode pad 226, and a second bonding structure 228.

[0073] The second interlayer insulating layer 222 may include an insulating material formed not only between the logic transistor 214 and the second metal interconnect 224, but also between the second metal interconnect 224. For example, the second interlayer insulating layer 222 may include at least one of silicon oxide, silicon nitride, and silicon oxide nitride.

[0074] The second metal interconnect 224 can be formed in the second interlayer insulating layer 222 and can be electrically connected to the logic transistor 214. Some of the metal interconnects included in the uppermost layer of the second metal interconnect 224 can be connected to the second bonding structure 228, and other metal interconnects included in the uppermost layer of the second metal interconnect 224 can be used as electrode pads 226. The metal interconnects included in the uppermost layer of the second metal interconnect 224 can be formed to be thicker than the other metal interconnects and can include aluminum (Al).

[0075] Electrode pads 226 may be disposed within a second interlayer insulating layer 222 within the second pad area PAD2, and the top surface of the electrode pads 226 may be exposed through a pad opening area 300. The exposed top surface of the electrode pads 226 may be directly connected to the bonding wires through the pad opening area 300. Electrode pads 226 may be a portion of the metal interconnect included in the uppermost layer of the second metal interconnect 224.

[0076] The second bonding structure 228 can be directly connected to the first bonding structure 126 of the first interconnect layer 120.

[0077] The pad opening region 300 may include an empty space formed by etching the first stacked structure 100 and the second stacked structure 200 to expose the electrode pads 226. For example, the pad opening region 300 may be formed by the first stacked structure 100 penetrating the first pad region PAD1, or by a second interlayer insulating layer 222 partially etched into the top surface of the electrode pads 226 in the second pad region PAD2. Bonding wires may be formed within the pad opening region 300.

[0078] Figures 5A to 5F This illustrates some implementation methods based on the disclosed technology for forming Figure 4 A cross-sectional view of an example of a structural method.

[0079] Reference Figure 5A The pixel transistor 119 and the lower substrate isolation structure 118a1 can be formed on the first front surface of the first substrate 111. The lower substrate isolation structure 118a1 can be formed as a shallow trench isolation (STI) structure and can be formed together with a means isolation layer for isolating the pixel transistor 119 from each other within the pixel region PA.

[0080] Subsequently, a first interconnect layer 120, comprising a first interlayer insulating layer 122, a first metal interconnect 124, and a first bonding structure 126, can be formed on the first front surface.

[0081] Furthermore, after the logic transistor 214 is formed on the second front surface of the second substrate 212, a second interconnect layer 220 including a second interlayer insulating layer 222, a second metal interconnect 224, an electrode pad 226, and a second bonding structure 228 can be formed on the second front surface.

[0082] Subsequently, the first stacked structure 100 and the second stacked structure 200 can be attached such that the first joining structure 126 and the second joining structure 228 are directly joined to each other.

[0083] Reference Figure 5B The first substrate 111 of the pixel region PA can be etched from the first rear surface to a predetermined depth, resulting in the formation of a trench 112' for forming the pixel isolation structure 112.

[0084] Reference Figure 5CSince the first substrate 111 is etched from the first rear surface to a predetermined depth in each of the intermediate region MA and the other region where the substrate isolation structure 118a is to be formed, adhesion reinforcement structures 132a and 132b for preventing lens layer peeling can be formed. For example, the adhesion reinforcement structures 132a and 132b may include a plurality of trenches etched such that the cross-section of each trench has a triangular shape. In some implementations, the first adhesion reinforcement structure 132a may be formed around the pixel region PA within the intermediate region MA, and the second adhesion reinforcement structure 132b may be formed around each of the first pad regions PAD1. Furthermore, as Figure 3 As shown, the third adhesion enhancement structure 132c can also be formed between adjacent first pad areas PAD1.

[0085] Reference Figure 5D The bottom surface of the second adhesion reinforcement structure 132b can be etched to form a trench 118a2' for forming the upper substrate isolation structure 118a2. For example, the trench 118a2' can be formed by etching the first substrate 111 until the lower substrate isolation structure 118a1 is exposed.

[0086] Reference Figure 5E The insulating material is formed to fill the trench ( Figures 5B to 5D 112' in Figure 5D 118a2' in the above, thereby forming pixel isolation structure 112 and upper substrate isolation structure 118a2. For example, pixel isolation structure 112 and upper substrate isolation structure 118a2 can be filled with trenches by stacking nitride layer and oxide layer (e.g., Al2O3, HfO2, HARP oxide layer) and nitride layer. Figures 5B to 5D 112' in Figure 5D It is formed by 118a2' in the middle. In some implementations, the corresponding insulating material can also be laminated on the first rear surface of the first substrate 111 on which adhesion reinforcement structures 132a, 132b are formed, thereby forming a planarization layer 113.

[0087] Since the planarization layer 113 is formed to have a uniform thickness, within the first substrate 111, the planarization layer 113 may include one or more protrusions and recesses formed in the region where the adhesion reinforcement structures 132a, 132b are formed.

[0088] Subsequently, a light-shielding layer 114 and a grid structure 116 can be formed above the planarization layer 113.

[0089] For example, after sequentially forming a barrier metal layer and an additional metal layer over planarization layer 113, the barrier metal layer and additional metal layer are patterned in such a way that the barrier metal layer and additional metal layer disposed in the pad area PAD of the peripheral region PERI are removed, while the barrier metal layer and additional metal layer disposed in the pixel area PA are selectively retained in the area where the mesh structure 116 is to be formed. As a result, a light-shielding layer 114 can be formed. When removing the barrier metal layer and additional metal layer from the pad area PAD, the barrier metal layer and additional metal layer can be removed over an area wider than the pad area PAD.

[0090] Subsequently, after the additional metal layer is removed so that only the barrier metal layer remains in the area where the grid structure 116 is to be formed, an air layer is formed above the barrier metal layer, thereby forming the grid structure 116.

[0091] The light-shielding layer 114 can be formed to have a uniform thickness, such that the light-shielding layer 114 may also include protrusions and recesses formed in the regions where the adhesion reinforcement structures 132a and 132b are formed in the first substrate 111.

[0092] Subsequently, color filters 115 can be formed in the pixel region PA and the intermediate region MA. In the intermediate region MA, color filters 115 can be formed only in some areas adjacent to the pixel region PA.

[0093] Then, a lens layer 117 can be formed in the pixel region PA and the peripheral region PERI. In some implementations, since the lens layer 117 is also formed above the light-shielding layer 114 with protrusions and recesses, the contact area between the lens layer 117 and the light-shielding layer 114 can be increased compared to the case where the protrusions and recesses are not formed on the light-shielding layer 114. As a result, tearing of the lens layer 117 can be more effectively prevented in subsequent processes.

[0094] Reference Figure 5F The lens layer 117, planarization layer 113, first substrate 111, first interlayer insulating layer 122 and second interlayer insulating layer 222 of the pad area PAD can be sequentially etched until the electrode pad 226 is exposed, thereby forming the pad opening area 300.

[0095] The pad opening area 300 can be formed to have a smaller size (e.g., width) than the area where the light-shielding layer 114 is removed, such that the side surface of the light-shielding layer 114 can be covered and protected by the lens layer 117 without being exposed through the pad opening area 300.

[0096] Figure 6 This is a cross-sectional view illustrating an example structure of an image sensing device based on some other implementations of the disclosed technology.

[0097] Reference Figure 6 The light-shielding layer 114' may include a barrier metal layer 114a and an additional metal layer 114b'.

[0098] and Figure 4 Compared to the light-shielding layer 114, Figure 6 The light-shielding layer 114' differs in structure from the additional metal layer 114b'. For example, the light-shielding layer 114' can be formed as a single layer (or a single layer) of the barrier metal layer 114a, without the additional metal layer 114b' above the first adhesion reinforcement structure 132a, and can be formed as a multilayer structure (i.e., a stacked structure) of the barrier metal layer 114a and the additional metal layer 114b' in areas other than the single-layer structure. When an adhesion reinforcement structure is formed between the pad areas (PADs) Figure 3 In the case of 132c), even in the corresponding adhesion reinforcement structure 132c, the light-shielding layer 114' can be formed as a single-layer structure of the barrier metal layer 114a. When the additional metal layer 114b' is removed to form the mesh structure 116, the additional metal layer 114b' formed above the adhesion reinforcement structures 132a and 132c can be removed simultaneously with the additional metal layer 114b'.

[0099] In some implementations, in the second adhesion enhancement structure 132b formed on the first substrate isolation structure 118a, the light-shielding layer 114' is formed as a multilayer structure of barrier metal layer 114a and additional metal layer 114b', thereby protecting the first substrate isolation structure 118a.

[0100] In the other adhesion reinforcement structures 132a and 132c besides the second adhesion reinforcement structure 132b, the light-shielding layer 114' is formed without the additional metal layer 114b', so that it is compatible with... Figure 4 Compared to the previous structure, the contact area of ​​the lens layer 117 is further increased, thereby more effectively preventing the lens layer 117 from peeling off.

[0101] When an adhesion-enhancing structure is formed between the pads (PADs) in the solder pad area Figure 3 When 132c is formed in the adhesion enhancement structure 132c, the light-shielding layer 114' formed in the adhesion enhancement structure 132c may also not include the additional metal layer 114b'.

[0102] although Figure 6 The illustration shows an example where the light-shielding layer 114' formed in the first adhesion reinforcement structure 132a consists only of the barrier metal layer 114a, but other implementations are possible, and it should be noted that the barrier metal layer 114a may not be formed in the first adhesion reinforcement structure 132a. In other words, the light-shielding layer 114' may not be formed on the first adhesion reinforcement structure 132a. Similarly, the light-shielding layer 114' may not be formed on the adhesion reinforcement structure between the pad areas (PADs).

[0103] exist Figure 6 In the middle, except for the light-shielding layer 114', the rest of the structure can be combined with... Figure 4 Since it is identical to that in the text, redundant descriptions will be omitted in this article for the sake of brevity.

[0104] Figure 7 This is a cross-sectional view illustrating an example structure of an image sensing device based on some other implementations of the disclosed technology.

[0105] Reference Figure 7 The first substrate 111 may include a first substrate isolation structure 118a and adhesion reinforcement structures 134a and 134b formed in the intermediate region MA. Figure 4 The adhesion-enhancing structures 132a and 132b shown are different. Figure 7 The adhesion enhancement structures 134a and 134b shown may include a plurality of trenches formed by etching the first substrate 111, such that the cross-section of each trench has a rectangular shape. Figure 7 The adhesion-enhancing structures 134a and 134b can be with Figure 4 The adhesion-enhancing structures 132a and 132b are formed at the same location.

[0106] Although for the sake of ease of description, Figure 7 Only adhesion-enhancing structures 134a and 134b are shown, but other implementations are possible, and it should be noted that each has its own characteristics. Figure 7 The adhesive reinforcement structure with a square cross-section can also be used with Figure 3 The same manner is used in the adhesion-enhancing structure 132c to form the area between the pads (PADs).

[0107] Figure 7 Besides the adhesion-reinforced structures 134a and 134b, the structures can be combined with... Figure 4 The structure is the same as that in the previous article, so for the sake of brevity, its redundant description will be omitted in this article.

[0108] Figure 8 This is a cross-sectional view illustrating an example structure of an image sensing device based on some other implementations of the disclosed technology.

[0109] Reference Figure 8 The light-shielding layer 114' may include a barrier metal layer 114a and an additional metal layer 114b'.

[0110] and Figure 7 Compared to the light-shielding layer 114, Figure 8The light-shielding layer 114' differs in structure from the additional metal layer 114b'. For example, in the adhesion-enhancing structure 134a formed in the intermediate region MA, the light-shielding layer 114' may consist only of the barrier metal layer 114a without the additional metal layer 114b'. Furthermore, when compared with... Figure 3 The same method is used to form between pads in the solder pad area. Figure 7 In the case of an adhesion-enhanced structure, even in the corresponding adhesion-enhanced structure, the light-shielding layer 114' may only include the barrier metal layer 114a.

[0111] although Figure 8 The illustration shows an example where the light-shielding layer 114' formed in the adhesion reinforcement structure 134a consists only of the barrier metal layer 114a, but other implementations are possible, and it should be noted that the barrier metal layer 114a may not be formed in the adhesion reinforcement structure 134a. In other words, the light-shielding layer 114' may not be formed on the first adhesion reinforcement structure 134a. Similarly, the light-shielding layer 114' may not be formed on the adhesion reinforcement structure between the pad areas (PADs).

[0112] exist Figure 8 In the middle, except for the light-shielding layer 114', the rest of the structure can be combined with... Figure 7 Since it is identical to that in the text, redundant descriptions will be omitted in this article for the sake of brevity.

[0113] While the above embodiments have disclosed an example of forming adhesion reinforcement structures in all intermediate regions MA, the substrate isolation structure 118a region, and the region disposed between the pad areas PAD, other implementations are possible, and it should be noted that the adhesion reinforcement structures can be selectively formed in the corresponding regions. For example, the adhesion reinforcement structures may be formed only in the substrate isolation structure 118a region. Alternatively, the adhesion reinforcement structures may be formed only in the region between the intermediate regions MA and the pad areas PAD.

[0114] Regardless of the presence or absence of an adhesion reinforcement structure, the light-shielding layers 114 and 114' can be formed as a barrier metal layer 114a and an additional metal layer 114b or 114b' above the substrate isolation structures 118a and 118b.

[0115] As described above, image sensing devices based on some implementations of the disclosed technology can prevent damage to the substrate isolation structure and peeling of the lens layer, thereby improving the operating characteristics of the image sensing device.

[0116] The disclosed technology can provide various effects, which can be directly or indirectly identified through the above-described embodiments and other embodiments.

[0117] Although several illustrative embodiments have been described, it should be understood that various modifications or enhancements to the disclosed embodiments and / or other embodiments can be designed based on what is described and / or shown in this patent document.

[0118] Cross-reference to related applications

[0119] This patent document claims priority and benefit to Korean Patent Application No. 10-2024-0145197, filed on October 22, 2024, which is incorporated herein by reference in its entirety as part of the disclosure of this patent document.

Claims

1. An image sensing device, the image sensing device comprising: A substrate, the substrate comprising: a pixel region including image sensing pixels; and a peripheral region located outside the pixel region, wherein the peripheral region includes a pad region and a first adhesion enhancement structure, and the first adhesion enhancement structure is located between the pixel region and the pad region and includes a plurality of protrusions and a plurality of recesses; A plurality of first substrate isolation structures are disposed in the substrate and surround each of the pad areas; and A light-shielding layer is disposed above the substrate and covers the first adhesion enhancement structure and the first substrate isolation structure.

2. The image sensing device according to claim 1, wherein, The light-shielding layer covers the peripheral area but not the solder pad area.

3. The image sensing device according to claim 1, wherein, The light-shielding layer is formed along the surface of the plurality of protrusions and plurality of recesses of the first adhesion reinforcement structure.

4. The image sensing device according to claim 1, wherein, The light-shielding layer includes: Barrier metal layer; and An additional metal layer is formed over the barrier metal layer.

5. The image sensing device according to claim 4, wherein, The light-shielding layer includes: A single-layer structure, the single-layer structure including the barrier metal layer disposed above the first adhesion enhancement structure; and The multilayer structure includes both the barrier metal layer and the additional metal layer disposed above the first substrate isolation structure.

6. The image sensing device according to claim 1, wherein, The substrate further includes: A plurality of second adhesion enhancement structures are disposed above the first substrate isolation structure and surrounding each of the pad areas, each of the plurality of second adhesion enhancement structures including a plurality of protrusions and a plurality of recesses.

7. The image sensing device according to claim 6, wherein, The light-shielding layer includes: The multi-layer structure includes both a barrier metal layer and an additional metal layer disposed above the second adhesion enhancement structure.

8. The image sensing device according to claim 7, wherein, The light-shielding layer is formed along the surface of the plurality of protrusions and plurality of recesses of the second adhesion reinforcement structure.

9. The image sensing device according to claim 6, wherein, The substrate further includes: Multiple third adhesion enhancement structures are disposed between the pad areas and include multiple protrusions and multiple recesses.

10. The image sensing device according to claim 9, wherein, The light-shielding layer comprises a single-layer structure, the single-layer structure including a barrier metal layer disposed above the third adhesion enhancement structure.

11. The image sensing device according to claim 1, further comprising: A second substrate isolation structure is disposed in the substrate at the edge of the substrate and surrounds the pixel region and the peripheral region.

12. The image sensing device according to claim 11, wherein, The light-shielding layer extends to cover the isolation structure of the second substrate.

13. The image sensing device according to claim 1, wherein, Each of the pad areas includes: Pad opening area, through which the substrate passes.

14. An image sensing device, the image sensing device comprising: A first stacked structure, comprising a pixel region and a plurality of first pad regions, wherein the pixel region includes image sensing pixels, and the plurality of first pad regions are located outside the pixel region; and A second stacked structure is stacked below and electrically connected to the first stacked structure. The second stacked structure includes a logic region containing logic circuitry and a plurality of second pad areas located outside the logic region, each second pad area including an electrode pad. The first stacked structure includes: The substrate includes a pad opening region formed in the first pad region and a first adhesion enhancement structure disposed between the pixel region and the pad opening region and including a plurality of protrusions and a plurality of recesses. A substrate isolation structure, the substrate isolation structure being configured to penetrate the substrate and surround each of the first pad regions in the first pad regions; and A light-shielding layer is disposed above the substrate and covers the first adhesion enhancement structure and the substrate isolation structure.

15. The image sensing device according to claim 14, wherein, The light-shielding layer is formed along the surface of the plurality of protrusions and plurality of recesses of the first adhesion reinforcement structure.

16. The image sensing device according to claim 14, wherein, The light-shielding layer includes: Barrier metal layer; and An additional metal layer is formed over the barrier metal layer.

17. The image sensing device according to claim 16, wherein, The light-shielding layer includes: A single-layer structure, the single-layer structure including the barrier metal layer disposed above the first adhesion enhancement structure; and A multilayer structure, the multilayer structure including both the barrier metal layer and the additional metal layer disposed above the substrate isolation structure.

18. The image sensing device according to claim 14, wherein, The substrate further includes: A plurality of second adhesion enhancement structures are disposed above the substrate isolation structure and surrounding each of the first pad areas in the first pad area.

19. The image sensing device according to claim 18, wherein, The light-shielding layer is formed along the second adhesion reinforcement structure above the surfaces of the plurality of protrusions and plurality of recesses.

20. The image sensing device according to claim 18, wherein, The substrate further includes: Multiple third adhesion enhancement structures are disposed between the first pad areas and include multiple protrusions and multiple recesses.

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