Chip packaging structure, manufacturing method of chip packaging structure and electronic equipment

Abstract

The invention discloses a chip packaging structure, a manufacturing method of the chip packaging structure and electronic equipment. The chip packaging structure comprises a chip, a lead frame and a packaging layer, the back surface of the chip is attached to the upper surface of the lead frame; the packaging layer is attached to the upper surface of the lead frame, and the chip is wrapped by the packaging layer; a first bonding pad is arranged on the front surface of the chip, an electric bonding pad is arranged on the lead frame, the first bonding pad is electrically connected with the electric bonding pad through a bonding wire, and the front surface of the chip is opposite to the back surface of the chip; a first stress buffer layer is arranged in at least partial area where the packaging layer is attached to the chip, and the first stress buffer layer is used for releasing heat engine stress between the packaging layer and the chip; a second stress buffer layer is arranged in at least part of the area where the packaging layer is attached to the lead frame, and the second stress buffer layer is used for releasing heat engine stress between the packaging layer and the lead frame. According to the invention, the heat engine stress between the packaging layer and the chip and the lead frame can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a chip packaging structure, a method for manufacturing the chip packaging structure, and an electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, integrated circuit packaging has become particularly important for chips that are highly sensitive to reliability. The packaging layer in the packaging structure provides physical protection for the chip, preventing it from being damaged, contaminated, or subjected to improper use; furthermore, it can resist environmental hazards such as chemicals, moisture, and gases, avoiding impact on chip performance. However, when the packaging layer is heated, due to the high modulus and differences in the coefficients of thermal expansion (CTE) between the packaging layer, chip, and lead frame, the thermomechanical stress cannot be effectively released during temperature shock, temperature cycling, preconditioning testing, and user use, which may lead to delamination between the chip or lead frame and the packaging layer. Summary of the Invention

[0003] In view of this, this application provides a chip packaging structure, a method for manufacturing the chip packaging structure, and an electronic device to solve the technical problem of heat dissipation in traditional chip packaging structures.

[0004] This application provides a chip packaging structure, including: a chip, a lead frame, and a packaging layer; the back side of the chip is attached to the upper surface of the lead frame; the packaging layer is attached to the upper surface of the lead frame, and the chip is covered by the packaging layer; a first pad is provided on the front side of the chip, and an electrical pad is provided on the lead frame, the first pad and the electrical pad are electrically connected by bonding wires, and the front and back sides of the chip are opposite each other; a first stress buffer layer is provided in at least a portion of the area where the packaging layer is attached to the chip, the first stress buffer layer being used to release the thermomechanical stress between the packaging layer and the chip; a second stress buffer layer is provided in at least a portion of the area where the packaging layer is attached to the lead frame, the second stress buffer layer being used to release the thermomechanical stress between the packaging layer and the lead frame.

[0005] Optionally, the bonding wire is covered by the encapsulation layer, and at least a portion of the encapsulation layer that is in contact with the bonding wire is provided with a third stress buffer layer, which is used to release the thermomechanical stress between the encapsulation layer and the bonding wire.

[0006] Optionally, the lead frame includes a first packaging substrate, which includes a top solder resist layer, a metal layer, a dielectric layer, and a bottom solder resist layer. The metal layer and the dielectric layer are disposed between the top solder resist layer and the bottom solder resist layer. The metal layer is divided into multiple mutually insulating metal sub-layers by the dielectric layer. The back side of the chip is attached to the upper surface of the top solder resist layer. The electrical pads are connected to the upper surface of the metal layer and extend beyond the upper surface of the top solder resist layer. The lower surface of the metal layer is connected to a solder ball, and the solder ball extends beyond the lower surface of the bottom solder resist layer.

[0007] Optionally, the first stress buffer layer, the second stress buffer layer, and the third stress buffer layer each comprise at least one of polymer-based, inorganic ceramic, silicone resin-based, and epoxy resin.

[0008] Optionally, the first stress buffer layer, the second stress buffer layer, and the third stress buffer layer have the same composition.

[0009] Optionally, the thickness range of the first stress buffer layer, the second stress buffer layer and the third stress buffer layer is [1um, 100um], and the elastic modulus range of the first stress buffer layer, the second stress buffer layer and the third stress buffer layer is [0.1Gpa, 5Gpa] in the temperature range of [20℃, 25℃].

[0010] Optionally, the encapsulation layer is made of a light-transmitting material; the chip encapsulation structure further includes a light-shielding layer, and the light transmittance of the light-shielding layer is lower than that of the encapsulation layer; the light-shielding layer is connected to a portion of the lower surface of the encapsulation layer, and the light-shielding layer is used to prevent light from entering the encapsulation layer from the lower surface side of the lead frame.

[0011] Optionally, the encapsulation layer includes a first encapsulation portion and a second encapsulation portion, wherein the first encapsulation portion fills the through-holes on the lead frame, and the second encapsulation portion fills the recessed area on the lower surface of the lead frame; the light-shielding layer is attached to the lower surfaces of the first encapsulation portion and the lower surfaces of the second encapsulation portion.

[0012] Optionally, the light-shielding layer fills the through holes on the lead frame and the recessed area on the lower surface of the lead frame.

[0013] A second aspect of this application provides a chip packaging structure, including: a chip, a lead frame, a packaging layer, and a light-shielding layer; the back side of the chip is attached to the upper surface of the lead frame; the packaging layer is attached to the upper surface of the lead frame, and the chip is covered by the packaging layer, the packaging layer including a light-transmitting material; a first pad is provided on the front side of the chip, and an electrical pad is provided on the lead frame, the first pad and the electrical pad are electrically connected by bonding wires, the front side and the back side of the chip are opposite to each other; the light-shielding layer is connected to a portion of the lower surface of the packaging layer, the light-shielding layer is used to prevent light from entering the packaging layer from the lower surface side of the lead frame, and the light transmittance of the light-shielding layer is lower than the light transmittance of the packaging layer.

[0014] Optionally, the encapsulation layer includes a first encapsulation portion and a second encapsulation portion, wherein the first encapsulation portion fills the through-holes on the lead frame, and the second encapsulation portion fills the recessed area on the lower surface of the lead frame; the light-shielding layer is attached to the lower surfaces of the first encapsulation portion and the lower surfaces of the second encapsulation portion.

[0015] Optionally, the light-shielding layer fills the through holes on the lead frame and the recessed area on the lower surface of the lead frame.

[0016] A third aspect of this application provides a method for manufacturing a chip package structure, comprising: attaching the back side of a chip to the upper surface of a lead frame and providing electrical pads on the lead frame; providing bonding wires to electrically connect a first pad on the front side of the chip to the electrical pads, wherein the front side and the back side of the chip are opposite to each other; providing a first stress buffer layer to at least a portion of the front and side surfaces of the chip, and providing a second stress buffer layer to at least a portion of the surface of the lead frame that is not attached to the chip; curing the first stress buffer layer and the second stress buffer layer; and encapsulating the chip and the lead frame, wherein the encapsulated package layer covers at least a portion of the surface of the chip and is attached to the upper surface of the lead frame.

[0017] Optionally, the manufacturing process of the chip package structure further includes: providing a third stress buffer layer on at least a portion of the bonding wire surface that is not attached to the first pad and the electrical pad.

[0018] Optionally, the process of providing a first stress buffer layer to at least a portion of the front and side surfaces of the chip, and providing a second stress buffer layer to at least a portion of the surface of the lead frame that is not attached to the chip, may further include: spraying or dipping the first stress buffer layer to at least a portion of the front and side surfaces of the chip, and spraying or dipping the second stress buffer layer to at least a portion of the surface of the lead frame that is not attached to the chip; the process of providing a third stress buffer layer to at least a portion of the surface of the bonding wire that is not attached to the first pad and the electrical pad may further include: spraying or dipping the third stress buffer layer to at least a portion of the surface of the bonding wire that is not attached to the first pad and the electrical pad.

[0019] A fourth aspect of this application provides an electronic device, comprising: a chip packaging structure as described in any of the first aspects above.

[0020] The chip packaging structure provided in this application, through a first stress buffer layer disposed in at least a portion of the area where the packaging layer is attached to the chip, can release the thermomechanical stress between the packaging layer and the chip. Through a second stress buffer layer disposed in at least a portion of the area where the packaging layer is attached to the lead frame, it can release the thermomechanical stress between the packaging layer and the lead frame. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0022] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application; Figure 2 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 3 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 4 This is a schematic diagram of a chip packaging structure including a light-shielding layer according to an embodiment of this application; Figure 5 This is a schematic diagram of a chip packaging structure including a light-shielding layer according to another embodiment of this application; Figure 6 This is a schematic diagram of a chip packaging structure including a light-shielding layer according to another embodiment of this application; Figure 7 This is a schematic diagram of a chip packaging structure including a light-shielding layer according to another embodiment of this application; Figure 8 This is a flowchart of the steps of a method for manufacturing a chip packaging structure according to an embodiment of this application; Figures 9a-9g This is a schematic diagram of the structure obtained in each step of the manufacturing method of a chip packaging structure according to an embodiment of this application; Figures 10a-10f This is a schematic diagram of the structure obtained in each step of the manufacturing method of the chip packaging structure according to another embodiment of this application; Figure 11 This is a schematic diagram of a chip package structure manufactured by a chip package structure manufacturing method according to another embodiment of this application.

[0023] List of reference numerals in the attached diagram: Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0025] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0026] It should be understood that although this application may use the terms first, second, third, etc., to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0027] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0028] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application, as shown below. Figure 1 As shown, the chip package structure 1 includes a chip 11, a lead frame 12, and a package layer 13. The back side of the chip 11 is bonded to the upper surface of the lead frame 12. The package layer 13 is bonded to the upper surface of the lead frame 12, and the chip 11 is covered by the package layer 13. A first pad 111 is provided on the front side of the chip 11, and an electrical pad 121 is provided on the lead frame 12. The first pad 111 and the electrical pad 121 are electrically connected by bonding wires 14, and the front and back sides of the chip 11 are opposite to each other. A first stress buffer layer 15 is provided in at least a portion of the area where the package layer 13 is bonded to the chip 11. The first stress buffer layer 15 is used to release the thermomechanical stress between the package layer 13 and the chip 11. A second stress buffer layer 16 is provided in at least a portion of the area where the package layer 13 is bonded to the lead frame 12. The second stress buffer layer 16 is used to release the thermomechanical stress between the package layer 13 and the lead frame 12.

[0029] To protect the chip 11 and lead frame 12, a passivation layer is often provided on the surfaces where the chip 11 and lead frame 12 are bonded to the packaging layer 13. As semiconductor devices develop towards higher density, thinner profiles, and higher power, the passivation layer thickness has gradually decreased; for example, it has dropped from the traditional 2-5 μm to below 1.5 μm, significantly reducing its resistance to external stress. Because the chip 11, lead frame 12, and packaging layer 13 are made of different materials, these components have high modulus and different coefficients of thermal expansion (CTE). The CTE of the packaging layer 13 (EMC) is approximately 25 × 10⁻⁶. -6 / ℃) and silicon chips (≈2.3×10 -6 / ℃), lead frame (copper ≈ 17×10) -6The difference in temperature (°C) is 1-2 orders of magnitude. Simultaneously, the chip package structure 1 needs to withstand temperature cycling from -55°C to 125°C, reflow soldering thermal shock (typically >250°C), and corrosion from humid environments. This can cause interfacial shear stress due to the dimensional difference between the package layer 13 and the chip 11 and / or lead frame 12 during temperature changes. This stress directly acts on the passivation layer, potentially leading to cracks in the passivation layer or delamination between the package layer 13 and the chip 11 and / or lead frame 12, making it unable to resist corrosion from humid environments. Therefore, a first stress buffer layer 15 can be provided in at least a portion of the area where the package layer 13 adheres to the chip 11, and a second stress buffer layer 16 can be provided in at least a portion of the area where the package layer 13 adheres to the lead frame 12. The first stress buffer layer 15 and the second stress buffer layer 16 are equivalent to flexible buffer pads. When thermomechanical stress is generated between the encapsulation layer 13 and the chip 11, the first stress buffer layer 15 absorbs, disperses and offsets the thermomechanical stress at least partially. When thermomechanical stress is generated between the encapsulation layer 13 and the lead frame 12, the second stress buffer layer 16 absorbs, disperses and offsets the thermomechanical stress at least partially.

[0030] It should be noted that, Figure 1 In the chip package structure 1 shown, the first stress buffer layer 15 is disposed on the front side of the chip 11, excluding the first pad 111, and the second stress buffer layer 16 is disposed on the upper surface of the lead frame 12. However, the first stress buffer layer 15 can also be disposed in at least a portion of the side surface of the chip 11, and the second stress buffer layer 16 can also be disposed in at least a portion of the side and lower surfaces of the lead frame 12. Figure 1 The diagram shows that chip 11 and lead frame 12 are connected via a bonding layer 20. The bonding layer 20 may include a die-attach film (DAF), primarily composed of epoxy resin, formed into a uniform film through a coating process, or it may include a DAA fluid material. Alternatively, chip 11 and lead frame 12 can be directly soldered. Terminals 30, which may be made of tin, can also be provided on the exposed end face of lead frame 12 within the encapsulation layer 13 for connection to external devices and communication.

[0031] In this embodiment, a first stress buffer layer 15, disposed in at least a portion of the area where the encapsulation layer 13 is attached to the chip 11, can release the thermomechanical stress between the encapsulation layer 13 and the chip 11. A second stress buffer layer 16, disposed in at least a portion of the area where the encapsulation layer 13 is attached to the lead frame 12, can release the thermomechanical stress between the encapsulation layer 13 and the lead frame 12.

[0032] Figure 2 This is a schematic diagram of a chip packaging structure according to another embodiment of this application, as shown below. Figure 2As shown, the bonding wire 14 is covered by the encapsulation layer 13. At least a portion of the encapsulation layer 13 and the bonding wire 14 are provided with a third stress buffer layer 17, which is used to release the thermomechanical stress between the encapsulation layer 13 and the bonding wire 14.

[0033] There is also a difference in the coefficient of thermal expansion between the bonding wire 14 and the packaging layer 13. Under temperature changes, the difference in dimensional changes between the bonding wire 14 and the packaging layer 13 will generate interfacial shear stress, which will directly act on the bonding wire 14. This may cause the solder joints at the connection points between the bonding wire 14 and the first pad 111 and the electrical pad 121 to break under stress, resulting in the failure of the electrical connection between the chip 11 and the lead frame 12. Therefore, a third stress buffer layer 17 can be provided in at least a part of the area where the packaging layer 13 and the bonding wire 14 are attached. The thermomechanical stress between the packaging layer 13 and the bonding wire 14 can be at least partially released through the third stress buffer layer 17.

[0034] The first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 can be buffer layers containing the same components or buffer layers containing different components.

[0035] In this embodiment, a third stress buffer layer 17 disposed in at least a portion of the area where the encapsulation layer 13 is attached to the bonding wire 14 can release the thermomechanical stress between the encapsulation layer 13 and the bonding wire 14.

[0036] Specifically, the first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 each include at least one of polymer-based, inorganic ceramic, silicone resin-based, and epoxy resin.

[0037] Specifically, the first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 have the same composition, which can reduce the difficulty of production and facilitate processing.

[0038] Specifically, the thickness range of the first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 is [1um, 100um]. The elastic modulus range of the first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 in the temperature range of [20℃, 25℃] is [0.1GPa, 5GPa]. The elastic modulus is the ability of a material to resist deformation. The lower the modulus, the softer the material and the easier it is to undergo elastic deformation. The encapsulation layer 13 is mainly composed of epoxy molding compound with an elastic modulus of ≈15-20 GPa. The elastic modulus of the chip 11 is ≈130 GPa. The lead frame 12 is mainly composed of a copper frame or substrate with an elastic modulus of ≈110 GPa. The elastic moduli of the first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 are relatively low. Under the same stress, the buffer layers can undergo significant elastic deformation (such as tension, compression, shear, etc.), converting the rigid stress between the chip 11, the lead frame 12, the bonding wire 14, and the encapsulation layer 13 into flexible deformation energy. This prevents stress from being transmitted to weak components such as the passivation layer on the surface of the chip 11 and the solder joints at both ends of the bonding wire 14 (where the metal fatigue threshold is low). The elastic modulus of the buffer layer should not be too low, otherwise the buffer layer will be too soft and lack strength. During the molding process, the injection pressure of the encapsulation layer 13 will cause the buffer layer to be over-compressed and deformed, failing to form a continuous buffer interface and losing its buffering effect. At the same time, if the elastic modulus is too low... During long-term use (such as in high-temperature and humid environments), creep (permanent deformation) is likely to occur, leading to a decrease in the buffering effect. By setting the thickness range of the first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 to [1um, 100um], sufficient deformation space can be ensured without affecting the practicality of the packaging.

[0039] Figure 3 This is a schematic diagram of a chip packaging structure according to another embodiment of this application, as shown below. Figure 3 As shown, the lead frame 12 includes a first packaging substrate, which includes a top solder resist layer 122, a metal layer 123, a dielectric layer 124, and a bottom solder resist layer 125. The metal layer 123 and the dielectric layer 124 are disposed between the top solder resist layer 122 and the bottom solder resist layer 125. The metal layer 123 is divided into multiple mutually insulating metal sublayers by the dielectric layer 124. The back side of the chip 11 is attached to the upper surface of the top solder resist layer 122. The electrical pads 121 are connected to the upper surface of the metal layer 123 and extend beyond the upper surface of the top solder resist layer 122. The lower surface of the metal layer 123 is connected to solder balls 40, and the solder balls 40 extend beyond the lower surface of the bottom solder resist layer 125.

[0040] The first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 can be applied to different upright chip package structures. Figure 3In the dual-layer wiring package substrate structure shown, the first stress buffer layer 15 is disposed on the front side of the chip except for the area where the first pad 111 is located, the second stress buffer layer 16 is disposed on the upper surface of the top solder resist layer 122 in the area that is not in contact with the chip 11, and the third stress buffer layer 17 is disposed on the upper surface of the bonding wire 14.

[0041] In this embodiment of the application, by providing a first stress buffer layer 15, a second stress buffer layer 16 and a third stress buffer layer 17 in the double-layer wiring package substrate structure, the thermomechanical stress between the chip 11, the lead frame 12, the package layer 13 and the bonding wire 14 in the double-layer wiring package substrate structure can be at least partially alleviated.

[0042] In one possible implementation, the encapsulation layer 13 is made of a light-transmitting material. The chip package structure 1 also includes a light-shielding layer 18, and the light transmittance of the light-shielding layer 18 is lower than that of the encapsulation layer 13. The light-shielding layer 18 is connected to a portion of the lower surface of the encapsulation layer 13, and the light-shielding layer 18 is used to prevent light from entering the encapsulation layer 13 from the lower surface side of the lead frame 12.

[0043] The chip 11 in the chip package structure 1 can be a photosensitive chip, which is used for light sensing. However, since the package layer 13 is made of a transparent material, some light will pass through the package layer 13 to reach the printed circuit board below the chip package structure 1. The surface of the printed circuit board is usually coated with solder resist, which reflects colored light to the package layer 13. After refraction, some of the colored light may reach the photosensitive plane of the chip 11, thus affecting the photosensitive effect of the chip 11.

[0044] Therefore, a light-shielding layer 18 with a light transmittance lower than that of the encapsulation layer 13 can be provided on the lower surface of the encapsulation layer 13 to prevent light from entering the encapsulation layer 13 from the lower surface side of the lead frame 12.

[0045] Specifically, the light-shielding layer 18 can be made of opaque materials such as black photosensitive ink, black adhesive film, or black coating.

[0046] In this embodiment, by providing a light-shielding layer 18, light can be prevented from entering the encapsulation layer 13 from the lower surface side of the lead frame 12, thus avoiding any impact on the photosensitive effect of the chip 11.

[0047] In one possible implementation, such as Figure 4As shown, the encapsulation layer 13 includes a first encapsulation portion 131 and a second encapsulation portion 132. The first encapsulation portion 131 fills the through-holes on the lead frame 12, and the second encapsulation portion 132 fills the recessed area on the lower surface of the lead frame. The light-shielding layer 18 is attached to the lower surface of the first encapsulation portion 131 and the lower surface of the second encapsulation portion 132.

[0048] In this embodiment of the application, by setting the light-shielding layer 18 to be attached to the lower surface of the first encapsulation part 131 and the lower surface of the second encapsulation part 132, the amount of material used in the light-shielding layer 18 can be reduced, thereby reducing costs.

[0049] In one possible implementation, such as Figure 5 As shown, the light-shielding layer 18 fills the through holes on the lead frame 12 and the recessed area on the lower surface of the lead frame 12.

[0050] In this embodiment of the application, by providing a light-shielding layer 18 to fill the through holes on the lead frame 12 and the recessed area on the lower surface of the lead frame 12, the processing difficulty of the light-shielding layer 18 can be reduced.

[0051] One embodiment of this application provides a chip packaging structure 2, which includes a chip 11, a lead frame 12, a packaging layer 13, and a light-shielding layer 18. The back side of the chip 11 is attached to the upper surface of the lead frame 12. The packaging layer 13 is attached to the upper surface of the lead frame 12, and the chip 11 is covered by the packaging layer 13, which includes a light-transmitting material. A first pad 111 is provided on the front side of the chip 11, and an electrical pad 121 is provided on the lead frame 12. The first pad 111 and the electrical pad 121 are electrically connected by bonding wires 14, and the front and back sides of the chip 11 are opposite to each other. The light-shielding layer 18 is connected to a portion of the lower surface of the packaging layer 13. The light-shielding layer 18 is used to prevent light from entering the packaging layer 13 from the lower surface side of the lead frame 12, and the light transmittance of the light-shielding layer 18 is lower than that of the packaging layer.

[0052] The chip 11 in the chip package structure 2 can be a photosensitive chip, which is used for light sensing. However, since the package layer 13 is made of a transparent material, some light will pass through the package layer 13 to reach the printed circuit board below the chip package structure 2. The surface of the printed circuit board is usually coated with solder resist, which reflects colored light to the package layer 13. After refraction, some of the colored light may reach the photosensitive plane of the chip 11, thus affecting the photosensitive effect of the chip 11.

[0053] Therefore, a light-shielding layer 18 with a light transmittance lower than that of the encapsulation layer 13 can be provided on the lower surface of the encapsulation layer 13 to prevent light from entering the encapsulation layer 13 from the lower surface side of the lead frame 12.

[0054] Specifically, the light-shielding layer 18 can be made of opaque materials such as black photosensitive ink, black adhesive film, or black coating.

[0055] In one possible implementation, such as Figure 6 As shown, the encapsulation layer 13 includes a first encapsulation portion 131 and a second encapsulation portion 132. The first encapsulation portion 131 fills the through-holes on the lead frame 12, and the second encapsulation portion 132 fills the recessed area on the lower surface of the lead frame. The light-shielding layer 18 is attached to the lower surface of the first encapsulation portion 131 and the lower surface of the second encapsulation portion 132.

[0056] In this embodiment of the application, by setting the light-shielding layer 18 to be attached to the lower surface of the first encapsulation part 131 and the lower surface of the second encapsulation part 132, the amount of material used in the light-shielding layer 18 can be reduced, thereby reducing costs.

[0057] In one possible implementation, such as Figure 7 As shown, the light-shielding layer 18 fills the through holes on the lead frame 12 and the recessed area on the lower surface of the lead frame 12.

[0058] In this embodiment of the application, by providing a light-shielding layer 18 to fill the through holes on the lead frame 12 and the recessed area on the lower surface of the lead frame 12, the processing difficulty of the light-shielding layer 18 can be reduced.

[0059] Figure 8 This is a flowchart illustrating the steps of a method for manufacturing a chip packaging structure according to an embodiment of this application, as follows: Figure 4 As shown, the manufacturing method of the chip package structure includes the following steps: Step 101: Attach the back of the chip to the upper surface of the lead frame and set electrical pads on the lead frame.

[0060] To manufacture the chip package structure, the chip 11 is first fixed onto the lead frame 12, and electrical pads 121 are provided on the lead frame 12. After this step is completed, the chip package structure can be manufactured as follows: Figure 9a As shown.

[0061] Step 102: Set up bonding wires to electrically connect the first pad on the front side of the chip to the electrical pad.

[0062] With the front and back sides of chip 11 facing each other, bonding wires 14 are used to electrically connect the chip to the lead frame. After this step, the chip package structure can be as follows: Figure 9b As shown.

[0063] Step 103: Deposit a first stress buffer layer on at least a portion of the front and side surfaces of the chip, and deposit a second stress buffer layer on at least a portion of the surface of the lead frame that is not attached to the chip.

[0064] A low-modulus buffer layer is sprayed onto the front and sides of the chip 11 and the surface of the lead frame 12 using a spraying device 50. This results in at least a portion of the front and sides of the chip 11 being covered by a first stress buffer layer 15, and at least a portion of the surface of the lead frame 12 not attached to the chip 11 being covered by a second stress buffer layer 16. After this step, the chip packaging structure can be configured as follows: Figure 9c As shown.

[0065] It should be noted that the method of setting the first stress buffer layer 15 and the second stress buffer layer 16 is not limited to spraying, but can also be dip coating or other methods. Spraying allows for control of the setting position of the first stress buffer layer 15 and the second stress buffer layer 16, while dip coating allows for the one-time processing and setting of the first stress buffer layer 15 and the second stress buffer layer 16 over a relatively wide area.

[0066] Step 104: Curing the first stress buffer layer and the second stress buffer layer.

[0067] The first stress buffer layer 15 and the second stress buffer layer 16 are cured by heating or other methods. After this step is completed, the chip packaging structure can be as follows: Figure 9d As shown.

[0068] Step 105: Moldulate the chip and lead frame, wherein the encapsulated layer covers at least a portion of the chip surface and adheres to the upper surface of the lead frame.

[0069] After molding and shaping the chip 11 and lead frame 12, the packaging layer 13 is formed by segmentation. Once this step is completed, the chip packaging structure can be as follows: Figure 9e As shown.

[0070] In one possible implementation, the method of manufacturing the chip package structure further includes: providing a third stress buffer layer on at least a portion of the bonding wire surface that is not attached to the first pad and the electrical pad.

[0071] Before encapsulating the chip 11 and the lead frame 12, a third stress buffer layer 17 may be provided on at least a portion of the surface of the bonding wire 14 that is not attached to the first pad 111 and the electrical pad 121.

[0072] Specifically, the first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 are all applied to their respective positions by spraying or dipping.

[0073] It should be noted that by applying the first stress buffer layer 15, the second stress buffer layer 16, and the third stress buffer layer 17 through dip coating, the buffer layer covers a wide area, for example... Figure 11As shown, both the side of the chip 11 and the side of the lead frame 12 are provided with corresponding buffer layers.

[0074] In this embodiment of the application, by providing a third stress buffer layer 17 on at least a portion of the surface of the bonding wire 14 that is not attached to the first pad 111 and the electrical pad 121, the thermomechanical stress between the surface of the bonding wire 14 and the encapsulation layer 13 can be at least partially relieved after molding.

[0075] In one possible implementation, the manufacturing method of the chip package structure may further include: applying a light-shielding layer 18 to the bottom surface of the package layer 13, the light-shielding layer 18 being used to prevent light from entering the package layer 13 from the lower surface side of the lead frame 12. The chip 11 in the chip package structure 1 can be a photosensitive chip, which is used for light sensing. However, since the package layer 13 is made of a transparent material, some light will pass through the package layer 13 to reach the printed circuit board below the chip package structure 1. The surface of the printed circuit board is usually coated with solder resist, which reflects colored light to the package layer 13. After refraction, some of the colored light may reach the photosensitive plane of the chip 11, thereby affecting the photosensitive effect of the chip 11. Therefore, a light-shielding layer 18 with a transmittance lower than that of the package layer 13 can be provided on the lower surface of the package layer 13 to prevent light from entering the package layer 13 from the lower surface side of the lead frame 12.

[0076] Specifically, such as Figure 9f As shown, the light-shielding layer 18 can be disposed only on the lower surface of the encapsulation layer 13, which can reduce the amount of material used in the light-shielding layer 18 and reduce costs. Figure 9f The light-shielding layer 18 shown can be applied to the lower surface of the packaging layer 13 by spraying, dipping, or other methods. After applying the light-shielding layer 18, openings for tin plating are made in the light-shielding layer 18. Tin plating is then performed to form terminals 30 on the lower surface of the lead frame 12. After this step is completed, the chip packaging structure can be configured as follows. Figure 9g As shown.

[0077] The thickness of the light-shielding layer 18 applied to the bottom surface of the encapsulation layer 13 can be one-third to one-half the thickness of the terminal 30 formed after tin plating.

[0078] Alternatively, the manufacturing method of the chip package structure includes: attaching the back side of the chip 11 to the upper surface of the lead frame 12, providing electrical pads 121 on the lead frame 12, and then providing a light-shielding layer 18 to fill the through holes on the lead frame 12 and the recessed areas on the lower surface of the lead frame 12. By providing a light-shielding layer 18 to fill the through holes on the lead frame 12 and the recessed areas on the lower surface of the lead frame 12, the processing difficulty of the light-shielding layer 18 can be reduced. Figure 9gThe light-shielding layer 18 shown can be shaped by etching, engraving, etc., and then fills the through holes on the lead frame 12 and the recessed area on the lower surface of the lead frame 12. After this step is completed, the chip packaging structure can be as follows: Figure 10a As shown.

[0079] Next, bonding wire 14 is installed to electrically connect the first pad 111 on the front side of chip 11 to the electrical pad 121. With the front and back sides of chip 11 facing each other, bonding wire 14 enables chip 11 to be electrically connected to the lead frame 12. After this step, the chip package structure can be as follows: Figure 10b As shown.

[0080] Next, a first stress buffer layer 15 is applied to at least a portion of the front and side surfaces of the chip 11, and a second stress buffer layer 16 is applied to at least a portion of the surface of the lead frame 12 that is not attached to the chip 11. A low-modulus buffer layer is then applied to the front and side surfaces of the chip 11 and the surface of the lead frame 12 using a spraying device 50, such that at least a portion of the front and side surfaces of the chip 11 are covered by the first stress buffer layer 15, and at least a portion of the surface of the lead frame 12 that is not attached to the chip 11 is covered by the second stress buffer layer 16. After this step is completed, the chip package structure can be as follows: Figure 10c As shown.

[0081] After solidifying the first stress buffer layer 15 and the second stress buffer layer 16, the chip packaging structure can be configured as follows: Figure 10d As shown.

[0082] After the first stress buffer layer 15 and the second stress buffer layer 16 are cured, the chip 11 and the lead frame 12 are encapsulated. The encapsulated packaging layer 13 covers at least a portion of the surface of the chip 11, and the encapsulated packaging layer 13 adheres to the upper surface of the lead frame 12. After this step is completed, the chip packaging structure can be as follows: Figure 10e As shown.

[0083] Finally, tin plating is performed on the lower surface of the lead frame 12. After this step is completed, the chip package structure can be as follows: Figure 10f As shown.

[0084] This application provides an electronic device, which includes a chip packaging structure as described in any of the foregoing embodiments. The electronic device may include one chip packaging structure or multiple chip packaging structures.

[0085] It should be noted that the electronic devices in this application are specific applications of the chip packaging structures in the foregoing embodiments in various electronic products (such as smartphones and tablets). For specific chip packaging structures in electronic devices, please refer to the description in the foregoing chip packaging structure embodiments, which will not be repeated here.

[0086] In this embodiment, a first stress buffer layer disposed in at least a portion of the area where the encapsulation layer is bonded to the chip can release the thermomechanical stress between the encapsulation layer and the chip. A second stress buffer layer disposed in at least a portion of the area where the encapsulation layer is bonded to the lead frame can release the thermomechanical stress between the encapsulation layer and the lead frame.

[0087] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0088] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0089] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0090] The above description is provided to enable any person skilled in the art to implement and use this application. Various details are set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0091] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0092] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: Chip, lead frame, and packaging layer; The back side of the chip is attached to the upper surface of the lead frame; The encapsulation layer is attached to the upper surface of the lead frame, and the chip is encapsulated by the encapsulation layer; The chip has a first pad on its front side and an electrical pad on its lead frame. The first pad and the electrical pad are electrically connected by a bonding wire. The front and back sides of the chip are opposite each other. At least a portion of the packaging layer that is attached to the chip is provided with a first stress buffer layer, which is used to release the thermomechanical stress between the packaging layer and the chip. At least a portion of the encapsulation layer that is in contact with the lead frame is provided with a second stress buffer layer, which is used to release the thermomechanical stress between the encapsulation layer and the lead frame.

2. The chip packaging structure according to claim 1, characterized in that, The bonding wire is covered by the encapsulation layer, and a third stress buffer layer is provided in at least a portion of the encapsulation layer that is in contact with the bonding wire. The third stress buffer layer is used to release the thermomechanical stress between the encapsulation layer and the bonding wire.

3. The chip packaging structure according to claim 2, characterized in that, The lead frame includes a first packaging substrate, which includes a top solder resist layer, a metal layer, a dielectric layer and a bottom solder resist layer. The metal layer and the dielectric layer are disposed between the top solder resist layer and the bottom solder resist layer. The metal layer is divided into multiple mutually insulating metal sublayers by the dielectric layer. The back side of the chip is attached to the upper surface of the top solder resist layer, the electrical pads are connected to the upper surface of the metal layer and extend through the upper surface of the top solder resist layer, the lower surface of the metal layer is connected to the solder ball and the solder ball extends through the lower surface of the bottom solder resist layer.

4. The chip packaging structure according to claim 2, characterized in that, The first stress buffer layer, the second stress buffer layer, and the third stress buffer layer each comprise at least one of polymer-based, inorganic ceramic, silicone resin-based, and epoxy resin.

5. The chip packaging structure according to claim 4, characterized in that, The first stress buffer layer, the second stress buffer layer, and the third stress buffer layer have the same composition.

6. The chip packaging structure according to claim 2, characterized in that, The thickness range of the first stress buffer layer, the second stress buffer layer and the third stress buffer layer is [1um, 100um], and the elastic modulus range of the first stress buffer layer, the second stress buffer layer and the third stress buffer layer is [0.1GPa, 5GPa] in the temperature range of [20℃, 25℃].

7. The chip packaging structure according to claim 1, characterized in that, The encapsulation layer is made of a light-transmitting material; The chip packaging structure also includes a light-shielding layer, and the light transmittance of the light-shielding layer is lower than that of the packaging layer; The light-shielding layer is connected to a portion of the lower surface of the encapsulation layer, and the light-shielding layer is used to prevent light from entering the encapsulation layer from the lower surface side of the lead frame.

8. The chip packaging structure according to claim 7, characterized in that, The encapsulation layer includes a first encapsulation portion and a second encapsulation portion, wherein the first encapsulation portion fills the through holes on the lead frame, and the second encapsulation portion fills the recessed area on the lower surface of the lead frame; The light-shielding layer is attached to the lower surface of the first encapsulation part and the lower surface of the second encapsulation part.

9. The chip packaging structure according to claim 7, characterized in that, The light-shielding layer fills the through holes on the lead frame and the recessed area on the lower surface of the lead frame.

10. A chip packaging structure, characterized in that, include: Chip, lead frame, packaging layer, and light-shielding layer; The back side of the chip is attached to the upper surface of the lead frame; The encapsulation layer is attached to the upper surface of the lead frame, and the chip is encapsulated by the encapsulation layer, which includes a light-transmitting material. The chip has a first pad on its front side and an electrical pad on its lead frame. The first pad and the electrical pad are electrically connected by a bonding wire. The front and back sides of the chip are opposite each other. The light-shielding layer is connected to a portion of the lower surface of the encapsulation layer. The light-shielding layer is used to prevent light from entering the encapsulation layer from the lower surface side of the lead frame. The light transmittance of the light-shielding layer is lower than that of the encapsulation layer.

11. The chip packaging structure according to claim 10, characterized in that, The encapsulation layer includes a first encapsulation portion and a second encapsulation portion, wherein the first encapsulation portion fills the through holes on the lead frame, and the second encapsulation portion fills the recessed area on the lower surface of the lead frame; The light-shielding layer is attached to the lower surface of the first encapsulation part and the lower surface of the second encapsulation part.

12. The chip packaging structure according to claim 10, characterized in that, The light-shielding layer fills the through holes on the lead frame and the recessed area on the lower surface of the lead frame.

13. A method for manufacturing a chip packaging structure, characterized in that, include: The back side of the chip is attached to the upper surface of the lead frame, and electrical pads are provided on the lead frame. Bonding wires are provided to electrically connect the first pad on the front side of the chip to the electrical pad, wherein the front side and the back side of the chip are opposite each other; A first stress buffer layer is provided on at least a portion of the front and side surfaces of the chip, and a second stress buffer layer is provided on at least a portion of the surface of the lead frame that is not attached to the chip. The first stress buffer layer and the second stress buffer layer are cured. The chip and the lead frame are encapsulated in a plastic encapsulation layer, which covers at least a portion of the surface of the chip and adheres to the upper surface of the lead frame.

14. The method according to claim 13, characterized in that, The method further includes: providing a third stress buffer layer on at least a portion of the bonding wire surface that is not in contact with the first pad and the electrical pad.

15. The method according to claim 14, characterized in that, The provision of a first stress buffer layer on at least a portion of the front and side surfaces of the chip, and the provision of a second stress buffer layer on at least a portion of the surface of the lead frame not attached to the chip, includes: The first stress buffer layer is sprayed or dipped onto at least a portion of the front and side surfaces of the chip, and the second stress buffer layer is sprayed or dipped onto at least a portion of the surface of the lead frame that is not attached to the chip. The provision of a third stress buffer layer on at least a portion of the bonding wire surface that is not in contact with the first pad and the electrical pad includes: The third stress buffer layer is sprayed or dipped onto at least a portion of the bonding wire surface that is not in contact with the first pad and the electrical pad.

16. An electronic device, characterized in that, Includes the chip packaging structure as described in any one of claims 1-9.

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