IC packaging structure and IC chip transfer method

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an IC packaging structure and an IC chip transfer method. The IC packaging structure comprises a temporary substrate, a plurality of IC chips arranged at intervals, a temporary spacing layer and a temporary anchor chain layer. The plurality of IC chips are arranged at intervals, each IC chip is provided with a first surface and a second surface which are opposite to each other, and a side surface positioned between the first surface and the second surface; the temporary spacer layer is located on the temporary substrate; a plurality of grooves arranged at intervals are formed in the surface of one side, deviating from the temporary substrate, of the temporary spacing layer; the temporary anchor chain layer covers at least part of the first surfaces and the side faces of the IC chips and extends to the surface of the side, away from the temporary substrate, of the temporary spacer layer so as to be connected with the IC chips and enable the IC chips to be suspended above the grooves in a one-to-one correspondence mode, and the IC chips are not in contact with the temporary spacer layer. Through the above design, the packaging efficiency and the preparation yield can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an IC packaging structure and an IC chip transfer method. Background Technology

[0002] In the field of IC wafer fabrication and packaging, with the increasing demand for miniaturization and high-density packaging, the size of IC chips continues to shrink (e.g., the target size of a single IC chip reaches 107×107μm), while the requirements for wafer thickness reduction are becoming increasingly stringent (e.g., the thickness of the incoming material needs to be reduced from 780μm to 10μm). To achieve large-scale mass production of such micro IC chips, mass transfer technology has become the core key, but the conventional grinding, cutting, and packaging processes used in existing technologies have many technical bottlenecks that are difficult to overcome.

[0003] Specifically, conventional processes require first thinning thick wafers to the target thickness through grinding, then dicing and separating individual chips, followed by packaging. This process involves multiple fine grinding steps, and the cutting process suffers from high tool wear and difficult trajectory control, resulting in extremely low production efficiency and failing to meet the demands of large-scale mass production. Furthermore, the cutting precision is difficult to match the size requirements of micro-IC chips, easily causing chip size deviations and affecting the compatibility of subsequent packaging. Therefore, solving the efficiency and precision problem of conventional grinding, cutting, and packaging processes is a challenge that needs to be addressed by those skilled in the art. Summary of the Invention

[0004] This invention provides an IC packaging structure that can solve at least one problem in the prior art to effectively improve the efficiency and yield of IC packaging.

[0005] An embodiment of the present invention provides an IC packaging structure, including a temporary substrate, a plurality of spaced IC chips, a temporary spacer layer, and a temporary anchor chain layer; the IC chips have opposing first surfaces, second surfaces, and a side surface located between the first and second surfaces; the temporary spacer layer is located on the temporary substrate; the temporary spacer layer has a plurality of spaced grooves on its surface away from the temporary substrate, the grooves accommodating the IC chips; the temporary anchor chain layer covers at least a portion of the first surfaces and side surfaces of the plurality of IC chips, and extends to the surface of the temporary spacer layer away from the temporary substrate, so as to interconnect the plurality of IC chips and such that the IC chips are suspended one-to-one above the grooves, and the IC chips are not in contact with the temporary spacer layer.

[0006] Another embodiment of the present invention provides an IC chip transfer method, comprising the following steps: providing an IC packaging structure as described in the above embodiment and providing a substrate; applying pressure to the IC chip to be transferred, causing the temporary anchor chain layer located between adjacent IC chips to break, and transferring the IC chip onto the substrate.

[0007] The IC packaging structure provided in this invention, through the design of temporary anchor chain layer, temporary spacer layer and groove, eliminates the need to cut and separate IC wafers individually. Instead, it connects several IC chips into a whole through temporary anchor chain layer. At the same time, the groove of temporary spacer layer enables precise pre-positioning of each IC chip, ensuring that the chip spacing and dimensional accuracy are controllable during the transfer process, effectively improving packaging efficiency and manufacturing yield.

[0008] Other features and beneficial effects of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a cross-sectional schematic diagram of an IC packaging structure provided in an embodiment of the present invention; Figure 2 This is a cross-sectional schematic diagram of an IC packaging structure provided in another embodiment of the present invention; Figure 3 This is a top view schematic diagram of an IC packaging structure provided in an embodiment of the present invention; Figure 4 This is a top view schematic diagram of an IC packaging structure provided in another embodiment of the present invention; Figure 5 This is a top view schematic diagram of the IC packaging structure provided in other embodiments of the present invention.

[0011] Figure label: 10. Temporary substrate; 20. IC chip; 21. First surface; 22. Second surface; 23. Side surface; 30. Temporary spacer layer; 31. Groove; 40. Temporary anchor chain layer; 41. Surface cover section; 42. Side cover section; 43. Connecting cover section. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings; the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0013] It should also be noted that the structural diagrams provided in the embodiments of the present invention are intended to more clearly express the structural features of the IC packaging structure, but are not made to scale.

[0014] This invention provides an IC packaging structure, including: a temporary substrate 10, a plurality of spaced IC chips 20, a temporary spacer layer 30, and a temporary anchor chain layer 40. The IC chips 20 have opposing first surfaces 21 and second surfaces 22, and a side surface 23 located between the first surface 21 and the second surface 22. The temporary spacer layer 30 is located on the temporary substrate 10. The temporary spacer layer 30 has a plurality of spaced grooves 31 on its surface facing away from the temporary substrate 10, the grooves 31 accommodating the IC chips 20. The temporary anchor chain layer 40 covers at least a portion of the first surfaces 21 and side surfaces 23 of the plurality of IC chips 20, and extends to the surface of the temporary spacer layer 30 facing away from the temporary substrate 10, to interconnect the plurality of IC chips 20 and such that the IC chips 20 are suspended one-to-one above the grooves 31, with no contact between the IC chips 20 and the temporary spacer layer 30.

[0015] In one embodiment, the temporary substrate 10 is a transparent material, and the coefficient of thermal expansion of the temporary substrate 10 is between 2 and 3.5.

[0016] In one embodiment, the temporary substrate 10 is made of silicon or glass.

[0017] In one embodiment, the temporary spacer layer 30 is a transparent material.

[0018] In one embodiment, the temporary anchor chain layer 40 is made of a transparent insulating material.

[0019] In one embodiment, the material of the temporary anchor chain layer 40 is selected from one or more combinations of SiN and SiO2.

[0020] In one embodiment, the thickness h of the temporary anchor chain layer 40 is between 2000 angstroms and 10200 angstroms.

[0021] In one embodiment, the second surface 22 of the IC chip 20 faces the groove 31, and along a direction perpendicular to the temporary substrate 10, the second surface 22 of the IC chip 20 is not lower than the side surface of the temporary spacer layer 30 facing away from the temporary substrate 10.

[0022] In one embodiment, the gap width W1 between the temporary anchor chain layers 40 covering the opposite sides 23 of the adjacent IC chips 20 is greater than 20 μm.

[0023] In one embodiment, the gap width W1 between the temporary anchor chain layers 40 covering the opposite sides 23 of the adjacent IC chips 20 is between 30 μm and 40 μm.

[0024] In one embodiment, the temporary anchor chain layer 40 covers a portion of the side 23 of the IC chip 20.

[0025] In one embodiment, the temporary anchor chain layer 40 covers an area of ​​1 / 5 to 1 / 3 of the total area of ​​the side surface 23 of the IC chip 20.

[0026] In one embodiment, the temporary anchor chain layer 40 covers a width W2 of the side 23 of the IC chip 20 that is 1 / 5 to 1 / 3 of the width W3 of the side 23 of the IC chip 20.

[0027] This invention also provides an IC chip 20 transfer method, comprising the following steps: providing an IC packaging structure as described in any of the above embodiments, providing a substrate; applying pressure to the IC chip 20 to be transferred, causing the temporary anchor chain layer 40 located between adjacent IC chips 20 to break, and transferring the IC chip 20 onto the substrate.

[0028] The technical solution of the present invention will now be described and explained in detail through various specific embodiments and accompanying drawings.

[0029] Example 1 Please see Figure 1 , Figure 2 , Figure 1 This is a cross-sectional schematic diagram of an IC packaging structure provided in an embodiment of the present invention; Figure 2 This is a cross-sectional schematic diagram of an IC packaging structure provided in another embodiment of the present invention. The IC packaging structure provided in Embodiment 1 of the present invention includes at least a temporary substrate 10, a plurality of IC chips 20 spaced apart, a temporary spacer layer 30, and a temporary anchor chain layer 40.

[0030] In this embodiment, the temporary substrate 10 is made of a transparent material to meet the light transmittance requirements of the packaging structure. Specifically, the temporary substrate 10 has a transmittance of not less than 85% in the visible light band of 380nm~760nm, ensuring that the IC chip 20 on the other side can be clearly observed with the naked eye through the temporary substrate 10, facilitating real-time detection of the positioning accuracy and integrity of the IC chip 20 during the process; more preferably, it has a transmittance of not less than 90%. The material of the temporary substrate 10 can be flexibly selected according to the actual application scenario.

[0031] Preferably, the coefficient of thermal expansion of the temporary substrate 10 is between 2 and 3.5. Compared to conventional processes that use sapphire substrates as temporary substrates 10, this embodiment, by limiting the coefficient of thermal expansion, can effectively reduce the thermal stress caused by temperature changes in subsequent processes, avoiding damage or deformation of the IC chip 20 due to thermal stress. This is especially beneficial for micro-IC chips 20, significantly reducing transfer deviations caused by thermal stress. Furthermore, the smaller the chip size, the more pronounced the impact of mismatched coefficients of thermal expansion on transfer accuracy. This temporary substrate 10, through precise matching of the coefficient of thermal expansion, fundamentally ensures the positional accuracy of the mass transfer of micro-IC chips 20. Simultaneously, the transparency of the temporary substrate 10 facilitates visual inspection of the IC chip 20 on the other side throughout the production process, enabling real-time verification of the chip's arrangement, integrity, and positioning accuracy. This provides support for precise process control and further ensures the stability of mass transfer and subsequent packaging processes. As an example, the material of the temporary substrate 10 is selected from silicon or glass to satisfy a coefficient of thermal expansion between 2 and 3.5.

[0032] Several IC chips 20 are spaced apart. Each IC chip 20 has a dedicated driving control circuit to drive and control the corresponding light-emitting elements. The specific circuit design is determined according to actual needs and is not limited in this embodiment. In this embodiment, the IC chip 20 is defined to have a first surface 21 and a second surface 22 opposite to each other, and a side surface 23 located between the first surface 21 and the second surface 22, wherein the second surface 22 faces the temporary substrate 10. As an example, the size of the IC chip 20 is less than 110 μm; for example, the IC chip 20 is a rectangular structure with a size of 107 × 107 μm, and the thickness of the IC chip 20 is preferably less than 12 μm.

[0033] A temporary spacer layer 30 is located on the temporary substrate 10. The temporary spacer layer 30 is made of a transparent material. In this embodiment, the temporary spacer layer 30 preferably uses a material that is transparent, laser-exfoliable, and resistant to acids and alkalis. Its transparency allows for visual observation of the bonding interface during the bonding process between the temporary spacer layer 30, the temporary substrate 10, and the temporary anchor chain layer 40, facilitating real-time monitoring for issues such as bubbles, misalignment, or loose bonding, ensuring that the bonding quality meets process requirements. Its acid and alkali resistance allows the temporary spacer layer 30 to maintain structural stability during subsequent acid and alkali treatment processes such as etching and cleaning in the packaging process, preventing swelling, damage, or failure, and ensuring the smooth progress of the entire process chain. Its laser-exfoliable characteristic provides an efficient and precise method for peeling off the temporary spacer layer 30 after mass transfer, enabling rapid separation of the temporary spacer layer 30 and the temporary anchor chain layer 40 without damaging the IC chip 20 or other core structures, thus improving production efficiency.

[0034] Please continue reading. Figure 1 , Figure 2 The temporary spacer layer 30 has several spaced grooves 31 on its surface facing away from the temporary substrate 10. The contours of the grooves 31 are adapted to accommodate the IC chips 20. By pre-setting the size and spacing of the grooves 31, the relative positions of each IC chip 20 can be pre-locked, laying a structural foundation for the subsequent connection and fixation of the temporary anchor chain layer 40 and the precise positioning during mass transfer, effectively avoiding problems such as chip displacement and skewness during transfer. The depth of the grooves 31 can be reasonably set according to actual needs; that is, the depth of the grooves 31 can be greater than, less than, or equal to the height of the IC chips 20.

[0035] A temporary anchor chain layer 40 covers at least a portion of the first surface 21 and side surface 23 of a plurality of IC chips 20 and extends to the side surface of the temporary spacer layer 30 opposite to the temporary substrate 10, so as to connect the plurality of IC chips 20 to each other and such that the IC chips 20 are suspended one-to-one above the groove 31, and the IC chips 20 are not in contact with the temporary spacer layer 30.

[0036] In specific implementation, the temporary anchor chain layer 40 is made of a transparent insulating material. In this embodiment, the material of the temporary anchor chain layer 40 is preferably selected from one or more combinations of SiN and SiO2; that is, the temporary anchor chain layer 40 can be an insulating material composed of SiN, SiO2, or a combination of SiN and SiO2. As an example, the thickness h of the temporary anchor chain layer 40 is between 2000 angstroms and 10200 angstroms, for example, a thickness h is preferably 5000 angstroms. This limited range ensures structural strength for stable support and connection of the IC chip 20, while also possessing good breakable and separable characteristics, facilitating disassembly after subsequent transfer.

[0037] Furthermore, the extended connection of the temporary anchor chain layer 40 ensures that the IC chip 20 maintains a gap with the inner wall and bottom of the groove 31, achieving a completely contactless suspended setup. That is, the IC chip 20 is suspended above the groove 31 by relying on the partial connection between the temporary anchor chain layer 40 and the temporary spacer layer 30. This avoids damage to the IC chip 20 caused by contact friction or stress transmission, and also provides clearance for the subsequent transfer device to grasp the IC chip 20, ensuring that the grasping action is accurate and efficient and does not interfere with the temporary spacer layer 30, further guaranteeing the packaging quality and the yield of mass transfer.

[0038] The temporary anchor chain layer 40 can cover part of the first surface 21 and part of the side surface 23 of the IC chip 20 and extend to the surface of the temporary spacer layer 30, and further extend to part of the side surface 23 and part of the first surface 21 of the adjacent IC chip 20, thereby connecting several spaced IC chips 20 into an integrated whole, and precisely adhering to the peripheral area of ​​the groove 31 to form a connection, ensuring the relative position stability of each chip during the mass transfer process. Of course, the temporary anchor chain layer 40 can also cover the entire first surface 21 of the IC chip 20 and extend to part of the side surface 23.

[0039] Please see Figure 3 In this embodiment, the temporary anchor chain layer 40 preferably covers a portion of the side surface 23 of the IC chip 20. Specifically, the temporary anchor chain layer 40 does not completely cover all the side surfaces 23 of the IC chip 20, but only a portion of them. This design reduces the amount of material used in the temporary anchor chain layer 40 while ensuring the connection and positioning strength of the IC chip 20. Furthermore, it creates a structurally weak area at the connection points between adjacent chips, facilitating rapid and precise breakage of the temporary anchor chain layer 40 in this area under external force. After the mass transfer is complete, only a small amount of mechanical or thermal stress is needed to cause the connection points between adjacent chips to break, effectively separating the previously connected IC chips 20. This ensures the efficiency of the chip separation process, avoids separation difficulties caused by excessive anchor chain layer coverage, and prevents damage to the surface and side surface 23 functional structures of the IC chip 20 during separation, significantly improving the yield after chip transfer and the compatibility with subsequent packaging processes.

[0040] When several IC chips 20 are arranged in an array, and the IC chips 20 are rectangular chips, each IC chip 20 has a closed rectangular side frame formed by two sets of opposing side surfaces 23. The temporary anchor chain layer 40 can then cover only one set of opposing side surfaces 23 of the IC chip 20 (the other set of opposing side surfaces 23 of the IC chip 20 may not cover the temporary anchor chain layer 40) and extend to one set of opposing side surfaces 23 of the adjacent IC chip 20. Specifically, as follows... Figure 4 , Figure 5 As shown, adjacent IC chips 20 arranged in an array form a first channel extending along the X-axis and a second channel extending along the Y-axis. The temporary anchor chain layer 40, in addition to covering the first surface 21 of the IC chip 20, also covers a portion of the side surface 23 of the adjacent IC chip 20 located in the first channel. The temporary anchor chain layer 40 connects the adjacent IC chips 20 by extending and covering the surface of the temporary spacer layer 30 at the first channel. The side surface 23 of the IC chip 20 and the surface of the temporary spacer layer 30 at the second channel may not be covered by the temporary anchor chain layer 40 to avoid excessive bonding force between the temporary anchor chain layer 40 and the IC chip 20, which could prevent the temporary anchor chain layer 40 from breaking.

[0041] In an optional embodiment, the temporary anchor chain layer 40 covers an area of ​​1 / 5 to 1 / 3 of the total area of ​​the side surface 23 of the IC chip 20.

[0042] In practical implementation, the aforementioned area ratio refers to the ratio of the coverage area of ​​the temporary anchor chain layer 40 on a single side 23 of the IC chip 20 to the total geometric area of ​​that single side 23. For an IC chip 20 with multiple sides 23, this ratio applies to each covered side 23. When the coverage area ratio is less than 1 / 5, the bonding area between the temporary anchor chain layer 40 and the IC chip 20 is too small, resulting in weak bonding force. This makes it impossible to provide stable support and positioning for the IC chip 20 during mass transfer, easily leading to chip displacement and detachment. When the coverage area ratio is greater than 1 / 3, the bonding area between the anchor chain layer and the chip side 23 is too large, and the structural strength of the anchor chain layer connection between adjacent chips is too high. This makes it difficult to break precisely under external force, increasing the difficulty of chip separation and potentially damaging the IC chip 20 due to forced separation. A ratio range of 1 / 5 to 1 / 3 achieves a balance between bonding force and breakability, ensuring structural stability during the transfer process while facilitating subsequent non-destructive chip separation.

[0043] In another alternative implementation, please refer to Figure 3 , Figure 4 , Figure 5 The width W2 of the temporary anchor chain layer 40 covering the side 23 of the IC chip 20 is 1 / 5 to 1 / 3 of the width W3 of the side 23 of the IC chip 20.

[0044] Here, width W2 refers to the coverage width of the temporary anchor chain layer 40 on the side 23 of the IC chip 20 along a preset direction (such as the chip arrangement direction), and width W3 is the total geometric width of the side 23 of the IC chip 20 in the same direction. Similarly, by limiting 1 / 5W3≤W2≤1 / 3W3, on the one hand, it can avoid the temporary anchor chain layer 40 and the side 23 of the IC chip 20 having too narrow a contact width, resulting in insufficient bonding force and difficulty in providing stable support for the IC chip 20; on the other hand, it can avoid the temporary anchor chain layer 40 covering the side 23 of the chip having too large a coverage width, resulting in excessively high structural strength at the connection part of the temporary anchor chain layer 40 between adjacent IC chips 20, making it difficult to break accurately under external force and increasing the difficulty of chip separation.

[0045] Based on the above design, in order to achieve precise breakage of the temporary anchor chain layer 40, this embodiment preferably provides a pre-breakage structure at the temporary anchor chain layer 40 between adjacent IC chips 20. The pre-breakage structure includes one or more evenly distributed grooves 31 or through slots, such as V-shaped grooves extending inward from the edge of the temporary anchor chain layer 40, one or more rectangular or circular through slots penetrating the thickness of the anchor chain layer, spaced dot-shaped pits, or linear shallow grooves extending along the chip arrangement direction. That is, by locally thinning the thickness of the temporary anchor chain layer 40, a structural stress concentration area is formed at the connection point of adjacent chips, thereby guiding the temporary anchor chain layer 40 to break precisely at a preset position. The design of this pre-breakage structure can effectively reduce the external force threshold required for breakage, and the breakage path is completely controllable. It avoids the problems of random breakage position and excessive breakage stress of the temporary anchor chain layer 40 without a pre-breakage structure, and prevents damage, displacement, or functional failure of the IC chip 20 due to forced pulling, further ensuring the yield and stability of the chip separation process after the mass transfer is completed.

[0046] For further information, please refer to [link / reference]. Figure 3 The temporary anchor chain layer 40 includes a side cover section 42 covering the IC chip 20, a surface cover section 41 covering the first surface 21 of the IC chip 20, and a connecting cover section 43 covering the surface of the temporary spacer layer 30. The side cover sections 42 covering the opposite sides 23 of adjacent IC chips 20 are connected by the connecting cover sections 43. In this design, the side cover sections 42 only serve to cover and position a single IC chip 20. The non-overlapping projection design avoids the side cover sections 42 of adjacent chips forming spatial cross connections, preventing excessive stress concentration in the chip side 23 area. The connecting cover section 43 acts as a bridge between the side cover sections 42 of adjacent chips, specifically undertaking the connection function between chips. Simultaneously, a pre-break structure can be precisely set on the connecting cover section 43, so that the fracture stress is completely concentrated in this area.

[0047] Please see Figure 4 When the temporary anchor chain layer 40 covers part of the side 23 of the adjacent IC chip 20, the side covering section 42 covering the opposite side 23 of the adjacent IC chip 20 does not overlap with the projection on the vertical projection plane parallel to the width direction of the corresponding side 23 of the IC chip 20.

[0048] In specific implementation, the vertical projection plane parallel to the width direction of the corresponding side 23 of the IC chip 20 refers to a plane that is parallel to the width direction of the side 23 of the IC chip 20 and perpendicular to the surface of the temporary substrate 10 as the projection reference plane (e.g., Figure 4(The vertical projection plane along the X-axis is shown). The projections do not overlap, which means that the areas formed by the side covering sections 42 that cover the opposite sides 23 of two adjacent IC chips 20 after being projected onto the projection reference plane have no intersection, and the gap between them is connected and transitioned by the connecting covering section 43.

[0049] This design ensures that the side coverage sections 42 of adjacent IC chip sides 23 are independent covering sections from a spatial structure perspective, and are connected only by the connecting coverage section 43 located at the chip gap, effectively avoiding cross-coverage of the anchor chain layer in the side 23 area. If the projection of the side coverage section 42 partially or completely overlaps, the connection strength of the anchor chain layer between adjacent chips will be relatively strong, and the stress will easily be transmitted to the chip side 23 when it breaks. This will not only significantly increase the external force threshold required for the anchor chain layer to break, but also cause the fracture site to deviate due to the disordered stress transmission path, resulting in irregular pulling of adjacent IC chips 20 during separation, leading to problems such as chip displacement, damage to the functional layer of side 23, or even chip breakage. However, the non-overlapping projection design of this embodiment can concentrate the fracture stress at the weak position between the connecting coverage section 43 and the side coverage section 42. Under the action of external force, the anchor chain layer can crack precisely along the preset path, which not only ensures the structural stability of the chip array during the mass transfer process, but also avoids damage to the functional layer of side 23 of IC chip 20 caused by the separation process, significantly improving the yield and reliability of micro IC chip 20 packaging.

[0050] Preferably, the second surface 22 of the IC chip 20 faces the groove 31, and along a direction perpendicular to the temporary substrate 10, the second surface 22 of the IC chip 20 is not lower than the side surface of the temporary spacer layer 30 facing away from the temporary substrate 10.

[0051] In specific implementation, the direction perpendicular to the temporary substrate 10 is used as the reference for the height direction, and the surface of the temporary spacer layer 30 facing away from the temporary substrate 10 is used as the height reference surface; the second surface 22 of the IC chip 20 is not lower than this reference surface, that is, the horizontal height of the second surface 22 of the chip is higher than or equal to the horizontal height of the reference surface, and the chip can be in a state of "protruding from the surface of the temporary spacer layer 30", wherein the second surface 22 can be flush with the reference surface, such as... Figure 1 As shown.

[0052] This design allows the second surface 22 of the IC chip 20 to be fully exposed on or flush with the surface of the temporary spacer layer 30, preventing the chip from being encased by the sidewalls due to being trapped in the groove 31. On one hand, the exposed second surface 22 provides ample adhesion space for the coating of the temporary anchor chain layer 40, ensuring that the anchor chain layer can simultaneously cover part of the chip's side surface 23 and the first surface 21, forming a stable encapsulation and positioning structure. On the other hand, the chip structure, protruding from or flush with the reference surface, also provides a clear point of action for the precise gripping of the mass transfer device, avoiding collision interference with the temporary spacer layer 30 during gripping, and further reducing the risk of damage during chip transfer.

[0053] In an alternative embodiment, the gap width W1 between the temporary anchor chain layers 40 covering the opposite sides 23 of the adjacent IC chips 20 is greater than 20 μm.

[0054] In specific implementation, such as Figure 1 , Figure 2 As shown, the gap width W1 refers to the minimum horizontal distance between the side cover sections 42 of the temporary anchor chain layer 40 on the opposite sides 23 of two adjacent IC chips 20. The preferred value of W1 is 20μm~50μm, more preferably 30μm~40μm, and can be adapted and adjusted according to the size of the IC chip 20 and subsequent process requirements. This limited gap width can effectively avoid stress coupling caused by the side cover sections 42 of adjacent chips being too close together, prevent the anchor chain layer from deforming during the mass transfer process, and ensure that the external force can be accurately applied to the connection between the side cover section 42 and the connecting cover section 43 of adjacent chips during the separation process. On the other hand, a gap greater than 20μm can reserve enough space to set the side cover section 42 and the connecting cover section 43, avoiding the overlap or structural distortion of the boundaries of the two types of cover sections due to limited space, and ensuring the yield of the process.

[0055] Example 2 Based on the above, Embodiment 2 of the present invention also provides an IC chip transfer method, comprising the following steps: Provides an IC packaging structure as described in Embodiment 1 above; Provide substrate; Pressure is applied to the IC chip 20 to be transferred, causing the temporary anchor chain layer 40 located between adjacent IC chips 20 to break, and the IC chip 20 is transferred onto the substrate.

[0056] In practice, the provided IC packaging structure is first positioned and fixed. Preferably, a vacuum adsorption platform is used to adsorb and fix the temporary substrate 10 on the side opposite to the IC chip 20, ensuring the packaging structure maintains stability during subsequent pressure application. Simultaneously, the provided substrate must be pre-cleaned and marked with positioning marks. The positioning marks on the substrate must match the array arrangement rules of the IC chips 20 to be transferred in the IC packaging structure, facilitating precise alignment during subsequent chip transfer.

[0057] Based on this, a suitable transfer device is used to precisely align with the central area of ​​the surface of a single IC chip 20 and apply pressure to break the temporary anchor chain layer 40. The direction of the applied pressure is perpendicular to the surface of the temporary substrate 10, and the pressure magnitude is adapted and adjusted according to the material properties of the temporary anchor chain layer 40 and the structural dimensions of the connection cover section 43 to ensure that the pressure can be precisely applied to the connection cover section 43 between adjacent chips to cause it to break, while avoiding excessive pressure that could damage the functional structure of the IC chip 20.

[0058] The specific structure, function, and purpose of the IC packaging structure can be referred to the content of the aforementioned Embodiment 1, and will not be repeated here.

[0059] The above-mentioned IC chip transfer method can achieve efficient and accurate transfer of IC chip 20, effectively improving the yield of mass transfer of IC chip 20.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An IC packaging structure, characterized in that, include: Temporary substrate; A plurality of IC chips are spaced apart, the IC chips having opposing first surfaces, second surfaces, and a side surface located between the first surface and the second surface; A temporary spacer layer is located on the temporary substrate; the temporary spacer layer has a plurality of spaced grooves on its surface away from the temporary substrate, the grooves accommodating the IC chip; A temporary anchor chain layer covers at least a portion of the first surface and side of a plurality of IC chips and extends to the side surface of the temporary spacer layer opposite to the temporary substrate, so as to interconnect the plurality of IC chips and such that the IC chips are suspended one-to-one above the groove, and the IC chips are not in contact with the temporary spacer layer.

2. The IC packaging structure according to claim 1, characterized in that: The temporary substrate is a transparent material, and the coefficient of thermal expansion of the temporary substrate is between 2 and 3.

5.

3. The IC packaging structure according to claim 1, characterized in that: The temporary substrate is made of silicon or glass.

4. The IC packaging structure according to claim 1, characterized in that: The temporary spacer layer is made of a transparent material.

5. The IC packaging structure according to claim 1, characterized in that: The temporary anchor chain layer is made of transparent insulating material.

6. The IC packaging structure according to claim 1, characterized in that: The material of the temporary anchor chain layer is selected from one or more combinations of SiN and SiO2.

7. The IC packaging structure according to claim 1, characterized in that: The thickness h of the temporary anchor chain layer is between 2000 angstroms and 10200 angstroms.

8. The IC packaging structure according to claim 1, characterized in that: The second surface of the IC chip faces the groove, and along a direction perpendicular to the temporary substrate, the second surface of the IC chip is not lower than the side surface of the temporary spacer layer that faces away from the temporary substrate.

9. The IC packaging structure according to claim 1, characterized in that: The gap width W1 between the temporary anchor chain layers covering the opposite sides of the adjacent IC chips is greater than 20 μm.

10. The IC packaging structure according to claim 1, characterized in that: The gap width W1 between the temporary anchor chain layers covering the opposite sides of the adjacent IC chips is between 30 μm and 40 μm.

11. The IC packaging structure according to claim 1, characterized in that: The temporary anchor chain layer covers part of the side of the IC chip.

12. The IC packaging structure according to claim 1, characterized in that: The temporary anchor chain layer covers an area of ​​1 / 5 to 1 / 3 of the total side area of ​​the IC chip.

13. The IC packaging structure according to claim 1, characterized in that: The width W2 of the temporary anchor chain layer covering the side of the IC chip is 1 / 5 to 1 / 3 of the side width W3 of the IC chip.

14. A method for transferring an IC chip, characterized in that, Includes the following steps: Provides an IC packaging structure as described in any one of claims 1 to 13; Provide substrate; Pressure is applied to the IC chip to be transferred, causing the temporary anchor chain layer located between adjacent IC chips to break, and the IC chip is transferred onto the substrate.

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