System and method for synchronizing and aligning multiple modules on same clock

Abstract

A system and method for synchronizing a module A (110) with each module Bj (120) of a set of modules S, where j = 1, M > = 1, and S = {B1,..., BM}, where module A (110) is configured for operation in synchronization with a clock signal CKA (210) of a period T, and module Bj (120) is configured for operation in synchronization with a clock signal CKBj of said period T, where M > = 1, and S = {B1,..., BM}. The method comprises: for each pair of modules formed by a module A (110) and a module Bj (120) of said modules Bj (120) and according to a total adjustment time TTDj calculated for each pair of modules; adjusting or controlling, by a phase adjustment circuit, a relative time between an arrival time at which signal SAj data arrives at a sampling position of a sampling means of a module Bj (120) and a sampling time of the data by the sampling means of the module Bj, the sampling time being directly adjacent in time to the arrival time; wherein the total adjustment time TTDj is configured for both sampling by the sampling means of the module A (110) a data value of a signal SBj sent by the module Bj (120) to the module A and sampling by the sampling means of the module Bj (120) a data value of a signal SAj, the time interval between the arrival of the data at the sampling position of the considered sampling component and the data sampling of the considered sampling component is increased, where the time at which the data sampling occurs is directly adjacent in time to the time at which the data arrives at the sampling position of the considered sampling component.

Description

Technical Field

[0001] This invention relates to synchronizing and aligning multiple modules on a common clock. Aspects of the invention particularly relate to simulation, and more precisely to clock latency in simulation systems comprising multiple modules (e.g., multiple integrated circuits or integrated circuit chips (hereinafter collectively referred to as "ICs")). Background Technology

[0002] Clock latency is a particularly important parameter in simulation systems, especially when high precision is required. Such systems typically involve ICs that need to communicate with each other at relatively high rates, where signals or data are sent and received synchronously with a clock. Typically, ICs use a reference clock signal to synchronize their operation or actions, such as sampling data values ​​from input signals or changing or holding data values ​​in output signals. This reference clock signal can be received by the IC from a global source clock signal centrally distributed to all ICs in the same simulation system, or it can be generated internally by the IC (e.g., using an internal electronic oscillator) and distributed to one or more other ICs.

[0003] Therefore, the corresponding clock signals used by ICs in a group or network of ICs that need to work synchronously with each other all have the same constant frequency. However, and unfortunately, because the amount of time it takes for the reference clock signal to travel and arrive at each IC in the group is different, the corresponding clock signals may be slightly out of phase or delayed. This can then prevent all the ICs in the group from operating or synchronizing together. In other words, the corresponding clocks of two ICs in the group that need to exchange data or synchronize their operations may be at slightly different times. The delay between the clock of the IC sending data and the clock of the IC receiving the data is commonly referred to as "clock skew." More generally, clock skew refers to the instantaneous difference between the clock time of the first IC and the clock time of the second IC communicating with the first IC.

[0004] Clock skew is problematic. In fact, when data is received by an IC whose clock is out of sync with the clock of the IC that sends the data, there is a risk that the data may be lost or distorted due to incorrect sampling by the latter.

[0005] To address this problem, it is known to link ICs in a daisy chain and propagate a start signal from the first IC in the chain to the last IC. Then, based on the delay time for the start signal to travel through the chain, it is possible to wait for the start signal to reach the last IC to initiate synchronous operation. However, this solution is unsuitable for new network configurations of ICs, where they are typically distributed in a star topology, and all ICs in the emulator system are directly connected to each other for bidirectional data exchange. Typically, in a daisy chain, the first IC is not directly connected to the last IC, but rather via a series of interconnected ICs in between, thus using a short connecting cable to the last IC. Conversely, in this new configuration, the first IC would be directly connected to the last IC, significantly increasing the cable length and therefore the data propagation time. Therefore, synchronous signal exchange is no longer possible in such a configuration. In fact, clock skew, along with the delay caused by the propagation time of the start signal through the cable length (typically tens of meters), makes synchronous signal exchange impossible.

[0006] Therefore, despite existing solutions, there is still a need to improve the synchronization of ICs that must work together, especially to improve sampling accuracy. Summary of the Invention

[0007] The purpose of this invention is to provide a method and system for synchronizing multiple modules on a clock signal so as to enable synchronous sampling of exchanged data.

[0008] This objective is achieved by the measures adopted according to the independent claim. The dependent claims propose further advantageous embodiments.

[0009] According to one aspect of the invention, a method is proposed for making module A compatible with each module B in set S. j The synchronization method, where j=1,...,M, M≥1, and S={B1,...,B...} M The set S therefore includes at least one module, such as module B1. Module A is usually referred to as the "main module," while module B... j This is typically referred to as a "slave module". Module A is configured to operate synchronously with a clock signal CK_A of period T, specifically to trigger actions synchronously with the clock signal CK_A, such as sending a signal to module B synchronously with the clock signal CK_A. j Output, generate, or send signal S_A j Or used to read from module B j Received input signal S_B j (For example, for the input signal S_B) j(The data in the sample is sampled), wherein the reading can be performed synchronously with the clock signal CK_A. Each module B j Configured for use with the clock signal CK_B of the period T j Synchronous operation, particularly for operation with the clock signal CK_B j Synchronously trigger actions, such as with clock signal CK_B j Synchronously read input signal S_A j (For example, used for signal S_A) j (sample the data), or with the clock signal CK_B j Synchronously generate, output, or send signal S_B j In addition, each module B j Includes being configured to perform sampling from module A to module B at the sampling location. j The signal S_A sent j A sampling component that samples data values. The sampling component is typically a trigger configured to sample data at the sampling signal. Specifically, clock A of module A can acquire or generate the clock signal CK_A, and module B... j Clock B j The clock signal CK_B with period T can be acquired or generated. j Specifically, according to the present invention, clock A and clock B... j Between (i.e., between clock signal CK_A and clock signal CK_B) j The deviation between (T / 2) is preferably less than or equal to T / 2.

[0010] According to the present invention, module A and module B j Preferably, the modules are connected to each other via a connecting device, such as one or more cables, the connecting device being configured to ensure that module A is connected to module B. j The data propagation time between modules is the same or substantially the same, regardless of the direction of data propagation, i.e., from module A to module B. j Or from module B j To module A. For example, module A can be connected to module B via a single cable that enables bidirectional data exchange. j This allows module A to transmit data to module B via the cable. j Send signal S_A j And module B j Signal S_B can be sent to module A. j Alternatively, the first cable can connect module A to module B. j So that module A can send data to module B j Send the signal S_A jThe second cable can connect module A to module B. j So that module B j Able to send signal S_B to module A j The first and second cables are configured to ensure that module A is connected to module B by having, for example, the same length and data propagation characteristics. j The propagation time of the signal data between them is the same, regardless of the direction of propagation.

[0011] The method according to the invention includes: for a module B consisting of said module A and a module B from set S. j Each pair of modules is formed and the total adjustment time TT_D is calculated for each pair of modules. j The phase adjustment circuit adjusts or controls the signal S_A. j Data arrives at module B j The arrival time of the sampling position of the sampling component is related to that of module B. j The relative time between the sampling times of the sampling components and the arrival times of the data, wherein the sampling time and the arrival time are directly adjacent in time; and

[0012] Wherein, the total adjustment time TT_D j Configured for: sampling components from module A to those from module B j Signal S_B sent to module A j Data value sampling and by module B j The sampling component for signal S_A j The sampling of data values ​​is both increased (e.g., maximized or optimized) by increasing (e.g., maximizing or optimizing) the time interval between the arrival of data at the sampling position of the considered sampling component and the data sampling of the considered sampling component, wherein the time when the data sampling occurs is directly adjacent in time to the time when the data arrives at the sampling position of the considered sampling component.

[0013] In other words, the present invention proposes a method that can automatically determine the total adjustment time TT_D. j For example, the total adjustment time value can be set automatically for both module A and module B. j Both (i.e., sampling performed on the sampling component of module A and simultaneously on module B) j The sampling unit performs sampling, increasing (e.g., optimizing or maximizing) the time interval between the arrival of data at the sampling position of the sampling unit and any sampling time that is temporally adjacent to that of the sampling unit. Therefore, the total adjustment time TT_D j It is the common phase adjustment value, that is, it is used for both module A and module B. jSecondly, this method applies to two paths (i.e., by the system for the path from module A to module B). j The signals sent and the signals sent to module B j The signal sent to module A is applied to produce an equal phase adjustment value (i.e., the TT_D). j The total phase adjustment value is used to ensure proper balance in sampling the data at the time when data changes occur within the input signal, and this applies to both paths.

[0014] According to another aspect of the invention, a system for synchronizing multiple modules is disclosed. Specifically, the system enables module A to synchronize with each module B in the module set S. j Synchronization, where j=1,...,M, M≥1, and S={B1,...,B M The system includes:

[0015] Module A is configured to operate synchronously with a clock signal CK_A of period T;

[0016] Module B j The set S, wherein each module B j The clock signal CK_B configured to operate with the period T j Operate synchronously, each module B j Includes being configured to perform sampling from module A to module B at the sampling location. j The signal S_A sent j A sampling component that samples data values;

[0017] The system is characterized in that it further includes at least one phase adjustment circuit, wherein the phase adjustment circuit is configured to:

[0018] For module A and module B j One of the modules B j Each pair of modules is formed and the total adjustment time TT_D is calculated for each pair of modules. j Adjust or control signal S_A j Data arrives at module B j The arrival time of the sampling position of the sampling component is related to that of module B. j The relative time between sampling times of the data by the sampling unit, wherein the sampling time and the arrival time are directly adjacent in time. The sampling time can be any of the adjacent sampling times of the arrival time. Preferably, the total adjustment time TT_D j This enables the system to adjust or control the arrival time and module B. j The relative time between adjacent sampling times of the data from the sampling component;

[0019] Wherein, the total adjustment time TT_D j Configured for: sampling components from module A to those from module B j Signal S_B sent to module A j Data value sampling and by module B j The sampling component for signal S_A j The sampling of data values ​​involves increasing (e.g., maximizing or optimizing) the time interval between the arrival of data at the sampling position of the corresponding sampling component of the module and the data sampling of the corresponding sampling component of the module, wherein the time of data sampling and the time of data arrival at the sampling position of the relevant corresponding sampling component are directly adjacent in time. By "optimizing" the time interval, it must be understood that the claimed invention seeks a total adjustment time TT_D. j The value of this value prevents sampling and data changes from reaching the sampling component of module A and module B. j The arrival times of the sampling positions of the two sampling components occur simultaneously. For example, the system may include a threshold stored in memory, wherein the system is then configured to determine the total adjustment time TT_D. j Which value, relative to the sampling performed by the sampling component of module A and the sampling performed by module B. j The sampling component performs sampling on adjacent sampling times of two samples, where the time interval is greater than a threshold, and then automatically selects TT_D where the time interval is greater than the threshold. j The value of TT_D j One of the values ​​(e.g., the minimum value). Specifically, if determined by the total adjustment time TT_D j The value of the time interval generated by the value is relative to the sampling performed by the sampling component of module A and the value of the sampling component of module B. j If any directly adjacent sampling time between the two sampling components exceeds the maximum threshold, then the total adjustment time TT_D j Maximize the time interval. Specifically, when the total adjustment time TT_D j The values ​​are combined (i.e., for module A and module B). j (Both simultaneously) result in sampling performed by the sampling component of module A and by module B. j When the minimum value of the time interval between the data arrival time and the adjacent data sampling time increases or is correspondingly maximized, the time interval can be considered to be increased or correspondingly maximized.

[0020] According to the present invention, the system preferably automatically determines the total adjustment time TT_D during the calibration phase. j Module B jconfigured to automatically return (e.g., loop back) the calibration signal S'_A received from module A j to module A. Preferably, the calibration phase includes a repeating loop configured to: automatically determine the total adjustment time TT_D i,j by iteratively changing the value of an adjustable time T_D used to iteratively modify the time interval j ; and set the value of the total adjustment time TT_D j equal to the value of the adjustable time that results in an interval time that, for both the sampling by the sampling component of module A and the sampling by the sampling component of module B j , prevents sampling of data at the time of data change. Preferably, during the calibration phase, the value of the total adjustment time TT_D j that optimizes or maximizes the time interval is automatically selected or determined.

[0021] Preferably, the adjustable time is defined as T_D i,j =(i - 1)•T_inc, where T_inc is a time increment, where T_inc < T, and i is an integer, where 0 < i ≤ i max , where i max •Tinc ≥ T, and where, during the repeating loop, the value of T_D is changed by iteratively taking different values for the integer i i,j . For example, N•T_inc ≥ T and (N - 1)T_inc < T, N is a positive integer preferably greater than or equal to 3, and i max = N. In particular, the time increment T_inc can be obtained or received or automatically determined by module A, for example, by dividing the period T by the number N, where the number N can be a parameter stored in the memory of module A or input by an operator. In particular, N ≥ n + 3, where n is a positive integer or positive real number that satisfies n•T_inc ≥ the maximum deviation between module A and module B j , the maximum deviation including, for example, the deviation between the clock signals CK_A and CK_B j , and optionally any latency caused by data propagation in the connecting device between module A and module B j and / or data processing in any internal components of module A and / or B j such as buffers, FPGAs, etc.

[0022] Then, for i = 1,..., N, the repeating loop for determining the total adjustment time TT_D j can include the following steps:

[0023] Step A: During the initial clock period CK0_i,j of the clock signal CK_A, module A outputs the calibration signal S'_A. j Calibration signal S'_A j This includes the change C_i,j from the first data value to the second data value, and the signal S'_A j Data arrives at module B j The arrival time of the sampling position of the sampling component is related to that of module B. j The sampling component applies a time adjustment T_D to the relative time between the sampling times of the data. i,j (represented in ns), where T_D i,j =(i-1)•T_inc, so as to utilize module B j The sampling component for signal S'_A j Sampling is performed, and a counter configured to count the cycles of the clock signal CK_A is started. Optionally, the system can be configured to perform sampling over a time period T_M. j During this period, maintain or retain the calibration signal S'_A at the output of module A. j The second data value in the time period extends at least from module A to module B. j Received back including the data change C_ i,j The calibration signal S'_A j The time (e.g., extending to module A in the time frame of module B) j The calibration signal S'_A sent back j The change was detected in the middle).

[0024] Step B: Using the counter and starting from the initial clock period CK0_i,j, count the number L of clock signal CK_A cycles. i,j The counting continues until the final clock cycle CKF_i,j, where the final clock cycle CKF_i,j is the clock cycle of the clock signal CK_A at which the counter receives the stop signal. The stop signal is configured to stop the counting performed by the counter. The stop signal is received by module A from module B. j Received signal S'_A j When the change is detected, module B is generated. j Configured to, for example, use loopback mode during the repeating cycle, transmit the received signal S'_A j Send back to module A, and in which, in order to be sent by module B j Signal S'_A j The system is configured to apply the time adjustment T_D to another relative time and send it back to module A. i,j The other relative time is the signal S'_Aj The relative time between the arrival time of data at the sampling position of the sampling component of module A and the sampling time of the data by the sampling component of module A, where the sampling time is when using the sampling component of module A to sample signal S'_A j For example, the number L i,j is the number of clock signal CK_A cycles between the time T_S when the transition or change C_i,j occurs i,j and the time T_R when the counter receives the stop signal i,j , where the stop signal indicates that module A detects the transition in the calibration signal S'_A received back from module B j . During the repetition loop, module B j is thus configured to automatically send back the received calibration signal S'_A j . Preferably, after module A detects the change C_ j in the calibration signal S'_A sent back by module B j , the method includes outputting by module A the calibration signal S'_A to be sent to module B j with a change from the second data value to the first data value, and preferably holding the calibration signal S'_A i,j at the first data value until step A starts again; j j j i,j i,j Step C: For the time adjustment T_D

[0025] , store the corresponding number L of clock signal CK_A cycles that have been counted i,j , and if i < N, repeat steps A to C for i = i + 1, otherwise stop the repetition loop; i,j

[0026] And after stopping the repetition loop, the system is configured to automatically select, among the set of time adjustments {T_D 1,j ,..., T_D,..., T_D N,j}, a time adjustment T_D s,j whose characteristic is that the number of cycles L_ s,j is even, where s ∈ {1,..., N}, and for both the sampling component of module A and the sampling component of module B j , the arrival of the change C_s,j to the sampling position of the sampling component under consideration is the farthest in time from the adjacent sampling time of the sampling component under consideration or is one of the farthest arrivals. The system is also configured to set TT_D j = T_D s,j = (s - 1)T_inc. In other words, the system is configured to select the time adjustment T_Ds,j For module A and module B j Both, the time adjustment together increases or maximizes or optimizes the minimum time interval between the arrival time of the change in sampling position C_s,j and the adjacent sampling time of the sampling position.

[0027] According to the present invention, the set {L1,...,L} of the number of counted clock signal CK_A cycles is... N,j} corresponds to the set {T_D} of time adjustments 1,j ,...,T_D N,j}: Adjust T_D for each time period i,j The corresponding number of cycles L has been counted. i,j Specifically, for a time increment that cumulatively covers one clock cycle T, a set {L} can be obtained. 1,j ,...,L N,j Preferably, the system can be configured to automatically determine a larger set {L}. 1,j ,..., L N,j ,L N+1,j , ... ,L N+N,j This corresponds to continuously adding time increments, cumulatively covering two consecutive clock cycles. Therefore, such a larger set is related to the larger set of time adjustments {T_D}. 1,j ,...,T_D N,j ,T+T_D 1,j ,...,T+T_D N,j Related (see in particular) Figure 6 ,exist Figure 6 In a specific case, a cumulatively increasing time increment is shown, such that it covers the first time period and the second clock period, where T_inc = T / N, N = 8 and T = 10 ns). Preferably, the system according to the invention is configured to: automatically determine a larger set {L} of the number of counted clock signal CK_A periods for a cumulative time increment covering two consecutive clock periods. 1,j ,...,L N,j ,L N+1,j ,...,L N+N,j Furthermore, within the larger set, a subset is automatically selected that contains the maximum number of consecutive identical even-numbered cycles; and within the selected subset, the system is configured to: if the selected subset contains an odd number of counting cycles, select the midpoint of the subset and direct it to TT_D. jAssign a time adjustment value corresponding to the midpoint; and if the subset contains an even number of counting cycles, the system is configured to select one of the two center points of the subset, preferably the center point corresponding to the lowest time adjustment value, and send it to TT_D. j Assign a time adjustment value corresponding to the selected center point. Specifically, if two equally largest subsets exist, repeat the previously described process for assigning the time adjustment value to TT_D for both subsets. j The process involves assigning time adjustment values, and finally, the system is configured to automatically select the lowest time adjustment value.

[0028] According to the present invention, the adjustment or control can be implemented in different ways. For example, the adjustment or control can be achieved through adjustment module B. j The sampling time and / or data arrival time of the sampling component of module B j The sampling is performed at the sampling position of the sampling component. Specifically, when adjusting the data arrival time, the phase adjustment circuit includes at least one adjustable delay component (i.e., a component for adjusting the delay), which is configured to delay the transition from module A to module B relative to the clock signal CK_A. j Send signal S_A j The time, and / or used in module B j Received the signal S_A j Then relative to module B j Received signal S_A j The time delay of the signal S_A j Arrival at module B j The time of the sampling position of the sampling component.

[0029] Preferably, the total adjustment time TT_D j It can be limited to TT_D j =TD_A j +TD_B j , among which, TD_A j and TD_B j The delay time is achieved by the phase adjustment circuit, such that it is output by module A and configured to be sent to module B. j The signal S_A sent j Any change between the first and second data values ​​in the clock signal CK_A is delayed by a delay time TD_A relative to the valid transition edge of the clock signal CK_A. j And the arrival of the change to the sampling position relative to the change is handled by module B. j The reception was delayed by a delay time TD_B j Therefore, the total adjustment time is TT_D jAccording to TD_A j and TD_B j The corresponding values ​​in module A and module B j Divide between them. For example, we can make TD_A j =TT_D j And TD_B j =0, or TD_B j =TT_D j And TD_A j =0, or TD_A j =TT_D j / 2=TD_B j Of course, another division is possible. To achieve this, if TD_Aj≠0, the system preferably includes a first adjustable delay component installed within module A, the first adjustable delay component being configured to adjust the delay time TD_Aj. j Applied to signal S_A j To Module B j The sending; and if TD_B j If the value is not equal to 0, then the system preferably includes a second adjustable delay component, which is installed in module B. j It is internally configured to implement the delay time TD_B j Of course, if TD_A j =0, or correspondingly TD_B j If the value is 0, then the first adjustable delay component is not needed, and correspondingly, the second adjustable component is not needed. The first adjustable delay component is, for example, a flip-flop whose clock can be controlled according to the clock signal CK_A, a programmable delay component, or a tapped delay line capable of controlling the timing of signal output from module A. Preferably, the second adjustable delay component is a programmable delay component or a tapped delay line.

[0030] Preferably, the system according to the invention is configured to implement waiting time adjustment so that multiple or all modules B in the set... j Synchronization. For example, a system (e.g., module A) can be configured to:

[0031] For each module B j Determine the output signal S_A from module A. j The time of the data and its origin from module B j The sampling unit samples the data using clock signals CK_A or CK_B between the sampling times. j The number of cycles L j Preferably, the system will L j Automatically set to L j =L s,j / 2;

[0032] In all numbers L j The following text is referred to as L. max The maximum number of, among which, , where q≠r;

[0033] To each module B j Simultaneously send using S_A j The start signal is configured to synchronously start all modules B. j Module B j Configured for: in module B j The sampling component for signal S_A j Before data sampling occurs, it is performed relative to signal S_A j Data from module B j The delay time TD_B of the received time j To adjust signal S_A j Data arrives at module B j The arrival time of the sampling position of the sampling component is related to that of module B. j The relative time between the sampling times of the data by the sampling unit, and the system is also configured to send signals S_A j Apply L Max -L j A further delay of one cycle is applied, which is a first further delay and a second further delay, such that the sum of the first further delay and the second further delay equals L. Max -L j Each cycle, wherein the first further delay is in signal S_A j The transmission is preceded by a delay of 0 or more clock signal CK_A cycles at module A, and a second further delay is applied to signal S_A. j After sampling, in module B j Zero or more clock signals CK_B at the location j Delay in the cycle.

[0034] Specifically, Module B j The sampling component may include a flip-flop, which has the ability to operate relative to a clock signal CK_B j The adjustable clock is adjusted according to the total adjustment time TT_D. j The sampling time is adjusted or controlled by time. In this case, the phase adjustment circuit preferably includes a circuit installed in module B. j The retiming element (e.g., a trigger) within module B is configured to trigger the timing function of module B. j The sampling component's trigger retims the sampled signal to the clock signal CK_B.j For example, module B j It can be configured to be used relative to the clock signal CK_B j Apply sampling delay TDS_B j With delayed signal S_A j Data sampling to adjust signal S_A j Data arrives at module B j The arrival time of the sampling position of the sampling component is related to that of module B. j The relative time between the sampling times of the sampling components for the data. In this case, during the waiting time adjustment, module B... j Configured for use in response to signal S_A j Apply sampling delay TDS_B during sampling j The system is also configured to send signals to S_A j Apply L Max -L j The further delay for each cycle, wherein, as previously described, the further delay can be applied as a combination of the first further delay and the second further delay.

[0035] According to the present invention, when module A and module B j When the role is reversed, that is, when module B j Send signal S_B to module A j Module A reads the signal S_B j The total adjustment time is TT_D. j It can be used to make module A and module B j Synchronization. In this case, the phase adjustment circuit is preferably also configured to: for the components of module A and module B j One of the modules B j Each pair of modules is formed and the total adjustment time TT_D is calculated for the considered pair of modules. j Adjust or control another relative time, which is signal S_B j The relative time between the arrival time of data at the sampling position of the sampling component of module A and the sampling time of the data by the sampling component of module A, wherein the sampling time and the arrival time are directly adjacent in time. Specifically, the adjustment or control of this other relative time can be performed by adjusting the sampling time of the sampling component of module A and / or the arrival time of the sampling position of the sampling component of module A. For example, a phase adjustment circuit can be configured for the module B. j Delay time TD'_B j Applied to signal S_B jThe signal is sent to module A, and within module A, it is used to transfer signal S_B. j The arrival time at the sampling position of module A is relative to the signal S_B received by module A. j Time delay TD'_A j , where TT_D j =TD'_A j +TD'_B j In other words, in the delayed signal S_B j In this specific case, when the data arrives at the sampling location of module A, module B... j The output is from module B j The output signal S_B is configured to be sent to module A. j The change or transformation between the first and second data values ​​in module B will be implemented. j Inside and relative to module B j clock signal CK_B j The delay is equal to the delay time TD'_B. j Furthermore, the arrival time of the change at the sampling position of module A will be delayed by a delay time TD'_A within module A relative to the reception time of the change by module A. j Preferably, TD'_A j =TD_A j And TD'_B j =TD_B j .

[0036] Finally, the system according to the invention is preferably configured to implement the previously described and claimed method each time it is powered on. Therefore, each time the system is powered on, and for each power-on of module A and module B... j One of the modules B j For each pair of modules formed, the total adjustment time TT_D is calculated by the system (e.g., by module A). j The total adjustment time TT_D j Specific to this pair of modules and particularly dependent on connecting module A to the relevant module B j The system also, and preferably for all modules B connected to module A, includes links (or connection devices). j Perform the aforementioned wait time adjustment so that all interconnected modules (i.e., modules A, B1, ..., B) are able to achieve the desired latency. M )synchronous. Attached Figure Description

[0037] Further aspects of the invention will be better understood through the following accompanying drawings, wherein the same reference numerals denote the same objects:

[0038] Figure 1 This is a schematic diagram of the system according to the present invention;

[0039] Figure 2 This is a schematic diagram illustrating the propagation of a signal that has delayed the first time increment.

[0040] Figure 3 This is a flowchart of a preferred embodiment of the method according to the present invention.

[0041] Figure 4 This is a schematic diagram illustrating the propagation of a signal with a delay of another time increment.

[0042] Figure 5 This is a table showing examples of the results of the iterative process according to the present invention.

[0043] Figure 6 This is a table showing an example of the results of an iterative process according to the invention lasting for two consecutive clock cycles. Detailed Implementation

[0044] Figure 1 A schematic illustration of a system 100 according to the present invention is shown. The system 100 typically includes multiple modules, namely a master module referred to as module A 110 and one or more slave modules B. j Where j=1,...,M. To illustrate this invention, module A and modules belonging to the set S={B1,..., B...} will be used. M Module B of} j Synchronization 120 is used as an example. Even if module A is the main module, module A and module B... j They could also be the same. They are typically electrical arrangements, such as ICs, configured to operate or act in sync with a clock signal.

[0045] Preferably, module A 110 includes:

[0046] Counter 111 is used to count the number of clock cycles relative to the clock signal CK_A;

[0047] Signal transmitter 112 includes, for example, a trigger for outputting signal S_A according to clock signal CK_A (e.g., synchronously with clock signal CK_A). j 220, where the clock signal CK_A can be received or generated by module A;

[0048] Signal receiver 114, for use from module B j 120 received signal S_B j The signal receiver 114 typically includes a sampling component, such as a trigger, for the signal S_B. jThe data passes through the sampling component and is sampled. For the purposes of this invention, the sampling component is considered to be configured to sample at the sampling location. As explained later, the signal receiver 114 can be connected to the counter 111 to [process data from module B]. j Receive back calibration signal S'_A j The counting of the number of clock cycles triggered by the clock signal CK_A is stopped. Therefore, the signal receiver 114 typically includes a sampling unit configured to, in particular via its trigger, sample the input signal (e.g., signal generated by module B) according to the clock signal CK_A (e.g., synchronously with the clock signal CK_A). j The signal S'_A sent back j Or more generally, by module B j The sent signal S_B j The input data is sampled. The signal receiver 114 and signal transmitter 112 of module A can be connected to each other;

[0049] Processor unit 115 is used to determine the total adjustment time TT_D j The total adjustment time TT_D j Specifically configured to act as a regulator for adjusting module A and module B. j The communication link between clock signals CK_A and CK_B j The waiting time adjustment parameter. The communication link can be implemented to connect module A to module B. j The cable. Preferably, it is output from module A and sent to module B. j signal S_A j The required cable length to be covered is determined by module B. j The signal S_B is output and sent to module A. j The cables that must be covered must be of the same length.

[0050] Preferably, module B j 120 includes:

[0051] Signal receiver 124 is used to receive the signal S_A sent by module A. j 220, the signal receiver 124 typically includes a sampling component, such as a trigger, for the signal S_A j Passing through the sampling component. The signal receiver 124 is typically configured to operate according to the clock signal CK_B. j (For example, with clock signal CK_B) j (Synchronously) via its sampling component and at a given sampling position, the signal S_A j The input data is sampled, and the clock signal CK_B j It can be made by module B jReceive or generate;

[0052] Signal transmitter 122 includes, for example, a trigger for responding to a clock signal CK_B j (For example, with clock signal CK_B) j (Synchronously) Send signal S_B to module A j Module B j The signal transmitter 122 and the signal receiver 124 are typically connected to each other to achieve the calibration signal S'_A j The reception and, in particular, the transmission back to module A.

[0053] Module B j It typically operates in loopback mode to transmit the calibration signal S'_A j Send back to module A. In other words, the calibration signal S'_A j It is sent back to module A without any processing or modification. In fact, module A and module B... j Each of these components may include an FPGA, which includes the signal transmitter, the signal receiver, the processing unit, and the counter.

[0054] Specifically, module A and / or module B j This can include the clock signals used to generate their clock signals (i.e., the clock signal CK_A of module A and the clock signal of module B). j clock signal CK_B j The internal local clock of ). According to another embodiment, and preferably, module A and module B j Connected to a global clock CK 130 configured to generate a global clock signal 131, the global clock signal 131 is distributed to all modules in the system, namely, module A and all modules B1,...,B M Specifically, this includes the corresponding signal transmitters 112, 122 and signal receivers 114, 124 assigned to the modules. Typically, modules A and B... j The triggers of the corresponding signal transmitters and receivers are configured to connect to the global clock CK 130 in order to receive the global clock signal 131. However, as is known in the art, since the global clock signal covers the difference in propagation time between the distance separating the global clock CK 130 from module A on the one hand and the distance separating the global clock CK 130 from module B on the other hand, the clock signal on which module A operates effectively (i.e., the clock signal CK_A) and the corresponding clock signal on which module B operates effectively are different. j The clock signal upon which effective operation is based (i.e., the clock signal CK_B) j They may each be slightly out of phase relative to the global clock signal output by global clock CK 130. Therefore, clock signals CK_A and CK_B...j Possible anomalies. This invention proposes methods for enabling module A and module B... j The new synchronization method allows them to operate synchronously, thus overcoming the problem of their respective clock deviations.

[0055] The clock signal according to the invention (e.g., Figure 2 The clock signal CK_A 210 or clock signal CK_B shown j A clock signal is typically a signal that oscillates periodically between two values ​​(i.e., a low value and a high value). It is usually a square wave. Each period or time interval T of this clock signal includes a rising edge 211 and a falling edge 212. The rising edge and / or the falling edge are typically used to trigger modules according to the invention (e.g., module A or module B). j Some actions or operations, such as sampling data synchronously with the rising or falling edge, and / or generating data transitions on the rising or falling edge. For example, module B 120 can perform some actions or operations on the clock signal CK_B. j On the rising edge of the input signal S_A j 220 data points are sampled. Alternatively, or in another location, the clock signal CK_B can be used. j On the falling edge of the signal S_A j The data is sampled. Preferably, module A and module B... j Both modules operate synchronously with the rising edge of their respective clock signals. Alternatively, or additionally, both modules operate synchronously with the falling edge of their respective clock signals. According to another embodiment, module A can operate synchronously with the rising edge of clock signal CK_A, while module B can operate synchronously with clock signal CK_B. j It operates synchronously with the falling edge. Conversely, module B... j It can be used with the clock signal CK_B j Module A can operate synchronously with the rising edge of the clock signal CK_A, while module A can operate synchronously with the falling edge of the clock signal CK_A. Other cases may occur regarding synchronous operation with the falling and / or rising edges of the corresponding clock signals of the modules, provided that for data (i.e., for signal S_A)... j From module A to module B j The propagation time (i.e., for signal S_B) j From module B jThe propagation time to module A is the same (or substantially the same). In the following text, rising and falling edges will be collectively referred to as "transition edges." Therefore, a transition edge can be either the rising or falling edge of a clock signal. Furthermore, the transition edge of the clock signal on which the module operates (e.g., to generate a change from a first value to a second value or from a second value to a first value in the output signal, or to sample data from the input signal) will be referred to as a valid transition edge, and the other transition edge (if any) will be referred to as an invalid transition edge (i.e., only if neither transition edge is used to trigger the operation of the relevant module).

[0056] According to the present invention, signal S_A j This can be represented as a data sequence or order with discrete values, which are either a first value or a second value. It is typically a binary signal (also called a logic signal), where the first value is, for example, zero, and the second value is, for example, one. Module A, particularly its signal transmitter 112, is configured, especially in nominal operating mode, to output any data transitions (e.g., 0->1 or 1->0) in the signal S_A in synchronization with its clock signal CK_A. More precisely, any data transition occurs on the valid transition edge of the clock signal CK_A. Therefore, the data transition from the first value to the second value is synchronized on the valid transition edge of the clock signal CK_A. For any signal S_B output by module B, i.e., by its signal transmitter 122... j This also applies to module B after necessary modifications to the details. j In its nominal operating mode, any transition between the first and second values ​​is related to its clock signal CK_B. j The effective transformation is achieved synchronously. Therefore, for module B... j The signal S_A sent back to module A j That's also true.

[0057] Figure 2 This is a diagram illustrating the waiting time within the system 100 according to the present invention. More precisely, it shows the signal output from the signal transmitter 112 of module A and transmitted to module B. j The signal S_A returns to module A in a loop. j The time required for 220 is counted in the number of clock cycles of module A. As previously explained, clock signal CK_A 210 and clock signal CK_B j They have the same frequency and therefore the same time period T. The signal transmitter 112 and signal receiver 114 of module A operate synchronously with the clock signal CK_A according to their respective nominal operating modes, while module B... jThe signal transmitter 122 and the signal receiver 124 operate synchronously with the clock signal CK_B according to their respective nominal operating modes. j operate synchronously. Figure 2 Together with Figure 1 will now be used to illustrate the method according to the invention as Figure 3 shown.

[0058] The method according to the invention comprises: for each pair of modules formed by one of the modules A 110 and the module B j 120 and according to the total adjustment time TT_D calculated for each pair of modules j , controlling or adjusting the signal S_A j the arrival time of the data at the sampling part of the module B j 120 and the relative time between the adjacent sampling times (e.g., each of the adjacent sampling times) of the data of the sampling part of the module B j . By controlling or adjusting the relative time, the system can control the time interval between the arrival time of the data at the sampling position and each of the adjacent sampling times at which the sampling part samples the data, which aims to optimize the time interval so that sampling does not occur when the data changes the arrival time at the sampling position. According to the method currently claimed, the total adjustment time TT_D j is automatically determined by the system 100. For this purpose, the method comprises a calibration phase, the preferred embodiment of which will be described in more detail below.

[0059] The calibration phase comprises the following steps:

[0060] At step 301, a time increment T_inc < T is set within the module A 110. Different values can be assigned to T_inc. However, the value selected for T_inc should verify N • T_inc ≥ T and (N - 1)T_inc < T, where N is a positive integer. Preferably, T_inc = T / N, where N ≥ 3. For example, the time increment T_inc can be received or acquired or determined by the module A. In particular, the time increment T_inc can be automatically calculated by the module A or the system 100 by dividing the time period T by the number N, where N can be a parameter stored in the module A. The typical order of magnitude of the time period T is from a few nanoseconds to dozens of nanoseconds, e.g., T = 10 ns. Preferably, N is included between 5 and 15. For example, as Figure 5 and Figure 6 shown, N = 8, T = 10 ns and T_inc = 1.25 ns. In particular, the processor unit 115 of the module A is configured to automatically calculate the time increment T_inc. Preferably, the processor unit 115 is also configured to calculate according to the cable length and the signal S_A jThe propagation speed in the cable is automatically determined by the numerical value N, specifically by setting N ≥ n + 3, where n can take any value that verifies the maximum deviation ≤ n•T_inc and preferably keeps N ≤ 2•(n + 3). Of course, N can also take a value greater than 2•(n + 3), which will increase the total settling time TT_D. j The accuracy is improved, but the determination of TT_D is also increased. j The required time. The proposed value is a trade-off between accuracy and keeping the processing time required for the calibration phase sufficiently low. Alternatively, the number N can be a parameter input by an operator within module A and stored in the memory of the processor unit 115. The time interval T can be measured by the processor unit 115, or, for example, a predefined parameter stored in module A for the processor unit 115 to calculate T_inc. Alternatively, the time increment T_inc can be calculated by an external system and sent to module A.

[0061] At step 302, module A is configured to determine the total adjustment time TT_D. j As previously mentioned, the total adjustment time allows the system to consider the adjustment to module B. j Send signal S_A j At that time, adjust the data to module B. j The arrival of the sampling position and the module B j The relative time between adjacent sampling times (relative to arrival time) of the sampling components, and optionally also enabling the system to consider sending signal S_B to module A. j At the same time, another relative time is adjusted. This other relative time is the relative time between the arrival of data at the sampling position of module A and the adjacent sampling time (relative to the arrival time) of the sampling component of module A. Therefore, it acts as a waiting time adjustment parameter, taking into account the arrival of the data output by module A at module B. j The amount of time spent (measured in clock cycles), according to the present invention, is assumed to be for module B j The data sent to module A will be the same and intended for module B. j The data described herein is sampled "as far away as possible" from the effective transition edge of the sampling clock signal, which may be, for example, the clock signal CK_B. j It is itself or module B j The adjustable sampling clock signal of the sampling component.

[0062] Specifically, in order to determine the total adjustment time TT_D j The system, or preferably module A, is configured to implement repeating loop 303, which is configured to search for the total adjustment time TT_D. jThe value that prevents the sampling components of module A and module B from being affected. j The sampling components sample the data changes in the signal to be sampled at or near the sampling position of the considered sampling component during the sampling time. Specifically, the system, or preferably module A, is configured to select a value for the total adjustment time, which applies to both module A and module B. j Both involve increasing, optimizing, or maximizing the time interval between the arrival time of the data change at the sampling location of the considered sampling component and each of the sampling times adjacent to the arrival time of the considered sampling component. Therefore, the selected total adjustment time is used to improve modules A and B. j This trade-off in time intervals: for data sampling by module A and by module B j The sampling of data is a common adjustment time that simultaneously optimizes the time interval.

[0063] According to the repetitive loop 303, the system, in particular module A, is configured to iteratively increase the adjustable time T_D. i,j And used to send data from module A to module B during each iteration. j The calibration signal S'_A of the loop back to module A j The number of clock signal cycles CK_A required for data changes is counted, where, in each iteration, module B... j The data change at the sampling position arrives at the adjacent sampling time of the sampling component (i.e., the sampling clock signal—the clock signal used for sampling, e.g., the clock signal CK_B of the sampling component). j The relative time between the effective transition edge of another clock signal (or the time when another clock signal) changes by the amount of time T_inc. This can be achieved by delaying the arrival of data in module B. j The arrival time of the sampling position and / or the sampling itself relative to the clock signal CK_B via delay sampling. j The timing of the event is determined by the time of occurrence. For example, the time delay between the transition between the first and second values ​​output by signal transmitter 112 and the occurrence of a valid transition edge in the clock signal CK_A can be iteratively increased by T_inc until the delay equals N•T_inc, at which point processing stops. For example, if T_inc = 1.25 ns and N = 8, the time delay can, for example, iteratively take the following values: 0 ns, 1.25 ns, 2.5 ns, 3.75 ns, 5 ns, 6.25 ns, 7.5 ns, 8.75 ns (see also...). Figure 5 (Table).

[0064] More precisely, when considering the components of module A and module B... jWhen a pair of modules is formed, repeating loop 303 preferably includes the following steps: for i=1,...,N, the iteration starts from i=1:

[0065] Step A: The signal transmitter 112 of module A is configured to output a calibration signal S'_A during the initial clock cycle CK0_1,j 213 of the clock signal CK_A, including a data transition or change C_1,j 221 from a first data value 222 (e.g., 0) to a second data value 223 (e.g., 1). j And the system (e.g., module A and / or module B) j ) to calibration signal S'_A j Data arrives at module B j The arrival time of the sampling position of the sampling component of 120 is related to that of module B. j The sampling component applies a time adjustment T_D to the relative time between adjacent sampling times. 1,j , where T_D 1,j =(1-1)•T_inc=0, so as to utilize module B j The sampling component for signal S'_A j Sampling is performed. During the initial clock cycle CK0_1,j 213, the system, preferably module A, starts a counter configured to count the cycles of the clock signal CK_A.

[0066] For example, the data change C_1,j can occur simultaneously with the occurrence of a valid transition edge in the initial clock period CK0_1,j 213 of the clock signal CK_A. In this case, the change C_1,j is output by the signal transmitter 112 synchronously with the valid transition edge of the initial clock period CK0_1,j 213 at time T_S1. Preferably, after the change C_1,j 221, the calibration signal S'_A is... j The value remains at the second value until the signal receiver 114 of module A receives a signal from module B. j The calibration signal S'_A sent back j until.

[0067] During the initial clock cycle CK0_1,j 213, counter 111 starts counting the cycles of clock signal CK_A. For example, both signal transmitter 112 and counter 111 can receive an initialization signal, for example, sent by processing unit 115, which, on the one hand, starts the output of signal transmitter 112 to the change C_1,j, and on the other hand, starts the counting of counter. Alternatively, this initialization signal can be generated by signal transmitter 112 when the change C_1,j is generated and transmitted to counter 111 to start the counting. Preferably, module A simultaneously starts counting the clock cycles of clock signal CK_A and outputs calibration signal S'_A. j The change C_1,j is described above. Of course, other implementations are also possible that start counting for the same clock cycle as the clock cycle in which the change C_1,j occurs. This can be applied to any other change C_i,j with necessary modifications to the details.

[0068] Step B: The counter adjusts the number of cycles L. 1,j The counting continues until the final clock cycle CKF_1,j, where the counting stops, for example, at time T_R1. In practice, at each new time period T or cycle of the clock signal CK_A, counter 111 automatically increments its count by one unit, as... Figure 2 As shown. This is a count of time, expressed in clock cycles, used for the data output by module A to be processed by module B. j It receives data and returns in a loop. Figure 1 Different positions a to e in system 100 (see Figure 1 Positions a to e in the diagram show the calibration signal S'_A, which includes the time-dependent change C_1,j 221. j The propagation, wherein position "a" is located at the output of signal transmitter 112 of module A, and position "b" is located in module B. j The input of the sampling component of the signal receiver 122, position "c" is located in module B. j At the output of the signal transmitter 124, position "d" is located at the input of the sampling component of the signal receiver 114 of module A, and finally, position "e" is located at the input of the counter 111. Figure 2 As shown, the data transformation or change C_1,j 221 will arrive at position b after n clock signal CK_A cycles starting from the initial clock cycle CK0_1,j. For example, module B operating in the loopback mode. j The received calibration signal S'_A j The calibration signal S'_A is sent back to module A, specifically without requiring modification and / or processing. jAccording to the present invention, system 100, particularly module B j Configured to apply the time adjustment T_D to another relative time. 1,j The other relative time is the arrival time of the calibration signal S'_Aj data at the sampling position of the sampling component of module A 110 and the time of the sampling component of module A on the calibration signal S'_Aj. j The relative time between adjacent times when data is sampled (particularly adjacent times to the arrival time). The techniques previously described for relative time are applied to this other relative time with necessary modifications to the details.

[0069] like Figure 2 As shown, module B j The signal transmitter 122 pairs the calibration signal S'_A j The change in the output of C_1,j 221 may occur n+1 clock signal CK_A cycles after the initial clock cycle CK0_1,j. Then, at 2n-1 cycles after the initial clock cycle CK0_1,j, the calibration signal S'_A... j The input is received as a sampling component (e.g., a trigger) of the signal receiver 114. At this time, the signal receiver 114 detects the change CK0_1,j and typically sends a stop signal to the counter 111, which stops counting clock cycles (L1 = 2n cycles) after starting its counting. The clock cycle at which the counting stops is the so-called final clock cycle CKF_1,j. For example, it could be a calibration signal S'_A forwarded by the signal receiver 114 to the counter 111. j The stop signal arrives at position e 2n clock cycles after the initial clock cycle CK0_1,j. Preferably, the detection of the change C_1,j by the signal receiver 114 automatically triggers the calibration signal S'_A output by the signal receiver 114 within the signal transmitter 112. j The transition from the second value back to the first value. Alternatively, the transition back to the first value may occur later, but in any case, it must occur before the new iteration.

[0070] Step C: For the time delay T_D 1,j Processing unit 115 stores the number of cycles L spent in response to the change in C_1,j to the loop module A to trigger the stop of counter 111. 1,j .

[0071] Then, the value of i is increased by one unit: i = i + 1 = 2, and steps A to C are repeated for the change C_2,j from the first value 222 to the second value 223 during the initial clock period CK0_2,j of the clock signal CK_A, wherein the system, such as module A and / or module B j Apply time adjustment T_D to the relative time 2,j =(2-1)•T_inc=1T_inc. For example, the change C_2,j can be delayed by adjusting the time T_D relative to the time when the effective transition edge occurs in the initial clock period CK0_2,j of the clock signal CK_A. 2,j =T_inc.

[0072] Continue iterating, and for each i, the calibration signal S'_A j Internal generation changes C_ i,j 224 and output it, while applying a time adjustment T_D to the relative time between data arrival and data sampling. i,j =(i-1)•T_inc 214, and for the final clock cycle CKF_ i,j The number of clock signal CK_A cycles L up to now i,j Perform the counting, wherein the final clock cycle CKF_ i,j It is the clock cycle of the clock signal CK_A received by the counter from the stop signal, the stop signal being received by module A from module B. j Received signal S'_A j The change C_ was detected in i,j Generated in time. For example, the change C_ is output by module A. i,j The timing can be determined by the effective transition of the signal transmitter 114 relative to the clock signal CK_A along a continuously delayed adjustment time T_D. i,j =(i-1)T_inc 214 (see also) Figure 4 ), and from the output of the signal transmitter, the change C_ i,j Initial clock period CK0_ i,j 226 pairs of corresponding period numbers L i,j 225 counts until signal is received from module B by signal receiver 114. j The change C_ received back i,j The detection is transmitted until the final clock cycle CKF_i,j227 of counter 111. At the end of each iteration, the number of cycles L... i,j Therefore, the corresponding time adjustment T_D i,j Related, and the pair (L) i,j T_D i,jPreferably, this is stored in the memory of module A, for example, in the memory of the processing unit 115 of module A. Finally, after completing steps A to C for i=N, loop 303 is repeated and stopped. Optionally, as... Figure 6 As shown, this iteration can occur for i=1,...,2N, where the above steps occur after necessary modifications to the details.

[0073] Figure 5 The possible results of this iterative process for i=1,...,N are shown. Different columns A to H show the time adjustment T_D. i,j =(i-1)T_inc, where T_inc=1.25 ns and i=1,...,8. In this example, the time adjustment is applied to delay the change in C_. i,j The output, in each row, shows the number of cycles L that have been counted during the same repeating cycle. i,j (For example, 2n, 2n+1, 2n+2, ...). Therefore, each row represents a different scenario that may occur during the same repeating cycle. For example, for the scenario in the first row of the table, regardless of the time adjustment T_D... i,j The value of L is the number of clock cycles counted until the counter receives a stop signal. i,j It is always the same and equal to 2n. In another case shown in row 10 of the table, for time adjustments of 0 ns and 1.25 ns, 2n+1 cycles will be counted, then for time adjustments of 2.5 ns, 3.75 ns, 5 ns, 6.25 ns and 7.5 ns, 2n+2 cycles will be counted, and finally, for a time adjustment equal to 8.75 ns, 2n+3 cycles will be counted.

[0074] At step 304, system 100, preferably module A (e.g., its processing unit 115), is configured to provide services to module B. j Determined pair (L) i T_D i,j Automatically select the pair (L) from the list. s T_D s,j ), characterized by the number of cycles L s It is an even number, where s∈{1,...,N}, and preferably, for this pair, the arrival of the corresponding change in the sampling position of the sampling component of module A is one of the arrivals that is furthest in time from any adjacent sampling time of the sampling component of module A. By means of Figure 5 To illustrate further, consider row 10 of the table, where the number of cycles L can be seen. i,jThe time adjustment is the same for different sets: 2n+1 cycles when a time adjustment of 0 ns and 1.25 ns is applied, 2n+2 cycles when a time adjustment of 2.5 ns, 3.75 ns, 5 ns, 6.25 ns, and 7.5 ns is applied, and 2n+3 cycles when a time adjustment of 8.75 ns is applied. In this case, the time adjustment E (5 ns) results in a calibration signal S'_A output by the signal transmitter 112. j The change included in the arrival time of the sampling position of module A will be the one furthest in time from any adjacent sampling time at the sampling component of module A, which is for module B. j The same applies to sampling. Typically, the time from which the change reaches the sampling position of module A is furthest from any valid transition edge of the sampling clock signal (e.g., clock signal CK_A) used to sample the input signal in module A. In practice, it is desirable to avoid the change occurring at the instant of sampling, as this can lead to uncertainty in the sampled values. For example, according to row 18 of the table, when the time adjustment is increased from 0 to 1.25 ns and then from 7.5 ns to 8.75 ns, the number of counting cycles increases from 2n+1 to 2n+2 and from 2n+2 to 2n+3, respectively. This means there exist time adjustments D_T1 where 0 ≤ D_T1 ≤ 1.25 ns and D_T2 where 7.5 ns ≤ D_T2 ≤ 8.75 ns, for which the corresponding output change will reach module B. j And it is sampled essentially at the effective transition edge of the sampling clock signal. This is, in fact, a situation that is to be avoided. Therefore, according to the present invention, one of the time adjustments, D or E, will be automatically selected by the processing unit, because for modules A and B... j Secondly, the time adjustment causes the arrival time of the change to the corresponding sampling position of the module to be one of the arrival times that is temporally furthest from any adjacent sampling time of the corresponding sampling component of the module, i.e., as far away as possible from any valid transition edge of the sampling clock signal used by the corresponding sampling component of the module to sample the input signal. By "one of the arrival times that is temporally furthest," it must be understood that the selected time adjustment is a trade-off between: i) increasing (and correspondingly maximizing) the time interval between the arrival time of the change to the sampling position of module A and any of the adjacent sampling times performed by the sampling component of module A; ii) increasing (and correspondingly maximizing) the time interval between the arrival time of the change to module B. j The arrival time of the sampling position and module B jThe time interval between any two adjacent sampling times. In other words, when considering two paths (i.e., for signals sent from module A to module B, and for signals sent from module B to module A), the chosen time adjustment is a combined optimized time adjustment value that increases or correspondingly maximizes the time adjustments of both module A and module B. j The stated time interval between the two may not be an optimal time adjustment value when considering a single path (e.g., only from module A to module B). In fact, according to the invention, the selected time adjustment preferably results in the maximum value of the minimum time interval between any data arrival time and any adjacent sampling time. In practice, for both module A and module B... j Both methods can combine to increase or maximize the minimum time interval between the arrival of data at the sampling location and the adjacent sampling time, that is, combine to increase, maximize or optimize:

[0075] Module B j The time interval between the arrival time of the data at the sampling location and the immediately preceding sampling time at the sampling location.

[0076] Module B j The time interval between the data arrival time at the sampling location and the immediately following sampling time at the sampling location.

[0077] The time interval between the data arrival time at the sampling position of module A and the immediately preceding sampling time at the sampling position of module A, and

[0078] The time interval between the data arrival time at the sampling location of module A and the immediately following sampling time at the sampling location of module A.

[0079] Therefore, when considering module A and module B j When sampling occurs in either of the two scenarios, the system optimizes or maximizes the time interval in combination by optimizing or maximizing the minimum value of the time interval.

[0080] Preferably, the processing unit 115 stores storage similar to Figure 5 The table is a set of time adjustments {T_D1,...,T_D}. N,j The constraint is that, given module A and module B... j Given the physical configuration of the link between them (e.g., cable length, propagation speed, etc.), the set {L1,...,L...} represents all physically possible numbers of cycles. N} physically possible And wherein, within the table, for each set {L1,...,L...} of the number of periods N} physically possiblePredefined time adjustment T_D to be applied s,j In this case, the processing unit is configured to determine which set {L1,…,L...} in the table. N} physically possible The set {L1,...,L} obtained through repeated loop 303 N,j Matching, and then used to automatically select the time adjustment T_D s，j This time adjustment applies to the set {L1,...,L...} obtained through repeated loops. N,j The matching set {L1,...,L} N} physically possible Predefined.

[0081] At step 305, module A (e.g., its processing unit 115) sets TT_D j =(T_D s ) j That is, relative to module B j The total adjustment time value used is set to be equal to the value previously used for module B in step 304. j The selected time adjustment T_D s , j The value of the total adjustment time TT_D. j =T_D s , j It can be done in module A and module B j The interval is divided into delay time TD_A j and delay time TD_B j .

[0082] According to the present invention, different techniques can be implemented to apply the time adjustment T_D. i,j Or based on the total adjustment time TT_D j This is used to adjust / control the relative time. In fact, both the time adjustment and the total adjustment time can adjust the relative time between the arrival of data at the sampling position and the sampling of data at that sampling position. Therefore, when a time adjustment T_D is applied... i,j Or when based on the total adjustment time TT_D j When adjusting / controlling relative time, it can be applied to the arrival time of data at the sampling position and / or the sampling time at the sampling position.

[0083] Specifically, apply a total adjustment time or a time adjustment T_D to the relative time. i,j This means, for example, relative to the local clock (i.e., considering module B). j The clock signal CK_B jOr, considering the clock signal CK_A when module A is being considered, the arrival time of the data at the sampling position is delayed, and / or the sampling time of the data at the sampling position is delayed.

[0084] For example, the relative time between the arrival of data at a sampling location and the sampling of data at that location can be adjusted by acting on the sampling time. In this case, the phase adjustment circuit includes a trigger with an adjustable clock mounted within the sampling component and a retiming element connected to the output of the sampling component. The system is then configured to control or adjust the trigger for the input signal (e.g., depending on the input signal S_A of the module under consideration) by means of the adjustable clock. j Or S'_A j or S_B j The sampling clock signal is sampled such that, for example, the sampling is relative to the "local" clock signal (i.e., the clock signal CK_A in the case of sampling by module A, or considering the clock signal sampled by module B). j Clock signal CK_B during sampling j The time delay is equal to the total adjustment time TT_D, which is equal to the time after the calibration phase. j The amount of time and accordingly equal to the time adjustment T_D during the calibration phase. i,j The signal output by the trigger, which has already undergone "delayed" sampling, is then passed through the retiming element to retime the output signal to the local clock of the module under consideration. For example, modules A and B. j The receivers can both be equipped with the flip-flops with adjustable clocks and the retiming element, wherein the signal output by the flip-flops is then resynchronized with the local clock via the retiming element. Typically, after calibration, the two flip-flops with adjustable clocks are configured to delay their respective sampling times relative to the local clock by a time amount equal to TT_D. j .

[0085] To operate on the arrival time, the phase adjustment circuit can delay the signal leaving the module (e.g., module A or module B). jThe system can adjust the time it takes for the input signal to travel from its creation / generation location to the output of the relevant module, and / or increase the time it takes for the input signal to travel from its creation / generation location to the module's sampling location. To delay the time it takes for the signal to leave the module, the system can act on the time it takes to generate data relative to the local clock of the relevant module (e.g., by using an adjustable delay component such as a tapped line to delay the signal by a predefined amount of time). Furthermore, such an adjustable delay component can be used to increase the time it takes for the input signal to travel from its creation / generation location to the module's sampling location.

[0086] For example, instead of generating a data transition between a first value and a second value synchronously with the effective transition edge of the clock signal CK_A of module A and directly outputting the generated signal including the data transition (which corresponds to the nominal operating mode), after determining the total adjustment, the signal transmitter 112 can output a data transition with a total adjustment time delayed relative to the clock signal CK_A (i.e., relative to the effective transition edge of the clock signal CK_A). This delay can be achieved by generating a signal S_A0 for which the transition occurs synchronously with the effective transition edge of the clock signal CK_A, and instead of directly outputting the signal S_A0, delaying its output by the signal transmitter 112 by an amount equal to T_DA. j The delay; or the effective transition of the clock signal CK_A is delayed to generate the time of the transition, and the generated signal including the transition is output without delay. In both cases, the transition between the first and second values ​​is ultimately output by the signal transmitter with a delay relative to the clock signal of module A. When signal S_B is sent to module A j This also applies to module B after necessary modifications to the details. j Therefore, after determining the total adjustment time, the process shifts from module A to module B. j Any data transitions in the transmitted signal can be output by the signal transmitter of module A with a delay T_DAj relative to the effective transition of the clock signal CK_A, and are therefore slightly out of phase with respect to the period of the clock signal CK_A. This also applies to the signal transmitter of module B after necessary modifications to the details. j The data transformation in the signal sent to module A.

[0087] Similarly, if the total adjustment time is implemented only within the receiving module, for example, then in order to delay module B... j For signal S_A j The reading or sampling is performed instead of the clock signal CK_B. jThe transition is synchronously sampled along the input data, and once the total adjustment time TT_D is determined... j The signal receiver 124 can be configured to sample relative to the clock signal CK_B j The effective transition is delayed by a certain amount of time, which is equal to the total adjustment time TT_D. j Therefore, after determining the total adjustment time, module B will take over. j Any sample of data from the signal received from module A relative to the clock signal CK_B j The period (i.e., relative to the clock signal CK_B) j The transition edge (e.g., rising edge or falling edge, depending on module B) j How to establish a connection with the clock signal CK_B j The synchronization is slightly out of phase. This, with necessary modifications to the details, also applies to the signal S_B received by module A. j .

[0088] In practice and preferably, the total adjustment time TT_D j Not only for signal S_A j Adjust the relative time between the arrival of data at the sampling location and the sampling of data at the same location, i.e., for data transfer from module A to module B. j Send data and use module B j The data is read, and the total adjustment time TT_D is the same. j It can also be used for signal S_B j Adjust the relative time between the arrival of data at the sampling location and the sampling of data at the same location, i.e., for use from module B. j Data is sent to module A and read by module A. For example, once the total adjustment time is determined, module B... j It can be configured to use the signal S_B j The transmission delay to module A is TD'_B. j Module A can be configured to transfer the signal S_B j The arrival time of the sampling position of module A relative to its arrival time in module A (i.e., the arrival time of the signal S_B) j (Received at the input of module A) Delay time TD'_A j , where TT_D j =TD'_A j +TD'_B j .

[0089] At step 306, system 100 can be configured to adjust the latency for each implementation in its modules. This allows the system to adapt to the "worst-case" scenario (i.e., all modules B connected to module A). j The module within is measured in clock cycles L. max (representing the maximum waiting time), and is able to be based on the L max The timing for initiating sampling is adjusted. Such delay adjustments, taking into account worst-case scenarios, are known in the art and need not be further explained here. However, contrary to the prior art, the present invention proposes to adjust the timing not only in the initiation module B... j Before the operation, it was aimed at module B. j Waiting for L max -L j The data is adjusted in one cycle, and further adjusted based on the value determined for the total adjustment time before reaching module B. j The clock cycles of all modules are synchronized by the relative time between the arrival time of the sampling position and the adjacent sampling time of the sampling position, wherein module A must wait for L Max It takes a cycle to operate synchronously with other modules.

[0090] In summary, this invention proposes a novel method for synchronizing modules with each other, which offers several advantages:

[0091] This allows for the alignment of completely independent modules without any interconnect constraints (as opposed to the daisy chain solution of previous solutions).

[0092] This allows the system to start with minimal latency (due solely to the physical propagation time of the start signal) and avoids losing any clock cycles due to the elastic buffering mechanism required for managing the asynchronous operation between modules;

[0093] This allows for checking the correct connectivity of all modules by measuring the corresponding latency each time the system is powered on, and ensures the expected programming latency, for example, based on the connection between module A and module B. j The length of the connecting cable is used to limit and / or store it in the system (e.g., in module A), and the expected programming latency can be reused in the system's software each time it is powered on, the system being configured to implement the claimed method, for example, via instructions included within the processing unit of module A;

[0094] It can be easily implemented inside an FPGA;

[0095] It avoids using complex mechanisms such as data phase alignment or oversampling for data sampling;

[0096] It can immediately detect any errors in the cables of the system module (e.g., poor cable length).

Claims

1. A method for making module A (110) and each module B in the module set S. j (120) Synchronized system (100), wherein, j=1,...,M, M≥1, and S={B1,...,B M The system includes: The module A (110) is configured to operate synchronously with the clock signal CK_A (210) of period T. Module B j The set S of (120), wherein each module B j (120) is configured to operate in conjunction with the clock signal CK_B of the period T. j Operate synchronously, each module B j Includes being configured to perform sampling from module A to module B at the sampling location. j The signal S_A sent j A sampling component that samples data values; The system (100) is characterized in that it further includes at least one phase adjustment circuit, wherein the phase adjustment circuit is configured to: For a given module A (110) and a module B from the set S j (120) Form each pair of modules and calculate the total adjustment time TT_D for each pair of modules. j Adjust or control signal S_A j Data arrives at module B j The arrival time of the sampling position of the sampling component (120) is related to that of module B. j The relative time between the sampling times of the sampling components of the data, wherein the sampling time and the arrival time are directly adjacent in time; Wherein, the total adjustment time TT_D j Configured for: sampling components of module A (110) to sample components of module B j (120) The signal S_B sent to module A j Data value sampling and by module B j (120) The sampling component for the signal S_A j The sampling of data values ​​is increased by increasing the time interval between the arrival of data at the sampling position of the considered sampling component and the data sampling of the considered sampling component, wherein the time when the data sampling occurs and the time when the data arrives at the sampling position of the considered sampling component are directly adjacent in time.

2. The system (100) according to claim 1 is configured to automatically determine the total adjustment time TT_D during the calibration phase. j ,in, Module B j Configured to receive calibration signal S'_A from module A j It automatically returns to module A.

3. The system (100) according to claim 2, wherein, The calibration phase includes a repetitive loop configured to iteratively change an adjustable time T_D used to iteratively modify the time interval. i,j The value is used to automatically determine the total adjustment time TT_D. j The value; and the total adjustment time TT_D j The value is set to be equal to the value of the adjustable time that results in the following intervals: for the sampling performed by the sampling component of module A (110) and by module B j The sampling of the two components of (120) is performed by the sampling interval, which prevents the sampling of data at the time when data changes.

4. The system (100) according to claim 3, wherein, T_D i,j =(i-1)•T_inc, where, T_inc is the time increment, where T_inc <T; i is an integer, where 0 <i≤i max , where i max •T_inc≥T; During the repeated loop, T_D is changed by iteratively taking different values ​​for integer i. i,j The value of .

5. The system (100) according to claim 4, wherein, N•T_inc ≥ T and (N - 1)T_inc < T, where N is an integer, i max = N, and wherein, for i = 1, ..., N, the repeated loop for determining the total adjustment time TT_D j includes the following steps: Step A: During the initial clock period CK0_i,j of the clock signal CK_A, module A outputs the calibration signal S'_A. j The calibration signal S'_A j Including the change C_ from the first data value to the second data value i,j And to signal S'_A j Data arrives at module B j The arrival time of the sampling position of the sampling component (120) is related to that of module B. j The sampling component applies a time adjustment T_D to the relative time between the sampling times of the data. i,j , where T_D i,j =(i-1)•T_inc, so as to utilize module B j The sampling component for the signal S'_A j Sample the signal and start the counter configured to count the cycles of the clock signal CK_A. Step B: Using the counter and starting from the initial clock period CK0_i,j, count the number L of clock signal CK_A cycles. i,j The counting continues until the final clock cycle CKF_i,j, where the final clock cycle CKF_i,j is the clock cycle of the clock signal CK_A at which the counter receives the stop signal. The stop signal is configured to stop the counting performed by the counter. The stop signal is received by module A from module B. j The received signal S'_A j When the change is detected, module B is generated. j Configured to receive the signal S'_A during the repeating cycle j Send back to module A, and wherein, in order to be sent by module B j The signal S'_A j The system (100) is configured to apply the time adjustment T_D to another relative time and send it back to module A. i,j The other relative time is the calibration signal S'_A. j The relative time between the arrival time of the data at the sampling position of the sampling component of module A (110) and the sampling time of the data by the sampling component of module A, wherein the sampling time is used to sample the signal S'_A by the sampling component of module A. j Perform sampling; Step C: For the time adjustment T_D i,j , store the corresponding number L of the counted clock signal CK_A cycles i,j , and if i < N, repeat steps A to C for i = i + 1, otherwise stop the repetition loop; And after stopping the repeating loop, the system is configured to adjust the time set {T_D}. 1,j ,... ,T_D N,j Automatically select time adjustment T_D within} s,j Its characteristic is that the number of cycles L_ s,j It is an even number, where s∈{1,...,N}, and for the time adjustment T_D s,j For the sampling component of module A and module B j The two sampling components, change C_ s,j The system is further configured to set TT_D, wherein the arrival time at the sampling position of the considered sampling component is either the furthest from the adjacent sampling time of the considered sampling component or the furthest from the adjacent sampling time. j =T_D s,j =(s-1)T_inc.

6. The system (100) according to any one of claims 1 to 5, wherein, The adjustment or control is performed through adjustment module B. j The sampling time and / or data arrival of the sampling component of (120) to module B j The sampling position of the sampling component (120) is performed at a specific time.

7. The system (100) according to any one of claims 1 to 5, wherein, The phase adjustment circuit includes at least one adjustable delay component, which is configured to delay the transition from module A (110) to module B relative to the clock signal CK_A (210). j (120) Send signal S_A j (220) time, and / or used in module B j (120) Received the signal S_A j (220) after which, relative to module B j (120) Received the signal S_A j (220) The time delay of the signal S_A j (220) Arrive at module B j (120) The time of the sampling position of the sampling component.

8. The system (100) according to claim 7, wherein, The total adjustment time TT_D j =TD_A j +TD_B j , among which, TD_A j and TD_B j The delay time is implemented by the phase adjustment circuit, such that it is output by module A (110) and configured to be sent to module B. j (120) The signal S_A sent j Any change between the first data value (222) and the second data value (223) in (220) is delayed by a delay time TD_A relative to the effective transition edge of the clock signal CK_A (210). j And the arrival of the change to the sampling position relative to the change is made by module B. j The reception of (120) was delayed by a delay time TD_B. j , where if TD_A j If ≠0, then the system (100) includes a first adjustable delay component installed within module A (110), the first adjustable delay component being configured to adjust the delay time TD_A. j Applied to signal S_A j (220) To module B j (120) is sent, and if TD_B j If ≠0, then the system (100) includes a second adjustable delay component, which is installed in module B. j (120) and configured to implement the delay time TD_B j .

9. The system (100) according to claim 8, configured to implement waiting time adjustment, wherein, The system (100) or module A (110) is configured to: For each module B j Determine the output signal S_A from module A (110). j The time of the data and its origin from module B j The sampling unit of (120) samples the data using clock signals CK_A or CK_B between the sampling times. j The number of cycles L j ; In all numbers L j The following text is referred to as L. Max The maximum number, of which, , where q≠r; To each module B j (120) Simultaneously send using S_A j The start signal is configured to synchronously start all modules B. j Module B j Configured for: in module B j The sampling component for signal S_A j Before data sampling occurs, it is performed relative to the signal S_A j Data from module B j The received reception time is the delay time TD_B j To adjust the signal S_A j Data arrives at module B j The arrival time of the sampling position of the sampling component (120) is related to that of module B. j The relative time between the sampling times of the data by the sampling components, and the system (100) is also configured to send the signal S_A j Apply L Max -L j A further delay of one cycle, wherein the further delay is applied by a first further delay and a second further delay, such that the sum of the first further delay and the second further delay equals L. Max -L j A number of cycles, wherein the first further delay is in the signal S_A j The second further delay is a delay of 0 or more clock signal CK_A cycles at module A prior to the transmission of the signal S_A. j After sampling, in module B j Zero or more clock signals CK_B at the location j Delay in the cycle.

10. The system (100) according to any one of claims 1 to 5, wherein, Module B j The sampling component of (120) includes a trigger, the trigger having a relative position to the clock signal CK_B j An adjustable clock so as to adjust according to the total adjustment time TT_D j The sampling time is adjusted or controlled by the time, and the phase adjustment circuit includes components installed in module B. j The retiming element within module B is configured to re-time the data generated by module B. j The sampling component's trigger-sampled signal is retied to the clock signal CK_B. j .

11. The system (100) according to any one of claims 1 to 10, wherein, The phase adjustment circuit is also configured to: for the phase adjustment circuit consisting of module A (110) and module B j Module B in (120) j (120) Each pair of modules is formed and the total adjustment time TT_D is calculated for the considered pair of modules. j Adjust or control another relative time, said other relative time being signal S_B j The relative time between the arrival time of the data at the sampling position of the sampling component of module A (110) and the sampling time of the data by the sampling component of module A, wherein the sampling time and the arrival time are directly adjacent in time.

12. The system (100) according to claim 11, wherein, The adjustment or control of the other relative time is performed by adjusting the sampling time of the sampling component of module A (110) and / or the arrival time of the sampling position of the sampling component of module A (110).

13. The system (100) according to claim 11, wherein, The phase adjustment circuit is configured for use with respect to module B. j (120) Delay time TD'_B j The signal S_B is applied j The transmission to module A (110), and the use of module A (110) to transmit the signal S_B j The arrival at the sampling position of module A (110) relative to the signal S_B received by module A j Time delay TD'_A j , where TT_D j =TD'_A j +TD'_B j .

14. A method for making module A (110) and each module B in set S j (120) Synchronization methods, wherein, j=1,...,M, M≥1, and S={B1,...,B M }, wherein module A (110) is configured to operate synchronously with a clock signal CK_A (210) of period T, and module B j (120) is configured to operate in conjunction with the clock signal CK_B of the period T. j The method, which operates synchronously, includes: For the combination of module A (110) and module B j Module B in (120) j (120) Form each pair of modules and calculate the total adjustment time TT_D for each pair of modules. j The phase adjustment circuit adjusts or controls the signal S_A. j Data arrives at module B j The arrival time of the sampling position of the sampling component (120) is related to that of module B. j The relative time between the sampling times of the sampling components of the data, wherein the sampling time and the arrival time are directly adjacent in time; and Wherein, the total adjustment time TT_D j Configured for: sampling components of module A (110) to sample components of module B j (120) The signal S_B sent to module A j Data value sampling and by module B j (120) The sampling component for the signal S_A j The sampling of data values ​​is increased by increasing the time interval between the arrival of data at the sampling position of the considered sampling component and the data sampling of the considered sampling component, wherein the time when the data sampling occurs and the time when the data arrives at the sampling position of the considered sampling component are directly adjacent in time.

15. The method of claim 14, further comprising automatically determining the total adjustment time TT_D during the calibration phase. j including module B j The calibration signal S'_A received from module A j It automatically returns to module A.

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