Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a substrate base plate and a plurality of sub-pixels arranged on the substrate base plate, and the plurality of sub-pixels comprise sub-pixels of various colors; the display panel further comprises a first kind of initialization signal line and a second kind of initialization signal line, at least part of the first kind of initialization signal line extends in the first direction, at least part of the second kind of initialization signal line extends in the second direction, and the first direction intersects with the second direction. The first initialization signal line and the second initialization signal line are coupled with different initialization signal input ends; the sub-pixels of at least two colors in the plurality of sub-pixels are coupled with the first initialization signal line; the sub-pixel of at least one color in the plurality of sub-pixels is coupled with the second initialization signal line.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, the application field of display products is becoming more and more extensive, and the display quality requirements of users for display products are becoming higher and higher. Organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display products have attracted widespread attention due to their advantages of high resolution, wide viewing angle, fast response speed, etc. With the continuous optimization of product performance of OLED display products, reducing the power consumption of the screen body has become the main direction of the development of OLED at the present stage.

[0003] SUMMARY

[0004] The purpose of the present disclosure is to provide a display panel and a display device.

[0005] In order to achieve the above-mentioned purpose, the present disclosure provides the following technical solutions:

[0006] The first aspect of the present disclosure provides a display panel, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels comprising sub-pixels of multiple colors; the display panel further comprises:

[0007] A first initialization signal line and a second initialization signal line, at least part of the first initialization signal line extends along a first direction, at least part of the second initialization signal line extends along a second direction, and the first direction intersects the second direction; the first initialization signal line and the second initialization signal line are coupled to different initialization signal input ends;

[0008] At least two colors of sub-pixels in the plurality of sub-pixels are coupled to the first initialization signal line; at least one color of sub-pixels in the plurality of sub-pixels is coupled to the second initialization signal line.

[0009] Optionally, the plurality of sub-pixels includes a plurality of sub-pixel driving circuits arranged in an array; the plurality of sub-pixel driving circuits is divided into a plurality of rows of sub-pixel driving circuit rows, and each row of sub-pixel driving circuit rows includes a plurality of sub-pixel driving circuits arranged along a first direction.

[0010] The display panel includes a plurality of first initialization signal lines, and each first initialization signal line is coupled to each sub-pixel driving circuit belonging to at least two colors of sub-pixels in a corresponding row of sub-pixel driving circuit rows.

[0011] Optionally, the plurality of sub-pixel driving circuits are divided into a plurality of sub-pixel driving circuit columns, each of the sub-pixel driving circuit columns comprises a plurality of the sub-pixel driving circuits arranged along the second direction.

[0012] The display panel comprises a plurality of the second initialization signal lines, each of the second initialization signal lines is coupled with each of the sub-pixel driving circuits belonging to at least one color of sub-pixel in the corresponding sub-pixel driving circuit column.

[0013] Optionally, the first initialization signal lines comprise first second initialization signal lines, and the second initialization signal lines comprise second second initialization signal lines.

[0014] The sub-pixel comprises a sub-pixel driving circuit and a light emitting element, the sub-pixel driving circuit comprises a second reset transistor, and a second electrode of the second reset transistor is coupled with an anode of the light emitting element.

[0015] The first electrode of the second reset transistor in the at least two colors of sub-pixel is coupled with the corresponding first second initialization signal line, and the first electrode of the second reset transistor in the at least one color of sub-pixel is coupled with the corresponding second second initialization signal line.

[0016] Optionally, in the sub-pixel driving circuits coupled with the same first second initialization signal line, the first electrodes of the second reset transistors in at least some adjacent sub-pixel driving circuits form an integral structure.

[0017] In the same row of sub-pixel driving circuits, the first electrodes of the second reset transistors connected with the first second initialization signal lines are independent of the first electrodes of the second reset transistors connected with the second second initialization signal lines.

[0018] Optionally, the plurality of sub-pixel driving circuits in the row of sub-pixel driving circuits are divided into a plurality of circuit groups arranged along the first direction, each of the circuit groups comprises two adjacent sub-pixel driving circuits, and the gate electrodes of the second reset transistors in the two sub-pixel driving circuits form a gate pattern of an integral structure.

[0019] The display panel further comprises a second scan line, the second scan line is coupled with each of the gate patterns in the corresponding row of sub-pixel driving circuits, and the second scan line is arranged in a layer different from the gate pattern.

[0020] Optionally, the display panel further comprises a first gate metal layer and a second gate metal layer, the first gate metal layer is located between the second gate metal layer and the substrate, the gate pattern is arranged in the same layer and of the same material as the first gate metal layer, and the second scan line is arranged in the same layer and of the same material as the second gate metal layer.

[0021] Optionally, the display panel further comprises a data line and a power line; the data line is coupled with each sub-pixel drive circuit in the corresponding sub-pixel drive circuit column; the power line is coupled with each sub-pixel drive circuit in the corresponding sub-pixel drive circuit column;

[0022] The power line connected with the sub-pixel drive circuit coupled with the second second initialization signal line is located between the second second initialization signal line and the data line connected with the sub-pixel drive circuit coupled with the second second initialization signal line.

[0023] The power line connected with the sub-pixel drive circuit coupled with the second second initialization signal line is located between the second second initialization signal line and the data line connected with the sub-pixel drive circuit coupled with the second second initialization signal line.

[0024] Optionally, the display panel further comprises:

[0025] A first initialization compensation line, at least part of the first initialization compensation line extends along the second direction, and the first initialization compensation line is coupled with each first second initialization signal line;

[0026] The first initialization compensation line and the second second initialization signal line are alternately arranged along the first direction, and the first initialization compensation line is located between two adjacent power lines forming a first power group.

[0027] The two adjacent power lines of the second second initialization signal line form a second power group, and the first power group and the second power group are alternately arranged.

[0028] Optionally, the display panel further comprises:

[0029] A first virtual compensation line, at least part of the first virtual compensation line extends along the second direction, and the first virtual compensation line is alternately arranged with the second second initialization signal line along the first direction, and the first virtual compensation line is located between two adjacent power lines forming a first power group.

[0030] The two adjacent power lines of the second second initialization signal line form a second power group, and the first power group and the second power group are alternately arranged.

[0031] Optionally, the sub-pixel comprises a sub-pixel drive circuit and a light emitting element, the sub-pixel drive circuit comprises a second reset transistor, and the second electrode of the second reset transistor is coupled with the anode of the light emitting element.

[0032] The display panel comprises a second initialization signal line, at least part of the second initialization signal line extends along the first direction.

[0033] The first electrode of the second reset transistor included in each of the sub-pixel drive circuits in a corresponding row of sub-pixel drive circuits is coupled to a second initialization signal line.

[0034] Optionally, the first initialization signal line includes a first third initialization signal line, and the second initialization signal line includes a second third initialization signal line.

[0035] The sub-pixel includes a sub-pixel drive circuit and a light emitting element, the sub-pixel drive circuit includes a drive transistor and a third reset transistor, the second electrode of the third reset transistor is coupled to the first electrode of the drive transistor.

[0036] The first electrode of the third reset transistor in the sub-pixel of the at least two colors is coupled to the corresponding first third initialization signal line, and the first electrode of the third reset transistor in the sub-pixel of the at least one color is coupled to the corresponding second third initialization signal line.

[0037] Optionally, the second third initialization signal line is located between a data line connected to the sub-pixel drive circuit to which the second third initialization signal line is coupled and a data line adjacent to the data line.

[0038] The data line connected to the sub-pixel drive circuit to which the second third initialization signal line is coupled is located between the second third initialization signal line and a power supply line connected to the sub-pixel drive circuit to which the second third initialization signal line is coupled.

[0039] Optionally, the display panel further includes:

[0040] A second initialization compensation line, at least part of the second initialization compensation line extends along a second direction, the second initialization compensation line is coupled to each of the first third initialization signal lines.

[0041] The second initialization compensation line and the second third initialization signal line are alternately arranged along a first direction, and the second initialization compensation line is located between two adjacent data lines, the two adjacent data lines form a first group of data lines.

[0042] The second third initialization signal line and the two adjacent data lines form a second group of data lines, and the first group of data lines and the second group of data lines are alternately arranged.

[0043] Optionally, the display panel further includes:

[0044] a second virtual compensation line, at least part of the second virtual compensation line extends along a second direction, the second virtual compensation line is arranged alternately with the second third initialization signal line along the first direction, and the second virtual compensation line is located between two adjacent data lines forming a first data group.

[0045] The two adjacent data lines of the second third initialization signal line form a second data group, and the first data group and the second data group are arranged alternately.

[0046] Optionally, a channel length of a driving transistor in a sub-pixel driving circuit coupled with the second third initialization signal line is smaller than a channel length of a driving transistor in a sub-pixel driving circuit coupled with the first third initialization signal line.

[0047] Optionally, the sub-pixel comprises a sub-pixel driving circuit and a light emitting element, the sub-pixel driving circuit comprises a driving transistor and a third reset transistor, and a second electrode of the third reset transistor is coupled with a first electrode of the driving transistor.

[0048] The display panel comprises a third initialization signal line, at least part of the third initialization signal line extends along a first direction.

[0049] The third initialization signal line is coupled with a first electrode of a third reset transistor included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0050] Optionally, the display panel further comprises a first source-drain metal layer and a second source-drain metal layer; the first initialization signal line is arranged in the same layer and made of the same material as the first source-drain metal layer; and the second initialization signal line is arranged in the same layer and made of the same material as the second source-drain metal layer.

[0051] Optionally, the display panel further comprises:

[0052] a first power transmission layer and a second power transmission layer, the sub-pixels of the at least two colors are coupled with the first power transmission layer, and the sub-pixels of the at least one color are coupled with the second power transmission layer.

[0053] a power management circuit, the power management circuit comprises a power signal output end.

[0054] a first connection line and a second connection line, the first connection line is coupled with the first power transmission layer and the power signal output end respectively, and the second connection line is coupled with the second power transmission layer and the power signal output end respectively; a line width of the first connection line is smaller than a line width of the second connection line, and a line length of the first connection line is greater than a line length of the second connection line.

[0055] Optionally, the plurality of sub-pixel driving circuits are divided into a plurality of columns of sub-pixel driving circuit columns, each column of sub-pixel driving circuit columns comprising a plurality of the sub-pixel driving circuits arranged along the second direction;

[0056] The first power transmission layer comprises a first power bus and a plurality of first power lines arranged along the first direction, the plurality of first power lines being respectively coupled to the first power bus; each first power line is coupled to each sub-pixel driving circuit belonging to the at least two colors in the corresponding column of sub-pixel driving circuit columns; the first power bus is coupled to the first connection line;

[0057] The second power transmission layer comprises a second power bus and a plurality of second power lines arranged along the first direction, the plurality of second power lines being respectively coupled to the second power bus; each second power line is coupled to each sub-pixel driving circuit belonging to the at least one color in the corresponding column of sub-pixel driving circuit columns; the second power bus is coupled to the second connection line.

[0058] Optionally, the sub-pixel driving circuit comprises a driving transistor and a storage capacitor, a first plate of the storage capacitor being coupled to a gate of the driving transistor;

[0059] In the same row of sub-pixel driving circuits, second plates of the storage capacitors comprised by each of the sub-pixel driving circuits are coupled in sequence to form a plate layer of an integrated structure, the plate layer being respectively coupled to the plurality of second power lines.

[0060] Optionally, the display panel further comprises:

[0061] An optical shielding layer, the optical shielding layer being located between the plurality of sub-pixels and the substrate, the optical shielding layer being coupled to the second power transmission layer.

[0062] Optionally, the sub-pixel driving circuit further comprises a driving transistor, a first reset transistor and a compensation transistor;

[0063] A second plate of the first reset transistor is coupled to a gate of the driving transistor; a first plate of the compensation transistor is coupled to a second plate of the driving transistor, and a second plate of the compensation transistor is coupled to the gate of the driving transistor;

[0064] The first power line includes a first power body part and a first power protruding part coupled thereto, the first power body part extends along a second direction, the first power protruding part protrudes from the first power body part along the first direction, a projection of the first power protruding part on the substrate substrate covers a projection of the first reset transistor in the sub-pixel drive circuit coupled thereto on the substrate substrate, and / or covers a projection of the compensation transistor in the sub-pixel drive circuit coupled thereto on the substrate substrate;

[0065] The second power line includes a second power body part and a second power protruding part coupled thereto, the second power body part extends along a second direction, the second power protruding part protrudes from the second power body part along the first direction, a projection of the second power protruding part on the substrate substrate covers a projection of the first reset transistor in the sub-pixel drive circuit coupled thereto on the substrate substrate, and / or covers a projection of the compensation transistor in the sub-pixel drive circuit coupled thereto on the substrate substrate.

[0066] Optionally, the plurality of colors of sub-pixels include red sub-pixels, green sub-pixels, and blue sub-pixels; the at least two colors of sub-pixels include red sub-pixels and green sub-pixels; and the at least one color of sub-pixels includes blue sub-pixels.

[0067] The red sub-pixel includes a red sub-pixel drive circuit and a red light emitting element coupled thereto; the green sub-pixel includes a green sub-pixel drive circuit and a green light emitting element coupled thereto; and the blue sub-pixel includes a blue sub-pixel drive circuit and a blue light emitting element coupled thereto.

[0068] The plurality of colors of sub-pixel drive circuits of the plurality of colors of sub-pixels are divided into a plurality of columns of sub-pixel drive circuit columns; the plurality of columns of sub-pixel drive circuit columns include a red sub-pixel drive circuit column, a first green sub-pixel drive circuit column, a blue sub-pixel drive circuit column, and a second green sub-pixel drive circuit column arranged in a first direction in a sequence and cyclically.

[0069] The green light emitting elements coupled to the first green sub-pixel drive circuit column form a first green light emitting element column, a projection of the first green light emitting element column on the substrate substrate overlaps a projection of the adjacent red sub-pixel drive circuit column on the substrate substrate.

[0070] The green light emitting elements coupled to the second green sub-pixel drive circuit column form a second green light emitting element column, a projection of the second green light emitting element column on the substrate substrate overlaps a projection of the adjacent blue sub-pixel drive circuit column on the substrate substrate.

[0071] The red light emitting elements coupled by the red sub-pixel driving circuit column are divided into at least one sub-red light emitting element column, the sub-red light emitting element column including the red light emitting elements coupled by the odd-numbered sub-pixel driving circuit in the red sub-pixel driving circuit column; or the sub-red light emitting element column including the red light emitting elements coupled by the even-numbered sub-pixel driving circuit in the red sub-pixel driving circuit column.

[0072] The red light emitting elements coupled by the red sub-pixel driving circuit column are divided into at least one sub-red light emitting element column, the sub-red light emitting element column including the red light emitting elements coupled by the odd-numbered sub-pixel driving circuit in the red sub-pixel driving circuit column; or the sub-red light emitting element column including the red light emitting elements coupled by the even-numbered sub-pixel driving circuit in the red sub-pixel driving circuit column.

[0073] The blue light emitting elements coupled by the blue sub-pixel driving circuit column are divided into at least one sub-blue light emitting element column, the sub-blue light emitting element column including the blue light emitting elements coupled by the odd-numbered sub-pixel driving circuit in the blue sub-pixel driving circuit column; or the sub-blue light emitting element column including the blue light emitting elements coupled by the even-numbered sub-pixel driving circuit in the blue sub-pixel driving circuit column.

[0074] The blue light emitting elements coupled by the blue sub-pixel driving circuit column are divided into at least one sub-blue light emitting element column, the sub-blue light emitting element column including the blue light emitting elements coupled by the odd-numbered sub-pixel driving circuit in the blue sub-pixel driving circuit column; or the sub-blue light emitting element column including the blue light emitting elements coupled by the even-numbered sub-pixel driving circuit in the blue sub-pixel driving circuit column.

[0075] Optionally, the red light emitting element includes a red anode layer, the red anode layer including a red anode main body part and a red anode connecting part coupled with each other, the red anode main body part having a projection on the substrate substrate overlapping with a projection of an adjacent green sub-pixel driving circuit column on the substrate substrate; an opening area of the red light emitting element having a projection on the substrate substrate located inside the projection of the red anode main body part on the substrate substrate; and the red anode connecting part coupled with a sub-pixel driving circuit in a sub-pixel belonging to the red anode connecting part.

[0076] The blue light emitting element includes a blue anode layer, the blue anode layer including a blue anode main body part and a blue anode connecting part coupled with each other, the blue anode main body part having a projection on the substrate substrate overlapping with a projection of an adjacent green sub-pixel driving circuit column on the substrate substrate; an opening area of the blue light emitting element having a projection on the substrate substrate located inside the projection of the blue anode main body part on the substrate substrate; and the blue anode connecting part coupled with a sub-pixel driving circuit in a sub-pixel belonging to the blue anode connecting part.

[0077] The length of the red anode connecting part is substantially the same as the length of the blue anode connecting part.

[0078] A second aspect of the present disclosure provides a display device including the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0079] The accompanying drawings, which are included to provide a further understanding of the disclosure and constitute a part of the disclosure, illustrate embodiments of the disclosure and serve to explain the disclosure together with the specification: in the drawings:

[0080] FIG. 1 is a first circuit schematic diagram of an RGB sub-pixel driving circuit according to an embodiment of the present disclosure;

[0081] FIG. 2 is a second circuit schematic diagram of an RGB sub-pixel driving circuit according to an embodiment of the present disclosure;

[0082] FIG. 3 is a layout schematic diagram of a light shielding layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0083] FIG. 4 is a first layout schematic diagram of a first active layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0084] FIG. 5 is a second layout schematic diagram of a first active layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0085] FIG. 6 is a layout schematic diagram of a light shielding layer and a first active layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0086] FIG. 7 is a layout schematic diagram of a first gate metal layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0087] FIG. 8 is a layout schematic diagram of a first active layer and a first gate metal layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0088] FIG. 9 is a layout schematic diagram of a second gate metal layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0089] FIG. 10 is a layout schematic diagram of a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0090] FIG. 11 is a layout schematic diagram of a second active layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0091] FIG. 12 is a layout schematic diagram of a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0092] FIG. 13 is a layout schematic diagram of a third gate metal layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0093] FIG. 14 is a layout schematic diagram of a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0094] FIG. 15 is a layout schematic diagram of a first source-drain metal layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0095] FIG. 16 is a layout diagram of a via on the first source-drain metal layer and the interlayer insulating layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0096] FIG. 17 is a layout diagram of a via on the first source-drain metal layer and the interlayer insulating layer added on the basis of FIG. 14;

[0097] FIG. 18 is a first layout diagram of the second source-drain metal layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0098] FIG. 19 is a layout diagram of the first kind of second source-drain metal layer added on the basis of FIG. 17;

[0099] FIG. 20 is a layout diagram of the anode layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0100] FIG. 21 is a layout diagram of the anode layer added on the basis of FIG. 19;

[0101] FIG. 22 is a second layout diagram of the second source-drain metal layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0102] FIG. 23 is a layout diagram of the second kind of second source-drain metal layer added on the basis of FIG. 17;

[0103] FIG. 24 is a third layout diagram of the second source-drain metal layer in a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0104] FIG. 25 is a layout diagram of the third kind of second source-drain metal layer added on the basis of FIG. 17;

[0105] FIG. 26 is a first layout diagram of a two-row six-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0106] FIG. 27 is a layout diagram of a first kind of first active layer in a two-row six-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0107] FIG. 28 is a layout diagram of another kind of first active layer in a two-row six-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0108] FIG. 29 is a layout diagram of the first active layer and the first source-drain metal layer in a two-row six-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0109] FIG. 30 is a layout diagram of the second source-drain metal layer added on the basis of FIG. 29;

[0110] FIG. 31 is a second layout diagram of a two-row six-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0111] FIG. 32 is a third layout diagram of a two-row six-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0112] FIG. 33 is a layout diagram of a two-row four-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0113] FIG. 34 is a fourth layout diagram of a two-row six-column sub-pixel driving circuit according to an embodiment of the present disclosure;

[0114] FIG. 35 is a connection diagram between a power management circuit and a power bus according to an embodiment of the present disclosure;

[0115] FIG. 36 is a diagram of data writing in the related art;

[0116] FIG. 37 is a timing diagram of data writing corresponding to FIG. 36;

[0117] FIG. 38 is another diagram of data writing in the related art;

[0118] FIG. 39 is a timing diagram of data writing corresponding to FIG. 38;

[0119] FIG. 40 is a layout diagram of a light emitting element and a sub-pixel driving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0120] To further illustrate the display panel and the display device provided by the embodiments of the present disclosure, the following will be described in detail in conjunction with the accompanying drawings.

[0121] With the development of OLED display technology, product performance is continuously optimized, and reducing screen power consumption has become the direction of the development of OLED display products at the present stage. However, in the traditional OLED display product, because the light emitting materials of R (red), G (green), and B (blue) sub-pixels are different, the voltages for turning on the R, G, and B sub-pixels, resetting the anode, and initializing are different. In order to enable sub-pixels of different colors to emit light normally, the related art adopts a larger voltage value for each of the above voltages to simultaneously meet the needs of different sub-pixels, but this way increases the power consumption of the display product. Therefore, how to reduce the power consumption of the display product has become a technical problem to be solved.

[0122] Referring to FIGS. 19 and 26, the display panel provided by the embodiments of the present disclosure includes a substrate and a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels including sub-pixels of multiple colors; the display panel further includes:

[0123] The first initialization signal lines (such as the first second initialization signal line V21 and the first third initialization signal line Vbias1) and the second initialization signal lines (such as the second second initialization signal line V22 and the second third initialization signal line Vbias2) are coupled to different initialization signal inputs.

[0124] The sub-pixels of at least two colors are coupled to the first initialization signal lines, and the sub-pixels of at least one color are coupled to the second initialization signal lines.

[0125] The display panel includes a plurality of sub-pixels, and the plurality of sub-pixels includes a plurality of sub-pixel driving circuits arranged in an array. The plurality of sub-pixel driving circuits is divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the second direction. The first direction and the second direction are intersected, for example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0126] The sub-pixel includes a sub-pixel driving circuit and a light emitting element. The sub-pixel driving circuit is coupled to an anode of the light emitting element to provide a driving signal for the light emitting element to emit light.

[0127] The plurality of sub-pixels of different colors include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. The sub-pixels of at least two colors include red sub-pixels and green sub-pixels, and the sub-pixels of at least one color include blue sub-pixels, but are not limited thereto.

[0128] The display panel includes a plurality of first initialization signal lines arranged along a second direction, and at least part of the first initialization signal lines extend along a first direction. The display panel includes a plurality of second initialization signal lines arranged along the first direction, and at least part of the second initialization signal lines extend along the second direction.

[0129] Exemplarily, the transistor in the sub-pixel connected by the first initialization signal line and the second initialization signal line is a transistor with the same function. For example, the first initialization signal line and the second initialization signal line are both connected to the second reset transistor T7 in the corresponding sub-pixel; the first initialization signal line and the second initialization signal line are both connected to the third reset transistor T8 in the corresponding sub-pixel, but are not limited thereto.

[0130] Exemplarily, the first initialization signal line and the second initialization signal line are coupled to different initialization signal input ends. The initialization signal input end coupled to the first initialization signal line inputs an initialization signal suitable for the at least two colors of sub-pixels; the initialization signal input end coupled to the second initialization signal line inputs an initialization signal suitable for the at least one color of sub-pixel.

[0131] Exemplarily, the display panel comprises, in a direction away from the substrate, a buffer layer, a first active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a third gate insulating layer, a second active layer, a fourth gate insulating layer, a third gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a passivation layer, a first planarization layer, a second source-drain metal layer, a second planarization layer, an anode layer, a pixel definition layer, a light-emitting functional layer, a cathode layer, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The display panel can further comprise a third source-drain metal layer and a third planarization layer, the third source-drain metal layer being located between the second planarization layer and the anode layer, and the third planarization layer being located between the third source-drain metal layer and the anode layer.

[0132] Exemplarily, the display panel further comprises a first source-drain metal layer and a second source-drain metal layer; the first initialization signal line and the first source-drain metal layer are provided in the same layer and are made of the same material; and the second initialization signal line and the second source-drain metal layer are provided in the same layer and are made of the same material. This arrangement enables the first initialization signal line to be formed at the same time as the first source-drain metal layer in the same patterning process, and enables the second initialization signal line to be formed at the same time as the second source-drain metal layer in the same patterning process, thereby effectively simplifying the manufacturing process flow of the display panel and reducing the manufacturing cost of the display panel.

[0133] According to the specific structure of the display panel, the display panel provided by the embodiment of the present disclosure is provided, in which a first initialization signal line and a second initialization signal line connected with different initialization signal input ends are arranged, and at least two colors of sub-pixels in the plurality of sub-pixels are coupled with the first initialization signal line, and at least one color of sub-pixels in the plurality of sub-pixels are coupled with the second initialization signal line. This arrangement enables the first initialization signal line to provide initialization signals matching the requirements of at least two colors of sub-pixels for the at least two colors of sub-pixels, and enables the second initialization signal line to provide initialization signals matching the requirements of at least one color of sub-pixels for the at least one color of sub-pixels, thereby realizing separate driving of initialization signals in at least part of sub-pixels of different colors and reducing the power consumption of the display product.

[0134] Therefore, in the display panel provided by the embodiment of the present disclosure, initialization signals meeting the requirements of sub-pixels of different colors can be adaptively provided according to the actual requirements of sub-pixels of different colors, and it is not necessary to provide initialization signals meeting the requirements of all colors of sub-pixels. Therefore, the initialization signals provided by the embodiment of the present disclosure do not need to be compatible with a larger voltage value meeting the requirements of various colors of sub-pixels, thereby effectively reducing the power consumption of the display panel.

[0135] As shown in FIGS. 19 and 26, in some embodiments, the plurality of sub-pixels includes a plurality of sub-pixel driving circuits arranged in an array; the plurality of sub-pixel driving circuits is divided into a plurality of rows of sub-pixel driving circuit rows, and each row of sub-pixel driving circuit rows includes a plurality of sub-pixel driving circuits arranged along a first direction.

[0136] The display panel includes a plurality of first initialization signal lines, and each first initialization signal line is coupled with each sub-pixel driving circuit belonging to the at least two colors of sub-pixels in a corresponding row of sub-pixel driving circuit rows.

[0137] For example, the plurality of first initialization signal lines correspond to the plurality of rows of sub-pixel driving circuit rows one by one, and each first initialization signal line is coupled with each sub-pixel driving circuit belonging to the at least two colors of sub-pixels in a corresponding row of sub-pixel driving circuit rows. For example, each row of sub-pixel driving circuit rows includes sub-pixel driving circuits belonging to the at least two colors of sub-pixels and sub-pixel driving circuits belonging to the at least one color of sub-pixels.

[0138] As shown in FIGS. 19 and 26, in some embodiments, the plurality of sub-pixel driving circuits is divided into a plurality of columns of sub-pixel driving circuit columns, and each column of sub-pixel driving circuit columns includes a plurality of sub-pixel driving circuits arranged along a second direction.

[0139] The display panel comprises a plurality of the second initialization signal lines, and each of the second initialization signal lines is coupled to each sub-pixel drive circuit of the sub-pixels belonging to the at least one color in the corresponding column of sub-pixel drive circuits.

[0140] For example, the plurality of the second initialization signal lines correspond to the plurality of columns of sub-pixel drive circuits one by one, and each of the second initialization signal lines is coupled to each sub-pixel drive circuit of the sub-pixels belonging to the at least one color in the corresponding column of sub-pixel drive circuits. For example, the column of sub-pixel drive circuits comprises the sub-pixel drive circuits of the sub-pixels belonging to the at least one color.

[0141] The display panel provided by the above embodiment arranges the plurality of first initialization signal lines in the second direction and couples the first initialization signal lines to the sub-pixel drive circuits in the corresponding row of sub-pixel drive circuits, and arranges the plurality of first initialization signal lines in the first direction and couples the first initialization signal lines to the sub-pixel drive circuits in the corresponding column of sub-pixel drive circuits. This arrangement reasonably utilizes the limited layout space inside the display panel, and effectively reduces the layout difficulty of various initialization signal lines inside the display panel while providing corresponding initialization signal terminals for sub-pixels of different colors.

[0142] As shown in FIGS. 1, 3-21, in some embodiments, the first initialization signal lines comprise a first second initialization signal line V21, and the second initialization signal lines comprise a second second initialization signal line V22.

[0143] The sub-pixel comprises a sub-pixel drive circuit and a light emitting element, and the sub-pixel drive circuit comprises a second reset transistor T7, and a second electrode of the second reset transistor T7 is coupled to an anode of the light emitting element.

[0144] The first electrode of the second reset transistor T7 in the sub-pixel of the at least two colors is coupled to the corresponding first second initialization signal line V21, and the first electrode of the second reset transistor T7 in the sub-pixel of the at least one color is coupled to the corresponding second second initialization signal line V22.

[0145] As shown in FIG. 4, for example, in the sub-pixel drive circuits coupled to the same first second initialization signal line V21, the first electrodes of the second reset transistors T7 included in at least some adjacent sub-pixel drive circuits form an integrated structure, and in the same row of sub-pixel drive circuits, the first electrodes of the second reset transistors T7 connected to the first second initialization signal line V21 are independent of the first electrodes of the second reset transistors T7 connected to the second second initialization signal line V22.

[0146] As shown in FIG. 17, in more detail, the sub-pixel drive circuits included in the row of sub-pixel drive circuits are divided into a plurality of groups of first circuits DL1 and a plurality of groups of second circuits DL2, the groups of first circuits DL1 and the groups of second circuits DL2 are arranged alternately along a first direction; the group of first circuits DL1 includes two adjacent sub-pixel drive circuits, the two sub-pixel drive circuits belong to the at least two colors of sub-pixels; the group of second circuits DL2 includes two adjacent sub-pixel drive circuits, one of the two sub-pixel drive circuits belongs to the at least two colors of sub-pixels, and the other of the two sub-pixel drive circuits belongs to the at least one color of sub-pixels.

[0147] The two sub-pixel drive circuits in the group of first circuits DL1 include a first electrode of a second reset transistor T7 formed as an integral structure; the two sub-pixel drive circuits in the group of second circuits DL2 include a first electrode of a second reset transistor T7 independent of each other.

[0148] The above arrangement is conducive to reducing the difficulty of coupling between the first electrode of the second reset transistor T7 in each sub-pixel drive circuit and the corresponding first or second second initialization signal line V21 or V22, while ensuring that the first electrode of the second reset transistor T7 in each sub-pixel drive circuit can accurately receive the initialization signal provided by the corresponding initialization signal line.

[0149] The above arrangement can adaptively provide second initialization signals that meet the needs of sub-pixels of different colors according to the actual needs of sub-pixels of different colors, without providing second initialization signals that meet the needs of all color sub-pixels. Therefore, the second initialization signal provided by the above embodiment does not need to be compatible with a larger voltage value that meets the needs of sub-pixels of various colors, thereby effectively reducing the power consumption of the display panel.

[0150] As shown in FIGS. 3 to 10, in some embodiments, the plurality of sub-pixel drive circuits in the row of sub-pixel drive circuits are divided into a plurality of groups of circuits arranged along a first direction, each group of circuits includes two adjacent sub-pixel drive circuits, the gate electrodes of the second reset transistors T7 included in the two sub-pixel drive circuits form a gate pattern 40 of an integral structure; the display panel further includes a second scan line GA2, the second scan line GA2 is coupled with each gate pattern 40 in a corresponding row of sub-pixel drive circuits, and the second scan line GA2 and the gate pattern 40 are arranged in different layers.

[0151] As shown in FIG. 17, for example, the plurality of groups of circuits include the groups of first circuits DL1 and the groups of second circuits DL2, but are not limited thereto.

[0152] Exemplarily, the display panel further comprises a plurality of second scan lines GA2 corresponding to the plurality of rows of sub-pixel driving circuit rows, each of the second scan lines GA2 is coupled with each gate pattern 40 in a corresponding row of sub-pixel driving circuit rows, for providing a second scan signal to the gate pattern coupled with the second scan line, so as to control the second reset transistor T7 to transmit the second initialization signal received by the second reset transistor T7 to the anode of the light emitting element.

[0153] Exemplarily, the display panel further comprises a first gate metal layer and a second gate metal layer, the first gate metal layer is located between the second gate metal layer and the substrate; the gate pattern 40 is arranged in the same layer and of the same material as the first gate metal layer, and the second scan line GA2 is arranged in the same layer and of the same material as the second gate metal layer.

[0154] The above arrangement is not only conducive to simplifying the manufacturing process flow of the display panel, but also conducive to reducing the layout difficulty of the second scan line GA2.

[0155] As shown in FIGS. 18 and 19, in some embodiments, the display panel further comprises a data line DA and a power supply line (such as a first power supply line VDD1 and a second power supply line VDD2); the data line DA is coupled with each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuit columns; the power supply line is coupled with each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuit columns.

[0156] The second kind of second initialization signal line V22 is located between the power supply line connected with the sub-pixel driving circuit coupled with the second kind of second initialization signal line V22 and the power supply line adjacent to the power supply line.

[0157] The power supply line connected with the sub-pixel driving circuit coupled with the second kind of second initialization signal line V22 is located between the second kind of second initialization signal line V22 and the data line DA connected with the sub-pixel driving circuit coupled with the second kind of second initialization signal line V22.

[0158] Exemplarily, the display panel comprises a plurality of data lines DA corresponding to the plurality of columns of sub-pixel driving circuit columns, each data line DA is coupled with each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuit columns.

[0159] Exemplarily, the display panel comprises a plurality of power supply lines corresponding to the plurality of columns of sub-pixel driving circuit columns, each power supply line is coupled with each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuit columns.

[0160] Exemplarily, the second second initialization signal line V22 is located between two power supply lines corresponding to a circuit group to which the sub-pixel driving circuit coupled to the second second initialization signal line V22 belongs.

[0161] The above arrangement makes the second second initialization signal line V22 have a closer distance to the first electrode of the second reset transistor T7 to be coupled to the second second initialization signal line V22, and better realize the electrical connection between the second second initialization signal line V22 and the first electrode of the second reset transistor T7, and reduce the overall layout difficulty of the display panel.

[0162] As shown in FIGS. 22 and 23, in some embodiments, the display panel further comprises:

[0163] A first initialization compensation line VB1, at least part of the first initialization compensation line VB1 extends along the second direction, and the first initialization compensation line VB1 is coupled to each of the first second initialization signal lines V21;

[0164] The first initialization compensation line VB1 and the second second initialization signal line V22 are arranged alternately along the first direction, and the first initialization compensation line VB1 is located between two adjacent power supply lines forming a first power supply group DY1.

[0165] The two adjacent power supply lines of the second second initialization signal line V22 form a second power supply group DY2, and the first power supply group DY1 and the second power supply group DY2 are arranged alternately.

[0166] Exemplarily, the first power supply group DY1 corresponds to the first circuit group DL1 one by one, and the second power supply group DY2 corresponds to the second circuit group DL2 one by one. The first initialization compensation line VB1 is located between the two power supply lines in the corresponding first power supply group DY1, and the second second initialization signal line V22 is located between the two power supply lines in the corresponding second power supply group DY2.

[0167] Exemplarily, the first initialization compensation line VB1 and the second second initialization signal line V22 are arranged in the same layer and the same material as the second source-drain metal layer, but are not limited thereto.

[0168] The above arrangement makes the overall layout of the second source-drain metal layer have better uniformity, and the above structure can make the first initialization compensation line VB1 and the first second initialization signal line V21 jointly form a mesh structure, thereby facilitating reducing the loading of the first second initialization signal line V21 in transmitting the second initialization signal.

[0169] As shown in FIGS. 24 and 25, in some embodiments, the display panel further comprises:

[0170] a first dummy compensation line Dum1, at least part of the first dummy compensation line Dum1 extends along the second direction, the first dummy compensation line Dum1 is arranged alternately with the second second initialization signal line V22 along the first direction, the first dummy compensation line Dum1 is located between two adjacent power lines forming a first power group DY1;

[0171] the two adjacent power lines of the second second initialization signal line V22 form a second power group DY2, and the first power group DY1 and the second power group DY2 are arranged alternately.

[0172] For example, the first power group DY1 corresponds to the first circuit group DL1 one by one, and the second power group DY2 corresponds to the second circuit group DL2 one by one. The first dummy compensation line Dum1 is located between two power lines in the corresponding first power group DY1, and the second second initialization signal line V22 is located between two power lines in the corresponding second power group DY2.

[0173] For example, the first dummy compensation line Dum1 and the second second initialization signal line V22 are arranged in the same layer and material as the second source-drain metal layer, but are not limited thereto.

[0174] The above arrangement makes the overall layout of the second source-drain metal layer have better uniformity.

[0175] As shown in FIG. 26, in some embodiments, the sub-pixel comprises a sub-pixel driving circuit and a light emitting element, the sub-pixel driving circuit comprises a second reset transistor T7, and the second electrode of the second reset transistor T7 is coupled with the anode of the light emitting element.

[0176] The display panel comprises a second initialization signal line V2, at least part of the second initialization signal line V2 extends along the first direction; and the first electrode of the second reset transistor T7 included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits is coupled with the second initialization signal line V2.

[0177] For example, the display panel comprises a plurality of second initialization signal lines V2, the plurality of second initialization signal lines V2 correspond to the plurality of rows of sub-pixel driving circuits one by one, and the first electrode of the second reset transistor T7 included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits is coupled with the second initialization signal line V2.

[0178] The above arrangement enables the sub-pixels of various colors to receive the same second initialization signal.

[0179] As shown in FIGS. 26-34, in some embodiments, the first initialization signal line includes a first third initialization signal line Vbias1, and the second initialization signal line includes a second third initialization signal line Vbias2.

[0180] The sub-pixel includes a sub-pixel driving circuit and a light emitting element coupled thereto, and the sub-pixel driving circuit includes a driving transistor T3 and a third reset transistor T8, a second electrode of the third reset transistor T8 being coupled to a first electrode of the driving transistor T3.

[0181] The first electrode of the third reset transistor T8 in the sub-pixel of at least two colors is coupled to the corresponding first third initialization signal line Vbias1, and the first electrode of the third reset transistor T8 in the sub-pixel of at least one color is coupled to the corresponding second third initialization signal line Vbias2.

[0182] For example, the third reset transistor T8 resets the first electrode of the driving transistor T3 using the third initialization signal, which can improve the hysteresis effect.

[0183] It is worth noting that when the sub-pixel driving circuit is laid out, the gate of the second reset transistor T7 and the gate of the third reset transistor T8 can be coupled to the same second scan line, which can reduce the number of traces and is conducive to further improving the resolution of the display panel.

[0184] The above arrangement can adaptively provide third initialization signals that meet the needs of sub-pixels of different colors according to the actual needs of sub-pixels of different colors, without providing third initialization signals that meet the needs of all color sub-pixels. Therefore, the third initialization signal provided by the above embodiment does not need to be compatible with a larger voltage value that meets the needs of sub-pixels of various colors, thereby effectively reducing the power consumption of the display panel.

[0185] As shown in FIGS. 26-30, in some embodiments, the second third initialization signal line Vbias2 is located between a data line DA connected to the sub-pixel driving circuit to which the second third initialization signal line Vbias2 is coupled and a data line DA adjacent to the data line DA.

[0186] The data line DA connected to the sub-pixel driving circuit to which the second third initialization signal line Vbias2 is coupled is located between the second third initialization signal line Vbias2 and a power supply line connected to the sub-pixel driving circuit to which the second third initialization signal line Vbias2 is coupled.

[0187] The above arrangement mode makes the second third initialization signal line Vbias2 and the first electrode of the third reset transistor T8 to be coupled have a closer distance, and can better realize the electrical connection between the second third initialization signal line Vbias2 and the first electrode of the third reset transistor T8, and reduce the overall layout difficulty of the display panel.

[0188] As shown in FIG. 31, in some embodiments, the display panel further comprises:

[0189] A second initialization compensation line VB2, at least part of the second initialization compensation line VB2 extends along the second direction, and the second initialization compensation line VB2 is coupled with each of the first third initialization signal lines Vbias1;

[0190] The second initialization compensation line VB2 and the second third initialization signal line Vbias2 are arranged alternately along the first direction, and the second initialization compensation line VB2 is located between two adjacent data lines DA, and the two adjacent data lines DA form a first data group SJ1.

[0191] The second third initialization signal line Vbias2 and the two adjacent data lines DA form a second data group SJ2, and the first data group SJ1 and the second data group SJ2 are arranged alternately.

[0192] For example, in each data group, the distance between the two data lines is substantially the same, which is beneficial to ensure the layout uniformity of the display panel.

[0193] For example, the second initialization compensation line and the second third initialization signal line are arranged in the same layer and the same material with the second source-drain metal layer, but are not limited thereto.

[0194] The above arrangement mode makes the second source-drain metal layer have better uniformity in overall layout, and the above structure can make the second initialization compensation line and the first third initialization signal line form a mesh structure together, thereby being beneficial to reduce the loading of the first third initialization signal line in transmitting the third initialization signal.

[0195] As shown in FIG. 32, in some embodiments, the display panel further comprises:

[0196] A second virtual compensation line Dum2, at least part of the second virtual compensation line Dum2 extends along the second direction, and the second virtual compensation line Dum2 is arranged alternately with the second third initialization signal line Vbias2 along the first direction, and the second virtual compensation line Dum2 is located between two adjacent data lines DA, and the two adjacent data lines DA form a first data group SJ1.

[0197] The second group of data groups SJ2 is formed by two data lines DA adjacent to the second third initialization signal line Vbias2, and the first group of data groups SJ1 and the second group of data groups SJ2 are arranged alternately.

[0198] Exemplarily, the second dummy compensation line Dum2 and the second third initialization signal line Vbias2 are arranged in the same layer and material as the second source-drain metal layer, but are not limited thereto.

[0199] The above arrangement manner makes the overall layout of the second source-drain metal layer have better uniformity.

[0200] As shown in FIG. 27, in some embodiments, the channel length d1 of the driving transistor T3 in the sub-pixel driving circuit coupled with the second third initialization signal line Vbias2 is smaller than the channel length d2 of the driving transistor T3 in the sub-pixel driving circuit coupled with the first third initialization signal line Vbias1.

[0201] It should be noted that the channel length refers to the length in the channel length direction of the channel width-length ratio of the transistor.

[0202] Exemplarily, the difference between the channel length of the driving transistor T3 in the sub-pixel driving circuit coupled with the second third initialization signal line Vbias2 and the channel length of the driving transistor T3 in the sub-pixel driving circuit coupled with the first third initialization signal line Vbias1 is greater than or equal to the line width of the second third initialization signal line Vbias2, but is not limited thereto.

[0203] The above arrangement manner effectively reduces the width of the layout space occupied by the sub-pixel driving circuit coupled with the second third initialization signal line Vbias2 in the first direction, thereby facilitating providing more space for the layout of the second third initialization signal line Vbias2.

[0204] As shown in FIG. 19, in some embodiments, the sub-pixel includes a sub-pixel driving circuit and a light emitting element, the sub-pixel driving circuit includes a driving transistor T3 and a third reset transistor T8, the second electrode of the third reset transistor T8 is coupled with the first electrode of the driving transistor T3.

[0205] The display panel includes a third initialization signal line Vbias, at least part of the third initialization signal line Vbias extends in a first direction;

[0206] The third initialization signal line Vbias is coupled with the first electrode of the third reset transistor T8 included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits.

[0207] Exemplarily, the display panel comprises a plurality of third initialization signal lines Vbias, the plurality of third initialization signal lines Vbias correspond to the plurality of rows of sub-pixel driving circuit rows one by one, and the third initialization signal line Vbias is coupled to the first electrode of the third reset transistor T8 included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuit rows.

[0208] The above arrangement enables the sub-pixels of various colors to receive the same third initialization signal.

[0209] More specifically, the following specific embodiments are provided in the present disclosure, but not limited thereto.

[0210] Embodiment one: as shown in FIGS. 3-21, the first initialization signal line comprises a first second initialization signal line V21, the second initialization signal line comprises a second second initialization signal line V22, and the display panel comprises a plurality of third initialization signal lines.

[0211] Embodiment two: as shown in FIGS. 22 and 23, based on embodiment one, a first initialization compensation line VB1 is added.

[0212] Embodiment three: as shown in FIGS. 24 and 25, based on embodiment one, a first dummy compensation line Dum1 is added.

[0213] Embodiment four: as shown in FIGS. 26-30, the first initialization signal line comprises a first third initialization signal line Vbias1, the second initialization signal line comprises a second third initialization signal line Vbias2, and the display panel comprises a plurality of second initialization signal lines.

[0214] Embodiment five: as shown in FIG. 31, based on embodiment four, a second initialization compensation line VB2 is added.

[0215] Embodiment six: as shown in FIG. 32, based on embodiment four, a second dummy compensation line Dum2 is added.

[0216] Embodiment seven: as shown in FIG. 33, the first initialization signal line comprises a first second initialization signal line V21, the second initialization signal line comprises a second second initialization signal line V22, the first initialization signal line comprises a first third initialization signal line Vbias1, and the second initialization signal line comprises a second third initialization signal line Vbias2.

[0217] Embodiment eight: as shown in FIG. 34, based on embodiment seven, a first initialization compensation line VB1 and / or a second initialization compensation line VB2 is added.

[0218] Embodiment Nine: on the basis of Embodiment Seven, a first dummy compensation line Dum1 and / or a second dummy compensation line Dum2 are added.

[0219] In the related art, the same power voltage is used for all colors of sub-pixels, and since the power voltage needs to match all colors of sub-pixels, i.e., needs to ensure that sub-pixels of various colors can normally emit light, this results in a situation of power waste. Therefore, it is considered to use different power signals to control sub-pixels of different colors, so as to reduce the power consumption of the display panel.

[0220] As shown in FIG. 35, in some embodiments, the display panel further comprises:

[0221] a first power transmission layer and a second power transmission layer, the at least two colors of sub-pixels being coupled with the first power transmission layer; the at least one color of sub-pixel being coupled with the second power transmission layer;

[0222] a power management circuit 10, the power management circuit 10 comprising a power signal output end 101;

[0223] a first connection line L1 and a second connection line L2, the first connection line L1 being coupled with the first power transmission layer and the power signal output end 101 respectively, the second connection line L2 being coupled with the second power transmission layer and the power signal output end 101 respectively; the line width of the first connection line L1 is smaller than the line width of the second connection line L2, and the line length of the first connection line L1 is greater than the line length of the second connection line L2.

[0224] For example, the display panel comprises a display area and a peripheral area, and the peripheral area surrounds the display area, but is not limited thereto.

[0225] For example, the plurality of sub-pixels are located in the display area. The first power transmission layer and the second power transmission layer each comprise a portion located in the display area and a portion located in the peripheral area. The power management circuit 10 is located in the peripheral area. The first connection line L1 and the second connection line L2 are located in the peripheral area, for example, the first connection line L1 and the second connection line L2 can cross a bending area in the peripheral area.

[0226] As shown in FIG. 35 and FIG. 19, the first power transmission layer includes a first power bus VDDZ1 and a plurality of first power lines VDD1 arranged along a first direction. The first power bus VDDZ1 is located in the peripheral region, and the first power lines VDD1 include a portion located in the display region and a portion located in the peripheral region. The first power lines VDD1 are respectively coupled to the first power bus VDDZ1. The first power lines VDD1 are respectively coupled to the sub-pixel drive circuits of the at least two colors in the corresponding column of sub-pixel drive circuit columns. The first power bus VDDZ1 is coupled to the first connection line L1.

[0227] As shown in FIG. 35 and FIG. 19, the second power transmission layer includes a second power bus VDDZ2 and a plurality of second power lines VDD2 arranged along a first direction. The second power bus VDDZ2 is located in the peripheral region, and the second power lines VDD2 include a portion located in the display region and a portion located in the peripheral region. The second power lines VDD2 are respectively coupled to the second power bus VDDZ2. The second power lines VDD2 are respectively coupled to the sub-pixel drive circuits of the at least one color in the corresponding column of sub-pixel drive circuit columns. The second power bus VDDZ2 is coupled to the second connection line L2.

[0228] The power management circuit 10 includes a power signal output terminal 101. The power management circuit 10 can output only one power signal through the power signal output terminal 101.

[0229] The first connection line L1 can have an arch-shaped trace including a plurality of first extension portions extending along a first direction and a plurality of second extension portions extending along a second direction, but is not limited thereto.

[0230] The first connection line L1 has a line width smaller than a line width of the second connection line L2, and a line length greater than a line length of the second connection line L2. The first connection line L1 and the second connection line L2 have different resistances, so that the first power transmission layer and the second power transmission layer can be divided into different voltages.

[0231] For example, the at least two colors of sub-pixels include red sub-pixels and green sub-pixels, and the at least one color of sub-pixels includes blue sub-pixels. The red sub-pixels require a power supply voltage value of 3.9V, and the green sub-pixels require a power supply voltage value of 3.6V. Since the power supply voltage values required by the red sub-pixels and the green sub-pixels are close, the red sub-pixels and the green sub-pixels can be connected to the same first power supply transmission layer. The blue sub-pixels require a power supply voltage value of 4.6V. Since the power supply voltage value required by the blue sub-pixels is large, by setting the line width of the first connection line L1 to be smaller than the line width of the second connection line L2 and the line length of the first connection line L1 to be greater than the line length of the second connection line L2, the first power supply transmission layer and the second power supply transmission layer can be provided with different power supply voltages under the condition that the same power supply signal is provided by the power supply signal output end 101, and the respective requirements can be met.

[0232] For example, since the second power supply signal transmission layer receives a large power supply signal voltage value, the number of the second connection lines L2 can be set to be larger.

[0233] In the display panel provided by the above embodiment, the power supply signal meeting the requirements of sub-pixels of different colors can be adaptively provided according to the actual requirements of sub-pixels of different colors, and the power supply signal meeting the requirements of sub-pixels of all colors does not need to be provided. Therefore, the power supply signal provided by the embodiment of the present disclosure does not need to be compatible with a large voltage value meeting the requirements of sub-pixels of various colors, thereby effectively reducing the power consumption of the display panel.

[0234] In the display panel provided by the above embodiment, by setting one power management circuit 10 and combining the layout of the first connection line L1 and the second connection line L2, different power supply signals can be provided for different power supply transmission layers, which not only simplifies the complexity of the layout of the peripheral region, but also effectively reduces the research and development cost of the PMIC capable of outputting three power supply signals.

[0235] In the display panel provided by the above embodiment, the power supply signals of sub-pixels of different colors, the separate driving of the second initialization signal and the third initialization signal can be realized without increasing the film layer and the pixel density (PPI), thereby effectively reducing the power consumption of the display device.

[0236] As shown in FIGS. 7 to 19, in some embodiments, the sub-pixel driving circuit includes a driving transistor T3 and a storage capacitor C, a first plate C1 of the storage capacitor C is coupled to a gate of the driving transistor T3.

[0237] In the same row of sub-pixel driving circuit, the second plate C2 of the storage capacitor C included in each of the sub-pixel driving circuits is coupled in sequence to form a plate layer 80 in an integrated structure, and the plate layer 80 is coupled with the plurality of second power supply lines VDD2.

[0238] The above arrangement not only improves the voltage stabilizing effect of the storage capacitor C, but also reduces the voltage drop of the power signal transmitted by the second power supply transmission layer, and is also conducive to reducing the plate area of the storage capacitor C to some extent, reducing the layout space occupied by the storage capacitor C, and improving the PPI of the display panel.

[0239] As shown in FIG. 3, in some embodiments, the display panel further comprises:

[0240] A light shielding layer LS is located between the plurality of sub-pixels and the substrate, and the light shielding layer LS is coupled with the second power supply transmission layer.

[0241] For example, the light shielding layer LS is coupled with the second power supply transmission layer in the peripheral area.

[0242] When the at least one color of sub-pixel includes a blue sub-pixel, the voltage value of the power signal transmitted by the second power supply transmission layer is 4.6V. The above coupling of the light shielding layer LS with the second power supply transmission layer not only reduces the voltage drop of the power signal transmitted by the second power supply transmission layer, but also ensures the voltage stabilizing effect of the light shielding layer LS on the gate potential of the driving transistor T3.

[0243] As shown in FIGS. 8-19, in some embodiments, the sub-pixel driving circuit further comprises a driving transistor T3, a first reset transistor T1, and a compensation transistor T2.

[0244] The second electrode of the first reset transistor T1 is coupled with the gate electrode of the driving transistor T3, the first electrode of the compensation transistor T2 is coupled with the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled with the gate electrode of the driving transistor T3.

[0245] The first power supply line VDD1 includes a first power supply main part VDD11 and a first power supply protruding part VDD12 coupled with each other, the first power supply main part VDD11 extends along the second direction, the first power supply protruding part VDD12 protrudes from the first power supply main part VDD11 along the first direction, the orthographic projection of the first power supply protruding part VDD12 on the substrate covers the orthographic projection of the first reset transistor T1 in the sub-pixel driving circuit coupled therewith on the substrate, and / or covers the orthographic projection of the compensation transistor T2 in the sub-pixel driving circuit coupled therewith on the substrate.

[0246] The second power supply line VDD2 includes a second power supply body part VDD21 and a second power supply protruding part VDD22 coupled with each other, the second power supply body part VDD21 extends along a second direction, the second power supply protruding part VDD22 protrudes from the second power supply body part VDD21 along the first direction, a projection of the second power supply protruding part VDD22 on the substrate substrate covers a projection of the first reset transistor T1 in the sub-pixel drive circuit coupled with the second power supply protruding part VDD22 on the substrate substrate, and / or covers a projection of the compensation transistor T2 in the sub-pixel drive circuit coupled with the second power supply protruding part VDD22 on the substrate substrate.

[0247] For example, the first reset transistor T1 and the compensation transistor T2 are both oxide transistors, and the active layer thereof can be an IGZO layer, but is not limited thereto.

[0248] The above arrangement enables the first power supply line VDD1 and the second power supply line VDD2 to shield the active layer of the corresponding oxide transistor, thereby effectively preventing light from affecting the properties of the oxide transistor.

[0249] In the related art, as shown in FIGS. 36-39, when the RGBG pixel arrangement is used, the power consumption is generally reduced by reducing the transition of the data signal for the R sub-pixel and the data signal for the B sub-pixel transmitted on the same data line DA; as shown in FIGS. 36 and 37, a mode of realizing the data signal by the transition of the data signal for the R sub-pixel and the data signal for the B sub-pixel is illustrated, and it is illustrated that the data signal Y1 transmitted by the data line connected to the first column is a transition data signal, the data signal Y2 transmitted by the data line connected to the second column is a non-transition data signal, the data signal Y3 transmitted by the data line connected to the third column is a transition data signal, and the data signal Y4 transmitted by the data line connected to the fourth column is a non-transition data signal. As shown in FIGS. 38 and 39, a scheme after reducing the transition is illustrated, and in order to cooperate with the driving chip, the pixel arrangement is strictly limited, that is, the sub-pixel drive circuit in the first column must be R, however, in the actual display process, due to the limitation of the pixel arrangement, the problem of purple at the edge of the display panel will occur.

[0250] In more detail, as shown in FIGS. 38 and 39, the order of the data signals that the driving chip can provide is R (corresponding to Y1), G (corresponding to Y2), B (corresponding to Y3), and G (corresponding to Y4) in turn. Therefore, the arrangement of the sub-pixel driving circuit columns is limited by the output of the driving chip, that is, the data signal received by the first column of sub-pixel driving circuit columns must be R, and the first column of light emitting elements are red light emitting elements and blue light emitting elements arranged alternately, so the first column of light emitting elements needs to receive data signals of R, B, R, B, R, B alternately, the R data signal is provided by the first column of sub-pixel driving circuit columns, and the B data signal is provided by the third column of sub-pixel driving circuit columns. This results in that only the red light emitting elements emit light when the first column of sub-pixel driving circuit columns is driven, and the number of light emitting elements is small, so this setting will cause the first column to emit purple in high-end machines. It should be noted that n-1, n, n+1 in FIGS. 36 to 39 represent the number of rows.

[0251] As shown in FIG. 40, in some embodiments, the plurality of colors of sub-pixels include red sub-pixels, green sub-pixels, and blue sub-pixels; the at least two colors of sub-pixels include red sub-pixels and green sub-pixels; and the at least one color of sub-pixels includes blue sub-pixels.

[0252] The red sub-pixels include red sub-pixel driving circuits and red light emitting elements coupled thereto; the green sub-pixels include green sub-pixel driving circuits and green light emitting elements coupled thereto; and the blue sub-pixels include blue sub-pixel driving circuits and blue light emitting elements coupled thereto. As shown in FIG. 40, the dashed boxes in the figure represent sub-pixel driving circuits, and the anode layer represents light emitting elements of the corresponding color.

[0253] The plurality of colors of sub-pixel driving circuits included in the plurality of colors of sub-pixels are divided into a plurality of columns of sub-pixel driving circuit columns; the plurality of columns of sub-pixel driving circuit columns include a red sub-pixel driving circuit column Q1, a first green sub-pixel driving circuit column Q2, a blue sub-pixel driving circuit column Q3, and a second green sub-pixel driving circuit column Q4 arranged in the first direction in turn and cyclically;

[0254] The green light emitting elements coupled to the first green sub-pixel driving circuit column form a first green light emitting element column, and the orthogonal projection of the first green light emitting element column on the substrate substrate overlaps the orthogonal projection of the adjacent red sub-pixel driving circuit column on the substrate substrate;

[0255] The green light emitting elements coupled to the second green sub-pixel driving circuit column form a second green light emitting element column, and the orthogonal projection of the second green light emitting element column on the substrate substrate overlaps the orthogonal projection of the adjacent blue sub-pixel driving circuit column on the substrate substrate;

[0256] The red light-emitting elements coupled to the red sub-pixel driving circuit column are divided into at least one column of sub-red light-emitting elements, wherein the sub-red light-emitting element column includes the red light-emitting element coupled to the odd-numbered sub-pixel driving circuit in the red sub-pixel driving circuit column; or, the sub-red light-emitting element column includes the red light-emitting element coupled to the even-numbered sub-pixel driving circuit in the red sub-pixel driving circuit column.

[0257] The orthographic projection of the red sub-light-emitting element on the substrate overlaps with the orthographic projection of the adjacent green sub-pixel driving circuit on the substrate.

[0258] The blue light-emitting elements coupled to the blue sub-pixel driving circuit column are divided into at least one sub-blue light-emitting element column, wherein the sub-blue light-emitting element column includes the blue light-emitting element coupled to the odd-numbered sub-pixel driving circuit in the blue sub-pixel driving circuit column; or, the sub-blue light-emitting element column includes the blue light-emitting element coupled to the even-numbered sub-pixel driving circuit in the blue sub-pixel driving circuit column.

[0259] The orthographic projection of the sub-blue light-emitting element on the substrate overlaps with the orthographic projection of the adjacent green sub-pixel driving circuit on the substrate.

[0260] For example, the red light-emitting elements coupled to the first column of red sub-pixel driving circuits are divided into a column of sub-red light-emitting elements, the column of sub-red light-emitting elements including the red light-emitting element coupled to the odd-numbered sub-pixel driving circuit in the column of red sub-pixel driving circuits; or, the column of sub-red light-emitting elements including the red light-emitting element coupled to the even-numbered sub-pixel driving circuit in the column of red sub-pixel driving circuits; the orthographic projection of the column of sub-red light-emitting elements on the substrate overlaps with the orthographic projection of the adjacent first green sub-pixel driving circuit column on the substrate.

[0261] For example, the red light-emitting elements coupled to the red sub-pixel driving circuit columns other than the first column are divided into two sub-red light-emitting element columns. One sub-red light-emitting element column includes the red light-emitting element coupled to the odd-numbered sub-pixel driving circuit in the red sub-pixel driving circuit column; the other sub-red light-emitting element column includes the red light-emitting element coupled to the even-numbered sub-pixel driving circuit in the red sub-pixel driving circuit column. The two sub-red light-emitting element columns are located above different adjacent green sub-pixel driving circuit columns.

[0262] For example, the orthogonal projection of one of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent first column of sub-green pixel driving circuits on the substrate; and the orthogonal projection of another of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent second column of sub-green pixel driving circuits on the substrate. Alternatively, the orthogonal projection of one of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent second column of sub-green pixel driving circuits on the substrate; and the orthogonal projection of another of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent first column of sub-green pixel driving circuits on the substrate.

[0263] For example, the orthogonal projection of one of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent first column of sub-green pixel driving circuits on the substrate; and the orthogonal projection of another of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent second column of sub-green pixel driving circuits on the substrate. Alternatively, the orthogonal projection of one of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent second column of sub-green pixel driving circuits on the substrate; and the orthogonal projection of another of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent first column of sub-green pixel driving circuits on the substrate.

[0264] For example, the orthogonal projection of one of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent first column of sub-green pixel driving circuits on the substrate; and the orthogonal projection of another of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent second column of sub-green pixel driving circuits on the substrate. Alternatively, the orthogonal projection of one of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent second column of sub-green pixel driving circuits on the substrate; and the orthogonal projection of another of the columns of sub-red light emitting elements on the substrate overlaps with the orthogonal projection of the adjacent first column of sub-green pixel driving circuits on the substrate.

[0265] According to the above arrangement, the first column and the last column of light emitting elements of the display panel are both a column of green light emitting elements, and the plurality of columns of sub-pixel driving circuits include, in sequence along the first direction, a column of red sub-pixel driving circuits, a first column of green sub-pixel driving circuits, a column of blue sub-pixel driving circuits, and a second column of green sub-pixel driving circuits, i.e., the first column of sub-pixel driving circuits is a column of red sub-pixel driving circuits, which can meet the output requirements of the driving chip. Therefore, in the display panel provided by the above embodiment, the light emitting elements can be arranged flexibly while reducing power consumption, and the problem of purple edges of the display panel is improved.

[0266] As shown in FIG. 20, FIG. 21 and FIG. 40, in some embodiments, the red light emitting element comprises a red anode layer Ano-R, the red anode layer Ano-R comprises a red anode main part Ano-R1 and a red anode connecting part Ano-R2 coupled with each other, a normal projection of the red anode main part Ano-R1 on the substrate substrate overlaps with a normal projection of an adjacent green sub-pixel driving circuit column on the substrate substrate; a normal projection of an opening area of the red light emitting element on the substrate substrate is located inside a normal projection of the red anode main part Ano-R1 on the substrate substrate; the red anode connecting part Ano-R2 is coupled with a sub-pixel driving circuit in a sub-pixel to which the red anode connecting part Ano-R2 belongs.

[0267] The blue light emitting element comprises a blue anode layer Ano-B, the blue anode layer Ano-B comprises a blue anode main part Ano-B1 and a blue anode connecting part Ano-B2 coupled with each other, a normal projection of the blue anode main part Ano-B1 on the substrate substrate overlaps with a normal projection of an adjacent green sub-pixel driving circuit column on the substrate substrate; a normal projection of an opening area of the blue light emitting element on the substrate substrate is located inside a normal projection of the blue anode main part Ano-B1 on the substrate substrate; the blue anode connecting part Ano-B2 is coupled with a sub-pixel driving circuit in a sub-pixel to which the blue anode connecting part Ano-B2 belongs; a length of the red anode connecting part Ano-R2 is substantially the same as a length of the blue anode connecting part Ano-B2.

[0268] It should be noted that in FIG. 20, it is also shown that the green light emitting element comprises a green anode layer Ano-G, the green anode layer Ano-G comprises a green anode main part Ano-G1 and a green anode connecting part Ano-G2 coupled with each other.

[0269] For example, the opening area of the light emitting element, i.e. the pixel opening area of the sub-pixel to which the light emitting element belongs, is an effective light emitting area of the sub-pixel.

[0270] The above setting that the length of the red anode connecting part Ano-R2 is substantially the same as the length of the blue anode connecting part Ano-B2 is beneficial to guarantee the loading uniformity of the anode layers of sub-pixels of various colors.

[0271] The circuit schematic of the sub-pixel driving circuit provided by the embodiments of the present disclosure will be described in detail below.

[0272] As shown in FIG. 1 and FIG. 2, the sub-pixel driving circuit shown adopts the following structure:

[0273] The gate of the first reset transistor T1 is coupled with a corresponding first scan line GA1, the first scan line GA1 includes a first sub-film layer GA11 and a second sub-film layer GA12, the first pole of the first reset transistor T1 is coupled with a first initialization signal line V1, and the second pole of the first reset transistor T1 is coupled with the gate T3-g of the driving transistor T3.

[0274] The gate of the compensation transistor T2 is coupled with a corresponding third scan line GA3, the third scan line GA3 includes a first sub-film layer GA31 and a second sub-film layer GA32, the first pole of the compensation transistor T2 is coupled with the second pole of the driving transistor T3, and the second pole of the compensation transistor T2 is coupled with the gate of the driving transistor T3.

[0275] The gate of the data writing transistor T4 is coupled with a corresponding fourth scan line GA4, the first pole of the fourth transistor T4 is coupled with a corresponding data line DA, and the second pole of the fourth transistor T4 is coupled with the first pole of the driving transistor T3.

[0276] The gate of the power control transistor T5 is coupled with a corresponding light-emitting control signal line EM, the first pole of the power control transistor T5 is coupled with a corresponding power supply line, and the second pole of the power control transistor T5 is coupled with the first pole of the driving transistor T3. It should be noted that in FIG. 1, the first pole of the power control transistor T5 in the R, G, and B sub-pixel driving circuits receives the power supply signals VDD-R, VDD-G, and VDD-B, respectively, but is not limited thereto.

[0277] The gate of the light-emitting control transistor T6 is coupled with a corresponding light-emitting control signal line EM, the first pole of the light-emitting control transistor T6 is coupled with the second pole of the driving transistor T3, and the second pole of the light-emitting control transistor T6 is coupled with the anode of the light-emitting element.

[0278] The gate of the second reset transistor T7 is coupled with a corresponding second scan line GA2, the first pole of the second reset transistor T7 is coupled with a second initialization signal line, and the second pole of the second reset transistor T7 is coupled with the anode of the light-emitting element. The cathode of the light-emitting element receives a negative power supply signal VSS, but is not limited thereto. It should be noted that in FIG. 1, the first pole of the second reset transistor T7 in the R, G, and B sub-pixel driving circuits is coupled with the first second initialization signal line V21 in the R sub-pixel driving circuit, the first second initialization signal line V21 in the G sub-pixel driving circuit, and the second second initialization signal line V22 in the B sub-pixel driving circuit, but is not limited thereto.

[0279] The gate of the third reset transistor T8 is coupled with the corresponding second scan line GA2, the first electrode of the third reset transistor T8 is coupled with the corresponding third initialization signal line, and the second electrode of the third reset transistor T8 is coupled with the first electrode of the driving transistor T3. It should be noted that in the R, G, and B sub-pixel drive circuits shown in FIG. 1, the first electrodes of the third reset transistors T8 are all coupled with a third initialization signal line Vbias. In the R, G, and B sub-pixel drive circuits shown in FIG. 2, the first electrode of the third reset transistor T8 in the R sub-pixel drive circuit is coupled with a first third initialization signal line Vbias1, the first electrode of the third reset transistor T8 in the G sub-pixel drive circuit is coupled with the first third initialization signal line Vbias1, and the first electrode of the third reset transistor T8 in the B sub-pixel drive circuit is coupled with a second third initialization signal line Vbias2, but not limited thereto.

[0280] The first plate C1 of the storage capacitor C is coupled with the gate T3-g of the driving transistor T3, for example, the first plate C1 is multiplexed as the gate T3-g of the driving transistor T3, and the second plate C2 of the storage capacitor C receives the same power supply signal VDD-B as the first electrode of the power supply control transistor T5 in the B sub-pixel drive circuit.

[0281] As shown in FIGS. 4, 5, and 11, the first reset transistor T1 includes a first active pattern 51, the second reset transistor T2 includes a second active pattern 52, the driving transistor T3 includes a third active pattern 53, the data write transistor T4 includes a fourth active pattern 54, the power supply control transistor T5 includes a fifth active pattern 55, the light-emitting control transistor T6 includes a sixth active pattern 56, the second reset transistor T7 includes a seventh active pattern 57, and the third reset transistor T8 includes an eighth active pattern 58.

[0282] It should be noted that the first active pattern 51 and the second active pattern 52 are oxide active patterns, which can adopt IGZO material, and are beneficial to reduce the leakage current of the gate of the driving transistor T3. The first reset transistor T1 and the compensation transistor T2 are oxide transistors with a double-gate structure, which is beneficial to stabilize the properties of the oxide transistors and improve the display effect. It should be noted that the third active pattern 53 of the driving transistor T3 in the blue sub-pixel drive circuit adopts a one-word channel, which is designed to ensure that the driving transistor T3 can provide higher driving current and ensure better light emission of the blue sub-pixel.

[0283] As shown in FIGS. 15 to 20, the first conductive connection part 61 is coupled with the first electrode of the data write transistor T4 through a first via Via1, and is coupled with the data line DA through a sixteenth via Via16.

[0284] The second conductive connection 62 is coupled with the first electrode of the compensation transistor T2 through the fifth via Via5, and coupled with the second electrode of the driving transistor T3 through the sixth via Via6.

[0285] The third conductive connection 63 is coupled with the second electrode of the first reset transistor Tl and the second electrode of the compensation transistor T2 through the third via Via3, and coupled with the gate of the driving transistor T3 through the fourth via Via4.

[0286] The fourth conductive connection 64 is coupled with the second electrode of the light emitting control transistor T6 and the second electrode of the second reset transistor T7 through the seventh via Via7, and coupled with the ninth conductive connection 69 through the seventeenth via Via 17.

[0287] The fifth conductive connection 65 is coupled with the first electrode of the power control transistor T5 through the eleventh via Via 11, and coupled with the power line through the eighteenth via Via 18.

[0288] The sixth conductive connection 66 is coupled with the first electrode of the driving transistor T3 through the ninth via Via 9, and coupled with the second electrode of the third reset transistor T8 through the tenth via Via 10.

[0289] The seventh conductive connection 67 is coupled with the second scan line GA2 through the twelfth via Via 12, and coupled with the gate pattern 40 through the thirteenth via Via 13.

[0290] The eighth conductive connection 68 is coupled with the second plate C2 of the storage capacitor C through the eighth via Via 8, coupled with the first electrode of the power control transistor T5 through the eleventh via Via 11, and coupled with the power line through the eighteenth via Via 18.

[0291] The first initialization signal line Vl is coupled with the first electrode of the first reset transistor Tl through the second via Via 2. The first second initialization signal line V21 is coupled with the first electrode of the second reset transistor T7 through the fourteenth via Via 14. The tenth conductive connection 610 is coupled with the first electrode of the second reset transistor T7 through the twenty-sixth via Via 26, and coupled with the second second initialization signal line V22 through the twentieth via Via 20. A third initialization signal line Vbias or a first third initialization signal line 1 is coupled with the first electrode of the third reset transistor T8 through the fifteenth via Via 15.

[0292] As shown in FIGS. 18-20, the ninth conductive connection 69 is also coupled to the corresponding anode layer through a twenty-first via Via21.

[0293] As shown in FIG. 22, the first initialization compensation line VB1 is coupled to the first second initialization signal line V21 through a twenty-second via Via22.

[0294] As shown in FIGS. 26, 29 and 30, the eleventh conductive connection 60 is coupled to the first electrode of the third reset transistor T8 through a twenty-third via Via23, and the eleventh conductive connection 60 is coupled to the second third initialization signal line Vbias2 through a twenty-fourth via Via24.

[0295] As shown in FIG. 31, the second initialization compensation line VB2 is coupled to the first third initialization signal line Vbias1 through a twenty-fifth via Via25.

[0296] The display panel provided by the embodiments of the present disclosure can be used in a display device.

[0297] For example, the display device includes an organic light-emitting diode display device, but is not limited thereto.

[0298] For example, the display device adopts an RGBG pixel arrangement manner and an LTPO technical solution.

[0299] It should be noted that the display device can be any product or component having a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, etc., and the display device further includes a flexible circuit board, a printed circuit board, a back plate, etc.

[0300] The display panel provided by the above embodiment is provided with a first initialization signal line and a second initialization signal line connected with different initialization signal input ends, and at least two colors of sub-pixels in the plurality of sub-pixels are coupled with the first initialization signal line, and at least one color of sub-pixels in the plurality of sub-pixels are coupled with the second initialization signal line. This setting mode enables the first initialization signal line to provide initialization signals matching the requirements of at least two colors of sub-pixels for the at least two colors of sub-pixels, and enables the second initialization signal line to provide initialization signals matching the requirements of at least one color of sub-pixels for the at least one color of sub-pixels, thereby realizing separate driving of initialization signals in at least part of sub-pixels of different colors and reducing the power consumption of the display product. Therefore, in the display panel provided by the above embodiment, initialization signals meeting the requirements of sub-pixels of different colors can be adaptively provided according to the actual requirements of sub-pixels of different colors, and it is not necessary to provide initialization signals meeting the requirements of all colors of sub-pixels. Therefore, the initialization signals provided by the embodiments of the present disclosure do not need to be compatible with a large voltage value of the requirements of sub-pixels of various colors, thereby effectively reducing the power consumption of the display panel.

[0301] The display device provided by the embodiments of the present disclosure also has the beneficial effects described above when including the display panel described above, and details are not repeated here.

[0302] It should be noted that the signal line extending in a certain direction refers to that the signal line includes a main part and a secondary part connected with the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0303] It should be noted that the "same layer" of the embodiments of the present disclosure can refer to a film layer on the same structure layer. Alternatively, for example, the film layers on the same layer can be layers formed by using the same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by using the same mask plate through a one-time patterning process. According to different specific patterns, the one-time patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous. These specific patterns can also be at different heights or have different thicknesses.

[0304] In the method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the sequence of the steps, and for those skilled in the art, the changes in the sequence of the steps without creative labor are also within the protection scope of the present disclosure.

[0305] It should be noted that each of the embodiments described in the specification of the present disclosure adopts a progressive description manner, and the same or similar parts between the embodiments can be mutually referred to. Each of the embodiments focuses on the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the product embodiments.

[0306] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person skilled in the art. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect", "couple", or "link" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0307] It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intermediate element can be present. In the description of the above-described embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0308] The above description is merely a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: A substrate and a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels including sub-pixels of a plurality of colors; The display panel further includes: A first initialization signal line and a second initialization signal line, at least part of the first initialization signal line extends along a first direction, at least part of the second initialization signal line extends along a second direction, the first direction intersects the second direction; the first initialization signal line and the second initialization signal line are coupled to different initialization signal inputs; At least two colors of sub-pixels in the plurality of sub-pixels are coupled to the first initialization signal line; at least one color of sub-pixels in the plurality of sub-pixels is coupled to the second initialization signal line.

2. The display panel of claim 1, wherein, The plurality of sub-pixels includes a plurality of sub-pixel driving circuits arranged in an array; the plurality of sub-pixel driving circuits is divided into a plurality of rows of sub-pixel driving circuit rows, and each row of sub-pixel driving circuit rows includes a plurality of sub-pixel driving circuits arranged along a first direction; The display panel includes a plurality of first initialization signal lines, and each first initialization signal line is coupled to each sub-pixel driving circuit belonging to at least two colors of sub-pixels in a corresponding row of sub-pixel driving circuit rows.

3. The display panel of claim 2, wherein, The plurality of sub-pixel driving circuits is divided into a plurality of columns of sub-pixel driving circuit columns, and each column of sub-pixel driving circuit columns includes a plurality of sub-pixel driving circuits arranged along a second direction; The display panel includes a plurality of second initialization signal lines, and each second initialization signal line is coupled to each sub-pixel driving circuit belonging to at least one color of sub-pixels in a corresponding column of sub-pixel driving circuit columns.

4. The display panel of claim 3, wherein The first initialization signal line includes a first second initialization signal line, and the second initialization signal line includes a second second initialization signal line; The sub-pixel includes a sub-pixel driving circuit and a light emitting element, the sub-pixel driving circuit includes a second reset transistor, and a second electrode of the second reset transistor is coupled to an anode of the light emitting element; The first electrode of the second reset transistor in the at least two colors of sub-pixels is coupled to a corresponding first second initialization signal line; and the first electrode of the second reset transistor in the at least one color of sub-pixels is coupled to a corresponding second second initialization signal line. In the sub-pixel driving circuits coupled to the same first second initialization signal line, at least part of the adjacent sub-pixel driving circuits include the first electrodes of the second reset transistors formed in an integrated structure; 5. The display panel of claim 4, wherein, In the same row of sub-pixel driving circuit rows, the first electrodes of the second reset transistors connected to the first second initialization signal lines are independent of the first electrodes of the second reset transistors connected to the second second initialization signal lines. The plurality of sub-pixel driving circuits in the row of sub-pixel driving circuits is divided into a plurality of circuit groups arranged along the first direction, each circuit group includes two adjacent sub-pixel driving circuits, and the gates of the second reset transistors included in the two sub-pixel driving circuits form a gate pattern in an integrated structure; 6. The display panel of claim 4, wherein, ​ The display panel further comprises a second scan line, the second scan line is coupled with each gate pattern in a corresponding row of sub-pixel drive circuit rows respectively, and the second scan line is arranged in a layer different from the gate pattern.

7. The display panel of claim 6, wherein, The display panel further comprises a first gate metal layer and a second gate metal layer, the first gate metal layer is located between the second gate metal layer and the substrate, the gate pattern is arranged in a same layer and same material as the first gate metal layer, and the second scan line is arranged in a same layer and same material as the second gate metal layer.

8. The display panel of claim 4, wherein, The display panel further comprises a data line and a power line, the data line is coupled with each sub-pixel drive circuit in a corresponding column of sub-pixel drive circuits respectively, and the power line is coupled with each sub-pixel drive circuit in a corresponding column of sub-pixel drive circuits respectively. The second second initialization signal line is located between a power line connected with a sub-pixel drive circuit coupled with the second second initialization signal line and a power line adjacent to the power line. The power line connected with the sub-pixel drive circuit coupled with the second second initialization signal line is located between the second second initialization signal line and a data line connected with the sub-pixel drive circuit coupled with the second second initialization signal line.

9. The display panel of claim 8, wherein, The display panel further comprises: A first initialization compensation line, at least part of the first initialization compensation line extends along a second direction, The first initialization compensation line is coupled with each first second initialization signal line; The first initialization compensation line and the second second initialization signal line are arranged alternately along a first direction, the first initialization compensation line is located between two adjacent power lines, and the two adjacent power lines form a first power group; Two adjacent power lines of the second second initialization signal line form a second power group, and the first power group and the second power group are arranged alternately.

10. The display panel of claim 8, wherein, The display panel further comprises: A first virtual compensation line, at least part of the first virtual compensation line extends along a second direction, and the first virtual compensation line and the second second initialization signal line are arranged alternately along a first direction, and the first virtual compensation line is located between two adjacent power lines, and the two adjacent power lines form a first power group; Two adjacent power lines of the second second initialization signal line form a second power group, and the first power group and the second power group are arranged alternately.

11. The display panel of claim 3, wherein, The sub-pixel comprises a sub-pixel drive circuit and a light emitting element, the sub-pixel drive circuit comprises a second reset transistor, and a second electrode of the second reset transistor is coupled with an anode of the light emitting element; The display panel comprises a second initialization signal line, at least part of the second initialization signal line extends along a first direction; The second initialization signal line is coupled with a first electrode of a second reset transistor included in each sub-pixel drive circuit in a corresponding row of sub-pixel drive circuit rows.

12. The display panel according to any one of claims 3-11, wherein The first second initialization signal line comprises a first third initialization signal line, and the second second initialization signal line comprises a second third initialization signal line. The sub-pixel includes a sub-pixel driving circuit and a light emitting element, the sub-pixel driving circuit includes a driving transistor and a third reset transistor, a second electrode of the third reset transistor is coupled with a first electrode of the driving transistor; The first electrode of the third reset transistor in the sub-pixel of the at least two colors is coupled with the corresponding first third initialization signal line; the first electrode of the third reset transistor in the sub-pixel of the at least one color is coupled with the corresponding second third initialization signal line.

13. The display panel of claim 12, wherein, The second third initialization signal line is located between the data line connected with the sub-pixel driving circuit coupled with the second third initialization signal line and the data line adjacent to the data line; The data line connected with the sub-pixel driving circuit coupled with the second third initialization signal line is located between the second third initialization signal line and the power line connected with the sub-pixel driving circuit coupled with the second third initialization signal line.

14. The display panel of claim 13, wherein, The display panel further includes: A second initialization compensation line, at least part of the second initialization compensation line extends along the second direction, and the second initialization compensation line is coupled with each first third initialization signal line; The second initialization compensation line and the second third initialization signal line are alternately arranged along the first direction, and the second initialization compensation line is located between two adjacent data lines, the two adjacent data lines forming a first data group; The two adjacent data lines of the second third initialization signal line form a second data group, and the first data group and the second data group are alternately arranged.

15. The display panel of claim 13, wherein, The display panel further includes: A second virtual compensation line, at least part of the second virtual compensation line extends along the second direction, and the second virtual compensation line is alternately arranged with the second third initialization signal line along the first direction, and the second virtual compensation line is located between two adjacent data lines, the two adjacent data lines forming a first data group; The two adjacent data lines of the second third initialization signal line form a second data group, and the first data group and the second data group are alternately arranged.

16. The display panel of claim 12, wherein, The channel length of the driving transistor in the sub-pixel driving circuit coupled with the second third initialization signal line is smaller than the channel length of the driving transistor in the sub-pixel driving circuit coupled with the first third initialization signal line.

17. The display panel according to any one of claims 3-11, wherein, The sub-pixel includes a sub-pixel driving circuit and a light emitting element, the sub-pixel driving circuit includes a driving transistor and a third reset transistor, a second electrode of the third reset transistor is coupled with a first electrode of the driving transistor; The display panel includes a third initialization signal line, at least part of the third initialization signal line extends along the first direction; The first electrode of the third reset transistor included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits is coupled with the third initialization signal line. ​ 18. The display panel of claim 1, wherein, The display panel further comprises a first source-drain metal layer and a second source-drain metal layer; the first initialization signal line is arranged in the same layer and is made of the same material as the first source-drain metal layer; and the second initialization signal line is arranged in the same layer and is made of the same material as the second source-drain metal layer.

19. The display panel of claim 1, wherein, The display panel further comprises: a first power transmission layer and a second power transmission layer, the at least two colors of sub-pixels being coupled with the first power transmission layer, and the at least one color of sub-pixels being coupled with the second power transmission layer; a power management circuit, the power management circuit comprising a power signal output end; a first connection line and a second connection line, the first connection line being coupled with the first power transmission layer and the power signal output end respectively, and the second connection line being coupled with the second power transmission layer and the power signal output end respectively; the line width of the first connection line is smaller than that of the second connection line, and the line length of the first connection line is greater than that of the second connection line.

20. The display panel of claim 19, wherein, The plurality of sub-pixel driving circuits are divided into a plurality of columns of sub-pixel driving circuit columns, and each column of sub-pixel driving circuit columns comprises a plurality of sub-pixel driving circuits arranged along a second direction; the first power transmission layer comprises a first power bus and a plurality of first power lines arranged along a first direction, the plurality of first power lines being coupled with the first power bus respectively; each first power line is coupled with each sub-pixel driving circuit belonging to the at least two colors of sub-pixels in a corresponding column of sub-pixel driving circuit columns; and the first power bus is coupled with the first connection line; the second power transmission layer comprises a second power bus and a plurality of second power lines arranged along the first direction, the plurality of second power lines being coupled with the second power bus respectively; each second power line is coupled with each sub-pixel driving circuit belonging to the at least one color of sub-pixels in a corresponding column of sub-pixel driving circuit columns; and the second power bus is coupled with the second connection line.

21. The display panel of claim 20, wherein, The sub-pixel driving circuit comprises a driving transistor and a storage capacitor, and a first plate of the storage capacitor is coupled with a gate of the driving transistor; in the same row of sub-pixel driving circuits, second plates of the storage capacitors included in each sub-pixel driving circuit are coupled in sequence to form a plate layer of an integrated structure, and the plate layer is coupled with the plurality of second power lines respectively.

22. The display panel of claim 19, wherein, The display panel further comprises: a light shielding layer between the plurality of sub-pixels and the substrate, the light shielding layer being coupled with the second power transmission layer.

23. The display panel of claim 20, wherein, The sub-pixel driving circuit further comprises a driving transistor, a first reset transistor and a compensation transistor; a second plate of the first reset transistor is coupled with a gate of the driving transistor; a first plate of the compensation transistor is coupled with a second plate of the driving transistor, and a second plate of the compensation transistor is coupled with the gate of the driving transistor; The first power line includes a first power body part and a first power protruding part coupled thereto, the first power body part extends along a second direction, the first power protruding part protrudes from the first power body part along the first direction, a projection of the first power protruding part on the substrate substrate covers a projection of the first reset transistor in the sub-pixel drive circuit coupled thereto on the substrate substrate, and / or covers a projection of the compensation transistor in the sub-pixel drive circuit coupled thereto on the substrate substrate; The second power line includes a second power body part and a second power protruding part coupled thereto, the second power body part extends along a second direction, the second power protruding part protrudes from the second power body part along the first direction, a projection of the second power protruding part on the substrate substrate covers a projection of the first reset transistor in the sub-pixel drive circuit coupled thereto on the substrate substrate, and / or covers a projection of the compensation transistor in the sub-pixel drive circuit coupled thereto on the substrate substrate.

24. The display panel of claim 1, wherein, The plurality of colors of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels; the at least two colors of sub-pixels include red sub-pixels and green sub-pixels; the at least one color of sub-pixels includes blue sub-pixels; The red sub-pixel includes a red sub-pixel drive circuit and a red light emitting element coupled thereto; the green sub-pixel includes a green sub-pixel drive circuit and a green light emitting element coupled thereto; the blue sub-pixel includes a blue sub-pixel drive circuit and a blue light emitting element coupled thereto; The plurality of colors of sub-pixels includes a plurality of colors of sub-pixel drive circuits, which are divided into a plurality of columns of sub-pixel drive circuit columns; the plurality of columns of sub-pixel drive circuit columns include a column of red sub-pixel drive circuit columns, a first column of green sub-pixel drive circuit columns, a column of blue sub-pixel drive circuit columns, and a second column of green sub-pixel drive circuit columns arranged in a first direction in a cycle; The green light emitting elements coupled to the first column of green sub-pixel drive circuit columns form a first column of green light emitting elements, a projection of the first column of green light emitting elements on the substrate substrate overlaps a projection of an adjacent column of red sub-pixel drive circuit columns on the substrate substrate; The green light emitting elements coupled to the second column of green sub-pixel drive circuit columns form a second column of green light emitting elements, a projection of the second column of green light emitting elements on the substrate substrate overlaps a projection of an adjacent column of blue sub-pixel drive circuit columns on the substrate substrate; The red light emitting elements coupled to the column of red sub-pixel drive circuit columns are divided into at least one column of sub-red light emitting element columns, the sub-red light emitting element column includes red light emitting elements coupled to odd-numbered sub-pixel drive circuits in the column of red sub-pixel drive circuit columns; or, the sub-red light emitting element column includes red light emitting elements coupled to even-numbered sub-pixel drive circuits in the column of red sub-pixel drive circuit columns; A projection of the sub-red light emitting element column on the substrate substrate overlaps a projection of an adjacent column of green sub-pixel drive circuit columns on the substrate substrate. ​ The blue light emitting elements coupled by the blue sub-pixel driving circuit column are divided into at least one sub-blue light emitting element column, the sub-blue light emitting element column includes the blue light emitting elements coupled by the odd-numbered sub-pixel driving circuit in the blue sub-pixel driving circuit column; or the sub-blue light emitting element column includes the blue light emitting elements coupled by the even-numbered sub-pixel driving circuit in the blue sub-pixel driving circuit column. The orthographic projection of the sub-blue light emitting element column on the substrate substrate overlaps the orthographic projection of the adjacent green sub-pixel driving circuit column on the substrate substrate.

25. The display panel of claim 24, wherein, The red light emitting element includes a red anode layer, the red anode layer includes a red anode main body part and a red anode connecting part coupled, the orthographic projection of the red anode main body part on the substrate substrate overlaps the orthographic projection of the adjacent green sub-pixel driving circuit column on the substrate substrate; The orthographic projection of the opening area of the red light emitting element on the substrate substrate is located inside the orthographic projection of the red anode main body part on the substrate substrate; The red anode connecting part is coupled with the sub-pixel driving circuit in the sub-pixel belonging to the red anode connecting part; The blue light emitting element includes a blue anode layer, the blue anode layer includes a blue anode main body part and a blue anode connecting part coupled, the orthographic projection of the blue anode main body part on the substrate substrate overlaps the orthographic projection of the adjacent green sub-pixel driving circuit column on the substrate substrate; The orthographic projection of the opening area of the blue light emitting element on the substrate substrate is located inside the orthographic projection of the blue anode main body part on the substrate substrate; the blue anode connecting part is coupled with the sub-pixel driving circuit in the sub-pixel belonging to the blue anode connecting part; The length of the red anode connecting part is substantially the same as the length of the blue anode connecting part.

26. A display device, comprising the display panel of any one of claims 1-25. ​

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