Plasma etch in semiconductor processing

Abstract

Methods of semiconductor processing may include forming plasma effluents of a variety of precursors (e.g., etchant precursors, oxygen-containing precursors, and silicon and fluorine-containing precursors, such as silicon tetrafluoride). The plasma effluent may then contact the silicon-containing material and the mask material on the substrate in the processing region of the semiconductor processing chamber. The mask material may have one or more apertures therein to allow plasma effluents to access the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluent may result in (i) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, and (ii) concurrently etching the mask material with the plasma effluent and depositing the silicon and oxygen-containing material on the mask material.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. non-provisional application No. 18 / 234,685, filed August 16, 2023, entitled “PLASMA ETCHING IN SEMICONDUCTOR PROCESSING,” the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This technology relates to methods and components for semiconductor processing. More specifically, this technology relates to systems and methods for etching silicon-containing materials. Background Technology

[0004] Integrated circuits are realized through processes that create complex patterned material layers on the surface of a substrate. Creating patterned material on the substrate requires controlled methods to remove exposed material. Chemical etching is used for a variety of purposes, including transferring patterns from photoresist to the underlying layer, thinning layers, or thinning the lateral dimensions of existing features on a surface. Often, it is desirable to have an etching process that can etch one material faster than another, thereby facilitating processes such as pattern transfer. Due to the diversity of materials, circuits, and processes, etching processes have evolved to be selective for a wide range of materials.

[0005] Depending on the materials used in the process, etching processes can be divided into wet etching and dry etching. Wet HF etching preferentially removes silicon oxide, rather than other dielectrics and materials. However, wet processes may struggle to penetrate some confined trenches and can sometimes deform the remaining material. Dry etching, generated in localized plasma within the substrate processing area, can penetrate more confined trenches and causes less deformation to the fine remaining structure. However, localized plasma can generate arcs during discharge, potentially damaging the substrate.

[0006] Therefore, there is a need to improve systems and methods in order to produce high-quality components and structures. This technology can meet these and other requirements. Summary of the Invention

[0007] Exemplary methods of semiconductor processing may include a plasma effluent forming a variety of precursors, such as etchant precursors, oxygen-containing precursors, and silicon- and fluorine-containing precursors. An example of a silicon- and fluorine-containing precursor is silicon tetrafluoride. The plasma effluent may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. More specifically, the silicon-containing material may be disposed on the substrate, and the mask material (e.g., a dielectric material) may be disposed on the silicon-containing material. The mask material may have one or more apertures to allow the plasma effluent to contact the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluent may result in (i) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, and (ii) simultaneously etching the mask material with the plasma effluent and depositing a silicon- and oxygen-containing material on the mask material.

[0008] In some embodiments, the etchant precursor may include one or more of the following: a chlorine-containing precursor, a bromine-containing precursor, and a fluorine-containing precursor that is not silicon tetrafluoride. In some embodiments, the volume ratio of the oxygen-containing precursor to the silicon-containing and fluorine-containing precursors may be less than or about 50:1. Furthermore, the volume ratio of the etchant precursor to the oxygen-containing precursor may be less than or about 20:1. In some cases, a carrier gas may be present during the formation of the plasma effluent, and the volume ratio of the carrier gas to the oxygen-containing precursor may be less than or about 10:1.

[0009] In some embodiments, the silicon-containing material may include one or more of the following: crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicide, tungsten silicide, tungsten boron carbide, and silicon germanium. Semiconductor processing methods may selectively remove the silicon-containing material relative to a mask material. For example, semiconductor processing methods may remove the silicon-containing material relative to a mask material with a selectivity greater than or about 4.

[0010] In some cases, one or more pores are characterized by a critical dimension of less than or about 1000 nm, or preferably less than or about 50 nm, for example, 5 nm to 25 nm. After etching the silicon-containing material, one or more features are characterized by a depth greater than or about 100 nm. After etching the silicon-containing material, one or more features are characterized by an aspect ratio greater than or about 5:1.

[0011] In some embodiments, the pressure in the processing zone may be maintained at about 5 Torr or lower. In some embodiments, the temperature in the processing zone may be maintained at about 100°C or lower. In some embodiments, the plasma effluent may be generated at a plasma power of about 5000 W or lower.

[0012] Some embodiments of this technology may cover semiconductor processing methods. This method may include forming a plasma effluent containing various precursors (e.g., etchant precursors, oxygen-containing precursors, and silicon- and fluorine-containing precursors) in the presence of a carrier gas. An example of a silicon- and fluorine-containing precursor is silicon tetrafluoride. The volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor may be less than or about 50:1; the volume ratio of the etchant precursor to the oxygen-containing precursor may be less than or about 20:1; and the volume ratio of the carrier gas to the oxygen-containing precursor may be less than or about 10:1. The plasma effluent may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. More specifically, the silicon-containing material may be disposed on the substrate, and the mask material (e.g., a dielectric material) may be disposed on the silicon-containing material. The mask material may have one or more pores to allow the plasma effluent to contact the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluent can result in (i) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, and (ii) simultaneously etching the mask material with the plasma effluent and depositing silicon- and oxygen-containing materials on the mask material.

[0013] Semiconductor processing methods can selectively remove silicon-containing material relative to a mask material. For example, semiconductor processing methods can remove silicon-containing material relative to a mask material with a selectivity greater than or about 4. In some cases, one or more apertures are characterized by a critical dimension of less than or about 1000 nm, or preferably less than or about 50 nm, for example, 5 nm to 25 nm. After etching the silicon-containing material, one or more features are characterized by a depth greater than or about 100 nm. After etching the silicon-containing material, one or more features are characterized by an aspect ratio greater than or about 5:1.

[0014] Some embodiments of this technology may cover semiconductor processing methods. The methods may include forming a plasma effluent that forms multiple precursors (e.g., etchant precursors, oxygen-containing precursors, and silicon tetrafluoride, wherein the volume ratio of the oxygen-containing precursor to silicon tetrafluoride is less than or about 50:1). The plasma effluent may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. More specifically, the silicon-containing material may be disposed on the substrate, and the mask material (e.g., a dielectric material) may be disposed on the silicon-containing material. The mask material may have one or more pores to allow the plasma effluent to contact the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluent may result in (i) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, and (ii) simultaneously etching the mask material with the plasma effluent and depositing silicon-containing and oxygen-containing materials on the mask material.

[0015] In some embodiments, the plasma effluent may be a first plasma effluent of a first plurality of precursors, and the method may further include forming a second plasma effluent from a second plurality of precursors that do not contain silicon tetrafluoride. The second plasma effluent may etch a silicon-containing material to form and / or deepen one or more features in the silicon-containing material.

[0016] Semiconductor processing methods can selectively remove silicon-containing material relative to a mask material. For example, semiconductor processing methods can remove silicon-containing material relative to a mask material with a selectivity greater than or about 4. In some cases, one or more apertures are characterized by a critical dimension of less than or about 1000 nm, or preferably less than or about 50 nm, for example, 5 nm to 25 nm. After etching the silicon-containing material, one or more features are characterized by a depth greater than or about 100 nm. After etching the silicon-containing material, one or more features are characterized by an aspect ratio greater than or about 5:1.

[0017] This technology can offer many advantages over conventional systems and techniques. For example, embodiments of this technology can enhance the formation and refinement of features in semiconductor structures. These and other embodiments, along with their many advantages and features, are described in more detail below, in conjunction with the accompanying drawings. 。 Attached Figure Description

[0018] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of the specification and the accompanying drawings.

[0019] Figure 1 A schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown.

[0020] Figure 2 Operations in a semiconductor processing method according to some embodiments of the present technology are illustrated.

[0021] Figures 3A to 3C An exemplary schematic cross-sectional structure produced according to some embodiments of the present technology is shown.

[0022] Several figures in the accompanying drawings are included as schematic diagrams. It should be understood that these figures are for illustrative purposes and should not be considered to scale unless specifically stated otherwise. Additionally, as schematic diagrams, the figures are provided to aid understanding and may not include all aspects or information compared to a true representation, and may include material exaggerated for illustrative purposes.

[0023] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Additionally, various parts of the same type may be distinguished by following the reference numerals with letters that differentiate them. If only the main reference numerals are used in the description, the description applies to any of the similar parts having the same main reference numerals, regardless of the letters. Detailed Implementation

[0024] As the size of semiconductor structures decreases, the feature sizes on those structures also decrease and typically become more densely packed. Features can be formed on semiconductor structures using various methods, including etching, which uses a mask material to protect the underlying silicon-containing material. Apertures in the mask material allow etching of the underlying silicon-containing material at desired locations. Conventional techniques use plasma etching and masks to increase feature depth on semiconductor structures. However, etchants can damage the mask, resulting in irregular feature dimensions. Furthermore, as the critical dimension (or width) at feature openings decreases, reactions at the mask or on top of the feature are more likely to clog or seal the openings and hinder etchant penetration into the feature. One way to overcome this problem is to use thicker masks, where the cost and time of mask production increase with increasing thickness.

[0025] This technology overcomes these problems by utilizing silicon- and fluorine-containing precursors (e.g., silicon tetrafluoride). In plasma etching methods, silicon- and fluorine-containing precursors can generate silicon-containing plasma effluents and fluorine-containing plasma effluents. As described in more detail herein, the silicon-containing plasma effluents can facilitate the regeneration of mask material etched simultaneously during the process. Overall, this simultaneous effect minimizes variations in mask thickness during the process disclosed herein, thereby facilitating the use of thinner masks.

[0026] In addition, fluorinated plasma effluents have relatively high electronegativity, which enables them to prevent the deposition of unwanted materials, especially at characteristic openings, thereby reducing clogging of the openings.

[0027] While the remainder of this disclosure will routinely specify particular semiconductor processing methods utilizing the disclosed technology and will describe one type of semiconductor processing chamber, it should be readily understood that the processes can be performed in any number of semiconductor processing chambers. Therefore, the technology should not be considered limited to these specific deposition processes or chambers. Before describing the semiconductor processing methods according to this technology, this disclosure will discuss one possible chamber that can be used to perform the processes according to embodiments of this technology.

[0028] Figure 1A schematic cross-sectional view of an exemplary processing chamber 100 is shown, which is suitable for patterning a material layer on a substrate 102 located within the processing chamber 100. The exemplary processing chamber 100 is suitable for performing patterning processes; however, it should be understood that aspects of this technology can be performed in any number of chambers, and substrate supports according to this technology can be incorporated into etching chambers, deposition chambers, disposal chambers, or any other processing chambers. The plasma processing chamber 100 may include a chamber body 105 defining a chamber space 101 in which a substrate can be processed. The chamber body 105 may have sidewalls 112 and a bottom 118 coupled to a ground terminal 126. The sidewalls 112 may have pads 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limited and are generally proportionally larger than the dimensions of the substrate 102 to be processed therein. Examples of substrate sizes include diameters of 200 mm, 250 mm, 300 mm, and 450 mm, for example, substrates for displays or solar cells.

[0029] The chamber body 105 supports the chamber cover assembly 110 to surround the chamber space 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate pick-up port 113 may be formed through the sidewall 112 of the chamber body 105 to facilitate the transfer of a substrate 102 into and out of the plasma processing chamber 100. The pick-up port 113 may be coupled to a transfer chamber and / or other chambers of the substrate processing system as described above. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber space 101. A pumping device may be coupled to the chamber space 101 through the pumping port 145 to evacuate and control the pressure within the processing space. The pumping device may include one or more pumps and a throttle valve.

[0030] Gas panel 160 can be coupled to chamber body 105 via gas line 167 to supply process gases to chamber space 101. Gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may additionally include inert gases, non-reactive gases, and reactive gases, as applicable to a variety of processes. Examples of process gases that gas panel 160 can provide include, but are not limited to, hydrocarbon gases including methane, silicon tetrafluoride, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon gases, argon, chlorine, nitrogen, helium, or oxygen, as well as a variety of additional materials. Additionally, process gases may include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as H2, NH3, H2O, H2O2, NF3, HF, F2, CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, BrF3, ClF3, SF6, CH3F, CH2F2, BCl3, PF3, PH3, SO2, and COS, as well as any number of additional precursors.

[0031] Valve 166 controls the flow of process gases from sources 161, 162, 163, and 164 of gas panel 160 and is managed by controller 165. The flow of gas supplied from gas panel 160 to chamber body 105 may include a combination of gases from one or more sources. Cover assembly 110 may include nozzle 114. Nozzle 114 may be one or more ports for introducing process gases from sources 161, 162, 164, and 163 of gas panel 160 into chamber space 101. After the process gases are introduced into plasma processing chamber 100, the gases may be energized to form plasma. Antenna 148 (e.g., one or more inductors) may be disposed near plasma processing chamber 100. Antenna power supply 142 may power antenna 148 via matching circuit 141 to inductively couple energy (e.g., RF energy) to the process gases, thereby maintaining plasma formed by the process gases in chamber space 101 of plasma processing chamber 100. Alternatively, in addition to the antenna power supply 142, process electrodes located below and / or above the substrate 102 can be used to couple the RF power capacitor to the process gas, thereby maintaining the plasma within the chamber space 101. The operation of the power supply 142 can be controlled by a controller (e.g., controller 165), which also controls the operation of other components in the plasma processing chamber 100.

[0032] A substrate support base 135 may be disposed within a chamber space 101 to support a substrate 102 during processing. The substrate support base 135 may include an electrostatic chuck 122 for holding the substrate 102 during processing. The electrostatic chuck (“ESC”) 122 may use electrostatic attraction to hold the substrate 102 to the substrate support base 135. The ESC 122 may be powered by an RF power supply 125 integrating matching circuitry 124. The ESC 122 may include electrodes 121 embedded within a dielectric body. The electrodes 121 may be coupled to the RF power supply 125 and may provide a bias voltage to attract plasma ions formed from process gases in the chamber space 101 to the ESC 122 and the substrate 102 on the base. During processing of the substrate 102, the RF power supply 125 may cycle between on and off (or pulsed). The ESC 122 may have an isolator 128 to reduce the attraction of the ESC 122's sidewalls to the plasma, thereby extending the maintenance life of the ESC 122. Additionally, the substrate support base 135 may have a cathode pad 136 to protect the sidewalls of the substrate support base 135 from the effects of plasma gas and to extend the maintenance interval of the plasma processing chamber 100.

[0033] Electrode 121 may be coupled to power supply 150. Power supply 150 may provide an adsorption voltage of approximately 5000 volts to approximately -5000 volts to electrode 121. Power supply 150 may also include a system controller for controlling the operation of electrode 121 to adsorb and desorb substrate 102 by directing direct current to electrode 121. For example, similar to RF power supply 125, power supply 150 may provide a bias voltage to attract plasma ions formed by process gases in chamber space 101 to ESC 122 and substrate 102 located on the pedestal. During substrate 102 processing, power supply 150 may be cycled on and off or pulsed. In embodiments, power supply 150 may supply RF power, direct current or voltage for adsorption and / or bias, or a combination of the above. In additional embodiments, multiple power supplies may be configured to supply RF power and direct current or voltage for adsorption and / or bias. ESC122 may include a heater disposed within a base and connected to a power source for heating the substrate, while the cooling base 129 supporting ESC122 may include a conduit for circulating heat transfer fluid to maintain the temperature of ESC122 and the substrate 102 disposed on ESC122. ESC122 may be configured to operate within the temperature range required by the thermal budget of the components manufactured on substrate 102. For example, ESC122 may be configured to maintain substrate 102 at a temperature of about -150°C or lower to about 500°C or higher, depending on the process being performed.

[0034] Cooling base 129 can be used to assist in controlling the temperature of substrate 102. To mitigate process drift and time, the temperature of substrate 102 can be kept substantially constant by cooling base 129 throughout the time substrate 102 is located in the cleaning chamber. In some embodiments, the temperature of substrate 102 can be maintained between about -150°C and about 500°C in subsequent cleaning processes, but any temperature may be used. Cover ring 130 may be disposed on ESC 122 and along the periphery of substrate support base 135. Cover ring 130 may be configured to confine etching gases to the desired portion of the exposed top surface of substrate 102 while shielding the top surface of substrate support base 135 to isolate it from the plasma environment within plasma processing chamber 100. Lifting pins may selectively move through substrate support base 135 to elevate substrate 102 above substrate support base 135 for access by a transfer robot or other suitable transfer mechanism, as described above.

[0035] The controller 165 can be used to control the process sequence, regulate the gas flow rate from the gas panel 160 into the plasma processing chamber 100, and other process parameters. When the CPU executes a software routine, it is transformed into a dedicated computer (e.g., a controller) that controls the plasma processing chamber 100 to perform the process according to the disclosure herein. The software routine may also be stored and / or executed by a second controller associated with the plasma processing chamber 100.

[0036] The chambers discussed earlier can be used to perform exemplary methods, including etching methods and processing methods. Go to Figure 2 This illustrates exemplary operations in method 200 according to an embodiment of the present technology. Prior to the first operation of the method, the substrate may be processed in one or more ways (e.g., front-end processing, deposition, etching, polishing, cleaning, or any other operation) before the substrate is placed in the processing area of ​​the chamber in which method 200 can be performed. Some or all of these operations may be performed in the previously described chambers or system tools, or may be performed in different chambers on the same system tool, which may include the chambers for performing the operations of method 200.

[0037] Method 200 may include several optional operations that may or may not be specifically related to some embodiments of the methods according to the present technology. For example, many operations are described as providing a broader range of structure formation, but are not critical to the technology, or can be performed by alternative methods, as will be discussed further below. Method 200 describes Figures 3A-3C The operations illustrated herein are schematic diagrams that will be used to describe these operations in conjunction with the operations of method 200. It should be understood that... Figures 3A-3BOnly partial schematic diagrams are shown, and the substrate may contain any number of structural segments having the aspects shown, as well as alternative structural aspects that may still benefit from the operation of this technology.

[0038] Method 200 may (or may not) involve optional operations to develop the semiconductor structure 300 for a specific manufacturing operation. It should be understood that method 200 can be performed on any number of semiconductor structures 300, and Figure 3A An exemplary structure is shown in which contact cleaning or etching processes can be performed. Figure 3A As shown, the processed semiconductor structure 300 may include a substrate 305 on which a silicon-containing material 310 is disposed, and a patterned mask material 315 is disposed on the substrate 305 itself. The substrate 305 may be or may include a dielectric material, such as an oxide or nitride of any number of materials. For example, the silicon-containing material 310 may be or may include crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicide, tungsten silicide, tungsten boron carbide, silicon germanium, or any combination thereof.

[0039] Although mask material 315 is shown as a single-layer material, mask material 315 may include one or more material layers. Mask material 315 may be a hard mask, a photoresist mask, or a combination thereof. For example, mask material 315 may include a hard mask on which a photoresist mask is disposed. Alternatively, mask material 315 may consist only of a hard mask. A hard mask may consist of one or more material layers (e.g., up to 10 layers). The individual layers of the hard mask may include materials such as silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, or any combination thereof. Mask material 315 may be or include a patterned photoresist layer, such as a photolithographic patterned mask, or may be made of other materials. The photoresist layer may be a positive photoresist, a negative photoresist, an ultraviolet photoresist, an i-line photoresist, an electron beam photoresist (e.g., chemically amplified photoresist (CAR)), or other suitable photoresists. The mask may be characterized by a thickness of less than or about 2000 nm, such as 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm.

[0040] Mask material 315 may be patterned to form apertures 320 through mask material 315, exposing portions 325 of the underlying silicon-containing material 310. Apertures 320 may be characterized by a critical dimension 330 (or the width of aperture 320) smaller than or about 1000 nm, for example, 5 nm to 1000 nm, 5 nm to 25 nm, 5 nm to 50 nm, 10 nm to 20 nm, 50 nm to 250 nm, 50 nm to 500 nm, 250 nm to 750 nm, or 500 nm to 1000 nm. It should be understood that the described structure is not intended to be limiting, and similarly covers any of a variety of other semiconductor structures. Although the method 200 of this disclosure is applicable to both small and large apertures, it is advantageous that the method of this disclosure is associated with apertures having a small critical dimension 330 of less than or about 50 nm, for example, 5 nm to 50 nm, 5 nm to 25 nm, 10 nm to 20 nm, or 25 nm to 50 nm. Other exemplary structures may include two-dimensional and three-dimensional structures commonly found in semiconductor manufacturing, within which silicon-containing material is to be removed.

[0041] Method 200 may include forming plasma effluents 335, 340, 345, and 350 in operation 205, comprising a variety of precursors including silicon- and fluorine-containing precursors, etchant precursors, and oxygen-containing precursors. For example, silicon- and fluorine-containing precursors may include silicon tetrafluoride (SiF4). For example, etchant precursors may include one or more materials, including chlorine-containing precursors, bromine-containing precursors, or fluorine-containing precursors. For example, chlorine-containing precursors may include one or more materials, including diatomic chlorine (Cl2) or hydrogen chloride (HCl). For example, bromine-containing precursors may include hydrogen bromide (HBr). For example, fluorine-containing precursors may comprise one or more materials, including nitrogen trifluoride (NF3), hydrogen fluoride (HF), diatomic fluorine (F2), carbon tetrafluoride (CF4), trifluoromethane (CHF3), hexafluoroethane (C2F6), hexafluoropropylene (C3F6), bromine trifluoride (BrF3), chlorine trifluoride (ClF3), sulfur hexafluoride (SF6), additional fluorine-substituted hydrocarbons, or fluorine-containing materials. For example, oxygen-containing precursors may comprise one or more materials, including oxygen (O2), carbon dioxide (CO2), carbon monoxide (CO), nitrous oxide (N2O), nitrogen dioxide (NO2), ozone (O3), or water (H2O).

[0042] The precursor may also include any amount of carrier gas, which may include nitrogen, helium, argon, or other rare, inert, or useful precursors. The carrier gas can be used to dilute the precursor, thereby further reducing the etch rate and / or allowing sufficient diffusion through the pores 320.

[0043] Plasma effluents 335, 340, 345, and 350 formed from precursors can be formed in situ in the processing region or in a remote plasma system. That is, plasma effluents 335, 340, 345, and 350 can be generated in the processing region of the semiconductor processing chamber housing the semiconductor structure 300. Alternatively, plasma effluents 335, 340, 345, and 350 can be generated remotely and provided to the processing region of the semiconductor processing chamber housing the semiconductor structure 300. For example, plasma processing can be generated by a remote plasma source (RPS), capacitively coupled plasma (CCP), or inductively coupled plasma (ICP), with or without one or more carrier gases, such as argon (Ar), helium (He), NH3, nitrogen (N2), H2, or mixtures thereof. Plasma effluents 335, 340, 345, and 350 can be low-level plasmas to limit the amount of bombardment, sputtering, and surface modification. In embodiments, the plasma power may be less than or about 5,000 W, less than or about 4,500 W, less than or about 4,000 W, less than or about 3,500 W, less than or about 3,000 W, less than or about 2,500 W, less than or about 2,000 W, less than or about 1,500 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, or less, but the plasma power may also be included in the range between any two of the above-mentioned figures, or in any smaller range covered by any of the above ranges. By utilizing low-order plasma power, plasma effluents 335, 340, 345, 350 can be better controlled for delivery through the apertures 320 of the mask material 315, while limiting sputtering of the mask material 315 and other exposed surfaces.

[0044] Method 200 may include contacting a silicon-containing material 310 and a mask material 315 with plasma effluents 335, 340, 345, 350 in a processing region of a semiconductor processing chamber during operation 210. Figure 3B As shown, in operation 215, contacting the silicon-containing material 310 with the plasma effluents 335, 340, 345, and 350 can result in etching of the silicon-containing material 310, which can form and / or deepen the features 355 in the silicon-containing material 310. Furthermore, in operation 215, contacting the mask material 315 with the plasma effluents 335, 340, 345, and 350 can result in simultaneous etching of the mask material 315 and deposition of silicon-containing and oxygen-containing materials on the mask material 315.

[0045] Unrestricted by theory, it is believed that silicon-containing plasma effluent 335 from silicon- and fluorine-containing precursors (e.g., silicon tetrafluoride) and oxygen-containing plasma effluent 345 from oxygen-containing precursors can lead to the deposition of silicon- and oxygen-containing materials on mask material 315. Simultaneously, plasma effluent 350 from etchant precursors and / or silicon- and fluorine-containing precursors can etch mask material 315 and silicon-containing material 350. Fluorine-containing plasma effluent 340 from etchant precursors and / or silicon- and fluorine-containing precursors (e.g., silicon tetrafluoride) preferentially contacts silicon-containing material because it has a higher electronegativity compared to other plasma effluents 335, 345, 350 (especially oxygen-containing plasma effluent 345 from oxygen-containing precursors and silicon-containing plasma effluent 335 from silicon- and fluorine-containing precursors). By preferentially contacting the silicon-containing material 310, the fluorinated plasma effluent 340 can mitigate the formation of silicon and oxygen-containing materials on the silicon-containing material 310, thereby reducing the width (or critical dimension) of the feature 355, especially near the interface between the mask material 315 and the silicon-containing material 310. The reduction in feature width reduces the inflow of plasma effluent 350 from the etchant precursor into the feature 355, thereby reducing the etching of the silicon-containing material 310 that deepens the feature 355. Therefore, while the silicon-containing material 310 can be etched, the mask material 315 can be simultaneously etched and replenished (by deposition), resulting in the selective removal of the silicon-containing material 310 relative to the mask material 315. Advantageously, the method 200 of this disclosure results in minimal variation in the thickness of the mask material 315 while still forming a deep feature 355, which allows for the use of a thinner mask material 315 at the start of the method.

[0046] While the illustrated method 200 and semiconductor structure 300 show the formation of feature 355 using plasma effluents 335, 340 from silicon- and fluorine-containing precursors, in alternative embodiments, feature 355 may have already been formed (or begun), and plasma effluents 335, 340 from silicon- and fluorine-containing precursors may only be used to deepen feature 355. For example, the method may include: forming a first plasma effluent from a first precursor comprising a first etchant precursor; contacting a mask material and a silicon-containing material with the first plasma effluent to induce etching of the silicon-containing material, thereby forming and deepening the feature (e.g., deepening by about 5 nm to 100 nm); then forming a second plasma effluent from a second precursor comprising silicon- and fluorine-containing precursors, an oxygen-containing precursor, and a second etchant precursor (which may be the same as or different from the first etchant precursor); and contacting the silicon-containing material and the mask material with the second plasma effluent to etch the silicon-containing material to deepen the feature, while simultaneously etching and depositing the mask material, as described herein.

[0047] The silicon-containing material 310 defines the sidewalls 360 and bottom 365 of the feature 355, and each aperture 320 defines an opening 370 at the top of each feature 355, wherein the mask material 315 intersects with the silicon-containing material 310. (The text abruptly ends here.) Figure 3C After method 200 is shown, feature 355 may be characterized by: a critical dimension 375 at the opening 370 at the top of feature 355, a depth 380 from the opening 370 to the bottom 365 of feature 355, an aspect ratio (depth 380 relative to critical dimension 375), or any combination of the above. After completing method 200, feature 355 may be characterized by a critical dimension 375 less than or about 1000 nm, such as 5 nm to 1000 nm, 5 nm to 25 nm, 5 nm to 50 nm, 10 nm to 20 nm, 50 nm to 250 nm, 50 nm to 500 nm, 250 nm to 750 nm, or 500 nm to 1000 nm, and preferably less than or about 50 nm, such as 5 nm to 50 nm, 5 nm to 25 nm, 10 nm to 20 nm, or 25 nm to 50 nm. After completing method 200, feature 355 may be characterized by a depth 380 greater than or about 100 nm, such as 100 nm to 50,000 nm, 100 nm to 1000 nm, 500 nm to 5000 nm, 1000 nm to 10,000 nm, or 5000 nm to 50,000 nm. After completing method 200, feature 355 may have a depth-to-width ratio greater than or about 5:1, for example greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35:1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 60:1, greater than or about 70:1, greater than or about 80:1, greater than or about 90:1, greater than or about 100:1 or greater, or 5:1 to 200:1, 5:1 to 50:1, 25:1 to 100:1, 50:1 to 200:1 or greater.

[0048] The mask material 315, prior to contact with the plasma effluent, may be characterized by a thickness of less than or about 2000 nm, such as 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm. After operations 210 and 215, the mask material 315 may be characterized by a thickness of less than or about 2000 nm, such as 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm. Comparing the thickness of the mask material 315 before and after operations 210 and 215, the mask material 315 can be characterized by a thickness variation of less than or about 200 nm, such as 0 nm to 10 nm, 0 nm to 20 nm, 1 nm to 50 nm, 25 nm to 100 nm, or 50 nm to 200 nm. The thickness of the mask material 315 after operations 210 and 215 may depend on a variety of factors, including but not limited to the precursor gas ratio, the applied RF power, and the chamber pressure.

[0049] Method 200 is characterized by the preferential (or selective) removal of silicon-containing material 310 relative to mask material 315. Selectivity is defined as the depth 380 of feature 355 divided by the initial thickness (MT) of mask material 315. S ) and the final thickness (MT) of mask material 315 F The difference between them is shown in the formula below.

[0050] Selective = Feature depth / (MT) S -MT F )

[0051] For example, method 200 can be executed, where (i) in Figure 3A In the process, before etching, the thickness of the mask material 315 can be 100 nm, and (ii) in Figure 3CIn this process, after etching, the thickness of the mask material 315 can be 60 nm, and the depth 380 of the feature 355 can be 300 nm. In the example described, the selective removal of the silicon-containing material 310 relative to the mask material 315 will be 300 nm / (100 nm – 60 nm) = 7.5. Method 200 may be characterized by a selective removal of the silicon-containing material 310 relative to the mask material 315, which is greater than or about 4, for example, greater than or about 6, greater than or about 8, greater than or about 10, greater than or about 12, greater than or about 14, greater than or about 16, greater than or about 18, greater than or about 20, or greater than or about 22, or even greater, or 4 to 30, 4 to 15, 10 to 20, or 15 to 30. The selectivity may depend on various factors, including but not limited to precursor gas ratio, RF power, chamber pressure, etc.

[0052] The volume ratio of oxygen-containing precursors to silicon- and fluorine-containing precursors can be less than or about 50:1, for example, 10:1 to 50:1, 10:1 to 30:1, 15:1 to 40:1, or 20:1 to 50:1. Without theoretical constraints, it is believed that increasing the SiF4 flow rate relative to the O2 flow rate (i.e., a lower volume ratio of oxygen-containing precursors to silicon- and fluorine-containing precursors) may lead to increased mask deposition, resulting in increased blockage. However, the O2:SiF4 volume ratio may have an inflection point where there is insufficient O2 to support the increased deposition, and the mask material deposition rate decreases.

[0053] During operation 205, the volume ratio of etchant precursor to oxygen-containing precursor can be less than or approximately 20:1, for example, 1:1 to 20:1, or 1:1 to 15:1, or 5:1 to 20:1. Without theoretical limitations, oxygen-containing precursors (such as O2) can be used both as precursors for mask material deposition (in synergy with SiF4) and as precursors for passivating the sidewalls 360 of feature 355. While it is believed that reducing the oxygen-containing precursor (i.e., a higher volume ratio of etchant precursor to oxygen-containing precursor) can reduce clogging, it may also lead to increased feature width and feature bend. The appropriate volume ratio of etchant precursor to oxygen-containing precursor may be highly dependent on the composition of silicon-containing material 310. Therefore, clogging can be more effectively controlled or mitigated by the amount of silicon and fluorine precursors used (i.e., the volume ratio of oxygen-containing precursor to silicon and fluorine precursors, rather than the volume ratio of etchant precursor to oxygen-containing precursor).

[0054] During operation 205, the volume ratio of the carrier gas (e.g., nitrogen, helium, argon) to the oxygen-containing precursor can be less than or about 10:1, for example, 1:1 to 10:1, 1:1 to 5:1, 3:1 to 7:1, or 5:1 to 10:1. Without theoretical constraints, most inert carrier gases are believed to have minimal impact on overall process performance and are used to dilute highly electronegative plasmas, providing greater plasma stability by reducing the reflection power observed in RF systems. However, diatomic inert gases (e.g., N2) can significantly affect plasma chemistry by increasing the fluorine signal (observed in optical emission spectra), leading to reduced selectivity and increased mask damage.

[0055] During any of the operations 205, 210, and / or 215 of method 200, a bias power may be applied to substrate 305. The bias power provides directional flow of plasma effluent to substrate 305. Thus, etchant may be directed into the apertures 320, which may facilitate the plasma effluent through the etched material and to substrate 305. In embodiments, the plasma power may be greater than or about 500 W, and may be greater than or about 750 W, greater than or about 1,000 W, greater than or about 1,500 W, greater than or about 2,000 W, greater than or about 2,500 W, greater than or about 2,750 W, greater than or about 3,000 W, greater than or about 3,250 W, greater than or about 3,500 W, greater than or about 4,000 W, greater than or about 4,500 W, greater than or about 5,000 W, or more, although the bias power may also be included within the range of any two of these stated figures or any smaller range covered by any of the stated ranges. By applying bias power, a narrow ion angle distribution can be produced, providing better profile control (e.g., no bending and / or twisting) and etch perpendicularity. A narrow ion angle distribution can reduce sidewall erosion, increase the etch rate, and make the etch front more square.

[0056] In this embodiment, the bias power can be applied via an RF power supply (e.g., RF power supply 125) and / or a power supply (e.g., power supply 150) for directing DC current or voltage to the ESC. As previously discussed... Figure 1The RF power supply and / or the power supply used to guide the DC current or voltage discussed may be cyclically turned on and off or pulsed during processing. Pulsing allows for better control of ion energy and ion flux, and enables lower angular spread of the plasma effluent. Additionally, pulses can neutralize the charge of the plasma effluent at the etch front, which can improve the uniformity of etching. In embodiments where the bias power is applied by the RF power supply and the power supply used to guide the DC current or voltage to the ESC, the power supplies may be synchronous or asynchronous. The DC current or voltage may be pulsed on the microsecond scale and may be characterized by a duty cycle between 0% and 100%. In some embodiments, an additional electrode for pulsed DC current or voltage may be present in the ESC, while in other embodiments, the same electrode may be used for adsorption and pulses. In some embodiments, the RF and pulsed DC may be supplied only to the cooling base 129, while a separate DC adsorption power supply 150 may be connected to the adsorption electrodes (grid) within the ceramic ESC.

[0057] In some embodiments, each operation of method 200 may be performed at a constant temperature, while in others, the temperature may be adjusted during different operations. For example, during method 300, the temperature of the substrate, base, or chamber may be maintained at a temperature less than or about 100°C, less than or about 80°C, less than or about 60°C, less than or about 40°C, less than or about 20°C, or less than or about 0°C. In some embodiments, the temperature may be maintained at a temperature less than or about -20°C, less than or about -40°C, less than or about -50°C, less than or about -60°C, less than or about -70°C, less than or about -80°C, less than or about -90°C, less than or about -100°C, less than or about -110°C, less than or about -120°C, or lower, although the temperature may also be included within a range between any two of these figures or within any smaller range covered by any of the stated ranges.

[0058] The pressure within the processing chamber can be controlled during method 300. For example, the pressure within the semiconductor processing chamber can be maintained below or about 5 Torr while forming the plasma effluent and contacting the material with the plasma effluent. Additionally, in embodiments, the pressure within the semiconductor processing chamber can be maintained below or about 4 Torr, below or about 3 Torr, below or about 2 Torr, below or about 1 Torr, below or about 500 millitors, below or about 250 millitors, below or about 200 millitors, below or about 150 millitors, below or about 100 millitors, below or about 80 millitors, below or about 60 millitors, below or about 50 millitors, below or about 45 millitors, below or about 40 millitors, below or about 35 millitors, below or about 30 millitors, below or about 25 millitors, below or about 20 millitors, below or about 15 millitors, below or about 10 millitors, or lower, although the pressure may also be included within a range between any two of these figures, or any smaller range covered by any of the said ranges. The pressure within the processing chamber affects the ability of the plasma effluent to flow into the pores. For example, as the pressure increases, the plasma effluent may have more difficulty penetrating the pores 320 to reach the silicon-containing material 310. Therefore, in some embodiments, the pressure may be maintained below or about 1 Torr to allow the effluent to flow into the pores 320 and into the features 355 etched in the silicon-containing material 310 on the substrate 305.

[0059] In the foregoing description, numerous details have been set forth for purposes of explanation in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with the addition of the additional details.

[0060] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Additionally, to avoid unnecessarily obscuring the present technology, many well-known processes and elements have not been described. Therefore, the foregoing description should not be considered as limiting the scope of the present technology. Additionally, methods or processes may be described as sequential or step-by-step, but it should be understood that operations may be performed concurrently or in a different order than those listed.

[0061] Where a range of values ​​is provided, it should be understood that, unless the context clearly specifies otherwise, each intermediate value (the smallest fraction to the lower limit unit) between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated or unstated intermediate value within the stated range and any other stated or intermediate value within the stated range is included. The upper and lower limits of those smaller ranges may be independently included or excluded from the range, and each range in which any one limit, no limit, or both limits are included is also included within this technique, but is limited by any specifically excluded limit in the stated range. When a stated range includes one or both limits, ranges excluding any one or both of those included limits are also included.

[0062] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly specifies otherwise. Thus, for example, the citation “precursor” includes a variety of such precursors, and the citation “layer” includes one or more layers and their equivalents known to those skilled in the art, and so on.

[0063] Furthermore, the terms “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including” are intended, when used in this specification and the appended claims, to indicate the presence of the stated feature, integral, component, or operation, but do not exclude the presence or addition of one or more other features, integrals, components, operations, actions, or groups.

Claims

1. A semiconductor processing method, comprising: i) Forming a plasma effluent containing multiple precursors, the multiple precursors including etchant precursors, oxygen-containing precursors and silicon- and fluorine-containing precursors, wherein the silicon- and fluorine-containing precursors include silicon tetrafluoride; ii) In a processing region of a semiconductor processing chamber, a silicon-containing material and a mask material are brought into contact with the plasma effluent, wherein a substrate is disposed on a substrate support in the processing region, wherein the silicon-containing material is disposed on the substrate, and the mask material is disposed on the silicon-containing material, wherein the mask material has one or more pores to allow the plasma effluent to access the silicon-containing material, wherein the mask material comprises a dielectric material; iii) Etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material; and iv) Simultaneously etch the mask material with the plasma effluent and deposit a silicon- and oxygen-containing material on the mask material.

2. The semiconductor processing method of claim 1, wherein the etchant precursor comprises one or more of the following: a chlorine-containing precursor, a bromine-containing precursor, and a fluorine-containing precursor that is not silicon tetrafluoride.

3. The semiconductor processing method of claim 1, wherein the volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor is less than or about 50:

1.

4. The semiconductor processing method of claim 1, wherein the volume ratio of the etchant precursor to the oxygen-containing precursor is less than or about 20:

1.

5. The semiconductor processing method of claim 1, wherein a carrier gas is present when forming the plasma effluent.

6. The semiconductor processing method of claim 5, wherein the volume ratio of the carrier gas to the oxygen-containing precursor is less than or about 10:

1.

7. The semiconductor processing method of claim 1, wherein the silicon-containing material comprises one or more of the following: crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicide, tungsten silicide, tungsten boron carbide, and silicon germanium.

8. The semiconductor processing method of claim 1, wherein the method selectively removes the silicon-containing material relative to the mask material.

9. The semiconductor processing method of claim 1, wherein the method removes the silicon-containing material relative to the mask material with a selectivity greater than or about 4.

10. The semiconductor processing method of claim 1, wherein one or more pores are characterized by a critical size of less than or about 1000 nm.

11. The semiconductor processing method of claim 1, wherein after etching the silicon-containing material, the one or more features are characterized by a depth greater than or about 100 nm.

12. The semiconductor processing method of claim 1, wherein after etching the silicon-containing material, the one or more features are characterized by an aspect ratio greater than or about 5:

1.

13. The semiconductor processing method of claim 1, wherein the pressure in the processing region is maintained at about 5 Torr or lower.

14. The semiconductor processing method of claim 1, wherein the temperature within the processing region is maintained at about 100 degrees Celsius or lower.

15. The semiconductor processing method of claim 1, wherein the plasma effluent is generated at a plasma power of about 5000W or less.

16. A semiconductor processing method, comprising: i) A plasma effluent forming multiple precursors in the presence of a carrier gas, wherein the multiple precursors include an etchant precursor, an oxygen-containing precursor, and a silicon- and fluorine-containing precursor, wherein the silicon- and fluorine-containing precursor includes silicon tetrafluoride, wherein the volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor is less than or about 50:1, wherein the volume ratio of the etchant precursor to the oxygen-containing precursor is less than or about 20:1, and wherein the volume ratio of the carrier gas to the oxygen-containing precursor is less than or about 10:1; ii) In a processing region of a semiconductor processing chamber, a silicon-containing material and a mask material are brought into contact with the plasma effluent, wherein a substrate is disposed on a substrate support in the processing region, wherein the silicon-containing material is disposed on the substrate and the mask material is disposed on the silicon-containing material, wherein the mask material has one or more pores to allow the plasma effluent to access the silicon-containing material, wherein the mask material comprises a dielectric material; iii) Etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, wherein the silicon-containing material defines a plurality of sidewalls and bottoms along the one or more features of the substrate, and each of the one or more apertures defines an opening at the top of each of the one or more features; as well as iv) Simultaneously etching the mask material with the plasma effluent and depositing a silicon- and oxygen-containing material on the mask material, wherein the method selectively removes the silicon-containing material relative to the mask material.

17. The semiconductor processing method of claim 16, wherein the method removes the silicon-containing material relative to the mask material with a selectivity greater than or about 4.

18. A semiconductor processing method, comprising: i) Forming a plasma effluent containing multiple precursors, the multiple precursors including an etchant precursor, an oxygen-containing precursor and silicon tetrafluoride, wherein the volume ratio of the oxygen-containing precursor to the silicon tetrafluoride is less than or about 50:

1. ii) In a processing region of a semiconductor processing chamber, a silicon-containing material and a mask material are brought into contact with the plasma effluent, wherein a substrate is disposed on a substrate support within the processing region, wherein the silicon-containing material is disposed on the substrate and the mask material is disposed on the silicon-containing material, wherein the mask material has one or more pores that allow the plasma effluent to access the silicon-containing material, wherein the mask material comprises a dielectric material; iii) Etching the silicon-containing material with the plasma effluent to deepen one or more features in the silicon-containing material, wherein the silicon-containing material defines a plurality of sidewalls and bottom along the one or more features of the substrate, and each of the one or more apertures defines an opening at the top of each of the one or more features; as well as iv) Simultaneously etching the mask material with the plasma effluent and depositing a silicon- and oxygen-containing material on the mask material, wherein the method selectively removes the silicon-containing material relative to the mask material.

19. The semiconductor processing method of claim 18, wherein the plasma effluent is a first plasma effluent of a first plurality of precursors, and wherein the method further comprises: A second plasma effluent is formed from a second plurality of precursors, wherein the second plurality of precursors does not include silicon tetrafluoride; as well as The silicon-containing material is etched with the second plasma effluent to form and / or deepen one or more of the features in the silicon-containing material.

20. The semiconductor processing method of claim 18, wherein the method removes the silicon-containing material relative to the mask material with a selectivity greater than or about 4.

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