Chip test circuit, chip test method and chip

Abstract

The invention provides a chip testing circuit, a chip testing method and a chip, and is applied to the technical field of chip testing, the chip testing circuit comprises a plurality of grouping testing circuits, each grouping testing circuit comprises a plurality of tested circuit modules, and each tested circuit module comprises a plurality of IP cores; each grouping test circuit is connected with a special test channel pin; the tested circuit modules in the same grouping test circuit are connected in series with the special test channel pins, and the plurality of grouping test circuits are tested in a parallel test mode.

Description

Technical Field

[0001] This application belongs to the field of testing technology, and in particular relates to a chip testing circuit, a chip testing method, and a chip. Background Technology

[0002] With the rapid development of integrated circuit manufacturing technology, large-scale integrated circuits such as general-purpose microprocessors and system-on-a-chip (SoC) are evolving towards the integration of multiple intellectual property (IP) cores. In particular, with the maturity of system-in-a-package (SIP) technology, chips with different functions, such as processor chips, bridge chips, or memory chips, are integrated into a single package to form a complete chip, becoming a common industrial solution.

[0003] In existing technologies, chips are typically integrated from multiple IP cores. Currently, the most common testing method in the industry is to test each IP individually, meaning that all IP tests reuse the same set of test channels. This results in longer serial testing times between test modules, lower testing efficiency, and increased testing costs. Summary of the Invention

[0004] In view of this, embodiments of this application propose a chip testing circuit, a chip testing method, and a chip to solve, as far as possible, the problem that in the prior art, all IP tests reuse the same set of test channels, which leads to long serial testing times between test modules, low testing efficiency, and increased testing costs.

[0005] The first aspect of this application provides a chip test circuit, which includes multiple group test circuits, each group test circuit including multiple circuit under test modules, and each circuit under test module including multiple IP cores; wherein, the multiple circuit under test modules are modules divided according to the physical layout of the IP cores in the chip, and the physical layout division refers to dividing multiple adjacent IP cores into a group as a circuit under test module according to the physical layout of the IP cores on the chip. Each of the group test circuits is connected to a dedicated test channel pin; the circuit under test module in the same group test circuit is connected in series with the dedicated test channel pin, and multiple group test circuits are tested in parallel test mode.

[0006] Optionally, the group test circuit further includes: a test input channel distribution circuit; The test input channel distribution circuit is used to distribute the test input signal input from the test channel pin to each of the circuit modules under test in the group test circuit.

[0007] Optionally, the group test circuit further includes: the test output channel selection circuit; The test output channel selection circuit is used to send the test output signal output by the circuit module under test in response to the test input signal to the test channel pin.

[0008] Optionally, multiple circuit modules under test in the same group test circuit are tested using a time-division serial model.

[0009] Optionally, it further includes: a test channel routing circuit, wherein each of the group test circuits is connected to the test channel pin through the test channel routing circuit; The test channel routing circuit is used to distribute the test input signal sent by the test channel pin to the group test circuit, and to output the test output signal output by the group test circuit in response to the test input signal through the test channel pin.

[0010] Optionally, the test channel routing circuit includes: a multiplexing circuit; The multiplexing circuit is used to distribute the test input signal from the external input Nth test channel pin to the Nth group test circuit, and to output the test output signal of the Nth group test circuit in response to the test input signal through the Nth test channel pin.

[0011] Optionally, the test channel routing circuit further includes: a test input channel routing circuit, a first pipeline module, and a second pipeline module; the first pipeline module is disposed at the input end of the test input channel routing circuit, and the second pipeline module is disposed at the output end of the test input channel routing circuit. The first pipeline module is used to send the test input signal to the multiplexing circuit in stages, and the second pipeline module is used to send the test input signal to the designated group test circuit in stages.

[0012] Optionally, the test channel routing circuit further includes: a test output channel routing circuit, a third pipeline module, and a fourth pipeline module; the third pipeline module is disposed at the input end of the test output channel routing circuit, and the fourth pipeline module is disposed at the output end of the test output channel routing circuit. The third pipeline module is used to send the test output signal to the multiplexing circuit in stages, and the fourth pipeline module is used to send the test output signal output by the multiplexing circuit to the designated test channel pin in stages.

[0013] According to a second aspect of this application, a chip testing method is provided, the method being applied to the aforementioned chip testing circuit, the method comprising: Upon receiving test instructions corresponding to different circuit modules under test on the chip, the test instructions corresponding to the circuit modules under test are sent to the test channel pins corresponding to the circuit modules under test, so that the circuit modules under test execute the test instructions.

[0014] According to a third aspect of this application, a chip is provided, including the chip test circuit described above.

[0015] Compared with the prior art, this application has the following advantages: This application provides a chip testing circuit, chip testing method, and chip. By dividing multiple IP cores in the chip into multiple group test circuits according to the physical layout, and allocating dedicated test channel pins to each group test circuit, the IP cores in different group test circuits can be tested in parallel, thereby improving the efficiency of chip testing. Furthermore, the same group test circuit is further divided into multiple serially connected circuit under test modules, so that different circuit under test modules in the same group test circuit can be tested in a time-division serial manner using dedicated test channel pins, overcoming the defect of limited number of test channel pins and improving the utilization rate of test channel pins.

[0016] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the structure of a chip testing circuit provided in an embodiment of this application; Figure 2 This is one of the schematic diagrams of another chip testing circuit provided in the embodiments of this application; Figure 3 This is one of the transmission schematic diagrams of a chip testing circuit provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of this application; Figure 5This is a second schematic diagram of another chip testing circuit provided in the embodiments of this application; Figure 6 This is a third schematic diagram of another chip testing circuit provided in the embodiments of this application; Figure 7 This is a second schematic diagram of the transmission of a chip testing circuit provided in an embodiment of this application; Figure 8 This is the third schematic diagram of a chip testing circuit provided in the embodiments of this application; Figure 9 This is a schematic flowchart of a chip testing method provided in an embodiment of this application. Detailed Implementation

[0018] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0019] Figure 1 This application provides a schematic diagram of a chip testing circuit, comprising: multiple group test circuits 10, each group test circuit 10 including multiple circuit under test (DUT) modules 101, each DUT module including multiple IP cores 1011, and each group test circuit 10 connected to a dedicated test channel pin 20; the DUT modules 101 in the same group test circuit 10 are serially connected to the dedicated test channel pin 20, and the multiple group test circuits 10 are tested in parallel. The IP cores can be processor cores.

[0020] It should be noted that the chip can be a SOC or SIP packaged chip. The test circuit is set inside the chip and is used to test each IP core in the chip. IP cores are the intellectual property cores in the chip. They are obtained by designing modules with modifiable parameters from some commonly used but relatively complex functional modules in digital circuits, such as FIR filters, SDRAM controllers, and PCI interfaces.

[0021] The plurality of circuit modules under test are modules obtained by dividing the IP cores in the chip according to the physical layout of the IP cores. Physical layout division refers to dividing multiple adjacent IP cores into a group as a circuit module under test according to the physical layout of the IP cores on the chip. This is mainly because the adjacency relationship in the physical layout is conducive to providing conditions for setting pins for different circuit modules under test. It can be understood that if the different IP cores in the same group are too far apart or there are other groups of IP cores in between, it will be difficult to design pins for different circuit modules under test in terms of physical layout.

[0022] In this embodiment, considering that traditional chip testing circuits reuse the same test channel throughout the entire chip testing process, requiring individual testing of each module under test in the chip, which is cumbersome, this embodiment divides multiple adjacent IP cores in the chip into a unified group test circuit according to their physical layout. Then, the chip is packaged with test channel pins and assigned to each group test circuit. This allows different group test circuits on the same chip to use their dedicated test channel pins for parallel testing. Compared to the traditional chip testing method that uses only one set of test channels and adopts time-division serial testing, this greatly improves the efficiency of chip testing.

[0023] Furthermore, considering the limited number of test channel pins in the chip package, an insufficient number of test channel pins may occur if too many group test circuits are set up. Therefore, this embodiment of the application can further divide each group test circuit into subgroups, further dividing multiple IP cores that need to be tested collaboratively within the group test circuit into the same circuit under test module. Since each group test circuit is connected to a dedicated test channel pin, multiple circuit under test modules in the same group test circuit can be tested in a time-division serial manner using the dedicated test channel pins of the group test circuit, thereby improving the utilization rate of the test channel pins.

[0024] For example, refer to Figure 1 Based on the chip's physical layout structure, the chip is divided into four group test circuits 10. The IP cores in each group test circuit are further divided into four circuit under test modules 101. Each circuit under test module 101 contains four IP cores 1011. Each group test circuit is connected to a dedicated test channel pin for inputting and outputting test signals. Of course, this is just an example description. The way the chip is divided into circuit under test modules, group test circuits, and test channel pins is allocated can be set according to actual needs and is not limited here.

[0025] This application embodiment divides multiple IP cores in a chip into multiple group test circuits according to their physical layout. Each group test circuit is assigned a dedicated test channel pin, which enables parallel testing of IP cores in different group test circuits, improving chip testing efficiency. Furthermore, the same group test circuit is further divided into multiple serially connected circuit-under-test modules, allowing different circuit-under-test modules in the same group test circuit to perform time-division serial testing using dedicated test channel pins. This overcomes the limitation of the limited number of test channel pins and improves the utilization rate of test channel pins.

[0026] Optionally, refer to Figure 2 The group test circuit 10 further includes a test input channel distribution circuit 102; the test input channel distribution circuit 102 is used to distribute the test input signal input by the test channel pin 20 to each of the circuit modules under test 101 in the group test circuit 10.

[0027] In this embodiment of the application, since multiple circuit modules under test in the same group test circuit are connected in series, during the time-division serial test using the dedicated test channel pin of the group test circuit, a test input channel distribution circuit needs to be set in the group test circuit to distribute the test input signal input from the test channel pin to the specified circuit module under test. For example, if the test channel pin receives the test input signal input to the Nth circuit module under test, the input channel distribution circuit can distribute the test input signal to the Nth circuit module under test.

[0028] Optionally, refer to Figure 2 The group test circuit 10 further includes: the test output channel selection circuit 103; the test output channel selection circuit 103 is used to send the test output signal output by the circuit module under test 101 in response to the test input signal to the test channel pin 20.

[0029] In this embodiment, multiple circuit modules under test (DUTs) in the same group test circuit share a set of test channel pins through an output channel selection circuit. The DUTs obtain test output signals by testing based on test input signals and send them to the output channel selection circuit. The output channel selection circuit marks the test output signals of different DUTs and sends the test output signals to the dedicated test channel pins of the group test circuit, so that the test output signals can be distinguished from which DUTs they come from, thus completing the test process.

[0030] Specifically, for the transmission process of test input and output signals in the group test circuit, please refer to... Figure 3Each group test circuit can be configured with a set of test channel pins, each containing one test input channel and one test output channel. During testing, the test input channel of the Nth test channel pin, dedicated to the Nth group test circuit, first sends the test input signal to the test input channel distribution circuit of the Nth group test circuit. Then, the test input channel distribution circuit distributes the test input signal to each circuit module under test, for example... Figure 3 The circuit under test (DUT) module 1 and DUT module 2 are in the test circuit. When the DUT module completes the test in response to the test input signal, the DUT module sends the test output signal to the test output channel selection circuit. The test channel selection circuit then sends the test output signal to the dedicated test output channel pin of the Nth group test circuit.

[0031] Optionally, multiple grouped test circuits may be tested in parallel testing mode.

[0032] Optionally, multiple circuit modules under test in the same group test circuit are tested using a time-division serial model.

[0033] Optionally, refer to Figure 5 The chip test circuit further includes a test channel routing circuit 30, wherein each of the group test circuits is connected to the test channel pin through the test channel routing circuit; the test channel routing circuit is used to distribute the test input signal sent by the test channel pin to the group test circuit, and to output the test output signal output by the group test circuit in response to the test input signal through the test channel pin.

[0034] In the embodiments of this application, reference is made to Figure 4 This is a chip packaged using SiP (System-in-Package) technology. Because some pins of chips packaged using SiP technology cannot be fully encapsulated, there are insufficient channel pins required for chip testing, making normal testing impossible. Therefore, refer to... Figure 5 In this embodiment, a test path routing circuit is further designed in the chip to associate the relationship between the group test circuits and the test channel pins. That is, each group test circuit can use any test channel pin, so that even if the group test circuit in the chip obtained by using SIP packaging technology does not package the test channel pins, it can still use the test channel pins packaged by other group test circuits for testing. This requires the input and output of different group test circuits to be changed from the original inter-group parallel to inter-group serial, but the test instructions executed by different group test circuits can be different.

[0035] Optionally, refer to Figure 6The test channel routing circuit 30 includes a multiplexing circuit 301; the multiplexing circuit 301 is used to distribute the test input signal of the external input Nth test channel pin to the Nth group test circuit, and to output the test output signal of the Nth group test circuit in response to the test input signal through the Nth test channel pin.

[0036] In this embodiment, N is a number used for the test channel pins and group test circuits. In this embodiment, the dedicated pin of the Nth group test circuit is the Nth test channel pin. For example, the dedicated pin of the 1st group test circuit is the 1st test channel pin, the dedicated pin of the 2nd group test circuit is the 2nd test channel pin, and so on.

[0037] Optionally, refer to Figure 6 The test channel routing circuit 30 further includes: a test input channel routing circuit 302, a first pipeline module 3021, and a second pipeline module 3022; the first pipeline module 3021 is disposed at the input end of the test input channel routing circuit 302, and the second pipeline module 3022 is disposed at the output end of the test input channel routing circuit 302. The first pipeline module 3021 is used to send the test input signal to the multiplexing circuit in stages, and the second pipeline module 3022 is used to send the test input signal to the designated group test circuit in stages.

[0038] Optionally, refer to Figure 6 The test channel routing circuit 30 further includes: a test output channel routing circuit 303, a third pipeline module 3031, and a fourth pipeline module 3032; the third pipeline module 3031 is disposed at the input end of the test output channel routing circuit 303, and the fourth pipeline module 3032 is disposed at the output end of the test output channel routing circuit 303. The third pipeline module 3031 is used to send the test output signal to the multiplexing circuit in stages, and the fourth pipeline module 3032 is used to send the test output signal output by the multiplexing circuit to the dedicated test channel pin of the group test circuit from which the test output signal originates in stages.

[0039] In this embodiment, the test channel routing circuit consists of three parts: a test input channel routing circuit, a test output channel routing circuit, and a multiplexer.

[0040] Reference Figure 7During the input of test input signals, the test channel pins of different group test circuits receive the test input signals. The first pipeline module in the test input channel routing circuit sends the test input signals to the multiplexing circuit. The multiplexing circuit identifies which group test circuit the test input signal is destined for, thus determining the specific value of N (e.g., the first group test circuit, the second group test circuit, etc.). Then, the second pipeline module in the input channel routing circuit sends the test input signals to the determined Nth group test circuit. The first and second pipeline modules solve the long-path timing problem of the multiplexed pin signals from the test input channel reaching the Nth group test circuit. The number of pipeline stages can be one or more, depending on the specific physical layout; no limitation is made here. Pipelining technology refers to a quasi-parallel processing implementation technique where multiple instructions overlap during program execution. A CPU consists of 5-6 circuit units with different functions forming an instruction processing pipeline. An instruction is then divided into 5-6 steps, which are then executed by these circuit units respectively. This allows an instruction to be completed in one CPU clock cycle, thus improving the CPU's processing speed.

[0041] Reference Figure 8 During the test output process, the test output signals output by different group test circuits can be sent to the multiplexing circuit through the third pipeline module in the test output channel routing circuit. The multiplexing circuit distinguishes which test channel pin the test output signal is sent to, that is, determines the specific value of N, such as the first test channel pin, the second test channel pin, etc. The multiplexer sends the test output signal to the determined Nth test channel pin through the fourth pipeline module of the input channel routing circuit.

[0042] Reference Figure 9 This application provides a chip testing method, which is applied to a chip testing circuit provided in some embodiments of this application. The method includes: Step 401: Upon receiving test instructions corresponding to different circuit modules under test on the chip, the test instructions corresponding to the circuit modules under test are sent to the corresponding test channel pins of the circuit modules under test, so that the circuit modules under test execute the test instructions.

[0043] In this embodiment of the application, when testing different IP cores in a chip, the test input signal can be set according to the circuit under test module to which the IP core belongs. The test input signal needs to specify the circuit under test module to which the IP core belongs. Then the test input signal is sent to the group test circuit of the circuit under test module. The test input channel distribution circuit in the group test circuit can distribute the input test signal to the specified circuit under test module, thereby enabling IP cores in multiple different circuit under test modules to execute different test tasks in parallel.

[0044] The beneficial effects achievable by this chip testing method can be referred to in the above-described embodiments for chip testing circuits, and will not be repeated here.

[0045] This application provides a chip that includes the chip testing circuit described in any of the above embodiments.

[0046] For a detailed description of the chip and the beneficial effects it can achieve, please refer to the above-described embodiment of the chip test circuit, which will not be repeated here.

[0047] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0048] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0049] The above provides a detailed description of a data processing method, a data processing device, an electronic device, and a storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A chip testing circuit, characterized in that, The chip testing circuit includes: Multiple group test circuits, each group test circuit includes multiple circuit modules under test, each circuit module under test includes multiple IP cores; wherein, the multiple circuit modules under test are modules obtained by dividing according to the physical layout of IP cores in the chip, the physical layout division refers to dividing multiple adjacent IP cores into a group as a circuit module under test according to the physical layout of IP cores on the chip; Each of the group test circuits is connected to a dedicated test channel pin; the circuit under test module in the same group test circuit is connected in series with the dedicated test channel pin, and multiple group test circuits are tested in parallel test mode.

2. The chip testing circuit according to claim 1, characterized in that, The group test circuit also includes: a test input channel distribution circuit; The test input channel distribution circuit is used to distribute the test input signal input from the test channel pin to each of the circuit modules under test in the group test circuit.

3. The chip testing circuit according to claim 2, characterized in that, The group test circuit also includes: the test output channel selection circuit; The test output channel selection circuit is used to send the test output signal output by the circuit module under test in response to the test input signal to the test channel pin.

4. The chip testing circuit according to claim 1, characterized in that, Multiple circuit modules under test in the same group test circuit are tested using a time-division serial model.

5. The chip testing circuit according to claim 1, characterized in that, Also includes: A test channel routing circuit is provided, and each of the group test circuits is connected to the test channel pins through the test channel routing circuit. The test channel routing circuit is used to distribute the test input signal sent by the test channel pin to the group test circuit, and to output the test output signal output by the group test circuit in response to the test input signal through the test channel pin.

6. The chip testing circuit according to claim 5, characterized in that, The test channel routing circuit includes: a multiplexer circuit; The multiplexing circuit is used to distribute the test input signal from the external input Nth test channel pin to the Nth group test circuit, and to output the test output signal of the Nth group test circuit in response to the test input signal through the Nth test channel pin.

7. The chip testing circuit according to claim 6, characterized in that, The test channel routing circuit further includes: a test input channel routing circuit, a first pipeline module, and a second pipeline module; the first pipeline module is disposed at the input end of the test input channel routing circuit, and the second pipeline module is disposed at the output end of the test input channel routing circuit; The first pipeline module is used to send the test input signal to the multiplexing circuit in stages, and the second pipeline module is used to send the test input signal to the designated group test circuit in stages.

8. The chip testing circuit according to claim 7, characterized in that, The test channel routing circuit further includes: a test output channel routing circuit, a third pipeline module, and a fourth pipeline module; the third pipeline module is located at the input end of the test output channel routing circuit, and the fourth pipeline module is located at the output end of the test output channel routing circuit. The third pipeline module is used to send the test output signal to the multiplexing circuit in stages, and the fourth pipeline module is used to send the test output signal output by the multiplexing circuit to the designated test channel pin in stages.

9. A chip testing method, characterized in that, The method is applied to the chip testing circuit according to any one of claims 1-8, and the method includes: Upon receiving test instructions corresponding to different circuit modules under test on the chip, the test instructions corresponding to the circuit modules under test are sent to the test channel pins corresponding to the circuit modules under test, so that the circuit modules under test execute the test instructions.

10. A chip, characterized in that, Includes the chip test circuit described in any one of claims 1-8.

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