Bipolar band-gap reference circuit and power management chip

Abstract

The invention provides a bipolar band-gap reference circuit and a power management chip, the bipolar band-gap reference circuit comprises a starting module, a core reference module, an imbalance module and a temperature compensation module, the starting module provides starting voltage, the core reference module is driven by the starting voltage to complete power-on operation and output initial reference voltage, and the imbalance module outputs the initial reference voltage; the offset control module is bridged between the current mirror image structures of the core reference module, and is used for adjusting the current of the current mirror image structures, so that the current of the current mirror image structures in the core reference module is equal, and the current is balanced; high-order temperature compensation is carried out on the initial reference voltage through the temperature compensation module, and therefore the target reference voltage with the low temperature coefficient is output within the wide temperature range. According to the reference circuit provided by the invention, the matching performance of the current mirror is improved by introducing the improved current mirror structure, the temperature range is widened by adding the temperature compensation module, and the reference circuit which has a lower temperature coefficient and is suitable for a wide temperature range is provided.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a bipolar bandgap reference circuit and a power management chip. Background Technology

[0002] Bandgap reference circuits are widely used in analog and digital circuits and are an indispensable basic circuit in circuits such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), phase-locked loops (PLLs), power management chips, and linear regulators (LDOs).

[0003] Due to its higher transconductance efficiency, lower noise, better matching, and stronger current drive capability, bipolar technology remains widely used in pursuit of ultimate performance. Currently, bandgap reference circuits formed using bipolar technology suffer from base current. If current mirror structures suitable for transistor technology (such as cascode structures) are directly applied, current mismatch will occur, especially when the transistor's current amplification factor β is small. Traditional bipolar structures remain the mainstream bandgap reference circuit structure due to their simplicity (no operational amplifier), reliable performance, and low power consumption. However, the temperature coefficient of this traditional bandgap reference circuit is 20-60 ppm / ℃ (parts per million per degree Celsius), which is relatively high and increasingly unable to meet the stable reference voltage requirements of today's high-precision integrated circuit chips.

[0004] Currently, the temperature drift of a circuit can be reduced through piecewise linear compensation and high-order curvature compensation techniques. However, the operation amplifier is designed in the compensation circuit, which increases the complexity of the overall circuit structure. Furthermore, the misalignment of the operation amplifier can also have a certain impact on the circuit. Summary of the Invention

[0005] This invention provides a bipolar bandgap reference circuit and a power management chip to solve the technical problems of current adaptation, high temperature drift, and complex circuit structure of the aforementioned mainstream bipolar bandgap reference circuits.

[0006] In a first aspect, the present invention provides a bipolar bandgap reference circuit, comprising: The startup module is used to provide the startup voltage; The core reference module, connected to the startup module, is used to respond to the startup voltage and generate an initial reference voltage; An offset control module is connected across the current mirror structure of the core reference module to adjust the potential of the current mirror structure in order to balance the operating current of the core reference module. The temperature compensation module, connected to the core reference module, is used to inject a high-order temperature compensation amount into the initial reference voltage to obtain a target reference voltage with a low temperature coefficient within a preset temperature range.

[0007] In one embodiment of the present invention, the startup module includes a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a fifth NPN transistor, and a sixth NPN transistor. The collector of the first NPN transistor is connected to a positive power supply voltage, and the collector of the first NPN transistor is also connected to the base of the first NPN transistor. The emitter of the first NPN transistor is connected to the collector of the second NPN transistor, the collector of the second NPN transistor is connected to the base of the second NPN transistor, the emitter of the second NPN transistor is connected to the collector of the third NPN transistor, and the collector of the third NPN transistor is connected to the sixth NPN transistor. The base of a third NPN transistor is connected to the base of a fourth NPN transistor, the emitter of the fourth NPN transistor is connected to the collector of the fifth NPN transistor, the collector of the fifth NPN transistor is connected to the base of the fifth NPN transistor, the emitter of the fifth NPN transistor is connected to the collector of the fifth NPN transistor, the collector of the fifth NPN transistor is connected to the base of the fifth NPN transistor, the emitter of the fifth NPN transistor is connected to a negative power supply voltage, the emitter of the third NPN transistor is also connected to the base of a sixth NPN transistor, and the collector of the sixth NPN transistor is connected to the positive power supply voltage. The emitter of the sixth NPN transistor outputs the start-up voltage.

[0008] In one embodiment of the present invention, the core reference module includes a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor, a first PNP transistor, a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The first terminal of the first resistor is connected to a positive power supply voltage. The first terminal of the first resistor is also connected to the first terminal of the second resistor. The second terminal of the first resistor is connected to the emitter of the first PNP transistor. The base of the first PNP transistor is connected to the base of the second PNP transistor. The second terminal of the second resistor is connected to the emitter of the second PNP transistor. The collector of the first PNP transistor is connected to the emitter of the third PNP transistor. The collector of the second PNP transistor is connected to the emitter of the fourth PNP transistor. The base of the third PNP transistor is connected to the fourth PNP transistor. The base of the third PNP transistor is connected to the collector of the third PNP transistor, the collector of the third PNP transistor is connected to the collector of the seventh NPN transistor, the collector of the fourth PNP transistor is connected to the collector of the eighth NPN transistor, the base of the seventh NPN transistor is connected to the base of the eighth NPN transistor, the emitter of the seventh NPN transistor is connected to the first terminal of the third resistor, the second terminal of the third resistor is connected to the negative power supply voltage via the fourth resistor and the fifth resistor, the emitter of the eighth NPN transistor is connected to the second terminal of the third resistor, the collector of the eighth NPN transistor is also connected to the collector of the ninth NPN transistor, the base of the ninth NPN transistor is connected to the emitter of the ninth NPN transistor, and the emitter of the ninth NPN transistor is connected to the negative power supply voltage. The base of the seventh NPN transistor outputs the initial reference voltage.

[0009] In one embodiment of the present invention, the ratio of the number of the seventh NPN transistor to the number of the eighth NPN transistor is N:1, and the ratio of the number of the seventh NPN transistor to the number of the ninth NPN transistor is N:N-1; the number of the first PNP transistor, the number of the second PNP transistor, the number of the third PNP transistor, the number of the fourth PNP transistor and the number of the eighth NPN transistor are equal, wherein N is a positive integer greater than or equal to 2.

[0010] In one embodiment of the present invention, the offset control module includes a fifth PNP transistor, a sixth PNP transistor, a seventh PNP transistor, an eighth PNP transistor, a ninth PNP transistor, and a sixth resistor. The base of the fifth PNP transistor is connected to the base of the sixth PNP transistor and the base of the eighth PNP transistor. The base of the fifth PNP transistor is connected to its collector. The base of the sixth PNP transistor is connected to its collector. The collector of the fifth PNP transistor is also connected to the emitter of the seventh PNP transistor. The collector of the sixth PNP transistor is also connected to the emitter of the seventh PNP transistor. The collector of the seventh PNP transistor is connected to the negative resistor. The source voltage is such that the first terminal of the sixth resistor is connected to the positive power supply voltage, the second terminal of the sixth resistor is connected to the emitter of the eighth PNP transistor, the collector of the eighth PNP transistor is connected to the emitter of the ninth PNP transistor, and the collector of the ninth PNP transistor is connected to the negative power supply voltage. The emitter of the fifth PNP transistor is the first input terminal of the offset control module, the emitter of the sixth PNP transistor is the second input terminal of the offset control module, the base of the fifth PNP transistor is the first control terminal of the offset control module, the base of the seventh PNP transistor is the second control terminal of the offset control module, and the base of the ninth PNP transistor is the third control terminal of the offset control module.

[0011] In one embodiment of the present invention, the ratio of the number of the fifth PNP transistor, the sixth PNP transistor, the seventh PNP transistor, the eighth PNP transistor, and the ninth PNP transistor is 1:1:2:4:4.

[0012] In one embodiment of the present invention, the temperature compensation module includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth NPN transistor, and an eleventh NPN transistor. The collector of the tenth NPN transistor is connected to a positive power supply voltage. The emitter of the tenth NPN transistor is connected to the first terminal of the seventh resistor. The emitter of the tenth NPN transistor is also connected to the first terminal of the eighth resistor. The second terminal of the eighth resistor is connected to the base of the eleventh NPN transistor. The second terminal of the eighth resistor is also connected to the first terminal of the ninth resistor. The second terminal of the ninth resistor is connected to the emitter of the eleventh NPN transistor. The emitter of the eleventh NPN transistor is connected to a negative power supply voltage. The second terminal of the seventh resistor is connected to the collector of the eleventh NPN transistor. The base of the tenth NPN transistor is the control terminal of the temperature compensation module. The second terminal of the seventh resistor is the input terminal of the temperature compensation module. The first terminal of the seventh resistor is the output terminal of the temperature compensation module.

[0013] Secondly, this application provides an optoelectronic imaging device, which includes a bipolar bandgap reference circuit as described above.

[0014] The beneficial effects of this invention are as follows: This invention provides a bipolar bandgap reference circuit and a power management chip. The bipolar bandgap reference circuit includes a startup module, a core reference module, an offset module, and a temperature compensation module. The startup module provides a startup voltage. Driven by the startup voltage, the core reference module completes the power-on operation and outputs an initial reference voltage. The offset control module is connected across the current mirror structures of the core reference module to adjust the current in the current mirror structures, making the currents in the current mirror structures of the core reference module equal. The temperature compensation module performs high-order temperature compensation on the initial reference voltage, thereby outputting a target reference voltage with a low temperature coefficient within a preset temperature range. The reference circuit provided by this invention improves the matching performance of the current mirror by introducing an improved current mirror structure and widens the temperature range by adding a temperature compensation module, providing a reference circuit with a low temperature coefficient and suitable for a wide temperature range. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] In the attached diagram: Figure 1 This is a block diagram of the bipolar bandgap reference circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the specific structure of the bipolar bandgap reference circuit provided in the embodiment of the present invention; Figure 3 This is a schematic diagram of the temperature relationship curve when the target reference voltage provided in this embodiment of the invention is not temperature compensated; Figure 4 A schematic diagram of the temperature relationship after temperature compensation for the target reference voltage provided in this embodiment of the invention; Figure 5 This is a schematic diagram of the simulation curve of the power supply rejection ratio of the bipolar bandgap reference circuit provided in the embodiment of the present invention.

[0017] Figure reference numerals: 110 - Startup module; 120 - Core reference module; 130 - Offset control module; 140 - Temperature compensation module; V d -Start-up voltage; V 0-ref - Initial reference voltage; V g-ref- Target reference voltage; VCC - Positive power supply voltage; VSS - Negative power supply voltage. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0021] To solve the above problems, such as Figure 1 As shown, this application provides a bipolar bandgap reference circuit, comprising: Startup module 110 is used to provide startup voltage V d ; The core reference module 120, connected to the startup module 110, is used to respond to the startup voltage V. d And generate the initial reference voltage V 0-ref ; Offset control module 130 is connected across the current mirror structure of core reference module 120 to adjust the potential of the current mirror structure in order to balance the operating current of core reference module 120. Temperature compensation module 140, connected to core reference module 120, is used to supply the initial reference voltage V. 0-ref Injecting high-order temperature compensation to obtain a target reference voltage V with a low temperature coefficient within a preset temperature range. g-ref .

[0022] In detail, such as Figure 2As shown, the startup module 110 includes a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, a fifth NPN transistor Q5, and a sixth NPN transistor Q6. The collector of the first NPN transistor Q1 is connected to the positive power supply voltage VCC, and the collector of the first NPN transistor Q1 is also connected to the base of the first NPN transistor Q1. The emitter of the first NPN transistor Q1 is connected to the collector of the second NPN transistor Q2, the collector of the second NPN transistor Q2 is connected to the base of the second NPN transistor Q2, the emitter of the second NPN transistor Q2 is connected to the collector of the third NPN transistor Q3, and the collector of the third NPN transistor Q3 is connected to the... The base of the third NPN transistor Q3 is connected to the base of the fourth NPN transistor Q4, the emitter of the fourth NPN transistor Q4 is connected to the collector of the fifth NPN transistor Q5, the collector of the fifth NPN transistor Q5 is connected to the base of the fifth NPN transistor Q4, the emitter of the fifth NPN transistor Q4 is connected to the collector of the fifth NPN transistor Q5, the collector of the fifth NPN transistor Q5 is connected to the base of the fifth NPN transistor Q5, the emitter of the fifth NPN transistor Q5 is connected to the negative power supply voltage VSS, the emitter of the third NPN transistor Q3 is also connected to the base of the sixth NPN transistor Q6, and the collector of the sixth NPN transistor Q6 is connected to the positive power supply voltage VCC. The emitter of the sixth NPN transistor Q6 outputs a start-up voltage Vd.

[0023] In detail, such as Figure 2As shown, the core reference module 120 includes a seventh NPN transistor Q7, an eighth NPN transistor Q8, a ninth NPN transistor Q9, a first PNP transistor Q101, a second PNP transistor Q102, a third PNP transistor Q103, a fourth PNP transistor Q104, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The first terminal of the first resistor R1 is connected to the positive power supply voltage VCC, and the first terminal of the first resistor R1 is also connected to the first terminal of the second resistor R2. The second terminal of resistor R1 is connected to the emitter of the first PNP transistor Q101. The base of the first PNP transistor Q101 is connected to the base of the second PNP transistor Q102. The second terminal of resistor R2 is connected to the emitter of the second PNP transistor Q102. The collector of the first PNP transistor Q101 is connected to the emitter of the third PNP transistor Q103. The collector of the second PNP transistor Q102 is connected to the emitter of the fourth PNP transistor Q104. The base of the third PNP transistor Q103 is connected to the emitter of the fourth PNP transistor Q104. The base of transistor Q104 is connected to the base of transistor Q103, the base of transistor Q103 is connected to the collector of transistor Q103, the base of transistor Q103 is connected to the base of transistor Q104, the collector of transistor Q103 is connected to the collector of transistor Q7, the collector of transistor Q104 is connected to the collector of transistor Q8, the base of transistor Q7 is connected to the base of transistor Q8, and the emitter of transistor Q7 is connected to the base of transistor Q8. The first terminal of resistor R3 and the second terminal of the third resistor R3 are connected to the negative power supply voltage VSS via resistors R4 and R5. The emitter of the eighth NPN transistor Q8 is connected to the second terminal of the third resistor R3. The collector of the eighth NPN transistor Q8 is also connected to the collector of the ninth NPN transistor Q9. The base of the ninth NPN transistor Q9 is connected to its emitter. The emitter of the ninth NPN transistor Q9 is connected to the negative power supply voltage VSS. The base of the seventh NPN transistor Q7 outputs the initial reference voltage V. 0-ref .

[0024] More specifically, the ratio of the number of seventh NPN transistors Q7 to the number of eighth NPN transistors Q8 is N:1; the ratio of the number of seventh NPN transistors Q7 to the number of ninth NPN transistors Q9 is N:N-1; the number of first PNP transistors Q101, second PNP transistors Q102, third PNP transistors Q103, fourth PNP transistors Q104, and eighth NPN transistors Q8 are equal, where N is a positive integer greater than or equal to 2. Specifically, the ratio of the number of seventh NPN transistors Q7, eighth NPN transistors Q8, first PNP transistors Q101, second PNP transistors Q102, third PNP transistors Q103, fourth PNP transistors Q104, and ninth NPN transistors Q9 is N:1:1:1:1:1:(N-1).

[0025] In detail, such as Figure 2As shown, the offset control module 130 includes a fifth PNP transistor Q105, a sixth PNP transistor Q106, a seventh PNP transistor Q107, an eighth PNP transistor Q108, a ninth PNP transistor Q109, and a sixth resistor R6. The base of the fifth PNP transistor Q105 is connected to the base of the sixth PNP transistor Q106 and the base of the eighth PNP transistor Q108. The base of the fifth PNP transistor Q105 is connected to the collector of the fifth PNP transistor Q105. The base of the sixth PNP transistor Q106 is connected to the collector of the eighth PNP transistor Q108. The collector of the sixth PNP transistor Q106 is connected to the collector of the fifth PNP transistor Q105, which is also connected to the emitter of the seventh PNP transistor Q107. The collector of the sixth PNP transistor Q106 is also connected to the emitter of the seventh PNP transistor. The collector of the seventh PNP transistor Q107 is connected to the negative power supply voltage VSS. The first terminal of the sixth resistor R6 is connected to the positive power supply voltage VCC. The second terminal of the sixth resistor R6 is connected to the emitter of the eighth PNP transistor Q108. The collector of the eighth PNP transistor Q108 is connected to the ninth PNP transistor Q107. The emitter of the ninth PNP transistor Q109 is connected to the negative power supply voltage VSS. The emitter of the fifth PNP transistor Q105 is the first input terminal of the offset control module 130, which is connected to the emitter (point X) of the first PNP transistor Q101. The emitter of the sixth PNP transistor Q106 is the second input terminal of the offset control module 130, which is connected to the emitter (point Y) of the second PNP transistor Q102. The fifth PNP transistor Q105... The base of transistor Q105 is the first control terminal of offset control module 130, and the first control terminal of offset control module 130 is connected to the base of first PNP transistor Q101. The base of seventh PNP transistor Q107 is the second control terminal of offset control module 130, and the second control terminal of offset control module 130 is connected to the base of third PNP transistor Q103. The base of ninth PNP transistor Q109 is the third control terminal of offset control module 130, and the third control terminal of offset control module 130 is connected to the collector of fourth PNP transistor Q104.

[0026] More specifically, the ratio of the number of the fifth PNP transistor Q105, the sixth PNP transistor Q106, the seventh PNP transistor Q107, the eighth PNP transistor Q108, and the ninth PNP transistor Q109 is 1:1:2:4:4.

[0027] More in detail, such as Figure 2As shown, the temperature compensation module 140 includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth NPN transistor Q10, and an eleventh NPN transistor Q11. The collector of the tenth NPN transistor Q10 is connected to the positive power supply voltage VCC. The emitter of the tenth NPN transistor Q10 is connected to the first terminal of the seventh resistor R7. The emitter of the tenth NPN transistor Q10 is also connected to the first terminal of the eighth resistor R8. The second terminal of the eighth resistor R8 is connected to the base of the eleventh NPN transistor Q11. The second terminal of the eighth resistor R8 is also connected to the first terminal of the ninth resistor R9. The second terminal of the ninth resistor R9 is connected to the emitter of the eleventh NPN transistor Q11. The emitter of the eleventh NPN transistor Q11 is connected to the negative power supply voltage VSS. The second terminal of the seventh resistor R7 is connected to the collector of the eleventh NPN transistor Q11. The base of the tenth NPN transistor Q10 is the control terminal of the temperature compensation module 140, which is connected to the collector of the eighth PNP transistor Q108. The second terminal of the seventh resistor R7 is the input terminal of the temperature compensation module 140, which is connected to the base of the seventh NPN transistor Q7. The first terminal of the seventh resistor R7 is the output terminal of the temperature compensation module 140, which outputs the target reference voltage V. g-ref .

[0028] Please refer to Figures 1 to 5 As shown, the working principle of the bipolar bandgap reference circuit provided by this invention is as follows: like Figure 1 As shown, the bipolar bandgap reference circuit includes a startup module 110, a core reference module 120, an offset control module 130, and a temperature compensation module 140. The startup module 110 provides a startup voltage V. d The core reference module 120 is at the startup voltage V d Driven by this, an initial reference voltage V is generated. 0-ref The offset control module 130 is connected across the core reference module 120, ensuring that the current flowing through the current mirror structure in the core reference module 120 is equal. The temperature compensation module 140 is connected to the core reference module 120, and when the temperature rises, it supplies power to the initial reference voltage V. 0-ref By inputting a high-order temperature compensation value, a target reference voltage V with a low temperature coefficient can be obtained. g-ref The preset temperature range is -55℃ to 125℃.

[0029] When the entire circuit is not powered on, there is no current in the reference core module 120, and the startup voltage V dWhen the circuit is powered on, the fourth NPN transistor Q4 and the fifth NPN transistor Q5 in the startup module 110 are turned on, generating two base-emitter voltages at the base of the sixth NPN transistor Q6. This increases the base-emitter voltage of the sixth NPN transistor Q6, making it sufficient to turn on the sixth NPN transistor Q6. The startup voltage V is zero. d The voltage continues to rise until the core reference module 120 starts up normally, at which point the starting voltage V... d After the voltage rises, the base-emitter voltage of the sixth NPN transistor Q6 is insufficient to turn on the sixth NPN transistor Q6, so the sixth NPN transistor Q6 is turned off, thus completing the power-on startup.

[0030] In the core reference module 120, the first PNP transistor Q101 and the second PNP transistor Q102 form a current mirror structure, the third PNP transistor Q103 and the fourth PNP transistor Q104 form a current mirror structure, the fourth resistor R4 is a Cr-Si thin film resistor with an extremely low temperature coefficient, and the fifth resistor R5 is a Poly resistor with a high temperature coefficient. Equal current is provided to the two branches, including the seventh NPN transistor Q7 and the eighth NPN transistor Q8. The voltage across the third resistor R3 is: V R3 =V be8 -V be7 =VT*lnN Among them, V R3 V is the voltage across the third resistor R3. be8 V is the base-emitter voltage of the eighth NPN transistor Q8. be7 VT is the base-emitter voltage of the seventh NPN transistor Q7, ln is the logarithmic function, and N is the ratio of the number of seventh NPN transistors.

[0031] The current flowing through the third resistor R3 is: I R3 =V R3 / R3 Among them, I R3 V is the current flowing through the third resistor R3. R3 R3 is the voltage across the third resistor R3.

[0032] Because the branch current including the seventh NPN transistor Q7 is equal to the branch current including the eighth NPN transistor Q8, the base output of the seventh NPN transistor Q7 has an initial reference voltage V. 0-ref for: V 0-ref =V be8 +2*(R4+R5)*I R3 Among them, V 0-ref V is the initial reference voltage. be8 I is the base-emitter voltage of the eighth NPN transistor Q8. R3 R3 is the current flowing through the third resistor, R4 is the fourth resistor, and R5 is the fifth resistor.

[0033] The base-emitter voltage V of the eighth NPN transistor Q8 be8 for: V be8 =VG0-T*(VG0-V be0 ) / T0-(η-α)VT*ln(T / T0) Among them, V be8 VG0 is the base-emitter voltage of the eighth NPN transistor Q8; VG0 is the bandgap voltage of silicon at 0K, which is 1.205V; T0 is a given temperature; T is an arbitrary thermodynamic temperature; η is a constant related to carrier mobility, which depends on the process technology used; α is the temperature dependence order of the transistor's collector circuit. When α=0, the collector input current is a zero-temperature coefficient current; when α=1, the collector input current is a PTAT (positively temperature-dependent) current; V be0 VT is the base-emitter voltage of the transistor at a given temperature; ln is the thermal voltage; and ln is a logarithmic function.

[0034] Therefore, the emitter voltage of the eighth NPN transistor Q8 is: V e8 =(2*V R3 )*{R4+R5·[1+(T-T0)Tc1+Tc2·(T-T0) 2 ]} / R3 Among them, V e8 V is the emitter voltage of the eighth NPN transistor Q8. R3 R is the voltage across the third resistor, T0 is a given temperature, T is any thermodynamic temperature, R3 is the third resistor, R4 is the fourth resistor, R5 is the fifth resistor, Tc1 is the first-order temperature coefficient of the fifth resistor R5, and Tc2 is the second-order temperature coefficient of the fifth resistor R5.

[0035] The base-emitter voltage of the eighth NPN transistor Q8 is negatively correlated with temperature, while the thermal voltage VT is positively correlated with temperature. By appropriately selecting the ratio of the fourth resistor R4 to the fifth resistor R5, an initial reference voltage V independent of temperature can be obtained. 0-ref By adjusting the relevant resistors, the initial reference voltage V can be adjusted. 0-ref The derivatives with respect to T are all zero in the lower temperature range, which greatly reduces the amount of temperature variation in the lower temperature range.

[0036] In the offset control module 130, the base voltages of the first PNP transistor Q101, the second PNP transistor Q102, the fifth PNP transistor Q105, the sixth PNP transistor Q106, and the eighth PNP transistor Q108 are equal. The emitter voltage of the first PNP transistor Q101 is equal to the emitter voltage of the fifth PNP transistor Q105, and the emitter voltage of the second PNP transistor Q102 is equal to the emitter voltage of the sixth PNP transistor Q106. Therefore, the current I flowing through the first PNP transistor Q101 is... Q101 It is equal to the current I flowing through the fifth PNP transistor Q105. Q105 The current I flowing through the second PNP transistor Q102 Q102 It is equal to the current I flowing through the sixth PNP transistor Q106. Q106 , that is I Q101 =I Q105 I Q102 =I Q106 The currents flowing through the first resistor R1 and the second resistor R2 are respectively, I R1 =2I Q101 I R2 =2I Q102 The currents flowing into the seventh NPN transistor Q7 and the eighth NPN transistor Q8 are respectively: I Q7 =I Q101 +(I Q101 +I Q102 +I Q105 +I Q106 ) / β,I Q8 =I Q102 +I Q108 / β, where β is the amplification factor of the NPN and PNP transistors, and the ratio of the number of the eighth PNP transistor Q108 to the number of the first PNP transistor Q101 is 4:1, therefore I Q108 =4I Q101 Therefore I Q7 =I Q8 This greatly reduces the current mismatch caused by the base current; the ninth NPN transistor Q9 is a redundant transistor, making the current leaked from the parasitic diodes in the seventh NPN transistor Q7 and the eighth NPN transistor Q8 equal.

[0037] In the temperature compensation module 140, the voltage output from the emitter of the tenth NPN transistor Q10 is divided by the eighth resistor R8 and the ninth resistor R9 to provide a bias voltage for the base of the eleventh NPN transistor Q11. When the temperature is low, the base-emitter voltage of the eleventh NPN transistor Q11 is relatively large, so the eleventh NPN transistor Q11 is in the off state, and the target reference voltage V... g-ref Approximately equal to the initial reference voltage V0-ref As the temperature rises, the turn-on voltage of the eleventh NPN transistor Q11 gradually decreases, and at a certain temperature, the eleventh NPN transistor Q11 turns on, and the current I of the eleventh NPN transistor Q11... Q11 It will flow through the seventh resistor R7, generating a voltage drop across it. At this time, the target reference voltage V g-ref =V 0-ref +R6×I Q11 As the temperature rises further, the current I flowing through the eleventh NPN transistor Q11 increases. Q11 It will also increase accordingly, which can be used to compensate for the initial reference voltage V. 0-ref The characteristic of decreasing voltage with increasing temperature at high temperatures ultimately leads to the target reference voltage V. g-ref The change in temperature is reduced in the high-temperature range, which improves the temperature coefficient across the entire preset temperature range.

[0038] like Figure 3 As shown, Figure 3 The target reference voltage V g-ref The temperature relationship curve without compensation, with the target reference voltage V on the vertical axis. g-ref The horizontal axis represents temperature, such as Figure 4 As shown, Figure 4 The target reference voltage V g-ref The temperature relationship curve after compensation, with the target reference voltage V on the vertical axis. g-ref The horizontal axis represents temperature. It can be seen that after temperature compensation by the temperature compensation module 140, the target reference voltage V... g-ref Instead of continuing to decrease, it rose slightly, thus improving the overall temperature. For example... Figure 5 As shown, the vertical axis dB represents the ratio of output current ripple to input (interference) current ripple, and the horizontal axis represents frequency. It can be seen that the ripple is 80dB at low frequencies, which has a good power supply rejection ratio.

[0039] The present invention also provides a power management chip, which includes a bipolar bandgap reference circuit as described above, thereby providing a stable reference voltage and stabilizing the performance of the power management chip.

[0040] This invention provides a bipolar bandgap reference circuit and a power management chip. The bipolar bandgap reference circuit includes a startup module, a core reference module, an offset module, and a temperature compensation module. The startup module provides a startup voltage. Driven by the startup voltage, the core reference module completes the power-on operation and outputs an initial reference voltage. The offset control module is connected across the current mirror structures of the core reference module to adjust the current in the current mirror structures, making the currents in the current mirror structures of the core reference module equal and balancing the current. The temperature compensation module performs high-order temperature compensation on the initial reference voltage, thereby outputting a target reference voltage with a low temperature coefficient within a preset temperature range. The reference circuit provided by this invention improves the matching performance of the current mirror by introducing an improved common-emitter common-base current mirror structure and widens the temperature range by adding a temperature compensation module, providing a reference circuit with a low temperature coefficient and suitable for a wide temperature range.

[0041] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A bipolar bandgap reference circuit, characterized in that, include: The startup module is used to provide the startup voltage; The core reference module, connected to the startup module, is used to respond to the startup voltage and generate an initial reference voltage; An offset control module is connected across the current mirror structure of the core reference module to adjust the potential of the current mirror structure in order to balance the operating current of the core reference module. The temperature compensation module, connected to the core reference module, is used to inject a high-order temperature compensation amount into the initial reference voltage to obtain a target reference voltage with a low temperature coefficient within a preset temperature range.

2. The bipolar bandgap reference circuit according to claim 1, characterized in that, The startup module includes a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a fifth NPN transistor, and a sixth NPN transistor. The collector of the first NPN transistor is connected to a positive power supply voltage, and the collector of the first NPN transistor is also connected to the base of the first NPN transistor. The emitter of the first NPN transistor is connected to the collector of the second NPN transistor, the collector of the second NPN transistor is connected to the base of the second NPN transistor, the emitter of the second NPN transistor is connected to the collector of the third NPN transistor, and the collector of the third NPN transistor is connected to the sixth NPN transistor. The base of the transistor, the emitter of the third NPN transistor is connected to the collector of the fourth NPN transistor, the collector of the fourth NPN transistor is connected to the base of the fourth NPN transistor, the emitter of the fourth NPN transistor is connected to the collector of the fifth NPN transistor, the collector of the fifth NPN transistor is connected to the base of the fifth NPN transistor, the emitter of the fifth NPN transistor is connected to a negative power supply voltage, the emitter of the third NPN transistor is also connected to the base of the sixth NPN transistor, and the collector of the sixth NPN transistor is connected to the positive power supply voltage, wherein the emitter of the sixth NPN transistor outputs the start-up voltage.

3. The bipolar bandgap reference circuit according to claim 1, characterized in that, The core reference module includes a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor, a first PNP transistor, a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The first terminal of the first resistor is connected to the positive power supply voltage. The first terminal of the first resistor is also connected to the first terminal of the second resistor. The second terminal of the first resistor is connected to the emitter of the first PNP transistor. The base of the first PNP transistor is connected to the base of the second PNP transistor. The second terminal of the second resistor is connected to the emitter of the second PNP transistor. The collector of the first PNP transistor is connected to the emitter of the third PNP transistor. The collector of the second PNP transistor is connected to the emitter of the fourth PNP transistor. The base of the third PNP transistor is connected to the base of the fourth PNP transistor. The base of the third PNP transistor is connected to the collector of the third PNP transistor, the collector of the third PNP transistor is connected to the collector of the seventh NPN transistor, the collector of the fourth PNP transistor is connected to the collector of the eighth NPN transistor, the base of the seventh NPN transistor is connected to the base of the eighth NPN transistor, the emitter of the seventh NPN transistor is connected to the first terminal of the third resistor, the second terminal of the third resistor is connected to the negative power supply voltage via the fourth resistor and the fifth resistor, the emitter of the eighth NPN transistor is connected to the second terminal of the third resistor, the collector of the eighth NPN transistor is also connected to the collector of the ninth NPN transistor, the base of the ninth NPN transistor is connected to the emitter of the ninth NPN transistor, and the emitter of the ninth NPN transistor is connected to the negative power supply voltage. The base of the seventh NPN transistor outputs the initial reference voltage.

4. The bipolar bandgap reference circuit according to claim 3, characterized in that, The ratio of the number of the seventh NPN transistor to the number of the eighth NPN transistor is N:1, and the ratio of the number of the seventh NPN transistor to the number of the ninth NPN transistor is N:N-1; the number of the first PNP transistor, the number of the second PNP transistor, the number of the third PNP transistor, the number of the fourth PNP transistor and the number of the eighth NPN transistor are equal, where N is a positive integer greater than or equal to 2.

5. The bipolar bandgap reference circuit according to claim 3, characterized in that, The offset control module includes a fifth PNP transistor, a sixth PNP transistor, a seventh PNP transistor, an eighth PNP transistor, a ninth PNP transistor, and a sixth resistor. The base of the fifth PNP transistor is connected to the bases of the sixth and eighth PNP transistors. The base of the fifth PNP transistor is connected to its collector. The base of the sixth PNP transistor is connected to its collector. The collector of the fifth PNP transistor is also connected to the emitter of the seventh PNP transistor. The collector of the sixth PNP transistor is also connected to the emitter of the seventh PNP transistor. The collector of the seventh PNP transistor is connected to the negative power supply voltage. The first terminal of the sixth resistor is connected to the positive power supply voltage, the second terminal of the sixth resistor is connected to the emitter of the eighth PNP transistor, the collector of the eighth PNP transistor is connected to the emitter of the ninth PNP transistor, and the collector of the ninth PNP transistor is connected to the negative power supply voltage. The emitter of the fifth PNP transistor is the first input terminal of the offset control module, the emitter of the sixth PNP transistor is the second input terminal of the offset control module, the base of the fifth PNP transistor is the first control terminal of the offset control module, the base of the seventh PNP transistor is the second control terminal of the offset control module, and the base of the ninth PNP transistor is the third control terminal of the offset control module.

6. The bipolar bandgap reference circuit according to claim 5, characterized in that, The ratio of the number of the fifth PNP transistor, the sixth PNP transistor, the seventh PNP transistor, the eighth PNP transistor, and the ninth PNP transistor is 1:1:2:4:

4.

7. The bipolar bandgap reference circuit according to claim 1, characterized in that, The temperature compensation module includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth NPN transistor, and an eleventh NPN transistor. The collector of the tenth NPN transistor is connected to a positive power supply voltage. The emitter of the tenth NPN transistor is connected to the first terminal of the seventh resistor. The emitter of the tenth NPN transistor is also connected to the first terminal of the eighth resistor. The second terminal of the eighth resistor is connected to the base of the eleventh NPN transistor. The second terminal of the eighth resistor is also connected to the first terminal of the ninth resistor. The second terminal of the ninth resistor is connected to the emitter of the eleventh NPN transistor. The emitter of the eleventh NPN transistor is connected to a negative power supply voltage. The second terminal of the seventh resistor is connected to the collector of the eleventh NPN transistor. The base of the tenth NPN transistor is the control terminal of the temperature compensation module. The second terminal of the seventh resistor is the input terminal of the temperature compensation module. The first terminal of the seventh resistor is the output terminal of the temperature compensation module.

8. A power management chip, characterized in that, Includes the bipolar bandgap reference circuit as described in any one of claims 1-7.

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