Display driving module, display driving equipment and display system

Abstract

The invention discloses a display driving module, a display driving device and a display system.The display driving module comprises a driving chip array and a display control module which are connected with each other; the driving chip array comprises an active driving array formed by a plurality of active matrix driving chips; the display control module is used for sending control signals to all the active matrix driving chips in the driving chip array according to input display data so as to achieve independent control over all the active matrix driving chips. According to the embodiment of the invention, an active driving framework is adopted, a traditional passive scanning mode is abandoned, and the problems of image vanishing, cross crosstalk among pixels and the like when a passive driving structure is applied to a micro-pitch display product are fundamentally solved. Meanwhile, the brightness, color and dynamic display performance can be remarkably improved through independent pixel control, images are clearer and smoother, and the overall display quality and visual experience are greatly improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driver module, a display driver device, and a display system. Background Technology

[0002] With the rapid development of the ultra-high-definition display industry, market demand for LED direct-view display products with smaller pixel pitch and higher image quality continues to rise, and pixel pitch is rapidly iterating towards micro-pitch below P1.0mm. Currently, LED displays generally adopt a passive driving architecture of "row scanning chip + column constant current driver chip," which is significantly insufficient for micro-pitch scenarios. In micro-pitch display products, passive scanning drives are prone to problems such as image ghosting and signal coupling crosstalk. Abnormalities in LEDs or circuits can also cause "caterpillar" defects, severely reducing image contrast and uniformity, affecting product reliability and visual effects. Therefore, the existing driving architecture is no longer suitable for the development needs of micro-pitch display devices, and there is an urgent need to develop new display control solutions adapted to micro-pitch displays. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a display driver module, a display driver device, and a display system to solve the problems of poor display effect caused by image aliasing, signal coupling crosstalk, and other effects when traditional passive driving architecture is applied in micro-pitch display devices.

[0004] A first aspect of this application provides a display driver module, including an array of driver chips and a display control module interconnected with each other; The driving chip array includes an active driving array composed of multiple active matrix driving chips. The display control module is used to send control signals to each of the active matrix driver chips in the driver chip array according to the input display data, so as to realize independent control of each of the active matrix driver chips.

[0005] This embodiment employs an active matrix driver chip deployment scheme. The display control module independently controls each active matrix driver chip, achieving precise single-pixel-level driving and constructing an active driving architecture. This scheme fundamentally abandons the traditional passive scanning method, resolving issues such as image ghosting and inter-pixel crosstalk that exist when passive driving structures are applied to micro-pitch display products. Simultaneously, independent pixel control significantly improves brightness, color, and dynamic display performance, resulting in clearer and smoother images and a substantial enhancement in overall display quality and visual experience.

[0006] In some embodiments of this application, the serial data signal input terminals of the active matrix driver chips in each row of the active driver array are connected in parallel, and the clock signal input terminals of the active matrix driver chips in each column are connected in parallel.

[0007] In some embodiments of this application, the serial data signal input terminals of each column of the active matrix driver chip in the active driver array are connected in parallel, and the clock signal input terminals of each row of the active matrix driver chip are connected in parallel.

[0008] Through the two embodiments described above, the serial data signal and clock signal of the active matrix driver chip can be separately controlled. The display control module only needs to adjust the clock signal and serial data signal of the driver chip in the same row or column to achieve individual control of different chips in that row or column; while reducing the overall wiring, it can independently drive each active matrix driver chip. In addition, by synchronously controlling the row and column signals, the circuit board wiring can be further simplified, reducing the complexity of the display system and the hardware cost.

[0009] In some embodiments of this application, the display control module sends control signals to each of the active matrix driver chips in the driver chip array, including: The display control module sequentially sends control signals to each simultaneous clock active matrix driver chipset; The simultaneous clock active matrix driver chip group consists of all the active matrix driver chips connected in parallel at their clock signal input terminals.

[0010] This embodiment achieves individual drive control for each active matrix driver chip in the driver chip array by sending different serial data signals through different serial data signal lines to different active matrix driver chips controlled by the same clock signal. This effectively improves the control accuracy of pixel brightness and color and avoids mutual interference between pixels. Simultaneously, the sequential control of active matrix driver chip groups with different clocks effectively prevents the transmitted serial data signals from affecting active matrix driver chips in other rows or columns, further improving the stability of the display and enhancing the visual experience.

[0011] In some embodiments of this application, the display control module includes a data parsing and processing unit, a clock group control unit and a data group control unit respectively connected to the data parsing and processing unit, and the clock group control unit is also connected to the data group control unit; The data parsing and processing unit is used to parse and process the input display data to obtain a clock control signal and a display data control signal, and sends the clock control signal to the clock group control unit and the display data control signal to the data group control unit. The data group control unit is used to send a clock synchronization signal to the clock group control unit based on the display data control signal, and to send a serial data signal to the active matrix driver chip in the active driver array; The clock group control unit is used to send clock signals to the active drive array based on the clock control signal and the clock synchronization signal.

[0012] By setting up clock group control units and data group control units, the clock signal and serial data signal of the active matrix driver chip can be independently controlled, ensuring that the two types of signals do not interfere with each other. Simultaneously, a data parsing and processing unit is included, enabling the display control module to perform display data parsing and processing capabilities, effectively improving the practicality of the display driver module.

[0013] In some embodiments of this application, the data parsing and processing unit includes a protocol parsing subunit, an image data caching subunit, and a data processing subunit, which are respectively connected to the protocol parsing subunit. The image data caching subunit is also connected to the data processing subunit. The protocol parsing subunit is used to parse the input display data to obtain parameter configuration information and the original image dataset. The parameter configuration information includes clock control signals and frame switching signals. The image data caching subunit is used to cache the original image data in the original image dataset; The data processing subunit is used to read and process the original image data from the image data buffer subunit after receiving the frame switching signal, so as to obtain the display data control signal.

[0014] In this embodiment, the protocol parsing subunit can separate parameter configuration information from the original image data and accurately extract control signals such as clock frame switching; the image data caching subunit can ensure the stability of the data source and avoid display abnormalities caused by transmission fluctuations; the data processing subunit reads and processes the data synchronously according to the frame switching signal, so that the processing timing is consistent with the display refresh.

[0015] In some embodiments of this application, each of the active matrix driver chips independently controls a pixel on the display panel.

[0016] Through the above settings, this embodiment can achieve precise and independent driving of individual pixels, effectively improving the control accuracy of pixel brightness and color, and avoiding mutual interference between pixels.

[0017] In some embodiments of this application, the display control module is further configured to transmit the display data to other display driver modules cascaded with this display driver module.

[0018] The above configuration enables the display driver module to have cascading expansion capabilities, achieving unified driving of large-size, multi-area display panels while reducing the number of control interfaces and wiring, simplifying the system architecture, improving the scalability and integration of the display system, and reducing overall hardware costs and control complexity.

[0019] A second aspect of this application provides a display driving device, including a driving array composed of a plurality of display driving modules, wherein the display driving modules are as described above, and the display driving modules in each row or column of the driving array are cascaded sequentially.

[0020] This embodiment uses the above-mentioned display driver module to form a display driver device, which can be adapted to micro-pitch display product applications and significantly improves image stability and display uniformity.

[0021] A third aspect of this application provides a display system including a display driving device as described above and a display panel driven by the display driving device.

[0022] It is understood that the beneficial effects of the third aspect mentioned above can be found in the relevant descriptions of the first and second aspects mentioned above, and will not be repeated here.

[0023] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 The diagram shown is a simplified structural schematic of the display driver module described in an embodiment of this application.

[0025] Figure 2 The diagram shown is a schematic of an active drive array connection for a display driver module as described in an embodiment of this application.

[0026] Figure 3 This is a schematic diagram of another active drive array connection for the display driver module described in an embodiment of this application.

[0027] Figure 4 The diagram shown is a specific structural schematic of the display driver module described in an embodiment of this application.

[0028] Figure 5The diagram shown is another specific structural schematic of the display driver module described in the embodiments of this application.

[0029] Figure 6 The diagram shown is a signal transmission timing diagram of the display control module in the display driver module described in this application embodiment.

[0030] Figure 7 The diagram shown is a structural schematic of the display driver device described in an embodiment of this application.

[0031] Figure 8 The diagram shown is a structural schematic of the display system described in an embodiment of this application.

[0032] Specific element symbol explanations: 1-Display driver module, 11-Driver chip array, 111-Active matrix driver chip, 12-Display control module, 121-Data parsing and processing unit, 1211-Protocol parsing subunit, 1212-Image data buffer subunit, 1213-Data processing subunit, 122-Clock group control unit, 123-Data group control unit, 10-Display driver device, 20-Display system, 30-Display panel. Detailed Implementation

[0033] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0034] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0036] With the rapid growth of the ultra-high-definition display market, the demand for LED direct-view display products with smaller pixel pitch and higher display quality is becoming increasingly urgent. Traditional commercial LED displays generally adopt a passive driving architecture of "row transistors + column constant current driver chips". However, in the micro-pitch stage where pixel pitch is below P1.0 mm, the traditional passive driving architecture has shown many insurmountable bottlenecks. For example, in terms of display performance, passive scanning is prone to problems such as ghosting and signal coupling. Open or short circuits in LEDs or circuits can also cause the "caterpillar effect", directly affecting image contrast, uniformity, and product reliability.

[0037] In addition to the aforementioned issues, applying traditional passive driving architectures to micro-pitch display products presents challenges in PCB design and cost. The exponential increase in the number of LEDs in micro-pitch displays leads to a surge in driver chip usage and highly complex wiring. Traditional COB solutions, due to their dense wiring, numerous board layers, and complex manufacturing processes, remain costly and fail to meet market demands. Furthermore, traditional PWM driving methods place extremely stringent requirements on LED performance: while the average current per LED is relatively low, the instantaneous peak current is significantly increased, placing higher demands on the current carrying capacity and lifespan of Micro LEDs. For example, in a 32-line scan solution, a peak current of 16mA is required when the average current is 500μA, further driving up LED costs.

[0038] Based on this, this application improves the display driving module, display driving device, and display system in the related technologies. The display driving module of this application can be applied to micro-pitch LED display products, as well as other adaptable display products, and this application does not impose any fixed limitations on it.

[0039] refer to Figure 1 As shown, the display driver module 1 in this embodiment includes a driver chip array 11 and a display control module 12; the driver chip array 11 and the display control module 12 are interconnected.

[0040] The driver chip array 11 includes an active driver array composed of multiple active matrix driver chips 111 (AMIC). The driver chip array 11 may also include other types of driver chips, which are not fixed in this application.

[0041] The display control module 12 is mainly used to send control signals to the driver chip array 11 based on the input display data. The specific control signals include clock signals and serial data signals. The display data can be video image data, image data, or other display data to be displayed; this application does not impose any fixed limitations on it. Specifically, the display control module 12 sends control signals to each active matrix driver chip 111 in the driver chip array 11 according to the input display data, thereby enabling the display control module 12 to independently control each active matrix driver chip 111 in the driver chip array 11, and ultimately enabling the driver chip array 11 to drive the corresponding display panel 30 for display.

[0042] To further improve the display effect, in this embodiment, each active matrix driver chip 111 in the driver chip array 11 independently controls one pixel on the display panel 30 it drives. This setting enables the driver chip array 11 to accurately and independently drive a single pixel, effectively improving the control accuracy of pixel brightness and color, and avoiding mutual interference between pixels.

[0043] This embodiment uses an active matrix driver chip 111 as the display driver chip, which can drive each pixel individually. The display control module 12 independently controls each active matrix driver chip 111 in the array, thereby building an active driving architecture. This driving architecture abandons the traditional passive scanning method in principle, and fundamentally solves the problems of image ghosting and inter-pixel crosstalk that exist in passive driving. At the same time, independent pixel control can significantly improve brightness, color and dynamic display effects, making the picture clearer and smoother, and greatly improving the overall display quality and visual experience.

[0044] In one embodiment, reference is made to Figure 2 As shown, assuming the active drive array is an M*N column array (M and N are both positive integers), to reduce the overall wiring count, this embodiment sets the serial data signal input terminals of the active matrix driver chips 111 in each row of the active drive array to be connected in parallel, and the clock signal input terminals of the active matrix driver chips 111 in each column to be connected in parallel. This design also has other advantages, which will not be listed here.

[0045] Furthermore, at this time, the M serial data signal output terminals of the display control module 12 are respectively connected to the M rows of serial data signal input lines of the active drive array (i.e., the connection lines that connect the serial data signal input terminals of each row of active matrix drive chips 111 in parallel), so that the M serial data signal output terminals of the display control module 12 provide serial data signals (DIN) to the M rows of active matrix drive chips 111 respectively. More specifically, a certain serial data signal output terminal of the display control module 12 provides the same serial data signal to the N active matrix drive chips 111 connected to it. Simultaneously, the N serial data signal output terminals of the display control module 12 are respectively connected to the N rows of clock signal input lines of the active drive array (i.e., the connection lines that connect the clock signal input terminals of each column of active matrix drive chips 111 in parallel), so that the N serial data signal output terminals of the display control module 12 provide clock signals (DCLK) for the N columns of active matrix drive chips 111 respectively. That is, a certain clock signal output terminal of the display control module 12 provides the same clock signal for the M active matrix drive chips 111 connected to it.

[0046] In one specific embodiment, the clock signal output type includes a high-level signal and a low-level signal. For example, the high-level signal can be set to 3.8V, and the low-level signal can be set to 2.8V. To adapt to non-powered carrier schemes, the low-level signal can also be set to 0V. The values ​​of the high-level and low-level signals mentioned above can be set based on actual conditions; the above is merely a specific example.

[0047] It should be noted that the active matrix driver chip 111 only performs its driving function when it simultaneously receives both a clock signal and a serial data signal. Therefore, the display control module 12 primarily achieves individual control of each active matrix driver chip 111 in the active driver array through the coordinated control of the clock signal on the input clock signal line and the serial data signal on the input serial data signal line. For example, when the display control module 12 sends a serial data signal 'a' to all active matrix driver chips 111 in row A via the serial data signal line of row A, and simultaneously sends a clock signal 'b' to all active matrix driver chips 111 in column B via the clock signal line of column B, only the active matrix driver chip 111 in row a and column b of the active driver array receives both the clock signal and the serial data signal simultaneously. Therefore, only the active matrix driver chip 111 in row a and column b of the active driver array performs its driving function at this time. This process can be repeated to achieve individual driving of each active matrix driver chip 111 in the active driver array by the display control module 12. Here, A, B, a, and b are all positive integers.

[0048] In one embodiment, reference is made to Figure 3As shown, in this embodiment, the serial data signal input terminals of each column of active matrix driver chips 111 in the active driver array can be connected in parallel, and the clock signal input terminals of each row of active matrix driver chips 111 can be connected in parallel. The working principle of this embodiment is similar to that of the previous embodiment, so it can be understood by referring to the previous embodiment, and will not be described in detail here.

[0049] In one embodiment, reference is made to Figure 4 As shown, the display control module 12 specifically includes a data parsing and processing unit 121, a clock group control unit 122, and a data group control unit 123. The data parsing and processing unit 121 is connected to both the clock group control unit 122 and the data group control unit 123. Furthermore, to facilitate the transmission of clock synchronization signals between the clock group control unit 122 and the data group control unit 123, the clock group control unit 122 and the data group control unit 123 are also interconnected.

[0050] Furthermore, the data parsing and processing unit 121 is mainly used to parse and process the input display data to obtain the clock control signal and the display data control signal. Then, the data parsing and processing unit 121 sends the clock control signal to the clock group control unit 122, so that the clock group control unit 122 can send a clock signal to the active matrix driver chip 111 in the active driver array based on the clock control signal. Simultaneously, the data parsing and processing unit 121 also sends the display data control signal to the data group control unit 123, so that the data group control unit 123 can send a serial data signal to the active matrix driver chip 111 in the active driver array based on the display data control signal.

[0051] Further, refer to Figure 5 As shown, the data parsing and processing unit 121 may specifically include a protocol parsing subunit 1211, an image data buffering subunit 1212, and a data processing subunit 1213. The protocol parsing subunit 1211 is connected to the image data buffering subunit 1212 and the data processing subunit 1213, respectively, and the image data buffering subunit 1212 is also connected to the data processing subunit 1213.

[0052] The protocol parsing subunit 1211 is mainly used to receive input display data and parse the display data according to a preset instruction format to obtain parameter configuration information and the original image dataset. The preset instruction format is an existing video image parsing format. Further parameter configuration information includes clock control signals and frame switching signals. The parameter configuration information may also include other parameter data such as those related to image algorithm processing; no fixed restrictions are imposed on these. The original image dataset includes at least one frame of original image data.

[0053] After obtaining the parameter configuration information and the original image dataset, the protocol parsing subunit 1211 also needs to send the clock control signal in the parameter configuration information to the clock group control unit 122; and transmit the original image data in the original image dataset to the image data caching subunit 1212 in sequence, so that the image data caching subunit 1212 can cache the original image data in the original image dataset in sequence according to the caching requirements.

[0054] The image data caching subunit 1212 is used to cache the raw image data sent by the protocol parsing subunit 1211, so that the data processing subunit 1213 can read the raw image data under the control of the frame switching signal. The data processing subunit 1213 is mainly used to read the raw image data from the raw image caching unit after receiving the frame switching signal, and to process the read raw image data to obtain the display data control signal. In a specific embodiment, the processing of the read raw image data by the data processing subunit 1213 may include GAMMA conversion and data correction. It should be noted that the data processing subunit 1213 can also process the read raw image data using other image processing algorithms; this application does not impose fixed limitations on these algorithms.

[0055] The data group control unit 123 is mainly used to send clock synchronization signals to the clock group control unit 122 based on the display data control signals, and simultaneously send serial data signals to the active matrix driver chip 111 in the active driver array. The purpose of the data group control unit 123 sending the clock synchronization signal to the clock group control unit 122 is to enable the data group control unit 123 and the clock group control unit 122 to synchronously send serial data signals and clock signals to the active matrix driver chip 111 in the active driver array, thereby realizing the drive control of the active matrix driver chip 111.

[0056] The clock control unit 122 is used to send clock signals to the active drive array when it receives clock control signals and clock synchronization signals.

[0057] It should be noted that the serial data signal sent by the data group control unit 123 and the clock signal sent by the clock group control unit 122 must both be set to communication protocol signals that can be recognized by the active matrix driver chip 111.

[0058] In one embodiment, the display driving module 1 controls the active driving array in the following way: the display control module 12 sequentially sends control signals to each group of simultaneous clock active matrix driving chips 111; wherein the group of simultaneous clock active matrix driving chips 111 consists of all active matrix driving chips 111 connected in parallel to each other at their clock signal input terminals. For example, for... Figure 2The active drive array shown can be driven by a display drive module 1, which can first send clock signals and corresponding serial data signals to all active matrix drive chips 111 in the first column (or simultaneously send the corresponding serial data signals to all active matrix drive chips 111 in the active drive array). Since only the active matrix drive chips 111 in the first column receive the clock signals, it can also achieve the effect of driving and controlling only the active matrix drive chips 111 in the first column. Figure 6 As shown), at this time, all active matrix driver chips 111 in the first column can realize drive control; then, clock signals and corresponding serial data signals are sent to all active matrix driver chips 111 in the second column, and so on, until clock signals and corresponding serial data signals are sent to all active matrix driver chips 111 in the Nth column, thus realizing the display control of a frame of image data by the display panel 30.

[0059] This method enables simultaneous and individual control of multiple active matrix driver chips 111 in the driver chip array 11, improving control efficiency. At the same time, the individual driving control of the active matrix driver chips 111 effectively improves the control accuracy of pixel brightness and color, avoiding mutual interference between pixels. Furthermore, the sequential control of active matrix driver chip groups 111 at different times can effectively avoid the influence of the transmitted serial data signals on active matrix driver chips 111 in other rows or columns, further improving the stability of the display and enhancing the visual experience.

[0060] In one embodiment, to flexibly expand the size of the display driver device 10, the display driver module 1 can also be configured to support cascading. Specifically, after receiving display data, the display control module 12 of the display driver module 1 also synchronously transmits the display data to other display driver modules 1 cascaded with the current display driver module 1. Through this design, large-size, multi-zone display panels 30 can be uniformly driven, effectively reducing the number of control interfaces and wiring complexity, optimizing the overall system architecture, enhancing the scalability and integration of the display system 20, and simultaneously reducing hardware costs and control logic complexity.

[0061] This embodiment employs an active matrix driver chip layout (111), with the display control module (12) independently controlling each chip to achieve precise single-pixel-level driving, forming an active driving architecture. This solution abandons the traditional passive scanning mode, fundamentally solving problems such as image ghosting and pixel crosstalk that exist when passive driving structures are applied to micro-pitch display products. It improves image stability and display uniformity, while optimizing brightness, color, and dynamic display effects, significantly improving display quality and visual experience. The display control module (12) only needs to adjust the clock and serial data signals of the row and column chips to achieve individual chip control. Combined with row and column signal synchronous control, it can greatly simplify wiring, reduce system complexity and hardware costs, and has lower requirements for LED performance, making it easier to implement in engineering and control costs.

[0062] refer to Figure 7 As shown, further, in order to better implement the display driving module 1 in any of the above embodiments, based on the above display driving module 1, this application embodiment also provides a display driving device 10. The display driving device 10 includes a driving array composed of a plurality of display driving modules 1. The display driving module 1 is as described above, and the display driving modules 1 in each row or column of the driving array are cascaded in sequence.

[0063] refer to Figure 8 As shown, in order to better implement the display driver device 10 in any of the above embodiments, based on the above display driver device 10, this application embodiment also provides a display system 20, which includes the display driver device 10 as described above and a display panel 30 driven by the display driver device 10.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0065] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0066] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0067] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0068] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display driver module, characterized in that, This includes an interconnected array of driver chips and a display control module; The driving chip array includes an active driving array composed of multiple active matrix driving chips. The display control module is used to send control signals to each of the active matrix driver chips in the driver chip array according to the input display data, so as to realize independent control of each of the active matrix driver chips.

2. The display driver module according to claim 1, characterized in that, The serial data signal input terminals of the active matrix driver chips in each row of the active driver array are connected in parallel, and the clock signal input terminals of the active matrix driver chips in each column are connected in parallel.

3. The display driver module according to claim 1, characterized in that, The serial data signal input terminals of each column of the active matrix driver chip in the active driver array are connected in parallel, and the clock signal input terminals of each row of the active matrix driver chip are connected in parallel.

4. The display driver module according to claim 2 or 3, characterized in that, The display control module sends control signals to each of the active matrix driver chips in the driver chip array, including: The display control module sequentially sends control signals to each simultaneous clock active matrix driver chipset; The simultaneous clock active matrix driver chip group consists of all the active matrix driver chips connected in parallel at their clock signal input terminals.

5. The display driver module according to claim 1, characterized in that, The display control module includes a data parsing and processing unit, a clock group control unit and a data group control unit respectively connected to the data parsing and processing unit, and the clock group control unit is also connected to the data group control unit. The data parsing and processing unit is used to parse and process the input display data to obtain a clock control signal and a display data control signal, and sends the clock control signal to the clock group control unit and the display data control signal to the data group control unit. The data group control unit is used to send a clock synchronization signal to the clock group control unit based on the display data control signal, and to send a serial data signal to the active matrix driver chip in the active driver array; The clock group control unit is used to send clock signals to the active drive array based on the clock control signal and the clock synchronization signal.

6. The display driver module according to claim 5, characterized in that, The data parsing and processing unit includes a protocol parsing subunit, an image data caching subunit, and a data processing subunit, which are respectively connected to the protocol parsing subunit. The image data caching subunit is also connected to the data processing subunit. The protocol parsing subunit is used to parse the input display data to obtain parameter configuration information and the original image dataset. The parameter configuration information includes clock control signals and frame switching signals. The image data caching subunit is used to cache the original image data in the original image dataset; The data processing subunit is used to read and process the original image data from the image data buffer subunit after receiving the frame switching signal, so as to obtain the display data control signal.

7. The display driver module according to claim 1, characterized in that, Each of the active matrix driver chips independently controls a pixel on the display panel.

8. The display driver module according to claim 1, characterized in that, The display control module is also used to transmit the display data to other display driver modules cascaded with this display driver module.

9. A display driving device, characterized in that, The display driving module comprises a driving array consisting of multiple display driving modules, wherein the display driving module is the display driving module according to any one of claims 1-8, and the display driving modules in each row or column of the driving array are cascaded sequentially.

10. A display system, characterized in that, It includes the display driving device as described in claim 9 and the display panel driven by the display driving device.

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