Memory device

Abstract

A memory device includes a plurality of memory dies that share a channel. Each of the plurality of memory dies includes a monitoring pad, and the monitoring pad is connected to a monitoring line. The plurality of memory dies are configured to alternately occupy the monitoring line and output a current monitoring signal including a peak value of a consumed current to the monitoring line. The current monitoring signal output to the monitoring line by a first memory die of the plurality of memory dies is transmitted to the remaining memory dies of the plurality of memory dies. Each of the remaining memory dies is configured to stop a control operation when a peak value of a consumption current of the first memory die is equal to or greater than a predetermined reference value.

Description

Technical Field

[0001] This disclosure relates to memory devices. Background Technology

[0002] Memory devices can provide the functions of storing and erasing data, retrieving stored data, and transferring data to external devices. A memory device may include multiple memory dies packaged together, and some of the memory dies may share a channel for communication with external memory controllers, etc. When the current consumption in one of the memory dies sharing the channel increases excessively, the power consumption of the memory device may exceed the effective power range that the power circuit supplying power to the memory device can provide. Therefore, the performance of the memory device and / or the system including the memory device may degrade, and unexpected failures, data loss, etc., may occur. Summary of the Invention

[0003] One aspect of this disclosure is to provide a memory device that can suppress potential problems when the power consumption of the memory device exceeds the effective power range by allowing the memory dies of a shared channel to share the peak current consumption.

[0004] According to one aspect of this disclosure, a memory device includes: a first memory die, the first memory die including a first monitoring pad and first current monitoring logic, the first monitoring pad being connected to a monitoring line, and the first current monitoring logic outputting a first current monitoring signal to the first monitoring pad; and a second memory die, the second memory die including a second monitoring pad and second current monitoring logic, the second monitoring pad being connected to the monitoring line, and the second current monitoring logic outputting a second current monitoring signal to the second monitoring pad, wherein the first current monitoring signal includes N bits (where N is a natural number equal to or greater than 2) of first current data encoding the peak value of the current consumed by the first memory die, and the second current monitoring signal includes N bits of second current data encoding the peak value of the current consumed by the second memory die, the first current monitoring logic and the second current monitoring logic alternately occupying the monitoring line, and the first current monitoring logic using the second current monitoring signal output to the monitoring line to recover a first clock signal, and the second current monitoring logic using the first current monitoring signal output to the monitoring line to recover a second clock signal.

[0005] According to one aspect of this disclosure, a memory device includes: a package substrate; and a plurality of memory dies mounted on the package substrate and configured to share a channel, wherein each of the plurality of memory dies includes a monitoring pad electrically isolated from the channel, wherein the monitoring pad is connected to a monitoring line, and the plurality of memory dies, while alternately occupying the monitoring line, output a current monitoring signal to the monitoring line including current data encoding peak values ​​of consumed current.

[0006] According to one aspect of this disclosure, a memory device includes: a plurality of memory dies configured to share a channel, wherein each of the plurality of memory dies includes a monitoring pad connected to a monitoring line, wherein the plurality of memory dies alternately occupy the monitoring line and output a current monitoring signal including a peak value of consumed current to the monitoring line, wherein the current monitoring signal output to the monitoring line by one of the plurality of memory dies is transmitted to the remaining memory dies, and wherein each of the remaining memory dies stops control operation when the peak value of consumed current of the one memory die is equal to or greater than a predetermined reference value. Attached Figure Description

[0007] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 It is simply a view showing the memory device according to its implementation.

[0008] Figure 2 and Figure 3 It is a simple block diagram showing a system including a memory device according to the implementation method.

[0009] Figure 4 and Figure 5 This is a view illustrating the operation of a memory die included in a memory device according to a specific implementation.

[0010] Figure 6 It is a block diagram that simply illustrates a memory device according to its implementation.

[0011] Figures 7 to 9 This is a view showing the operation of a memory device according to its implementation.

[0012] Figures 10 to 12 This is a view showing the operation of a memory device according to its implementation.

[0013] Figure 13This is a view showing the operation of a memory device according to its implementation.

[0014] Figure 14 This is a view showing the operation of a memory device according to its implementation.

[0015] Figure 15 and Figure 16 This is a view showing the operation of a memory device according to its implementation.

[0016] Figure 17 and Figure 18 This is a view showing the operation of a memory device according to its implementation. Detailed Implementation

[0017] In the following description, a preferred implementation will be presented with reference to the accompanying drawings.

[0018] Figure 1 It is simply a view showing the memory device according to its implementation.

[0019] refer to Figure 1 The memory device 10, depending on the implementation, may include a plurality of memory dies 11 to 18 and a package substrate 20. The plurality of memory dies 11 to 18 may be mounted on the upper surface of the package substrate 20 in a stacked structure, and a plurality of solder balls 22 may be formed on the lower surface of the package substrate 20. A protective layer 21 covering the plurality of memory dies 11 to 18 may be formed on the upper surface of the package substrate 20.

[0020] exist Figure 1 In the illustrated implementation, multiple memory dies 11 to 18 can be stacked to form a stepped shape in one direction. First memory dies 11 to fourth memory dies 14 can be stacked to form a stepped shape in the first direction, and fifth memory dies 15 to eighth memory dies 18 can be stacked to form a stepped shape in the opposite direction to the first direction. First memory dies 11 to fourth memory dies 14 can be connected to pads 23 exposed on the upper surface of the package substrate 20 via a first wiring W1, and fifth memory dies 15 to eighth memory dies 18 can be connected to pads 24 exposed on the upper surface of the package substrate 20 via a second wiring W2.

[0021] The stacked structure of multiple memory dies 11 to 18 is not limited to, for example Figure 1 As shown. For example, multiple memory dies 11 to 18 can be stacked vertically and electrically connected to the package substrate 20 via a through-silicon via structure penetrating at least a portion of the multiple memory dies 11 to 18. In the structure of the above implementation, the memory device 10 may not include wirings W1 and W2.

[0022] exist Figure 1 In the implementation shown, the first memory die 11 to the fourth memory die 14 can share the first channel, and the fifth memory die 15 to the eighth memory die 18 can share the second channel. The first channel and the second channel can respectively include signal paths for transmitting command signals, address signals, data signals, chip enable signals, write / read enable signals, etc.

[0023] The first to fourth memory dies 11, sharing the first channel, can monitor each other's peak current consumption via monitoring lines. Similarly, the fifth to eighth memory dies 15, sharing the second channel, can also monitor each other's peak current consumption via monitoring lines. These monitoring lines can be electrically isolated from the first and second channels, and also electrically isolated from the solder balls 22 formed on the lower surface of the package substrate 20.

[0024] For example, the first memory die 11 to the fourth memory die 14 can alternately and sequentially output the peak value of the current consumption through the monitoring line. When the first memory die 11 outputs the peak value of the current consumption, the second memory die 12 to the fourth memory die 14 can monitor the peak value of the current consumption of the first memory die 11 and control whether to perform a control operation, the timing of the control operation, etc.

[0025] For example, when a high-current operation is performed on each of two or more memory dies from the first memory die 11 to the fourth memory die 14, the power consumption of the memory device 10 may exceed the effective range of power that the power circuit can supply to the memory device 10. In this case, phenomena such as performance degradation of the memory device 10 and / or the system including the memory device 10, or temporary suspension of operation may occur.

[0026] In this implementation, such phenomena can be effectively suppressed by each of the memory dies 11 to 18 sharing a single channel monitoring the peak current consumption of each other. For example, when a control operation (such as a programming or erasing operation) that consumes a relatively large amount of current may be performed in the first memory die 11, the second to fourth memory dies 12 can temporarily suspend the control operation, and then resume the control operation by referring to the peak current consumption of the first memory die 11. Therefore, the power consumption of the memory device 10 can be managed so that the power circuit does not exceed the effective range of power that can be supplied to the memory device 10.

[0027] In this implementation, the memory dies 11 to 18 sharing the channel can monitor each other's peak current consumption via a monitoring line without a separate clock signal. Therefore, separate clock lines for mutual monitoring and sharing of peak current consumption are unnecessary, and each of the memory dies 11 to 18 can simply monitor the current consumption of the other memory dies by adding a pad connected to the monitoring line to each of the memory dies 11 to 18.

[0028] Figure 2 and Figure 3 It is a simple block diagram showing a system including a memory device according to the implementation method.

[0029] First, refer to Figure 2 System 30, depending on its implementation, may include a memory controller 40 and a memory device 50. The memory device 50 may include multiple memory dies 51 to 58, and the memory controller 40 may be connected to the multiple memory dies 51 to 58 via multiple channels CH1 and CH2. Figure 2 In the implementation shown, the memory controller 40 can be connected to the first memory die 51 to the fourth memory die 54 via the first channel CH1, and can be connected to the fifth memory die 55 to the eighth memory die 58 via the second channel CH2.

[0030] The first channel CH1 and the second channel CH2 can each include multiple signal paths for transmitting signals. For example, the first channel CH1 and the second channel CH2 can each include multiple signal paths for transmitting chip enable signals, write / read enable signals, data signals, data strobe signals, command signals, address signals, etc.

[0031] In this implementation, each of the plurality of memory dies 51 to 58 may include current monitoring logic for monitoring the current consumption of the other memory dies 51 to 58. For example, the first memory die 51 to the fourth memory die 54 sharing the first channel CH1 may each be commonly connected to a monitoring line and may each output the peak value of the current consumption alternately and sequentially through the monitoring line. For example, the peak value of the current consumption output to the monitoring line by each of the first memory die 51 to the fourth memory die 54 may be monitored by the other memory dies 51 to 54. For example, the first memory die 51 to the third memory die 53 may monitor the peak value of the current consumption output to the monitoring line by the fourth memory die 54.

[0032] Each of the memory dies 51 to 58 can stop and / or postpone the execution of a control operation by referring to the result of monitoring the peak value of the current consumption. For example, when the peak value of the current consumption output from the fourth memory die 54 to the monitoring line is greater than a predetermined reference value, each of the first memory dies 51 to the third memory die 53 can stop and / or postpone the execution of a control operation. Therefore, the total power consumption of the memory device 50 can be controlled within a range that does not exceed the maximum allowable power consumption.

[0033] refer to Figure 3 Depending on the implementation, system 100 may include a memory controller 110 and a memory die 120. The memory die 120 may be as described above (referring to...). Figure 2 The described memory device 50 includes one of a plurality of memory dies 51 to 58. Memory die 120 may include cell region 121, peripheral circuit region 123, memory interface circuitry 125, current monitoring logic 127, etc. Memory interface circuitry 125 may be connected to controller interface circuitry 115 of memory controller 110.

[0034] The memory interface circuit 125 can receive chip enable signal nCE, write enable signal nWE, read enable signal nRE, command latch enable signal CLE, address latch enable signal ALE, and data strobe signal DQS from the controller interface circuit 115 via multiple pads. The peripheral circuit region 123 of the memory die 120 can control the control region 121 in response to command / address signals CMD / ADDR included in signals received from the memory controller 110. For example, the peripheral circuit region 123 can store data DATA received as a data signal DQ in the cell region 121, or read data DATA stored in the cell region 121.

[0035] The current monitoring logic 127 of the memory die 120 can detect and output the peak value of the current consumed by the memory die 120. For example, the current monitoring logic 127 can output a current monitoring signal CMS to a monitoring line, which includes the peak value of the current consumption determined according to the control operation performed by the peripheral circuit region 123. For example, the current monitoring logic 127 can encode the peak value of the current consumption into N-bit current data (where N is a natural number equal to or greater than 2) and can output a current monitoring signal CMS including this current data to the monitoring line.

[0036] Using the current monitoring signal (CMS) output by memory die 120, the peak current consumed by other memory dies can be monitored within memory die 120. Similarly, memory die 120 can monitor the peak current consumed by each other memory die based on the current monitoring signal (CMS) output by each other memory die.

[0037] For example, during programming and erasing operations on the memory die 120, the peripheral circuit region 123 can apply a relatively large voltage to the cell region 121, and the current consumption of the memory die 120 increases. Therefore, when programming and erasing operations are performed simultaneously on memory dies connected to the same channel as the memory controller 110, the power consumption of the memory device, including the memory die 120, may exceed the allowable range. When the peak current consumed by another memory die is equal to or exceeds a predetermined reference value, the memory die 120 can temporarily suspend or postpone the control operation performed by the peripheral circuit region 123, thereby managing the power consumption of the memory device so that it does not exceed the allowable range.

[0038] Figure 4 and Figure 5 This is a view illustrating the operation of a memory die included in a memory device according to a specific implementation.

[0039] First, refer to Figure 4 The memory device 200, depending on its implementation, may include a plurality of memory dies 210 to 240. Figure 4 In the implementation shown, multiple memory dies 210 to 240 can be connected to the memory controller via channels and can be commonly connected to the monitoring line ML.

[0040] Multiple memory dies 210 to 240 can sequentially occupy monitoring line ML and can output current monitoring signals CMS1 to CMS4 to monitoring line ML. (Reference) Figure 5 The current monitoring signals CMS1 to CMS4 of each of the multiple memory dies 210 to 240 can be alternately and sequentially output to the monitoring line ML.

[0041] For example, the first memory die 210 can occupy the monitoring line M1 during a first time period while outputting a first current monitoring signal CMS1, and the second memory die 220 can occupy the monitoring line ML during a second time period after the first time period while outputting a second current monitoring signal CMS2. The third memory die 230 can occupy the monitoring line ML during a third time period after the second time period while outputting a third current monitoring signal CMS3, and the fourth memory die 240 can occupy the monitoring line ML during a fourth time period after the third time period while outputting a fourth current monitoring signal CMS4.

[0042] Multiple memory dies 210 to 240 can output current monitoring signals CMS1 to CMS4 to monitoring line ML while changing transmit / receive modes. For example, the first memory die 210 can operate in transmit mode and output a first current monitoring signal CMS1 to monitoring line ML. After the last bit of the first current monitoring signal CMS1 is output to monitoring line ML and before the first bit of the second current monitoring signal CMS2 is output to monitoring line ML, the first memory die 210 can switch from transmit mode to receive mode, and the second memory die 220 can switch from receive mode to transmit mode.

[0043] During the first time period, the second memory die 220 to the fourth memory die 240 can receive the first current monitoring signal CMS1. During the second time period, the first memory die 210, the third memory die 230, and the fourth memory die 240 can receive the second current monitoring signal CMS2. During the third time period, the first memory die 210, the second memory die 220, and the fourth memory die 240 can receive the third current monitoring signal CMS3. During the fourth time period, the first memory die 210 to the third memory die 230 can receive the fourth current monitoring signal CMS4.

[0044] The second memory die 220 to the fourth memory die 240 can detect the first peak value of the current consumed by the first memory die 210 with reference to the first current monitoring signal CMS1, and can temporarily suspend the execution of the control operation when the first peak value is equal to or greater than a predetermined reference value. The first memory die 210, the third memory die 230 and the fourth memory die 240 can detect the second peak value of the current consumed by the second memory die 220 with reference to the second current monitoring signal CMS2, and can temporarily suspend the execution of the control operation when the second peak value is equal to or greater than a predetermined reference value.

[0045] The first memory die 210, the second memory die 220, and the fourth memory die 240 can detect the third peak value of the current consumed by the third memory die 230 with reference to the third current monitoring signal CMS3, and can temporarily suspend the execution of the control operation when the third peak value is equal to or greater than a predetermined reference value. The first memory die 210 to the third memory die 230 can detect the fourth peak value of the current consumed by the fourth memory die 240 with reference to the fourth current monitoring signal CMS4, and can temporarily suspend the execution of the control operation when the fourth peak value is equal to or greater than a predetermined reference value.

[0046] Depending on the implementation, when the sum of the peak currents equals or exceeds a reference value, each of the multiple memory dies 210 to 240 can temporarily suspend the execution of control operations. For example, each of the first memory die 210 to the third memory die 230 can detect the fourth peak current consumed by the fourth memory die 240 by referring to the fourth current monitoring signal CMS4. When the sum of the internally calculated peak current consumption and the fourth peak current equals or exceeds the reference value, each of the first memory die 210 to the third memory die 230 can temporarily suspend the execution of control operations.

[0047] In this manner, each of the plurality of memory dies 210 to 240 can adjust the execution time of the control operation with reference to the peak current consumed by the other memory dies. Therefore, the power consumption of the memory device 200 is limited to within the allowable range specified in a predetermined specification, and the operational stability of the memory device 200 can be improved, while power consumption can be reduced.

[0048] like Figure 4 As shown, in this implementation, multiple memory dies 210 to 240 can output only current monitoring signals CMS1 to CMS4 to the monitoring line ML without a separate clock signal. Therefore, when implementing the current monitoring function among multiple memory dies 210 to 240 sharing a channel, only one monitoring pad can be added to each of the multiple memory dies 210 to 240.

[0049] For example, each of the plurality of memory dies 210 to 240 may include a clock recovery circuit for recovering clock signals from the output to the monitoring lines ML current monitoring signals CMS1 to CMS4. Each of the plurality of memory dies 210 to 240 may use the recovered clock signal to obtain the peak value of the current consumption included in the current monitoring signals CMS1 to CMS4.

[0050] Figure 6 It is a block diagram that simply illustrates a memory device according to its implementation.

[0051] refer to Figure 6 The memory die 300, depending on the implementation, may include a cell region 310, a row decoder 320, a page buffer circuit 330, a memory interface circuit 340, current monitoring logic 350, control logic 360, etc. The cell region 310 may include memory cells arranged in a cell array. Memory cells can be connected to the row decoder 320 via word lines, common source lines, ground select lines, and serial select lines, and can be connected to the page buffer circuit 330 via bit lines.

[0052] The memory interface circuit 340 can transmit data read from memory cells by the page buffer circuit 330 to the outside, or it can transmit data received from the outside to the page buffer circuit 330. The current monitoring logic 350 can monitor the peak current consumed by another memory die by using current data output from another memory die that shares the same channel as the memory die 300. The row decoder 320, page buffer circuit 330, memory interface circuit 340, and current monitoring logic 350 can be controlled by control logic 360.

[0053] In its implementation, the current monitoring logic 350 may include a clock recovery circuit 351, a current data input / output circuit 353, etc. The current data input / output circuit 353 may output a current monitoring signal to the monitoring line ML or receive a current monitoring signal from the monitoring line ML. The clock recovery circuit 351 may use the current monitoring signal received from the monitoring line ML to recover the clock signal.

[0054] Therefore, memory die 300 and other memory dies sharing the same channel with it can send and receive current monitoring signals to and from the monitoring line ML without a separate clock signal. Adding only one monitoring pad to memory die 300 to share the peak current consumption would be sufficient and would minimize the area increase of memory die 300.

[0055] The current monitoring logic 350 can output a current monitoring signal, including the peak value of the current consumed by the memory die 300, in response to the control of the control logic 360. The current monitoring logic 350 can receive a current monitoring signal from another memory die and transmit the received current monitoring signal to the control logic 360. When the peak value of the current consumed by the other memory die exceeds a reference value, the control logic 360 can temporarily suspend the control operations performed on the memory cells by the row decoder 320 and the page buffer circuit 330. Therefore, the power consumption of the memory device, including memory dies sharing the same channel as the memory die 300, can be controlled to not exceed an allowable range, and the stable operation of the memory device and the system including the memory device can be ensured.

[0056] Figures 7 to 9 This is a view showing the operation of a memory device according to its implementation.

[0057] Figure 7 This can be a view showing current monitoring signals CMS1 to CMS4 output by memory dies included in the memory device and sharing the same channel. As described above with reference to other implementations, the memory dies sharing the channel can be commonly connected to the monitoring line and can alternately output current monitoring signals CMS1 to CMS4 to the monitoring line.

[0058] exist Figure 7 In the illustrated implementation, the first to fourth memory dies included in the memory device can be commonly connected to a monitoring line. The first memory die can output a first current monitoring signal CMS1, the second memory die can output a second current monitoring signal CMS2, the third memory die can output a third current monitoring signal CMS3, and the fourth memory die can output a fourth current monitoring signal CMS4. Therefore, as Figure 7 As shown, the first current monitoring signal CMS1 to the fourth current monitoring signal CMS4 can be output in an alternating manner.

[0059] The first current monitoring signal CMS1 to the fourth current monitoring signal CMS4 can be return-to-zero (RZ) signals. (Reference) Figure 7 The first current monitoring signal CMS1 to the fourth current monitoring signal CMS4 can return to the first voltage V1 every cycle (TP1 to TP4), which can be used as a reference voltage.

[0060] Each of the first to fourth memory dies can encode the peak current consumption into N-bit current data. Each of the first to fourth memory dies can occupy the monitoring line for a period corresponding to N cycles (TP1 to TP4), and can output 1 bit of the N-bit current data in each of the N cycles (TP1 to TP4). Figure 7 In the implementation shown, each of the first to fourth memory dies can output 4 bits of current data to the monitoring line within four cycles (TP1 to TP4), with 1 bit per cycle. The number of bits of the current data can be changed depending on the implementation.

[0061] The minimum voltage of the current monitoring signals CMS1 to CMS4 can be a first voltage V1, and the maximum voltage can be a second voltage V2. In each of the four cycles (TP1 to TP4) during which 4-bit current data is output to the monitoring line, the current monitoring signals CMS1 to CMS4 can oscillate between the first voltage V1 and the second voltage V2, or between the first voltage V1 and a third voltage V3. The third voltage V3 can be an intermediate voltage that is less than the second voltage V2 and greater than the first voltage V1.

[0062] exist Figure 7 In the implementation shown, the current monitoring logic of the memory die can output logic "1" data by outputting current monitoring signals CMS1 to CMS4, which swing between the first voltage V1 and the second voltage V2, during one cycle. Alternatively, the current monitoring logic can output logic "0" data by outputting current monitoring signals CMS1 to CMS4, which swing between the first voltage V1 and the third voltage V3, during one cycle.

[0063] For example, the first current monitoring signal CMS1 can oscillate between a first voltage V1 and a second voltage V2 during each of the first cycle TP1, the third cycle TP3, and the fourth cycle TP4 in four cycles (TP1 to TP4), and can oscillate between the first voltage V1 and the third voltage V3 during the second cycle TP2. The first current monitoring logic included in the first memory die can output first current data

[1011] encoding the peak value of the current consumed by the first memory die as the first current monitoring signal CMS1.

[0064] Similarly, the second current monitoring logic of the second memory die can output second current data

[0110] encoded with the peak value of the current consumed by the second memory die as the second current monitoring signal CMS2, and the third current monitoring logic of the third memory die can output third current data

[0010] encoded with the peak value of the current consumed by the third memory die as the third current monitoring signal CMS3. The fourth current monitoring logic of the fourth memory die can output fourth current data

[1001] encoded with the peak value of the current consumed by the fourth memory die as the fourth current monitoring signal CMS4. Figure 7 As shown, it is understandable that during the time period of the output current monitoring signals CMS1 to CMS4 of the first to fourth memory dies, the peak current consumption in the first and fourth memory dies may be relatively large.

[0065] Each of the first to fourth memory dies can monitor the peak current consumed by the other memory dies by referring to current monitoring signals CMS1 to CMS4, and determine whether to perform / stop a control operation based on it. For example, assuming that the first current data included in the first current monitoring signal CMS1 output by the first memory die can be greater than a predetermined reference value, each of the second to fourth memory dies can temporarily stop performing control operations such as programming, erasing, and reading operations. Therefore, while the first memory die consumes a large amount of current, the current consumption of the other second to fourth memory dies can be reduced, and the power consumption of the memory device including the first to fourth memory dies can be limited to an acceptable range.

[0066] exist Figure 7 In the implementation shown, both logic "1" and logic "0" can be expressed as a voltage level greater than the first voltage V1. The current monitoring logic included in each of the first to fourth memory dies can recover the clock signal from the current monitoring signals CMS1 to CMS4 received through the monitoring line, and can use the recovered clock signal to decode the current data encoded as current monitoring signals CMS1 to CMS4.

[0067] Figure 8 It can be an enlarged view of the first current monitoring signal CMS1, and Figure 9 This could be a magnified view of the second current monitoring signal, CMS2. Figure 8 In the implementation shown, while the first current monitoring logic of the first memory die occupies the monitoring line and outputs the first current monitoring signal CMS1, the current monitoring logic of each of the second to fourth memory dies can receive the first current monitoring signal CMS1.

[0068] The current monitoring logic of each of the second to fourth memory dies can determine the clock cycle TCLK required to recover the clock signal by counting the time between a first rising edge of the first current monitoring signal CMS1 corresponding to the time point of the first cycle TP1 and a second rising edge of the first current monitoring signal CMS1 corresponding to the time point of the second cycle TP2. The current monitoring logic of each of the second to fourth memory dies can generate a clock signal with a clock cycle TCLK, and can decode the first current data

[1011] by comparing the first current monitoring signal CMS1 with a predetermined reference voltage at each time point synchronized with the clock signal. For example, the reference voltage used to decode the first current data by comparing the first current monitoring signal CMS1 with the rising and / or falling edge of the clock signal can be less than the second voltage V2 and greater than the third voltage V3.

[0069] exist Figure 9 In the implementation shown, while the second current monitoring logic of the second memory die occupies the monitoring line and outputs the second current monitoring signal CMS2, the current monitoring logic of each of the first memory die, the third memory die, and the fourth memory die can receive the second current monitoring signal CMS2.

[0070] The current monitoring logic of each of the first, third, and fourth memory dies can determine the clock period TCLK required to recover the clock signal by counting the time between the first rising edge of the first current monitoring signal CMS1 corresponding to the time point of the first cycle TP1 and the second rising edge of the first current monitoring signal CMS1 corresponding to the time point of the second cycle TP2. Since logic "0" corresponds to a third voltage V3 greater than the first voltage V1 and logic "1" corresponds to a second voltage V2 greater than the first voltage V1, the current monitoring logic can determine the clock period TCLK regardless of whether the bit transmitted in each of the first cycle TP1 and the second cycle TP2 is logic "0" or logic "1". The current monitoring logic of each of the first, third, and fourth memory dies can decode the second current data

[0110] by comparing the second current monitoring signal (CD2) with the reference voltage in sync with the recovered clock signal.

[0071] Figures 10 to 12 This is a view showing the operation of a memory device according to its implementation.

[0072] In this implementation, the memory die can generate and output current monitoring signals CMS1 to CMS4 as pulse amplitude modulation (PAM)-N signals, respectively. (Refer to...) Figures 10 to 12 In the described implementation, the current monitoring signals CMS1 to CMS4 can be generated as PAM-4 signals, and depending on the implementation, N in the PAM-N signal can be determined to be a value different from 4.

[0073] Figure 10 This can be a view showing the current monitoring signals CMS1 to CMS4 output from a memory die included in the memory device and sharing the same channel. Figure 10 In the implementation shown, the first to fourth memory dies included in the memory device can alternately output current monitoring signals CMS1 to CMS4 to the monitoring line.

[0074] refer to Figure 10 The current monitoring signals CMS1 to CMS4 can oscillate between a first voltage V1, which can be the minimum voltage, and a second voltage V2, which can be the maximum voltage. The first to fourth memory dies can simultaneously output the current monitoring signals CMS1 to CMS4 while occupying the monitoring line in two cycles TP1 and TP2, respectively. In the first cycle TP1 of the two cycles TP1 and TP2, a reference signal can be output, while in the second cycle TP2, a valid signal representing the current data can be output.

[0075] The reference signal may be a signal that does not include current data generated by each of the first to fourth memory dies, and may be an RZ signal regardless of whether the current data oscillates between the first voltage V1 and the second voltage V2. The valid signal may be a signal that includes current data generated by each of the first to fourth memory dies. Figure 10 In the implementation shown, each of the first to fourth memory dies can generate and output a multi-level signal as an effective signal using pulse amplitude modulation (PAM)-4.

[0076] Each of the first to fourth memory dies can output current monitoring signals CMS1 to CMS4 corresponding to 2-bit current data during the second cycle TP2 of the occupied monitoring line. The current monitoring logic of each of the first to fourth memory dies can encode the peak value of the consumed current to generate 2-bit current data, and can output current monitoring signals CMS1 to CMS4, which can be multi-level signals that match the 2-bit current data with one of the first voltage V1 to the fourth voltage V4.

[0077] The first current monitoring logic of the first memory die can output first current data

[10] encoding the peak value of the current consumed in the second cycle TP2 during the time the monitoring line is occupied as the first current monitoring signal CMS1. The second current monitoring logic of the second memory die can output second current data

[11] as the second current monitoring signal CMS2, and the third current monitoring logic of the third memory die can output third current data

[01] as the third current monitoring signal CMS3. The fourth current monitoring logic of the fourth memory die can output fourth current data

[00] as the fourth current monitoring signal CMS4.

[0078] Each of the first to fourth memory dies can monitor the peak current consumed by the other memory dies by referring to current monitoring signals CMS1 to CMS4, and can determine whether to perform / stop control operations based on the current monitoring signals. For example, when one of the first to fourth memory dies outputs a current monitoring signal including current data

[11] to the monitoring line, the other memory dies can stop performing control operations. Figure 10 In the implementation shown, while the second memory die first occupies the monitoring line, it outputs a second current monitoring signal including the second current data

[11] , and the first, third, and fourth memory dies can stop performing control operations. In addition, since the fourth memory die second occupies the second monitoring line and outputs a fourth current monitoring signal including the fourth current data

[11] , the first to third memory dies can stop performing control operations in this case.

[0079] exist Figure 10In the illustrated implementation, each of the first to fourth memory dies may include a clock recovery circuit, which can recover the clock signal from current monitoring signals CMS1 to CMS4. For example, the clock recovery circuit can use a reference signal that swings between a first voltage V1 and a second voltage V2 during the first cycle TP1 to recover the clock signal.

[0080] Figure 11 It can be shown Figure 10 The illustrated implementation shows enlarged views of the current monitoring signals CMS1 and CMS4 output to the monitoring line during the time the fourth memory die occupies the monitoring line and subsequently during the time the first memory die occupies the monitoring line. The clock period TCLK of the clock signal to be recovered for each of the first to fourth memory dies can be equal to the first period TP1.

[0081] like Figure 11 As shown, when the current data is

[00] , because the effective signal output in the second cycle TP2 can be maintained at the first voltage, it may be difficult to recover the clock cycle TCLK using only the reference signal of the first cycle TP1, such as... Figure 11 As shown. In this case, the memory die can recover the clock cycle TCLK by counting the time interval TDET between consecutive first cycles TP1.

[0082] refer to Figure 12 The current monitoring signals CMS1 to CMS4 can oscillate between a first voltage V1, which can be the minimum voltage, and a second voltage V2, which can be the maximum voltage. The first to fourth memory dies can simultaneously output current monitoring signals CMS1 to CMS4 while occupying the monitoring line during three cycles TP1 to TP3. During the first cycle TP1 of the three cycles TP1 to TP3 for outputting current monitoring signals CMS1 to CMS4, a reference signal can be output, while during the second cycle TP2 and the third cycle TP3, valid signals representing current data can be output. For example, the reference signal and the valid signal can each have a 50% duty cycle.

[0083] The reference signal does not include current data generated by each of the first through fourth memory dies, and can be a signal that swings between a first voltage V1 and a second voltage V2, regardless of the current data. The valid signal can include current data generated by each of the first through fourth memory dies.

[0084] Each of the first to fourth memory dies can output current monitoring signals CMS1 to CMS4, corresponding to the 4-bit current data, as multi-level signals during the second cycle TP2 and the third cycle TP3 of the occupied monitoring lines. For example, the high 2 bits of the 4-bit current data can be output during the second cycle TP2 of the current monitoring signals CMS1 to CMS4, and the remaining low 2 bits can be output during the third cycle TP3. Depending on the implementation, the low 2 bits of the 4-bit current data can be output during the second cycle TP2 of the current monitoring signals CMS1 to CMS4, and the remaining high 2 bits can be output during the third cycle TP3.

[0085] The first current monitoring signal CMS1, output by the first current monitoring logic of the first memory die, can oscillate between the first voltage V1 and the fourth voltage V4 during the second cycle TP2, and can oscillate between the first voltage V1 and the second voltage V2 during the third cycle TP3. Therefore, the first current data

[1011] can be output as the first current monitoring signal CMS1. The second current monitoring signal CMS2 can oscillate between the first voltage V1 and the second voltage V2 during the second cycle TP2, and can oscillate between the first voltage V1 and the third voltage V3 during the third cycle TP3. Therefore, the second current data

[1101] can be output as the second current monitoring signal CMS2.

[0086] The third current monitoring signal CMS3 can remain at the first voltage V1 during the second cycle TP2 and can oscillate between the first voltage V1 and the second voltage V2 during the third cycle TP3. Therefore, the third current data

[0011] can be output as the third current monitoring signal CMS3. The fourth current monitoring signal CMS4 can oscillate between the first voltage V1 and the second voltage V2 during the second cycle TP2 and can oscillate between the first voltage V1 and the fourth voltage V4 during the third cycle TP3. Therefore, the fourth current data

[1110] can be output as the fourth current monitoring signal CMS4.

[0087] Figure 13 and Figure 14 This is a view showing the operation of a memory device according to its implementation.

[0088] Figure 13 and Figure 14This can be a view showing current monitoring signals CMS1 to CMS4 output by memory dies included in the memory device and connected to the memory controller via channels as monitoring lines. Each memory die may include monitoring pads electrically isolated from the memory controller, and the monitoring pads may be connected to monitoring lines. The memory dies may occupy the monitoring lines alternately in sequence. Each memory die may alternately output current monitoring signals CMS1 to CMS4 to the monitoring lines, including current data encoding the peak value of the consumed current.

[0089] exist Figure 13 and Figure 14 In each of the implementations shown, the current monitoring logic of the corresponding first to fourth memory dies can encode the peak current consumption into N-bit current data. Each of the first to fourth memory dies can occupy the monitoring line while outputting current monitoring signals CMS1 to CMS4 for a period corresponding to N+1 cycles (TP1 to TP4).

[0090] refer to Figure 13 The current monitoring logic of each of the first to fourth memory dies can output current monitoring signals CMS1 to CMS4, comprising 3 bits of current data, during four cycles (TP1 to TP4). For example, the current monitoring logic can output a reference signal that swings between a first voltage V1 and a second voltage V2 during the first cycle TP1. The reference signal may not be a signal generated from the current data, but may be a signal provided to enable the current monitoring logic of each other memory die to recover the clock signal.

[0091] The current monitoring logic for each of the first to fourth memory dies can output one bit of the 3-bit current data during the second cycle TP2 to the fourth cycle TP4. Figure 13 In the implementation shown, data with logic "0" can be output as a signal that swings between the first voltage V1 and the third voltage V3, and data with logic "1" can be output as a signal that swings between the first voltage V1 and the fourth voltage V4.

[0092] exist Figure 13In the implementation shown, both logic "0" and logic "1" can be matched with signals that swing to a voltage level greater than the first voltage V1. The current monitoring logic included in each of the first to fourth memory dies can recover the clock signal from the current monitoring signals CMS1 to CMS4 received through the monitoring lines, and can extract current data from the current monitoring signals CMS1 to CMS4 using the recovered clock signal. In this implementation, the current monitoring logic can determine the clock period of the clock signal by counting the time from the rising edge of the reference signal output in each first cycle TP1 to the rising edge of the valid signal output in the second cycle TP2.

[0093] refer to Figure 14 The corresponding current monitoring logic for the first to fourth memory dies can output current monitoring signals CMS1 to CMS4, including 3 bits of current data, within four cycles (TP1 to TP4). For example, the current monitoring logic can output a reference signal that swings between a first voltage V1 and a second voltage V2 during the first cycle TP1. The current monitoring logic can output one bit of the 3-bit current data encoding the peak value of the consumed current during the second cycle TP2 to the fourth cycle TP4. Figure 14 In the implementation shown, data with logic "0" can be matched with the first voltage V1, while data with logic "1" can be matched with the second voltage V2.

[0094] Figure 15 and Figure 16 This is a view showing the operation of a memory device according to its implementation.

[0095] First, refer to Figure 15 According to the implementation, the operation of the memory device can begin with the output of a first current monitoring signal from a first memory die to a monitoring line (S10). The first current monitoring signal can be output by first current monitoring logic of the first memory die, and the first memory die may include a first monitoring pad connected to the monitoring line. The first current monitoring logic can output the first current monitoring signal while occupying the monitoring line for a predetermined first time.

[0096] The second memory die can receive a first current monitoring signal via a monitoring line (S11). For example, the second current monitoring logic of the second memory die can receive the first current monitoring signal via the monitoring line during a first time period when the first current monitoring logic occupies the monitoring line, and can use the first current monitoring signal to recover a second clock signal (S12). The second clock signal can be a clock signal generated by the clock recovery circuit of the second current monitoring logic using the first current monitoring signal, and the second current monitoring logic can use the second clock signal to detect the peak value of the current consumed by the first memory die encoded with the first current monitoring signal (S13).

[0097] The second current monitoring logic can determine whether the peak value of the current consumed by the first memory die detected in S13 is equal to or greater than a reference value (S14). The reference value applied in S14 can be a value stored during the manufacture of the memory die or during the manufacture of the memory device that packages the memory die. Alternatively, depending on the implementation, the reference value applied in S14 can be determined together with the memory die by a memory controller, power management integrated circuit (PMIC), etc., included in a memory device such as a solid-state drive (SSD), or the reference value can be determined by a host communicating with the memory device. When the peak value is equal to or greater than the reference value as the determination result in S14, the second memory die can stop the control operation within a predetermined reference time (S15). The control operation can be at least one of a programming operation, an erasing operation, or a reading operation.

[0098] Subsequently, the second memory die can determine whether the reference time has elapsed (S16), and when it is determined that the reference time has elapsed, it can perform a control operation (S17). When the peak value is less than the reference value as the determination result in S14, the second memory die can perform a control operation (S17).

[0099] Reference Figure 15 In the described implementation, when the peak current consumption of the first memory die is equal to or greater than a reference value, the second memory die, connected to the memory controller via the same channel as the first memory die, can stop performing control operations within a predetermined reference time. This can be a control method that takes into account the characteristic that the peak current consumption occurs within a very short time. By adding the current consumption of the second memory die to the channel during the period when the current consumption of the first memory die has a peak, it is possible to prevent the power consumption of the memory device from exceeding the allowable range.

[0100] Figure 16 This could be a graph showing the current consumption of the first memory die over time. Figure 16 In the implementation shown, during the first time period T1, the current consumption of the first memory die can have a very small first peak value CP1. Therefore, during the first time period T1, the second memory die sharing the channel with the first memory die can perform control operations without interruption.

[0101] During the second time period T2, the current consumption of the first memory die increases to a second peak value CP2, which is higher than the reference value REF. Therefore, the second memory die can temporarily suspend the execution of control operations during the second time period T2 by referring to a first current monitoring signal that includes current data encoded with the second peak value CP2. When the second time period T2 elapses, the second memory die can resume control operations.

[0102] During the third time period T3, the current consumption of the first memory die also increases to a third peak CP3, which is higher than the reference value REF. Therefore, the second memory die can stop performing control operations during the third time period T3 and can perform control operations after the third time period T3 has elapsed. During the fourth time period T4, because the current consumption of the first memory die has a fourth peak CP4, which is lower than the reference value REF, the second memory die can perform control operations without interruption.

[0103] Figure 17 and Figure 18 This is a view showing the operation of a memory device according to its implementation.

[0104] refer to Figure 17 According to the implementation, the operation of the memory device can begin with the output of a first current monitoring signal from a first memory die to a monitoring line (S20). The first current monitoring signal can be output by first current monitoring logic of the first memory die, and the first memory die may include a first monitoring pad connected to the monitoring line. The first current monitoring logic can output the first current monitoring signal while occupying the monitoring line for a predetermined first time.

[0105] The second memory die can receive a first current monitoring signal via a monitoring line (S21). For example, the second current monitoring logic of the second memory die can receive the first current monitoring signal via the monitoring line during a first time period when the first current monitoring logic occupies the monitoring line, and can use the first current monitoring signal to recover a second clock signal (S22). The second clock signal can be a clock signal generated by the clock recovery circuit of the second current monitoring logic using the first current monitoring signal, and the second current monitoring logic can use the second clock signal to detect the peak value of the current consumed by the first memory die encoded with the first current monitoring signal (S23).

[0106] The second current monitoring logic can determine whether the peak value of the current consumed by the first memory die detected in S23 is equal to or greater than a reference value (S24). The reference value applied in S24 can be a value stored during the manufacture of the memory die or during the manufacture of the memory device that packages the memory die. When the peak value is equal to or greater than the reference value as the determination result in S24, the second memory die can stop the control operation (S25). The control operation can be at least one of a programming operation, an erasing operation, or a reading operation.

[0107] After the second memory die stops the control operation, the second current monitoring logic can determine whether the peak value of the current consumed by the first memory die has decreased to below a reference value using the first current monitoring signal output to the monitoring line (S26). When it is determined that the peak value of the current consumed by the first memory die extracted from the first current monitoring signal is less than the reference value, the second memory die can perform the control operation (S27). When it is determined, as a result of S26, that the peak value of the current consumed by the first memory die extracted from the first current monitoring signal is greater than the reference value, the second memory die can remain in the state of stopping the control operation.

[0108] Reference Figure 17 In the described implementation, the second memory die can stop performing control operations when the peak current consumption of the first memory die is equal to or greater than a reference value. Subsequently, the second memory die can resume control operations once the peak current consumption of the first memory die is confirmed by a monitoring line to have decreased to below the reference value. Therefore, during the period when the first memory die's current consumption has a peak, the second memory die's current consumption can be prevented from being added to the channel, and the power consumption of the memory device including both the first and second memory dies can be prevented from exceeding the allowable range.

[0109] Figure 18 It could be a graph showing the current consumption of the first memory die over time. Figure 18 The curve can be equivalent to Figure 16 The graph shown.

[0110] refer to Figure 18 The first memory die can output a first current monitoring signal CMS1 to the monitoring line ML at least once during the second time T2. The second time T2 can be the time when the peak value of the current consumed by the first memory die is greater than the reference value REF. Therefore, the current data included in the first current monitoring signal CMS1 can be greater than the reference value REF.

[0111] When the second time interval T2 elapses, the first memory die can output a first current monitoring signal CMS1, which includes current data smaller than the reference value REF. Figure 18 In the implementation shown, the second memory die can resume control operation after confirming through the monitoring line ML that the current data included in the first current monitoring signal CMS1 has become less than the reference value REF.

[0112] According to the implementation, during the second time T2 when the current data of the first current monitoring signal CMS1 is greater than the reference value REF, the first current monitoring signal CMS1 can be repeatedly output through the monitoring line ML. During the second time T2, the second memory die may not output a current monitoring signal to the monitoring line ML, and the first memory die may repeatedly output the first current monitoring signal CMS1 while occupying the monitoring line ML during the second time T2. When the current data included in the first current monitoring signal CMS1 is less than the reference value REF, the first memory die and the second memory die may again alternately occupy the monitoring line ML.

[0113] Depending on the implementation, memory dies sharing a channel can be publicly connected to monitoring lines and can sequentially and repeatedly output peak current consumption values ​​via the monitoring lines without a separate clock signal. Each memory die can monitor the peak current consumption values ​​of other memory dies and can stop or delay the execution of control operations by referencing the peak current consumption value of at least one other memory die. Therefore, the power consumption of the memory device can be controlled within the effective range of the available power and the performance of the memory device can be improved.

[0114] The various advantages and effects of this disclosure are not limited to those described above, and can be more easily understood in the process of explaining the specific implementation.

[0115] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of any claims that may be made. Certain features described in individual implementations of this disclosure can also be implemented in combination within a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually in multiple implementations or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination can be removed from that combination in some cases, and the combination may involve sub-combinations or variations thereof.

Claims

1. A memory device, the memory device comprising: A first memory die, the first memory die including a first monitoring pad and a first current monitoring logic, the first monitoring pad being connected to a monitoring line, the first current monitoring logic being configured to output a first current monitoring signal to the first monitoring pad; as well as A second memory die, comprising a second monitoring pad and second current monitoring logic, wherein the second monitoring pad is connected to the monitoring line, and the second current monitoring logic is configured to output a second current monitoring signal to the second monitoring pad. The first current monitoring signal includes N bits of first current data, which includes the peak value of the current consumed by the first memory die, where N is a natural number equal to or greater than 2. The second current monitoring signal includes N bits of second current data, which includes the peak value of the current consumed by the second memory die. The first current monitoring logic and the second current monitoring logic are configured to alternately occupy the monitoring line, and The first current monitoring logic is configured to use the second current monitoring signal output to the monitoring line to recover the first clock signal, and the second current monitoring logic is configured to use the first current monitoring signal output to the monitoring line to recover the second clock signal.

2. The memory device according to claim 1, wherein, During the period, each of the first current monitoring signal and the second current monitoring signal (i) oscillates between a first voltage and a second voltage greater than the first voltage or (ii) oscillates between the first voltage and at least one intermediate voltage, the at least one intermediate voltage being greater than the first voltage and less than the second voltage.

3. The memory device according to claim 2, wherein, The first current monitoring logic and the second current monitoring logic are configured as follows: The monitoring line is occupied sequentially and repeatedly for N cycles, and Each cycle outputs the N bits one by one in the corresponding N cycles.

4. The memory device according to claim 2, wherein, The first current monitoring logic and the second current monitoring logic are configured to sequentially and repeatedly occupy the monitoring line for N+1 cycles, and Each of the first current monitoring logic and the second current monitoring logic is configured as follows: The reference signal is output in the first cycle of the N+1 cycles, and The output represents the valid signal of the N bits, each of the N bits being in the corresponding period of the remaining N periods in the N+1 periods.

5. The memory device according to claim 4, wherein, The at least one intermediate voltage includes a third voltage and a fourth voltage greater than the third voltage, and The reference signal oscillates between the first voltage and the second voltage during the first period, and Wherein, the effective signal oscillates between the first voltage and the third voltage or between the first voltage and the fourth voltage in each of the remaining N cycles.

6. The memory device according to claim 1, wherein, Each of the first current monitoring signal and the second current monitoring signal is a signal that oscillates between a first voltage and a second voltage greater than the first voltage.

7. The memory device according to claim 6, wherein, The first current monitoring logic and the second current monitoring logic are configured to sequentially and repeatedly occupy the monitoring line for N cycles, and Each of the first current monitoring logic and the second current monitoring logic is configured as follows: The reference signal is output in the first cycle of the N cycles, and In the remaining periods of the N periods, a valid signal representing the N bits is output.

8. The memory device according to claim 7, wherein, The reference signal is a zero-return signal that oscillates between the first voltage and the second voltage, and the effective signal is a multi-level signal that oscillates between the first voltage and the second voltage.

9. The memory device according to claim 6, wherein, The first current monitoring logic and the second current monitoring logic are configured to sequentially and repeatedly occupy the monitoring line for N+1 cycles, and Each of the first current monitoring logic and the second current monitoring logic is configured as follows: The reference signal is output in the first cycle of the N+1 cycles, and The output represents the valid signal of the N bits, each of the N bits being in the corresponding period of the remaining N periods in the N+1 periods.

10. The memory device according to claim 9, wherein, Each of the reference signal and the effective signal is a zero-return signal that oscillates between the first voltage and the second voltage.

11. The memory device according to claim 1, wherein, The first memory die is configured to switch from transmit mode to receive mode before outputting the last bit of the N bits of the first current data to the monitoring line and before outputting the first bit of the N bits of the second current data to the monitoring line. The second memory die is configured to switch from the receive mode to the transmit mode before the last bit of the N bits of the first current data is output to the monitoring line and before the first bit of the N bits of the second current data is output to the monitoring line.

12. A memory device, the memory device comprising: Packaging substrate; as well as Multiple memory dies are mounted on the package substrate and configured to share a channel. Each of the plurality of memory dies includes a monitoring pad electrically isolated from the channel, the monitoring pad being connected to a monitoring line. The plurality of memory dies are configured to output a current monitoring signal, including current data, to the monitoring line, wherein the current data includes the peak value of the current consumption. The plurality of memory dies are configured to alternately occupy the monitoring line.

13. The memory device according to claim 12, wherein, Each of the plurality of memory dies includes current monitoring logic connected to the monitoring pad.

14. The memory device according to claim 13, wherein, The current monitoring signal is a signal with two or more cycles, and The current monitoring logic of each of the plurality of memory dies is configured to output the current monitoring signal to the monitoring line in the two or more cycles.

15. The memory device according to claim 14, wherein, The current monitoring logic of each of the plurality of memory dies is configured to (i) output a reference signal in a first cycle of the two or more cycles, and (ii) output a valid signal including the current data in the remaining cycles after the first cycle of the two or more cycles. The swing range of the reference signal is equal to or greater than the swing range of the effective signal.

16. The memory device according to claim 15, wherein, The effective signal is a pulse amplitude modulated multilevel signal.

17. The memory device according to claim 15, wherein, The current monitoring logic includes a clock recovery circuit configured to recover a clock signal by counting the time interval between the rising edges of adjacent reference signals.

18. The memory device according to claim 12, wherein, The plurality of memory dies are mounted on the first surface of the packaging substrate. The packaging substrate includes a plurality of solder balls on a second surface opposite to the first surface, and The monitoring line is electrically isolated from the plurality of solder balls.

19. A memory device, the memory device comprising: Multiple memory dies configured to share a channel. Each of the plurality of memory dies includes a monitoring pad, and the monitoring pad is connected to a monitoring line. The plurality of memory dies are configured to alternately occupy the monitoring line and output a current monitoring signal including a peak value of the consumed current to the monitoring line. The plurality of memory dies includes a first memory die and the remaining memory dies, and the memory device is configured to transmit the current monitoring signal output by the first memory die to the remaining memory dies among the plurality of memory dies. Each of the remaining memory dies is configured to stop control operation based on the peak value of the current consumed by the first memory die being equal to or greater than a reference value.

20. The memory device according to claim 19, wherein, The control operation includes at least one of a programming operation, an erasing operation, or a reading operation.

Images