Memory device, memory system and operating method thereof

Abstract

The invention provides a memory device, a memory system and an operating method thereof. The memory device includes a first memory die and a die group stacked in a first direction; the tube core group comprises M second memory tube cores which are stacked along the first direction; each second memory die is connected with the third memory die and is configured to perform data interaction of (N * X) bit bandwidth with the third memory die through N data channels; m, N and X are positive integers; the first memory tube core is connected with the third memory tube core, and is configured to perform data interaction of (N * X) bit bandwidth with the third memory tube core through N data channels, and replace the first data channel when a storage part corresponding to the first data channel of the tube core group fails.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and for example to a storage device, a storage system, and a method of operating the same. Background Technology

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a storage device is provided, comprising: a first memory die and a die group stacked along a first direction; the die group includes M second memory dies stacked along the first direction; each second memory die is connected to a third memory die and configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die through N data channels; wherein M, N, and X are all positive integers; the first memory die is connected to the third memory die and is configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die through N data channels, and replace the first data channel when a storage portion corresponding to a first data channel of the die group fails.

[0004] In some alternative embodiments, the storage device includes P groups of the aforementioned dies, and the P groups of dies are stacked along the first direction; the first memory die is configured to replace the first data channel when a storage portion corresponding to the first data channel of any one of the P groups of dies fails, where P is a positive integer.

[0005] In some optional embodiments, the first memory die includes a first hybrid bonding layer, the second memory die includes a second hybrid bonding layer and a third hybrid bonding layer; the first memory die and the second memory die are connected through the first hybrid bonding layer and the second hybrid bonding layer, and two adjacent second memory dies along the first direction are connected to the third hybrid bonding layer through the second hybrid bonding layer.

[0006] In some optional embodiments, the first memory die includes a first bump bonding layer, and the second memory die includes a second bump bonding layer and a third bump bonding layer; the first memory die and the second memory die are connected through the first bump bonding layer and the second bump bonding layer, and two adjacent second memory dies along the first direction are connected to the third bump bonding layer through the second bump bonding layer.

[0007] In some alternative embodiments, the first memory die is located on one side of the P die groups on opposite sides along the first direction.

[0008] In some alternative embodiments, M is 4; P is 2 or 3.

[0009] In some optional embodiments, the structure of the storage portion corresponding to the data channel of the first memory die is the same as the structure of the storage portion corresponding to the data channel of the second memory die.

[0010] In some optional embodiments, both the first memory die and the second memory die include Y memory bank groups; each memory bank group includes multiple memory banks, and each memory bank includes multiple memory blocks; one data channel of the first memory die corresponds to (Y / N) memory bank groups of the first memory die, and one data channel of the second memory die corresponds to (Y / N) memory bank groups of the second memory die; Y is a positive integer, and Y > N.

[0011] According to a second aspect of the present disclosure, a storage system is provided, the storage system including a storage device and a third memory die; the third memory die and the storage device are stacked along a first direction; the storage device includes a first memory die and a die group stacked along the first direction, the die group including M second memory dies stacked along the first direction; each second memory die is connected to the third memory die and configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die through N data channels; where M, N, and X are all positive integers; the first memory die is connected to the third memory die and is configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die through N data channels; and the n data channels of the first memory die and the (M*Nn) data channels of the die group are configured to be able to perform parallel data interaction with the third memory die; where n is an integer, and 0 ≤ n ≤ N.

[0012] In some alternative embodiments, the die assembly is located between the first memory die and the third memory die.

[0013] In some alternative embodiments, the storage device includes P groups of the aforementioned dies stacked along the first direction; the first memory die is configured to replace the first data channel when a storage portion corresponding to the first data channel of any one of the P dies fails; where P is a positive integer.

[0014] In some optional embodiments, the first memory die includes a first hybrid bonding layer, the second memory die includes a second hybrid bonding layer and a third hybrid bonding layer; the first memory die and the second memory die are connected through the first hybrid bonding layer and the second hybrid bonding layer, and two adjacent second memory dies along the first direction are connected to the third hybrid bonding layer through the second hybrid bonding layer.

[0015] In some optional embodiments, the first memory die includes a first bump bonding layer, and the second memory die includes a second bump bonding layer and a third bump bonding layer; the first memory die and the second memory die are connected through the first bump bonding layer and the second bump bonding layer, and two adjacent second memory dies along the first direction are connected to the third bump bonding layer through the second bump bonding layer.

[0016] In some alternative embodiments, M is 4; P is 2 or 3.

[0017] In some optional embodiments, the structure of the storage portion corresponding to the data channel of the first memory die is the same as the structure of the storage portion corresponding to the data channel of the second memory die.

[0018] In some optional embodiments, both the first memory die and the second memory die include Y memory bank groups; each memory bank group includes multiple memory banks, and each memory bank includes multiple memory blocks; one data channel of the first memory die corresponds to (Y / N) memory bank groups of the first memory die, and one data channel of the second memory die corresponds to (Y / N) memory bank groups of the second memory die; Y is a positive integer, and Y > N.

[0019] In some optional embodiments, the storage device includes a first interface, which includes a plurality of first data transmission interfaces, each corresponding to a data channel; the third memory die includes a replacement control signal generation circuit and a selection circuit; the selection circuit includes a signal input terminal and a plurality of data input terminals, the signal input terminal of the selection circuit is connected to the output terminal of the replacement control signal generation circuit, and each data input terminal of the selection circuit is connected to one of the first data transmission interfaces.

[0020] In some optional embodiments, the replacement control signal generation circuit is configured to generate a corresponding replacement control signal based on the address of the data channel corresponding to the faulty memory portion in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die; the selection circuit is configured to replace the data channel corresponding to the faulty memory portion in the second memory die with the data channel in the first memory die based on the corresponding replacement control signal.

[0021] In some optional embodiments, the replacement control signal generation circuit includes: a storage component, a latch circuit, and a decoding circuit; the storage component is connected to the input terminal of the latch circuit, the output terminal of the latch circuit is connected to the first input terminal of the decoding circuit, the second input terminal of the decoding circuit is connected to the signal line of the storage system, and the output terminal of the decoding circuit is connected to the signal input terminal of the selection circuit.

[0022] In some optional embodiments, the storage component is configured to: store the address of the data channel corresponding to the faulty storage portion in the second memory die; the latch circuit is configured to: latch the address of the data channel corresponding to the faulty storage portion in the second memory die after the storage system is powered on; and the decoding circuit is configured to: generate a replacement control signal based on the address of the data channel corresponding to the faulty storage portion in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die.

[0023] In some optional embodiments, the third memory die further includes a second interface; the second interface includes a plurality of second data transmission interfaces; each of the plurality of outputs of the selection circuit is connected to one of the second data transmission interfaces; and the number of the first data transmission interfaces is greater than the number of the second data transmission interfaces.

[0024] According to a third aspect of the present disclosure, a method for operating a storage system is provided, comprising: (M*N) data channels of M second memory dies stacked along a first direction of a die group jointly performing (M*N*X) bit bandwidth data interaction with a third memory die in parallel; wherein M, N, and X are all positive integers; when a storage portion corresponding to n data channels of the die group fails, n data channels of a first memory die stacked along the first direction of the die group are used to replace the n data channels corresponding to the failed storage portion of the die group; wherein n is an integer, and 1≤n≤N; the n data channels of the first memory die and (M*Nn) data channels of the die group jointly perform (M*N*X) bit bandwidth data interaction with the third memory die in parallel.

[0025] In some optional embodiments, when a storage portion corresponding to the n data channels of the die group fails, replacing the n data channels corresponding to the failed storage portion of the die group with n data channels from the first memory dies stacked along the first direction of the die group includes: when a storage portion corresponding to the n data channels of any one of the P die groups stacked along the first direction of the storage system fails, replacing the n data channels of the die group whose storage portion has failed with n data channels from the first memory dies; where P is a positive integer.

[0026] In some alternative embodiments, the die assembly is located between the first memory die and the third memory die.

[0027] In some optional embodiments, when a memory portion corresponding to one of the n data channels of the die group fails, replacing the n data channels corresponding to the failed memory portion of the die group with n data channels from a first memory die stacked along the first direction includes: a replacement control signal generation circuit generating a corresponding replacement control signal based on the address of the data channel corresponding to the failed memory portion in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die; and a selection circuit replacing the data channel corresponding to the failed memory portion in the second memory die with the data channels from the first memory die based on the corresponding replacement control signal.

[0028] In some optional embodiments, the replacement control signal generation circuit generates a corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage portion of the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die. This includes: a storage component storing the address of the data channel corresponding to the faulty storage portion of the second memory die; a latching circuit latching the address of the data channel corresponding to the faulty storage portion of the second memory die after the storage system is powered on; and a decoding circuit generating the corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage portion of the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die.

[0029] In some optional embodiments, the method further includes: the decoding circuit generating a replacement control signal of a first value based on the address of the data channel of the second memory die that currently needs to interact with the third memory die, which is the same as the address of the first data channel corresponding to the faulty memory portion in the second memory die; different first data channels correspond to different first values; or, the decoding circuit generating a replacement control signal of a second value based on the address of the data channel of the second memory die that currently needs to interact with the third memory die, which is different from the address of the first data channel corresponding to the faulty memory portion in the second memory die.

[0030] In some optional embodiments, the method further includes: the selection circuit replacing the first data channel corresponding to the first value with a data channel in the first memory die based on the value of the replacement control signal being the first value.

[0031] In this embodiment, a first memory die is added. When a memory section corresponding to the first data channel of the die group fails, the data channel in the first memory die replaces the first data channel corresponding to the failed memory section. Firstly, this allows the die group to still perform parallel (M*N*X) bit bandwidth data interaction with the third memory die when the memory section corresponding to the first data channel of the die group fails, thereby effectively improving the yield of the memory device. Secondly, the solution provided by this embodiment is a data channel-level replacement, which not only solves the yield loss problem caused by failures in the memory cell array but also solves the yield loss problem caused by failures in peripheral circuits. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0033] Figure 2 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure.

[0034] Figure 3 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.

[0035] Figure 4 A schematic diagram of the composition structure of a storage device provided in an embodiment of this disclosure. Figure 1 .

[0036] Figure 5 A schematic diagram of a data channel for a storage device provided in an embodiment of this disclosure. Figure 1 .

[0037] Figure 6 A schematic diagram of the composition structure of a storage device provided in an embodiment of this disclosure. Figure 2 .

[0038] Figure 7 A schematic diagram of a data channel for a storage device provided in an embodiment of this disclosure. Figure 2 .

[0039] Figure 8a A schematic diagram of the composition structure of a storage device provided in an embodiment of this disclosure. Figure 3 .

[0040] Figure 8b A schematic diagram of the composition structure of a storage device provided in an embodiment of this disclosure. Figure 4 .

[0041] Figure 9 A schematic diagram of the composition structure of a storage device provided in an embodiment of this disclosure. Figure 5 .

[0042] Figure 10a A schematic diagram of the composition structure of a storage system provided in this embodiment of the disclosure. Figure 1 .

[0043] Figure 10b A schematic diagram of the composition structure of a storage system provided in this embodiment of the disclosure. Figure 2 .

[0044] Figure 11 A schematic diagram of the composition structure of a storage system provided in this embodiment of the disclosure. Figure 3 .

[0045] Figure 12 A schematic diagram of the composition structure of a storage system provided in this embodiment of the disclosure. Figure 4 .

[0046] Figure 13A schematic diagram of the structure of a storage system provided in an embodiment of this disclosure. Figure 1 .

[0047] Figure 14 A schematic diagram of the structure of a storage system provided in this embodiment of the disclosure. Figure 2 .

[0048] Figure 15 This is a schematic diagram of a selection circuit provided in an embodiment of the present disclosure.

[0049] Figure 16 This is a schematic diagram of a replacement control signal generation circuit provided in an embodiment of the present disclosure.

[0050] Figure 17 This is a flowchart illustrating an operation method of a storage system provided in an embodiment of the present disclosure. Detailed Implementation

[0051] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0052] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0053] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0054] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] Figure 1 This is a schematic diagram illustrating an electronic device 1 according to an embodiment of the present disclosure. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0057] like Figure 1As shown, electronic device 1 may include a host and electronic system 30, the electronic system 30 having one or more storage systems 20 and a controller 10. The host may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to or receive data from the storage system 20. The controller 10 is coupled to the storage system 20 and the host and is configured to control the storage system 20. The controller 10 may manage the data stored in the storage system 20 and communicate with the host.

[0058] Controller 10 can be configured to control the operation of storage system 20, such as read, erase, write, and refresh operations. In some embodiments, controller 10 is also configured to process error correction codes (ECCs) regarding data read from or written to storage system 20. Controller 10 can also perform any other suitable functions, such as formatting storage system 20.

[0059] In some specific embodiments, the controller 10 and one or more storage systems 20 can be integrated into various types of storage devices. For example, the controller 10 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple storage systems 20 can be integrated into memory modules. In other words, the electronic system 30 can be implemented and packaged into different types of terminal electronic products.

[0060] Controller 10 can send data to or receive data from the host (HOST), and can send commands (CMD) and addresses (ADDR) to the storage system 20. Controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 can receive commands (CMD) and addresses (ADDR) from the host (HOST). The command generator 110 can generate access commands, refresh commands, etc., by decoding the commands (CMD) received from the host (HOST), and can provide access commands and refresh commands to the storage system 20 through the device interface 130. An access command may be a signal instructing the storage system 20 to write or read data by accessing a row of the memory cell array 220 corresponding to address ADDR. A refresh command may be a signal instructing the storage system 20 to read and rewrite data by accessing a row of the memory cell array 220 corresponding to refresh address ADDR.

[0061] The address generator 120 in the controller 10 can generate the row and column addresses to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. Furthermore, the storage system 20 can generate addresses of the memory banks to be accessed when the memory cell array 220 comprises multiple banks.

[0062] The controller 10 can control memory operations such as writing and reading by providing various signals to the storage system 20 via the device interface 130. For example, the controller 10 can provide a write command to the storage system 20. The write command is used to instruct the storage system 20 to perform a write operation to store data in the storage system 20.

[0063] In some embodiments, such as Figure 2 As shown, the storage system 20 includes at least one chip 230, each chip 230 includes at least one bank group 231, each bank group 231 includes at least one bank 232, and each bank 232 includes at least one block 501. It should be noted that... Figure 2 The number of chips 230 in the storage system 20 and the number of memory cells 232 in the memory cell group 231 are merely examples, and this disclosure is not limited thereto.

[0064] In some embodiments, each memory block includes a portion of a memory cell array 220 and a portion of peripheral circuitry 210; the memory cell array includes multiple rows and columns of memory cells, each row of memory cells being coupled to a corresponding word line, and each column of memory cells being coupled to a corresponding bit line. Peripheral circuitry 210 can write data to or read data from memory cell array 220 based on commands CMD and addresses ADDR received from controller 10, or it can provide control signals CTRL to row decoders and column decoders for refreshing the memory cells included in memory cell array 220. In other words, peripheral circuitry 210 can perform all operations to process data in memory cell array 220. Peripheral circuitry 210 may include: control circuitry for each memory block, such as a Sensing Amplifier (SA) and a Word-Line Driver (WLD); control circuitry for each memory bank, such as a row decoder, a column decoder, etc.; and control circuitry for all memory banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0065] The storage system 20 can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following explanation uses DRAM as an example.

[0066] Figure 3 This is a schematic diagram illustrating a dynamic random access memory according to an embodiment of the present disclosure. (Refer to...) Figure 3 As shown, the Dynamic Random Access Memory (DRAM) includes a memory cell array and peripheral circuitry. The memory cell array comprises multiple memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T and a capacitor C. The word line is coupled to the gate of the transistor T, and the bit line is coupled to the drain of the transistor T. The primary operating principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, and the memory cell array uses rows and columns to specify addresses. By specifying the intersection of the rows and columns (by specifying the row and column addresses of the DRAM), the controller can independently access each memory cell in the DRAM chip and perform read, write, or refresh operations on the stored data.

[0067] It should be noted that the embodiments of this disclosure are illustrated by taking a memory cell including a capacitor and a transistor (1T1C) as an example, but this disclosure is not limited to this. The memory cell in this disclosure can also be a capacitorless architecture of nT0C, 1TnC, 2TnC, etc., and this disclosure does not limit it.

[0068] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 The architecture of transistors in memory cells has also evolved from planar array transistors to vertical gate transistors, thus forming the architecture of three-dimensional memory.

[0069] With increasingly demanding requirements for memory integration, three-dimensional stacking of memory chips in the vertical direction can achieve large capacity and high bandwidth. In some embodiments, the stacking method for three-dimensional memory involves stacking and packaging selected chips after testing, i.e., chip-to-chip (D2D) stacking. This method can avoid the failure of the entire three-dimensional memory due to the failure of a single chip. However, D2D stacking and packaging processes are complex and difficult, and new failure modes can easily be introduced during the packaging process. In some embodiments, wafer-to-wafer (W2W) stacking and packaging can be used. This method can greatly simplify the stacking and packaging process. However, because the chips in the wafer are not selected, the overall yield of the three-dimensional memory is prone to decrease due to the failure of a single chip.

[0070] The present disclosure provides the following implementation methods.

[0071] This disclosure provides a storage device, such as... Figure 4 as well as Figure 5 As shown, it includes: a first memory die 401 and a die group 402 stacked along a first direction (Z-axis direction); the die group 402 includes M second memory dies 403 stacked along the first direction (Z-axis direction); each second memory die 403 is connected to a third memory die 404 and is configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die 404 through N data channels; where M, N, and X are all positive integers; the first memory die 401 is connected to the third memory die 404 and is configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die 404 through N data channels, and replace the first data channel when the memory portion corresponding to the first data channel of the die group 402 fails.

[0072] The first direction here can be understood as the Z-axis direction in the accompanying drawings of this disclosure.

[0073] In this embodiment of the disclosure, the die group 402 can also be referred to as a memory rank. Each of the M second memory dies 403 within the die group 402 has N data channels, and the M second memory dies 403 within the die group 402 have a total of (M*N) data channels. Each data channel can interact with the third memory die 404 in a data exchange with a bandwidth of X bits, thus allowing the (M*N) data channels to perform parallel (M*N*X) bit bandwidth data exchange with the third memory die 404. The first memory die 401 has the same number of data channels as the second memory dies 403, and each data channel of the first memory die 401 can transmit the same number of bits of data as each data channel of the second memory die 403.

[0074] In this embodiment of the disclosure, the first data channel of the die group 402 can be understood as any one of the (M*N) data channels of the die group 402.

[0075] In this embodiment, a first memory die 401 is added. When a storage portion corresponding to the first data channel of the die group 402 fails, the data channel in the first memory die 401 replaces the first data channel corresponding to the failed storage portion. Firstly, this ensures that when the storage portion corresponding to the first data channel of the die group 402 fails, the die group 402 can still perform parallel (M*N*X) bit bandwidth data interaction with the third memory die 404, thereby effectively improving the yield of the storage device. Secondly, the solution provided by this embodiment is a data channel-level replacement, which not only solves the yield loss problem caused by failures in the storage cell array but also solves the yield loss problem caused by failures in peripheral circuits.

[0076] In some embodiments, such as Figure 4 As shown, the first memory die 401 is located on one side of the die group 402 along the first direction (Z-axis direction), but this disclosure is not limited thereto. In this embodiment, the first memory die 401 may also be located between two adjacent second memory dies 403 of the die group 402 along the first direction (Z-axis direction).

[0077] In this embodiment of the disclosure, such as Figure 5 As shown, a die group 402 includes four second memory dies 403 (Die0-Die3), each second memory die 403 having four data channels, and Die0 to Die3 comprising a total of 16 data channels (CH0 to CH15). Each data channel can transmit 64 bits of data. This illustrates that the die group 402 can perform parallel data interaction with the third memory die 404, achieving a bandwidth of 1024 bits. However, this embodiment is not limited to this. In this embodiment, as... Figure 5 As shown, the third memory die (Red to Die) includes four data channels (CH-red0 to CH-red3) as an example for illustration, but the embodiments disclosed herein are not limited to this.

[0078] In this embodiment, the second memory die 403 is connected to the third memory die 404, and the first memory die 401 is connected to the third memory die 404. Both the second memory die 403 and the first memory die 401 can be connected to the third memory die 404 through a connection structure extending along a first direction. The material of the connection structure includes a conductive material, which can be one of the following: doped semiconductor material (e.g., doped silicon, doped germanium, etc.), conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), metallic material (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0079] In some embodiments, such as Figure 6 as well as Figure 7 As shown, the storage device includes P sets of the aforementioned dies 402, and the P sets of dies 402 are stacked along the first direction (Z-axis direction); the first memory die 401 is configured to replace the first data channel when the storage portion corresponding to the first data channel of any one of the P sets of dies 402 fails, where P is a positive integer.

[0080] like Figure 6 as well as Figure 7 As shown, the storage device may include multiple die groups 402. These die groups 402 can serially interact with a third memory die 404, and each die group 402 contains M second memory dies 403 that can interact with the third memory die 404 in parallel. When a fault occurs in the storage portion corresponding to the first data channel of any die group 402, the first data channel can be replaced by a data channel from a first memory die 401, thereby enabling the die group 402 to perform parallel (M*N*X) bit bandwidth data interaction with the third memory die 404.

[0081] In some embodiments, M is 4; P is 2 or 3.

[0082] It should be noted that the specific values ​​of M and P listed in the above embodiments are merely examples and are not intended to limit the specific values ​​of M and P in the embodiments of this disclosure. The specific values ​​of M and P can also be set according to actual needs.

[0083] In this embodiment of the disclosure, such as Figure 7As shown, a storage system includes two die groups. One die group 402 includes four second memory dies 403 (Die0 to Die3), and the other die group includes four second memory dies (Die4 to Die7). Each second memory die 403 has four data channels. Die0 to Die3 together include 16 data channels (CH0 to CH15), and Die4 to Die7 together include 16 data channels (CH0 to CH15). Each data channel can transmit 64 bits of data. This illustrates that die group 402 can perform parallel data interaction with the third memory die 404, achieving a bandwidth of 1024 bits. However, this embodiment is not limited to this. In this embodiment, as... Figure 5 As shown, the third memory die (Red to Die) includes four data channels (CH-red0 to CH-red3) as an example for illustration, but the embodiments disclosed herein are not limited to this.

[0084] This embodiment of the disclosure uses a storage device including a first memory die 401 as an example for illustration, but is not limited thereto. In some specific examples, the number of first memory dies 401 can be adjusted accordingly, taking into account factors such as yield and cost, so that the storage device can achieve a high level in both yield and cost savings.

[0085] In this embodiment, the die group 402 and the first memory die 401 are stacked along a first direction, and a plurality of second memory dies 403 of the die group 402 are stacked along the first direction. This saves the area of ​​the storage device and is conducive to the miniaturization trend of storage devices. The first memory die 401 and the second memory die 403 can be stacked along the first direction by bonding.

[0086] In some embodiments, such as Figure 8a As shown, the first memory die 401 includes a first hybrid bonding layer 414, and the second memory die 403 includes a second hybrid bonding layer 415 and a third hybrid bonding layer 416. The first memory die 401 and the second memory die 403 are connected through the first hybrid bonding layer 414 and the second hybrid bonding layer 415. Two adjacent second memory dies 403 along the first direction are connected to the third hybrid bonding layer 416 through the second hybrid bonding layer 415.

[0087] As described in the above embodiments, the first memory die 401 and the second memory die 403 can be stacked along the first direction using a hybrid bonding method. The corresponding hybrid bonding layers may include dielectric layers, and these dielectric layers have corresponding bonding structures. The bonding structures in the connected hybrid bonding layers are interconnected. The materials of these bonding structures include conductive materials, such as tungsten, cobalt, copper, aluminum, nickel, silicides, or any combination thereof.

[0088] In this embodiment, the first memory die 401 and the second memory die 403 can be formed on the same or different wafers and then bonded together by a hybrid bonding method. The hybrid bonding method allows the first memory die 401 and the second memory die 403 to be stacked along the first direction, which can further save the area of ​​the storage device and is conducive to the miniaturization of the storage device.

[0089] In some embodiments, such as Figure 8b As shown, the first memory die 401 includes a first bump bonding layer 417, and the second memory die 403 includes a second bump bonding layer 418 and a third bump bonding layer 419. The first memory die 401 and the second memory die 403 are connected through the first bump bonding layer 417 and the second bump bonding layer 418. Two adjacent second memory dies 403 along the first direction are connected to the third bump bonding layer 419 through the second bump bonding layer 418.

[0090] As described in the above embodiments, the first memory die 401 and the second memory die 403 can also be stacked along the first direction by bump bonding. The corresponding bump bonding layers include bump structures, and the bump structures in the connected bump bonding layers are connected. The material of the bump structures includes conductive materials, such as tungsten, cobalt, copper, aluminum, nickel, silicides, or any combination thereof.

[0091] In this embodiment of the present disclosure, the first memory die 401 and the second memory die 403 can be formed on the same or different wafers and then bonded together by bump bonding. The bump bonding method allows the first memory die 401 and the second memory die 403 to be stacked along the first direction, which can further save the area of ​​the storage device and is conducive to the miniaturization of the storage device.

[0092] In this embodiment, both the first memory die 401 and the second memory die 403 may include a first semiconductor structure and a second semiconductor structure. The first and second semiconductor structures are stacked along a first direction. The first semiconductor structure includes a memory cell array, and the second semiconductor structure includes a first portion of peripheral circuitry. This first portion of peripheral circuitry includes, but is not limited to, a sensing amplifier circuit, a word line driving circuit, a row decoder, and a column decoder. The first and second semiconductor structures of the first memory die 401 or the second memory die 403 may be formed on the same wafer or on different wafers and then bonded together using a hybrid bonding method. The stacking of the first and second semiconductor structures along the first direction further saves the area of ​​the memory device.

[0093] In some embodiments, such as Figure 6 As shown, the first memory die 401 is located on one side of the two opposite sides of the P die groups 402 along the first direction (Z-axis direction).

[0094] In this embodiment of the disclosure, such as Figure 9 As shown, the first memory die 401 may also be located between two adjacent die groups 402 along the first direction (Z-axis direction).

[0095] In other embodiments, the first memory die 401 may also be located between two adjacent second memory dies 403 in the die group 402 along the first direction.

[0096] In some embodiments, the structure of the storage portion corresponding to the data channel of the first memory die 401 is the same as the structure of the storage portion corresponding to the data channel of the second memory die 403.

[0097] In this embodiment of the disclosure, the first memory die 401 and the second memory die 403 are identical in structure except for the connection structure between them and the third memory die 404. The other structures here include the structure of the storage part, which includes the storage cell array and peripheral circuits.

[0098] Here, the structure of the storage section corresponding to the data channel of the first memory die 401 is the same as the structure of the storage section corresponding to the data channel of the second memory die 403. It can be understood that the storage cell array of the first memory die and the storage cell array of the second memory die have the same structure, and the peripheral circuit of the first memory die and the peripheral circuit of the second memory die have the same structure.

[0099] In some embodiments, both the first memory die 401 and the second memory die 403 include Y memory bank groups; each memory bank group includes multiple memory banks, and each memory bank includes multiple memory blocks; one data channel of the first memory die 401 corresponds to (Y / N) memory bank groups of the first memory die 401, and one data channel of the second memory die 403 corresponds to (Y / N) memory bank groups of the second memory die 403; Y is a positive integer, and Y > N.

[0100] In some specific examples, both the first memory die 401 and the second memory die 403 include 16 memory bank groups, and both the first memory die 401 and the second memory die 403 have 4 data channels. One data channel of the first memory die 401 corresponds to the 4 memory bank groups of the first memory die 401, and one data channel of the second memory die 403 corresponds to the 4 memory bank groups of the second memory die 403. However, this disclosure does not limit this.

[0101] Based on a concept similar to the aforementioned storage device, this disclosure also provides a storage system, such as... Figure 10a as well as Figure 5 As shown, the storage system includes a storage device and a third memory die 404; the third memory die 404 and the storage device are stacked along a first direction (Z-axis direction); the storage device includes a first memory die 401 and a die group 402 stacked along the first direction (Z-axis direction), the die group 402 includes M second memory dies 403 stacked along the first direction (Z-axis direction); each second memory die 403 is connected to the third memory die 404 and is configured to be able to communicate with the third memory die 404 through N data channels. The memory die 404 performs data interaction with a bandwidth of (N*X) bits; where M, N, and X are all positive integers; the first memory die 401 is connected to the third memory die 404 and is configured to perform data interaction with the third memory die 404 with a bandwidth of (N*X) bits through N data channels; and the n data channels of the first memory die 401 and the (M*Nn) data channels of the die group 402 are configured to perform data interaction with the third memory die 404 in parallel; where n is an integer and 0≤n≤N.

[0102] In this embodiment, a first memory die 401 is added to the storage system. When a storage portion corresponding to the first data channel of the die group 402 fails, the data channel in the first memory die 401 replaces the first data channel corresponding to the failed storage portion. Firstly, this ensures that when the storage portion corresponding to the first data channel of the die group 402 fails, the die group 402 can still perform parallel (M*N*X) bit bandwidth data interaction with the third memory die 404, thereby effectively improving the yield of the storage device. Secondly, the solution provided by this embodiment is a data channel-level replacement, which not only solves the yield loss problem caused by failures in the storage cell array but also solves the yield loss problem caused by failures in peripheral circuits.

[0103] In the above embodiments, n is an integer, and 0 ≤ n ≤ N. When n equals 0, it means that none of the storage parts corresponding to the data channels of the die group 402 have failed, and there is no need to replace the data channels of the die group 402. When n is greater than 0, it means that among the multiple data channels of the die group 402, there is a data channel whose corresponding storage part has failed, so it is necessary to use n data channels of the die group 402 to replace the corresponding data channel in the storage part that has failed.

[0104] In some embodiments, such as Figure 10b As shown, the die group 402 is located between the first memory die 401 and the third memory die 404.

[0105] It is understandable that the die group 402 is located between the first memory die 401 and the third memory die 404. That is to say, the first memory die is far away from the third memory die, while the die group is close to the third memory die, which can effectively shorten the overall data transmission path.

[0106] In this embodiment of the disclosure, such as Figure 11 As shown, the first memory die 401 may also be located between the die group 402 and the third memory die 404. In other embodiments, such as Figure 12 As shown, the first memory die 401 may also be located between two adjacent die groups 402 along the first direction (Z-axis direction). In some other embodiments, the first memory die 401 may also be located between two adjacent second memory dies 403 of the die group 402 along the first direction (Z-axis direction). This disclosure does not limit this.

[0107] In some embodiments, such as Figure 10b , Figure 11 as well as Figure 12As shown, the storage device includes P sets of dies 402 stacked along the first direction (Z-axis direction). The first memory die 401 is configured to replace the first data channel when the storage portion corresponding to the first data channel of any one of the P sets of dies 402 fails; where P is a positive integer.

[0108] In some embodiments, the first memory die 401 includes a first hybrid bonding layer, and the second memory die 403 includes a second hybrid bonding layer and a third hybrid bonding layer; the first memory die 401 and the second memory die 403 are connected through the first hybrid bonding layer and the second hybrid bonding layer, and two adjacent second memory dies 403 along the first direction are connected to the third hybrid bonding layer through the second hybrid bonding layer.

[0109] In some embodiments, the first memory die 401 includes a first bump bonding layer, and the second memory die 403 includes a second bump bonding layer and a third bump bonding layer; the first memory die 401 and the second memory die 403 are connected through the first bump bonding layer and the second bump bonding layer, and two adjacent second memory dies 403 along the first direction are connected to the third bump bonding layer through the second bump bonding layer.

[0110] In this embodiment of the present disclosure, the die group 402 and the first memory die 401 are stacked along the first direction, and the plurality of second memory dies 403 of the die group 402 are stacked along the first direction. This can save the area of ​​the storage device and is conducive to the miniaturization trend of the storage device.

[0111] In some embodiments, M is 4; P is 2 or 3.

[0112] It should be noted that the specific values ​​of M and P listed in the above embodiments are merely examples and are not intended to limit the specific values ​​of M and P in the embodiments of this disclosure. The specific values ​​of M and P can also be set according to actual needs.

[0113] In some embodiments, the structure of the storage portion corresponding to the data channel of the first memory die 401 is the same as the structure of the storage portion corresponding to the data channel of the second memory die 403.

[0114] In this embodiment of the disclosure, the first memory die 401 and the second memory die 403 are identical in structure except for the connection structure between them and the third memory die 404. The other structures here include the structure of the storage part, which includes the storage cell array and peripheral circuits.

[0115] In some embodiments, both the first memory die 401 and the second memory die 403 include Y memory bank groups; each memory bank group includes multiple memory banks, and each memory bank includes multiple memory blocks; one data channel of the first memory die 401 corresponds to (Y / N) memory bank groups of the first memory die 401, and one data channel of the second memory die 403 corresponds to (Y / N) memory bank groups of the second memory die 403; Y is a positive integer, and Y > N.

[0116] In some specific examples, both the first memory die 401 and the second memory die 403 include 16 memory bank groups, and both the first memory die 401 and the second memory die 403 have 4 data channels. One data channel of the first memory die 401 corresponds to the 4 memory bank groups of the first memory die 401, and one data channel of the second memory die 403 corresponds to the 4 memory bank groups of the second memory die 403. However, this disclosure does not limit this.

[0117] In this embodiment, both the first memory die 401 and the second memory die 403 may include a first semiconductor structure and a second semiconductor structure, which are stacked along a first direction. The first semiconductor structure includes a memory cell array, and the second semiconductor structure includes a first part of peripheral circuitry, which includes, but is not limited to, a sensing amplifier circuit, a word line driving circuit, a row decoder, and a column decoder. The third memory die includes a second part of peripheral circuitry, which includes a test circuit, a second interface, and a replacement control signal generation circuit. The test circuit can be used to perform corresponding tests on the second memory dies stacked along the first direction, the second interface can be used to communicate with a graphics processor and a central processing unit, and the replacement control signal generation circuit can be used to generate corresponding replacement control signals.

[0118] In some embodiments, such as Figure 13 , Figure 14 as well as Figure 15 As shown, the storage device includes a first interface 405, which includes a plurality of first data transmission interfaces 406, each of which corresponds to a data channel; the third memory die 404 includes a replacement control signal generation circuit 407 and a selection circuit 408; the selection circuit 408 includes a signal input terminal and a plurality of data input terminals, the signal input terminal of the selection circuit 408 is connected to the output terminal of the replacement control signal generation circuit 407, and each data input terminal of the selection circuit 408 is connected to one of the first data transmission interfaces 406.

[0119] Here, the first data transmission interface 406 corresponding to the data channels of the selected circuit 408 and the first memory die 401 and the second memory die 403 are all connected.

[0120] In some embodiments, the replacement control signal generation circuit 407 is configured to generate a corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage portion in the second memory die 403 and the address of the data channel of the second memory die 403 that currently needs to interact with the third memory die 404; the selection circuit 408 is configured to replace the data channel corresponding to the faulty storage portion in the second memory die 403 with the data channel in the first memory die 401 based on the corresponding replacement control signal.

[0121] In this embodiment, based on the addition of a first memory die 401, a replacement control signal generation circuit 407 and a selection circuit 408 are added to the third memory die 404, thereby enabling the use of the data channel in the first memory die 401 to replace the data channel corresponding to the faulty storage portion in the second memory die 403 when the data channel in the second memory die 403 fails.

[0122] In some embodiments, such as Figure 16 As shown, the replacement control signal generation circuit 407 includes: a storage component 409, a latch circuit 410, and a decoding circuit 411; the storage component 409 is connected to the input terminal of the latch circuit 410, the output terminal of the latch circuit 410 is connected to the first input terminal of the decoding circuit 411, the second input terminal of the decoding circuit 411 is connected to the signal line of the storage system, and the output terminal of the decoding circuit 411 is connected to the signal input terminal of the selection circuit 408.

[0123] In this embodiment of the disclosure, after testing the storage device, a faulty data channel is found, and the address of the faulty data channel is written into the storage component 409. In some specific examples, the storage component 409 includes an electronic fuse.

[0124] In some embodiments, the storage component 409 is configured to: store the address of the data channel corresponding to the faulty storage portion in the second memory die 403; the latch circuit 410 is configured to: latch the address of the data channel corresponding to the faulty storage portion in the second memory die 403 after the storage system is powered on; and the decoding circuit 411 is configured to: generate a replacement control signal based on the address of the data channel corresponding to the faulty storage portion in the second memory die 403 and the address of the data channel of the second memory die 403 that currently needs to interact with the third memory die 404.

[0125] In some embodiments, the decoding circuit 411 is configured to generate a replacement control signal of a first value based on the address of the data channel of the second memory die 403 that currently needs to interact with the third memory die 404, which is the same as the address of the first data channel corresponding to the faulty storage portion in the second memory die 403; different first data channels correspond to different first values; or, the decoding circuit 411 is configured to generate a replacement control signal of a second value based on the address of the data channel of the second memory die 403 that currently needs to interact with the third memory die 404, which is different from the address of the first data channel corresponding to the faulty storage portion in the second memory die 403.

[0126] In some specific examples, the replacement control signal may include three bits. If the address of the data channel of the second memory die 403 that currently needs to interact with the third memory die 404 is different from the address of the first data channel corresponding to the faulty memory portion in the second memory die 403, the replacement control signal is a second value, specifically "100", which means that no replacement operation is required for the data channel of the second memory die 403 that currently needs to interact with the third memory die 404. If the address of the data channel of the second memory die 403 that currently needs to interact with the third memory die 404 is the same as the address of the first data channel corresponding to the faulty storage portion in the second memory die 403, the replacement control signal is set to a first value. This indicates that a replacement operation needs to be performed on the data channel of the second memory die 403 that currently needs to interact with the third memory die 404. Different first values ​​result in different first data channels being replaced. For example: when the first data channel is data channel 0 (CH0) of Die 0, the first value is "000"; when the first data channel is data channel 4 (CH4) of Die 1, the first value is "001"; when the first data channel is data channel 8 (CH8) of Die 2, the first value is "010"; and when the first data channel is data channel 12 (CH12) of Die 3, the first value is "011". Of course, the specific number of bits in the replacement control signal and the specific values ​​of the first and second values ​​given in the above embodiments are merely examples and are not intended to limit the specific values ​​of the first and second values ​​in this disclosure embodiment. In some specific examples, the number of bits of the replacement control signal can be adjusted according to the number of second memory dies 403 in die group 402 and the number of data channels in each second memory die 403.

[0127] In some embodiments, the selection circuit 408 is configured to replace the first data channel corresponding to the first value with a data channel in the first memory die 401 based on the value of the replacement control signal being the first value.

[0128] When the replacement control signal received by the selection circuit 408 is a first value, the selection circuit 408 replaces the first data channel corresponding to the first value with the data channel in the first memory die 401. When the replacement control signal received by the selection circuit is a second value, the selection circuit 408 does not replace the data channel of the second memory die 403 in the die group 402 that currently needs to interact with the third memory die 404.

[0129] In this embodiment, a first memory die is added. The added first memory die uses a dedicated connection structure to transmit data to a third memory die. A corresponding replacement circuit is designed in the third memory die to achieve different levels of replacement according to different failure degrees. For example, the first memory die replaces a second memory die, or a single data channel is replaced at a random location.

[0130] In some embodiments, such as Figure 14 As shown, the third memory die 404 further includes a second interface 412; the second interface 412 includes a plurality of second data transmission interfaces 413; each of the plurality of output terminals of the selection circuit 408 is connected to one of the second data transmission interfaces 413; and the number of the first data transmission interfaces 406 is greater than the number of the second data transmission interfaces 413.

[0131] In this embodiment, one data channel corresponds to one first data transmission interface 406. Each data input terminal of the selection circuit 408 is connected to one first data transmission interface 406, and each output terminal of the selection circuit 408 is connected to one second data transmission interface 413. The number of data input terminals of the selection circuit 408 is greater than the number of output terminals of the selection circuit 408. Under the replacement control signal, the selection circuit 408 will close the data input terminal of the selection circuit 408 connected to the first data transmission interface 406 corresponding to the data channel of the faulty storage section, and open the data input terminal of the selection circuit 408 connected to the first data transmission interface 406 corresponding to the data channel of the first memory die 401 that replaces the data channel.

[0132] Based on the above storage system, this disclosure also provides an operation method for the storage system, such as... Figure 17 As shown, the operation method of the storage system includes the following steps: M*N data channels of M second memory dies stacked along a first direction in the die group jointly perform (M*N*X) bit bandwidth data interaction with a third memory die in parallel; where M, N, and X are all positive integers; when the storage part corresponding to n data channels of the die group fails, n data channels in the first memory dies stacked along the first direction in the die group are used to replace the n data channels corresponding to the failed storage part of the die group; where n is an integer, and 1≤n≤N; the n data channels of the first memory die and the (M*Nn) data channels of the die group jointly perform (M*N*X) bit bandwidth data interaction with the third memory die in parallel.

[0133] It should be understood that Figure 17 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 17 The steps shown can be adjusted in order according to actual needs.

[0134] In some embodiments, when a storage portion corresponding to the n data channels of the die group fails, replacing the n data channels corresponding to the failed storage portion of the die group with n data channels from a first memory die stacked along the first direction includes: when a storage portion corresponding to the n data channels of any one of the P die groups stacked along the first direction of the storage system fails, replacing the n data channels of the die group whose storage portion has failed with n data channels from the first memory die; where P is a positive integer.

[0135] In some embodiments, the die assembly is located between the first memory die and the third memory die.

[0136] In some embodiments, when a memory portion corresponding to one of the n data channels of the die group fails, replacing the n data channels corresponding to the failed memory portion of the die group with n data channels in a first memory die stacked along the first direction includes: a replacement control signal generation circuit generating a corresponding replacement control signal based on the address of the data channel corresponding to the failed memory portion in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die; and a selection circuit replacing the data channels corresponding to the failed memory portion in the second memory die with data channels in the first memory die based on the corresponding replacement control signal.

[0137] In some embodiments, the replacement control signal generating circuit generates a corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage portion in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die. This includes: a storage component storing the address of the data channel corresponding to the faulty storage portion in the second memory die; a latching circuit latching the address of the data channel corresponding to the faulty storage portion in the second memory die after the storage system is powered on; and a decoding circuit generating the corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage portion in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die.

[0138] In some embodiments, the method further includes: the decoding circuit generating a replacement control signal of a first value based on the address of the data channel of the second memory die that currently needs to interact with the third memory die, which is the same as the address of the first data channel corresponding to the faulty storage portion in the second memory die; different first data channels generate different first values; or, the decoding circuit generating a replacement control signal of a second value based on the address of the data channel of the second memory die that currently needs to interact with the third memory die, which is different from the address of the first data channel corresponding to the faulty storage portion in the second memory die.

[0139] In some embodiments, the method further includes: the selection circuit, based on the value of the replacement control signal being the first value, replacing the first data channel corresponding to the first value with a data channel in the first memory die.

[0140] The details of the operation method of the above-mentioned storage system have been described in detail in the embodiments concerning the storage device and the storage system in the foregoing embodiments, and will not be repeated here for the sake of brevity.

[0141] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0142] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0143] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A storage device, characterized in that, include: A first memory die and a die group stacked along a first direction; the die group includes M second memory dies stacked along the first direction; Each of the second memory dies is connected to the third memory die and is configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die through N data channels; where M, N, and X are all positive integers; The first memory die is connected to the third memory die and is configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die through N data channels, and replace the first data channel when the storage part corresponding to the first data channel of the die group fails.

2. The storage device according to claim 1, characterized in that, The storage device includes P sets of the aforementioned dies, and the P sets of dies are stacked along the first direction; the first memory die is configured to replace the first data channel when a storage portion corresponding to the first data channel of any of the P sets of dies fails, where P is a positive integer.

3. The storage device according to claim 1, characterized in that, The first memory die includes a first hybrid bonding layer, and the second memory die includes a second hybrid bonding layer and a third hybrid bonding layer; the first memory die and the second memory die are connected through the first hybrid bonding layer and the second hybrid bonding layer, and two adjacent second memory dies along the first direction are connected to the third hybrid bonding layer through the second hybrid bonding layer.

4. The storage device according to claim 1, characterized in that, The first memory die includes a first bump bonding layer, and the second memory die includes a second bump bonding layer and a third bump bonding layer; the first memory die and the second memory die are connected through the first bump bonding layer and the second bump bonding layer, and two adjacent second memory dies along the first direction are connected to the third bump bonding layer through the second bump bonding layer.

5. The storage device according to claim 2, characterized in that, The first memory die is located on one side of the two opposite sides of the P die groups along the first direction.

6. The storage device according to claim 2, characterized in that, M is 4; P is 2 or 3.

7. The storage device according to claim 1, characterized in that, The structure of the storage portion corresponding to the data channel of the first memory die is the same as the structure of the storage portion corresponding to the data channel of the second memory die.

8. The storage device according to claim 1, characterized in that, Both the first memory die and the second memory die include Y memory bank groups; each memory bank group includes multiple memory banks, and each memory bank includes multiple memory blocks; one data channel of the first memory die corresponds to (Y / N) memory bank groups of the first memory die, and one data channel of the second memory die corresponds to (Y / N) memory bank groups of the second memory die; Y is a positive integer, and Y > N.

9. A storage system, characterized in that, The storage system includes a storage device and a third memory die; the third memory die and the storage device are stacked along a first direction; the storage device includes a first memory die and a die group stacked along the first direction, and the die group includes M second memory dies stacked along the first direction; Each of the second memory dies is connected to the third memory die and is configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die through N data channels; where M, N, and X are all positive integers; The first memory die is connected to the third memory die and is configured to: be able to perform (N*X) bit bandwidth data interaction with the third memory die through N data channels; and the n data channels of the first memory die and the (M*Nn) data channels of the die group are configured to be able to perform parallel data interaction with the third memory die together. The n is an integer, and 0 ≤ n ≤ N.

10. The storage system according to claim 9, characterized in that, The die assembly is located between the first memory die and the third memory die.

11. The storage system according to claim 9, characterized in that, The storage device includes P groups of the aforementioned dies stacked along the first direction; the first memory die is configured to replace the first data channel when a storage portion corresponding to the first data channel of any one of the P dies fails. P is a positive integer.

12. The storage system according to claim 9, characterized in that, The first memory die includes a first hybrid bonding layer, and the second memory die includes a second hybrid bonding layer and a third hybrid bonding layer; the first memory die and the second memory die are connected through the first hybrid bonding layer and the second hybrid bonding layer, and two adjacent second memory dies along the first direction are connected to the third hybrid bonding layer through the second hybrid bonding layer.

13. The storage system according to claim 9, characterized in that, The first memory die includes a first bump bonding layer, and the second memory die includes a second bump bonding layer and a third bump bonding layer; the first memory die and the second memory die are connected through the first bump bonding layer and the second bump bonding layer, and two adjacent second memory dies along the first direction are connected to the third bump bonding layer through the second bump bonding layer.

14. The storage system according to claim 11, characterized in that, M is 4; P is 2 or 3.

15. The storage system according to claim 9, characterized in that, The structure of the storage portion corresponding to the data channel of the first memory die is the same as the structure of the storage portion corresponding to the data channel of the second memory die.

16. The storage system according to claim 9, characterized in that, Both the first memory die and the second memory die include Y memory bank groups; each memory bank group includes multiple memory banks, and each memory bank includes multiple memory blocks; one data channel of the first memory die corresponds to (Y / N) memory bank groups of the first memory die, and one data channel of the second memory die corresponds to (Y / N) memory bank groups of the second memory die; Y is a positive integer, and Y > N.

17. The storage system according to claim 9, characterized in that, The storage device includes a first interface, which includes multiple first data transmission interfaces, each corresponding to a data channel; the third memory die includes a replacement control signal generation circuit and a selection circuit; the selection circuit includes a signal input terminal and multiple data input terminals, the signal input terminal of the selection circuit is connected to the output terminal of the replacement control signal generation circuit, and each data input terminal of the selection circuit is connected to one of the first data transmission interfaces.

18. The storage system according to claim 17, characterized in that, The replacement control signal generation circuit is configured to generate a corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage portion in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die. The selection circuit is configured to replace the data channel corresponding to the faulty memory portion in the second memory die with the data channel in the first memory die based on the corresponding replacement control signal.

19. The storage system according to claim 18, characterized in that, The replacement control signal generation circuit includes: a storage component, a latch circuit, and a decoding circuit; the storage component is connected to the input terminal of the latch circuit, the output terminal of the latch circuit is connected to the first input terminal of the decoding circuit, the second input terminal of the decoding circuit is connected to the signal line of the storage system, and the output terminal of the decoding circuit is connected to the signal input terminal of the selection circuit.

20. The storage system according to claim 19, characterized in that, The storage component is configured to store the address of the data channel corresponding to the faulty storage portion in the second memory die; The latch circuit is configured to latch the address of the data channel corresponding to the faulty storage portion in the second memory die after the storage system is powered on. The decoding circuit is configured to generate a replacement control signal based on the address of the data channel corresponding to the faulty storage portion in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die.

21. The storage system according to claim 17, characterized in that, The third memory die further includes a second interface; the second interface includes a plurality of second data transmission interfaces; each of the plurality of output terminals of the selection circuit is connected to one of the second data transmission interfaces; and the number of the first data transmission interfaces is greater than the number of the second data transmission interfaces.

22. A method for operating a storage system, characterized in that, include: The M second memory dies stacked along the first direction have (M*N) data channels that jointly perform (M*N*X) bit bandwidth data interaction with the third memory die in parallel; where M, N, and X are all positive integers. When the storage portion corresponding to the n data channels of the die group fails, the n data channels corresponding to the failed storage portion of the die group are replaced by the n data channels in the first memory die stacked along the first direction of the die group. The n is an integer, and 1 ≤ n ≤ N; The n data channels of the first memory die and the (M*Nn) data channels of the die group together perform (M*N*X) bit bandwidth data interaction in parallel with the third memory die.

23. The operating method according to claim 22, characterized in that, When a storage portion corresponding to n data channels of the die group fails, the method of replacing the n data channels corresponding to the failed storage portion of the die group with n data channels from a first memory die stacked along the first direction includes: When the storage portion corresponding to n data channels of any one of the P die groups stacked along the first direction in the storage system fails, the n data channels of the die group whose storage portion has failed are replaced by the n data channels of the first memory die; where P is a positive integer.

24. The operating method according to claim 22, characterized in that, The die assembly is located between the first memory die and the third memory die.

25. The operating method according to claim 22, characterized in that, When a storage portion corresponding to n data channels of the die group fails, the method of replacing the n data channels corresponding to the failed storage portion of the die group with n data channels from a first memory die stacked along the first direction includes: The replacement control signal generation circuit generates a corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage section in the second memory die and the address of the data channel of the second memory die that currently needs to interact with the third memory die. The selection circuit, based on the corresponding replacement control signal, replaces the data channel corresponding to the faulty memory section in the second memory die with the data channel in the first memory die.

26. The operating method according to claim 25, characterized in that, The replacement control signal generation circuit generates a corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage portion in the second memory die, and the address of the data channel of the second memory die that currently needs to interact with the third memory die. The replacement control signal includes: The storage component stores the address of the data channel corresponding to the faulty storage section in the second memory die; After the storage system is powered on, the latching circuit latches the address of the data channel corresponding to the faulty storage section in the second memory die; The decoding circuit generates a corresponding replacement control signal based on the address of the data channel corresponding to the faulty storage section in the second memory die, and the address of the data channel of the second memory die that currently needs to interact with the third memory die.

27. The operating method according to claim 26, characterized in that, The method further includes: The decoding circuit generates a replacement control signal with a first value based on the address of the data channel of the second memory die that currently needs to interact with the third memory die, which is the same as the address of the first data channel corresponding to the faulty storage portion in the second memory die; different first data channels correspond to different first values; or, The decoding circuit generates a replacement control signal with a second value based on the fact that the address of the data channel of the second memory die that currently needs to interact with the third memory die is different from the address of the first data channel corresponding to the faulty storage portion in the second memory die.

28. The operating method according to claim 27, characterized in that, The method further includes: The selection circuit, based on the value of the replacement control signal, replaces the first data channel corresponding to the first value with the data channel in the first memory die using the first value.

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