Checking circuit and checking method of memory and memory

Abstract

The invention discloses a check circuit and a check method of a memory, and the memory, and belongs to the technical field of memories. The check circuit of the memory comprises an anti-decoding module which is used for being connected to a decoding circuit of the memory and performing anti-decoding on an output signal of the decoding circuit to obtain a decoded signal; and the comparison module is connected to the anti-decoding module and is used for comparing the decoding signal with the control signal received by the decoding circuit and generating an alarm signal according to a comparison result. According to the embodiment of the invention, the decoding circuit can be nursed through signal verification, and the operation reliability of the memory can be improved.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a verification circuit and verification method for a memory, and a memory itself. Background Technology

[0002] Memory achieves data storage by combining multiple storage cells. Memory usually has a decoding circuit, which realizes the read and write operation of the target storage cell in the memory by parsing the control signals related to read and write control.

[0003] However, under conditions such as high temperature, radiation, or aging, decoding circuits are prone to single-event flips or logic errors. Traditional memory lacks an effective real-time monitoring mechanism for this part of the circuit, which can easily lead to erroneous access to memory cells, causing system failures and affecting the operational reliability of the memory. Summary of the Invention

[0004] This invention provides a verification circuit and verification method for a memory, and a memory in general, so as to protect the decoding circuit through signal verification, which helps to improve the operational reliability of the memory.

[0005] In a first aspect, embodiments of the present invention provide a verification circuit for a memory, comprising: A decoding module is used to connect to the decoding circuit of the memory and to decode the output signal of the decoding circuit to obtain a decoded signal; A comparison module is connected to the decoding module and is used to compare the decoded signal with the control signal received by the decoding circuit, and generate an alarm signal based on the comparison result.

[0006] Optionally, the control signal includes: a read / write control signal and a read / write access address signal; The decoding circuit includes: The first decoding circuit is used to generate an internal read / write control signal based on the read / write control signal, and to decode the read / write access address signal to generate row selection line signals and column selection line signals. The second decoding circuit is used to decode the row selection signal to generate a word line selection signal and decode the column selection signal to generate a bit line selection signal according to the control of the internal read / write control signal.

[0007] Optionally, the decoding module is connected to the first decoding circuit, and the decoding module is used to decode the internal read / write control signal to obtain the first decoded signal; The comparison module is used to generate a first alarm signal based on the first decoded signal and the read / write control signal.

[0008] Optionally, the inverse decoding module is connected to the second decoding circuit, and the inverse decoding module is used to inverse decode the word line selection signal and the bit line selection signal to obtain the second decoded signal; The comparison module is used to generate a second alarm signal based on the second decoded signal and the read / write control signal.

[0009] Optionally, the inverse decoding module is connected to the second decoding circuit, and the inverse decoding module is used to inverse decode the word line selection signal and the bit line selection signal to obtain a third decoding signal; The comparison module is used to generate a third alarm signal based on the third decoding signal and the read / write access address signal.

[0010] Optionally, the decoding module is connected to the first decoding circuit and is used to decode the row selection line signal and the column selection line signal to obtain a fourth decoding signal; The comparison module is used to generate a fourth alarm signal based on the fourth decoding signal and the read / write access address signal.

[0011] Optionally, the read / write control signal includes a chip select signal and a read / write enable signal; the internal read / write control signal includes an internal chip select signal and an internal read / write enable signal; the first decoding circuit is used to generate the internal chip select signal according to the chip select signal, decode the read / write access address signal to generate the row select line signal and the column select line signal when the internal chip select signal is valid, and generate the internal read / write enable signal according to the internal chip select signal and the read / write enable signal; The decoding module is used to decode the internal chip select signal to obtain a first sub-decoding signal, and to decode the internal read / write enable signal to obtain a second sub-decoding signal. The comparison module is used to generate the first alarm signal based on the first sub-decoding signal, the chip select signal, the second sub-decoding signal, and the read / write enable signal.

[0012] Optionally, the first decoding circuit includes: an input unit, a delay unit, and a read / write control unit; the delay unit is used to generate an internal delay signal, the input unit is used to generate the internal chip select signal according to the chip select signal, the clock signal, and the internal delay signal, and the read / write control unit is used to generate the internal read / write enable signal according to the internal chip select signal and the read / write enable signal; The decoding module includes: a latch, which is connected to the output of the input unit and the output of the read / write control unit, and is connected to the clock signal; the latch is used to latch the internal chip select signal and the internal read / write enable signal, and when the clock signal is at a preset level, outputs the latched internal chip select signal as the first sub-decoding signal and outputs the latched internal read / write enable signal as the second sub-decoding signal.

[0013] Optionally, the comparison module generates a first result signal based on the first sub-decoding signal and the chip select signal, generates a second result signal based on the second sub-decoding signal and the read / write enable signal, and generates the first alarm signal based on the first result signal and the second result signal.

[0014] Optionally, the decoding module includes: The encoding unit is used to decode the word line selection signal to obtain a third sub-decoding signal, and to decode the bit line selection signal to obtain a fourth sub-decoding signal. The first logic processing unit is used to concatenate the third sub-decoding signal and the fourth sub-decoding signal to obtain the third decoding signal.

[0015] Optionally, the memory array includes multiple word lines and multiple bit lines, the word line selection signal includes the level of each word line, and the bit line selection signal includes the level of each bit line; The encoding unit includes: The first decoding subunit is connected to each of the word lines and is used to decode the word line selection signal to obtain the third sub-decoding signal. The second decoding subunit is connected to each bit line and is used to decode the bit line selection signal to obtain the fourth sub-decoding signal.

[0016] Optionally, the number of decodes in the first decode subunit is equal to the number of word lines, and the number of decodes in the second decode subunit is equal to the number of bit lines; For any one of the first and second decoding subunits: the decoding subunit includes at least one encoder; wherein, If the number of decodes in the decoding subunit is less than or equal to the maximum number of codes in the encoder, then the decoding subunit includes one encoder, and the code output by the encoder is used as the sub-decoding signal output by the decoding subunit. If the number of decoded codes in the decoding subunit is greater than the maximum number of codes in the encoder, then the decoding subunit includes n encoders, n OR gates, and a high-order encoder; where n is the number of decoded codes in the decoding subunit divided by the maximum number of codes in the encoder and rounded up; the input of each OR gate is connected to the output of each encoder, and the output of each OR gate is connected to the high-order encoder; the code output by the encoder connected to the selected word line or bit line is used as the low-order address, the OR gate generates an encoder block selection signal based on the code output by the encoder, the high-order encoder generates a high-order address based on each encoder block selection signal, and the high-order address and the low-order address are concatenated as the sub-decoding signal output by the decoding subunit.

[0017] Optionally, the decoding module includes: The second logic processing unit is used to concatenate the row selection line signal and the column selection line signal to obtain the fourth decoding signal.

[0018] Optionally, the memory further includes: a RAM control unit and RAM macrocells; the RAM control unit is provided with a read / write access control circuit, which provides the control signal; the decoding circuit is disposed in the RAM macrocell; wherein, Both the comparison module and the decoding module are located in the RAM control unit; Alternatively, both the comparison module and the decoding module can be located within the RAM macrocell; Alternatively, the decoding module may be located in the RAM macrocell, and the comparison module may be located in the RAM control unit.

[0019] Optionally, the verification circuit of the memory further includes: a delay module connected to the comparison module and connected to the control signal; The delay module is used to delay the control signal for a preset duration before outputting it to the comparison module; wherein, the preset duration is configured to ensure that the output signal of the delay module and the decoded signal are transmitted to the comparison module synchronously.

[0020] Secondly, embodiments of the present invention also provide a method for verifying a memory, applied to the memory verification circuit provided in any embodiment of the present invention; the method includes: The decoding module decodes the output signal of the memory's decoding circuit to obtain the decoded signal; The comparison module compares the decoded signal with the control signal received by the decoding circuit and generates an alarm signal based on the comparison result.

[0021] Thirdly, embodiments of the present invention also provide a memory, including a verification circuit for the memory provided in any embodiment of the present invention.

[0022] Optionally, the memory is SRAM.

[0023] The memory verification circuit provided in this embodiment of the invention includes a decoding module and a comparison module. The decoding module decodes the output signal of the decoding circuit to obtain a decoded signal. The comparison module compares the control signal and the decoded signal and generates an alarm signal based on the comparison result to indicate an error in the decoding circuit. This effectively monitors the decoding circuit by verifying its output signal. Fault detection and timely alarms in the decoding circuit can effectively improve the operational reliability of the memory. Furthermore, when a memory fault exists, the presence of an alarm signal from the comparison module determines whether the decoding circuit is faulty, thus improving troubleshooting efficiency.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a verification circuit for another memory provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the connection relationship between a first decoding circuit and an inverse decoding module provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the working timing of a memory provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of a memory provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of another memory structure provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of another type of memory provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of the structure of a verification circuit for a memory provided in an embodiment of the present invention; Figure 18 This is a flowchart illustrating a memory verification method provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of another type of memory provided in an embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0029] This invention provides a verification circuit for a memory, consisting of a decoding module and a comparison module. It can verify the signal generated by the decoding circuit in the memory, thereby protecting the decoding circuit, detecting and promptly alarming decoding circuit faults, and thus improving the operational reliability of the memory.

[0030] Figure 1 This is a schematic diagram of a memory verification circuit provided in an embodiment of the present invention. For ease of explanation, the following will first refer to... Figure 1 A brief description of the memory is given, followed by a detailed explanation of the memory's verification circuit (hereinafter referred to as the verification circuit for ease of explanation).

[0031] See Figure 1 The memory typically includes a decoding circuit 11 and a memory array 12. The memory array 12 includes multiple memory cells. The decoding circuit 11 decodes the received control signal Ctrl to select the target memory cell specified by the control signal Ctrl in the memory array 12 for the read / write operation indicated by the control signal Ctrl. For example, the control signal Ctrl is encoded using a certain encoding method based on the read / write control information and the address information of the target memory cell, so that the control signal Ctrl can be used to indicate the location of the target memory cell and whether to perform a read or write operation on the target memory cell. The decoding circuit 11 can use a decoding method corresponding to the above encoding method to decode the control signal Ctrl, thereby parsing the read / write control information and address information, and then selecting the target memory cell specified by the control signal Ctrl from the memory array 12 according to the address information, and performing the read / write operation indicated by the control signal Ctrl on the target memory cell according to the read / write control information.

[0032] See also Figure 1 The verification circuit 100 includes a re-encode logic module 30 and a comparator module 40. The re-encode logic module 30 is connected to the decoding circuit 11 of the memory and performs re-decoding on the output signal of the decoding circuit 11 to obtain the decoded signal CtrlO. The comparator module 40 is connected to the re-encode logic module 30 and compares the decoded signal CtrlO with the control signal Ctrl received by the decoding circuit 11, generating an alarm signal SA based on the comparison result.

[0033] The output signal of the decoding circuit 11 is the signal obtained by decoding the control signal Ctrl, and may include the signal transmitted by the decoding circuit 11 to the storage array 12. When the decoding circuit 11 needs to perform multi-level decoding, the output signal of the decoding circuit 11 may include the decoded signal obtained after any one level of decoding.

[0034] The decoding module 30 can use a decoding method corresponding to the decoding method of the decoding circuit 11 to decode (or decode) the output signal of the decoding circuit 11. For example, after decoding by the decoding module 30, a decoded signal CtrlO with the same format as the control signal Ctrl can be obtained, so that the comparison module 40 can compare the control signal Ctrl and the decoded signal CtrlO. Alternatively, if the decoded signal CtrlO and the control signal Ctrl have different formats, the comparison module 40 can perform format conversion on at least one of the signals before comparison. The specific decoding method can be set according to actual needs and is not limited here.

[0035] The comparison module 40 can generate an alarm signal SA when the decoding signal CtrlO and the control signal Ctrl are inconsistent. The alarm signal SA is used to indicate that an error has occurred in the decoding circuit 11. It should be noted that the comparison module 40's determination that two signals are inconsistent can be understood as the information indicated by the two signals being inconsistent. For example, the read / write control information indicated by the decoding signal CtrlO and the control signal Ctrl are inconsistent, and / or the address information indicated is inconsistent. When comparing two signals, if the two signals have the same format, they can be directly compared; if the two signals have different formats, they can be converted to the same format before comparison. Here, "same format" can be understood as the two signals being the same in terms of signal type, such as both being digital signals / analog signals, and using the same transmission protocol. For example, for digital signals, the bit width and whether each bit of data is consistent can be compared; for analog signals, whether the waveform / potential is consistent can be compared. The above examples are not intended to limit the invention. Furthermore, depending on the actual needs, the comparison module 40 can compare signals extracted at a certain time period, or it can compare signals extracted at one or more time points. Furthermore, if the transmission timing of the two signals is inconsistent, they can be aligned in terms of timing before comparison; alternatively, the potential information of the decoded signal CtrlO and the control signal Ctrl at different times can be extracted based on the actual working timing to compare their consistency. For example, if the control signal Ctrl and the decoded signal CtrlO are data signals with the same number of bits using the same base, the comparison module 40 can compare each bit of the control signal Ctrl and the decoded signal CtrlO sequentially. When all bits are identical, the control signal Ctrl and the decoded signal CtrlO are determined to be consistent. When the decoded signal CtrlO and the control signal Ctrl are inconsistent, it indicates that the signal obtained by the decoding circuit 11 can no longer correctly represent the control target of the control signal Ctrl, and the decoding circuit 11 is deemed to be malfunctioning.

[0036] The verification circuit of the memory provided in this embodiment of the invention includes a decoding module 30 and a comparison module 40. The decoding module 30 decodes the output signal of the decoding circuit 11 to obtain the decoded signal CtrlO. The comparison module 40 compares the control signal Ctrl and the decoded signal CtrlO, and generates an alarm signal SA based on the comparison result to indicate that the decoding circuit 11 has an error. This is equivalent to monitoring the decoding circuit 11 by verifying its output signal. By detecting faults in the decoding circuit 11 and issuing timely alarms, the operational reliability of the memory can be effectively improved. Furthermore, when a fault exists in the memory, whether the comparison module 40 outputs the alarm signal SA can determine whether the decoding circuit 11 is faulty, which helps improve the efficiency of fault diagnosis.

[0037] Figure 2This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 2 Based on the above embodiments, optionally, the access control logic 21 in the memory provides a control signal Ctrl. The control signal Ctrl includes a read / write control signal RWC and a read / write access address signal Address. The read / write access address signal Address indicates address information, specifically specifying the address of the target memory cell in the memory array 12; the read / write access address signal Address can be a logic signal, such as a multi-bit digital signal. The read / write control signal RWC indicates read / write control information, specifically indicating read / write operations on the target memory cell; the read / write control signal RWC can be a single signal or a group of signals related to read / write control, and the number and type of signals it contains can be set according to actual needs.

[0038] The decoding circuit 11 includes a first decoding circuit (RAM X / Y decoder) 111 and a second decoding circuit (RAM WL / BL decoder) 112. The first decoding circuit 111 is connected, for example, to the read / write access control circuit 21. The first decoding circuit 111 generates an internal read / write control signal RWCTRL based on the read / write control signal RWC, and decodes the read / write access address signal Address to generate row select line signal XADR and column select line signal YADR. The second decoding circuit 112 is connected to the first decoding circuit 111. The second decoding circuit 112, based on the control of the internal read / write control signal RWCTRL, decodes the row select line signal XADR to generate a word line select signal WL, and decodes the column select line signal YADR to generate a bit line select signal BL.

[0039] Specifically, the storage array 12 includes multiple storage cells arranged in an array, such as a row-column storage structure, where the storage cells are arranged in a cross-linked manner using word lines and bit lines. For example, the storage array 12 includes multiple word lines and multiple bit lines, with each word line connecting to a row of storage cells and each row of bit lines connecting to a column of storage cells. By selecting a word line and a bit line, a unique storage cell can be located through cross-linking. See then... Figure 3Specifically, the read / write access address signal Address can be an M+K bit digital signal, specifically represented as Address[M+K-1:0], where M and K are both positive integers. For example, the high M bits of the read / write access address signal Address represent the row selection line signal, and the low K bits represent the column selection line signal. The first decoding circuit 111 is used to implement row / column decoding, translating the high and low bits of the input read / write access address signal Address into M-bit row selection line signals XADR[M-1:0] and K-bit column selection line signals YADR[K-1:0], respectively, so that the physical intersection of the target memory cell can be located in the memory array 12 later. The second decoding circuit 112 is used to implement word line / bit line decoding and driving. Specifically, the second decoding circuit 112 decodes the row selection line signal XADR[M-1:0] to generate a word line selection signal WL. The word line selection signal WL specifically includes the level of each word line, and the number of word lines is L, where L=2. M See Figure 3 The level of the i-th word line is represented as WL[i-1], where 1≤i≤L. For example, the level of the first word line is represented as WL[0] and the level of the L-th word line is represented as WL[L-1]. The selected word line can be determined by the level of each word line. Similarly, the second decoding circuit 112 decodes the column selection line signal YADR[K-1:0] to generate the bit line selection signal BL. The bit line selection signal BL specifically includes the level of each bit line. The number of bit lines is J, where J=2. K See Figure 3 The level on the i-th bit line is represented as BL[i-1], where 1 ≤ i ≤ J. For example, the level on the first bit line is represented as BL[0], and the level on the J-th bit line is represented as BL[J-1]. The selected bit line can be determined by the level on each bit line. Furthermore, the target memory cell can be located by the selected word line and the selected bit line. The specific level of the selected word line and the selected bit line can drive the target memory cell to perform specific read / write operations. In this way, through two-level decoding processing, the target memory cell can be reliably selected and the required read / write operations can be performed.

[0040] Based on the above embodiments, optionally, at least one of the output signals of the first decoding circuit 111 and the second decoding circuit 112 can be extracted by the inverse decoding module 30 as the output signal of the decoding circuit 11. Correspondingly, the comparison module 40 can select the signal source in the control signal Ctrl that corresponds to the signal extracted by the inverse decoding module 30, and compare it with the decoding signal Ctrl0 to determine whether the decoding circuit 11 has an error. There are various specific implementations of the verification circuit 100; several are described below as examples, but these are not intended to limit the invention. In the first embodiment, optionally, see Figure 3 The inverse decoding module 30 is connected to the first decoding circuit 111. The inverse decoding module 30 is used to inverse decode the internal read / write control signal RWCTRL to obtain the first decoded signal RWCO1. The comparison module 40 is used to generate the first alarm signal SA1 based on the first decoded signal RWCO1 and the read / write control signal RWC.

[0041] In this embodiment, the decoding module 30 extracts the internal read / write control signal RWCTRL for decoding. The comparison module 40 generates a first alarm signal SA1 when the first decoded signal RWCO1 is inconsistent with the read / write control signal RWC. This is equivalent to verifying the read / write control signal decoding function of the first decoding circuit 111. The first alarm signal SA1 indicates that an error has occurred in the first decoding circuit 111. For example, the first decoded signal RWCO1 and the read / write control signal RWC have the same format.

[0042] Figure 4 This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 4 Based on the above embodiments, optionally, the read / write control signal RWC includes: a chip select signal CEB and a read / write enable signal WREB; the internal read / write control signal RWCTRL includes: an internal chip select signal CEB_ENB and an internal read / write enable signal WERB_ENB. The first decoding circuit 111 is used to generate the internal chip select signal CEB_ENB based on the chip select signal CEB, decode the read / write access address signal Address to generate row select line signal XADR and column select line signal YADR when the internal chip select signal CEB_ENB is valid, and generate the internal read / write enable signal WREB_ENB based on the internal chip select signal CEB_ENB and the read / write enable signal WREB. For example, when the internal chip select signal CEB_ENB is active, the first decoding circuit 111 generates an internal read / write enable signal WREB_ENB based on the read / write enable signal WREB; and when the internal chip select signal CEB_ENB is active, the second decoding circuit 112 decodes the row select line signal XADR and the column select line signal YADR, and determines the level on each word line and the level on each bit line based on the internal read / write enable signal WREB_ENB, so as to select the word line and bit line indicated by the read / write access address signal Address, and provides the level corresponding to the read / write enable signal WREB to the selected word line and bit line. The active level of the internal chip select signal CEB_ENB can be set to low or high level according to actual needs.

[0043] Correspondingly, the decoding module 30 is used to decode the internal chip select signal CEB_ENB to obtain the first sub-decoding signal CEBO1, and to decode the internal read / write enable signal WREB_ENB to obtain the second sub-decoding signal WREBO1. The comparison module 40 is used to generate a first alarm signal SA1 based on the first sub-decoding signal CEBO1, the chip select signal CEB, the second sub-decoding signal WREBO1, and the read / write enable signal WREB.

[0044] Specifically, the comparison module 40 can generate a first result signal based on the first sub-decoding signal CEBO1 and the chip select signal CEB, generate a second result signal based on the second sub-decoding signal WREBO1 and the read / write enable signal WREB, and generate a first alarm signal SA1 based on the first and second result signals. More specifically, when the first result signal indicates that the first sub-decoding signal CEBO1 and the chip select signal CEB are inconsistent, and / or when the second result signal indicates that the second sub-decoding signal WREBO1 and the read / write enable signal WREB are inconsistent, the comparison module 40 outputs the first alarm signal SA1, indicating that an error has occurred in the first decoding circuit 111.

[0045] Based on the above embodiments, optionally, the read / write enable signal WREB may include a single write enable signal (denoted as WEB), a single read enable signal (denoted as REB), or both a write enable signal and a read enable signal, which can be set according to actual needs. Regardless of the form of the read / write enable signal WREB, the first decoding circuit 111 can generate a corresponding number and form of internal read / write enable signals WREB_ENB through decoding, and the inverse decoding module 30 will inverse decode the internal read / write enable signals WREB_ENB to obtain a corresponding number and form of second sub-decoding signals WREBO1.

[0046] The following example illustrates a specific implementation of the first decoding circuit 111 and the inverse decoding module 30, using the read / write enable signal WREB as an example, which includes a single write enable signal WEB. It can be understood that when the read / write enable signal WREB includes a single write enable signal WEB, the internal read / write enable signal WREB_ENB includes the internal write enable signal (denoted as WEB_ENB), and the second sub-decoding signal WREBO1 includes the first type of second sub-decoding signal (denoted as WEBO1).

[0047] Figure 5 This is a schematic diagram illustrating the connection relationship between a first decoding circuit and an inverse decoding module according to an embodiment of the present invention. See also... Figure 5In one embodiment, optionally, the first decoding circuit 111 includes: an input unit 1111, a delay unit 1112, and a read / write control unit 1113. The delay unit 1112 generates an internal delay signal DUMENB; the input unit 1111 generates an internal chip select signal CEB_ENB based on the chip select signal CEB, the clock signal CLK, and the internal delay signal DUMENB; and the read / write control unit 1113 generates an internal read / write enable signal (exemplarily an internal write enable signal WEB_ENB) based on the internal chip select signal CEB_ENB and a read / write enable signal (exemplarily a write enable signal WEB). It is understood that only the functional units related to the decoding of the read / write control signal in the first decoding circuit 111 are shown here, and the functional units related to address decoding are not shown.

[0048] The delay unit 1112 outputs the valid level of the internal delay signal DUMENB when the levels of the Dummy WL (virtual word line) and Dummy BL (virtual bit line) within the memory are established. Dummy WL and Dummy BL are redundant nets and bias circuits introduced to ensure that word lines and bit lines are in a "established" and defined level state even when not actually selected. Dummy WL and Dummy BL do not carry valid data and do not participate in read / write operations, but they are "established" to a suitable static level in the layout and bias to eliminate floating nodes, suppress leakage and coupling noise, and balance the load, thereby improving timing consistency and yield. The input unit 1111 performs logical processing on the chip select signal CEB, the clock signal CLK, and the internal delay signal DUMENB to generate the internal chip select signal CEB_EN. The read / write control unit 1113 performs logical processing on the read / write enable signal and the internal chip select signal CEB_ENB to generate the internal read / write enable signal.

[0049] The decoding module 30 includes a latch circuit 31, which is connected to the output of the input unit 1111 and the output of the read / write control unit 1113, and is connected to the clock signal CLK. The latch circuit 31 is used to latch the internal chip select signal CEB_ENB and the internal read / write enable signal (exemplarily the internal write enable signal WEB_ENB). When the clock signal CLK is at a preset level, it outputs the latched internal chip select signal CEB_ENB as the first sub-decoding signal CEBO1, and outputs the latched internal read / write enable signal (exemplarily the internal write enable signal WEB_ENB) as the second sub-decoding signal (exemplarily the first type of second sub-decoding signal WEBBO1). For example, latch 31 also receives an inverted clock signal CLKB. Specifically, latch 31 can latch the received internal chip select signal CEB_ENB and internal read / write enable signal when the clock signal CLK is at a first level, and output the latched internal chip select signal CEB_ENB and internal read / write enable signal when the clock signal CLK is at a second level, to obtain the first sub-decoding signal CEBO1 and the second sub-decoding signal. The first level and the second level are different; for example, the first level is a high level and the second level is a low level.

[0050] Figure 6 This is a schematic diagram of the working timing of a memory provided in an embodiment of the present invention, combined with... Figure 5 and Figure 6 Exemplary Figure 5 The signal level changes in the circuit structure shown can be: The internal delay signal DUMENB is an internal delay signal following the Dummy WL and Dummy BL, used to indicate whether the internal word lines and bit lines of the memory have been fully established. When CLK=1 and DUMENB=1, it indicates that the internal Dummy WL and Dummy BL have begun to be established; when DUMENB=0, it indicates that the establishment is complete. Upon completion, the backward transmission paths of the chip select signal CEB and the write enable signal WEB can be disabled.

[0051] The internal chip select signal CEB_ENB is generated by input unit 1111 through combinational logic of clock signal CLK, chip select signal CEB, and internal delay signal DUMENB. Specifically, CEB_ENB = 0 when CLK = 1 and CEB = 0, and CEB_ENB = 1 when DUMENB = 0. The internal chip select signal CEB_ENB indicates the internal chip select enable time. CEB_ENB = 0 is valid; only during this period can the read / write access address signal Address be input to the first decoding circuit 111, and the write enable signal WEB be input to the read / write control unit 1113. CEB_ENB = 1 is invalid, indicating that the above transmission paths are disabled.

[0052] The internal write enable signal WEB_ENB is generated by the read / write control unit 1113 through combinational logic of the internal chip select signal CEB_ENB and the write enable signal WEB. Specifically, WEB_ENB = 0 when both CEB_ENB and WEB = 0, and WEB_ENB = 1 when both CEB_ENB and CLK = 1. The internal write enable signal WEB_ENB indicates the timing of internal write enable. For example, WEB_ENB = 0 indicates a write operation; WEB_ENB = 1, and CLK = 1, indicates a read operation.

[0053] Latch 31 is used to latch the internal chip select signal CEB_ENB and the internal write enable signal WEB_ENB. When CLK=0, the states of the latched internal chip select signal CEB_ENB and the internal write enable signal WEB_ENB are output to the first sub-decoding signal CEBO1 and the first type of second sub-decoding signal WEBO1, respectively. Then, the comparison module 40 can specifically extract the chip select signal CEB and the write enable signal WEB at the rising edge of the clock signal CLK, compare them with the first sub-decoding signal CEBO1 and the first type of second sub-decoding signal WEBO1 at the falling edge of the clock signal CLK, and determine whether to output the first alarm signal SA1 based on the two comparison results. That is, for the read / write control signal, its consistency with the decoded signal obtained by inverse decoding means that the level of the read / write control signal at the rising edge of the clock signal CLK is consistent with the level of the decoded signal at the falling edge of the clock signal CLK. Figure 6 For example, the chip select signal CEB is low on the rising edge of the clock signal CLK, and the first sub-decode signal CEBO1 is low on the falling edge of the clock signal CLK, so they can be determined to be consistent; the write enable signal WEB is low on the rising edge of the clock signal CLK, and the first type of second sub-decode signal WEBO1 is low on the falling edge of the clock signal CLK, so they can be determined to be consistent.

[0054] Figure 7 This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 7 In the second embodiment, optionally, the decoding module 30 is connected to the second decoding circuit 112. The decoding module 30 is used to decode the word line selection signal and the bit line selection signal to obtain the second decoded signal. The comparison module 40 is used to generate a second alarm signal SA2 based on the second decoded signal and the read / write control signal.

[0055] Specifically, the read / write control signal may include the chip select signal CEB and the read / write enable signal RWEB. The second decoding signal may include the fifth sub-decoding signal CEBO2 and the sixth sub-decoding signal RWEBO2. The comparison module 40 compares the chip select signal CEB and the fifth sub-decoding signal CEBO2, and compares the read / write enable signal RWEB and the sixth sub-decoding signal RWEBO2. When at least one of the above comparison results indicates that the two compared signals are inconsistent, the comparison module 40 outputs the second alarm signal SA2.

[0056] In this embodiment, the decoding module 30 extracts the word line selection signal and the bit line selection signal for decoding to generate a second decoded signal representing the read / write control signal. The comparison module 40 generates a second alarm signal SA2 when the second decoded signal is inconsistent with the read / write control signal. This is equivalent to verifying the read / write control signal decoding function of the first decoding circuit 111 and the second decoding circuit 112. The second alarm signal SA2 is used to indicate that at least one of the first decoding circuit 111 and the second decoding circuit 112 has an error. For example, the second decoded signal has the same format as the read / write control signal.

[0057] The above embodiments provide specific implementation methods for verifying the read / write control signal decoding function, such as comparing the signal levels at different points. In other embodiments, the address decoding function related to the read / write access address signal can also be verified, as described below. For example, for comparing address information, the bit width and address result of the read / write access address signal can be compared with those of the decoded signal obtained by inverse decoding.

[0058] Figure 8 This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 8 In a third embodiment, optionally, the decoding module 30 is connected to the second decoding circuit 112. The decoding module 30 is used to decode the word line selection signal WL and the bit line selection signal BL to obtain the third decoding signal AddrO1. The comparison module 40 is used to generate a third alarm signal SA3 based on the third decoding signal AddrO1 and the read / write access address signal Address.

[0059] In this embodiment, the decoding module 30 extracts the word line selection signal WL and the bit line selection signal BL for decoding to generate a third decoding signal AddrO1 that represents the read / write access address signal. When the third decoding signal AddrO1 is inconsistent with the read / write access address signal Address, the comparison module 40 generates a third alarm signal SA3, which is equivalent to verifying the address decoding function of the first decoding circuit 111 and the second decoding circuit 112. The third alarm signal SA3 is used to indicate that at least one of the first decoding circuit 111 and the second decoding circuit 112 has an error.

[0060] Figure 9 This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 9 Specifically, the decoding module 30 includes an encoding unit 32 and a first logic processing unit 33. The encoding unit 32 is connected to the second decoding circuit 112. The encoding unit 32 is used to decode the word line selection signal to obtain the third sub-decoding signal XADRO, and to decode the bit line selection signal to obtain the fourth sub-decoding signal YADR0. The first logic processing unit 33 is connected to both the encoding unit 32 and the comparison module 40. The first logic processing unit 33 is used to concatenate the third sub-decoding signal XADR0 and the fourth sub-decoding signal YADRO to obtain the third decoding signal AddrO1. For example, the third sub-decoding signal XADR0 has the same format as the row selection line signal XADR, and the fourth sub-decoding signal YADRO has the same format as the column selection line signal YADR. The first logic processing unit 33 uses the same splicing method as the read / write access address signal Address to splice the third sub-decoding signal XADR0 and the fourth sub-decoding signal YADRO, to obtain the third decoding signal AddrO1 with the same format as the read / write access address signal Address.

[0061] In this embodiment, the encoding unit 32 performs inverse decoding corresponding to the decoding process of the second decoding circuit 112, and then the first logic processing unit 33 performs inverse decoding corresponding to the decoding process of the first decoding circuit 111 to obtain the final third decoded signal AddrO1.

[0062] Based on the above embodiments, optionally, the memory array 12 includes multiple word lines and multiple bit lines. The word line selection signal includes the level of each word line, and the bit line selection signal includes the level of each bit line. When the decoding circuit 11 is error-free, only one word line and one bit line are selected, and the memory cell jointly connected by the word line selected based on the word line selection signal and the bit line selected based on the bit line selection signal is the target memory cell specified by the control signal.

[0063] Figure 10 This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 10In one embodiment, optionally, the encoding unit 32 includes a first decoding subunit 321 and a second decoding subunit 322. The first decoding subunit 321 is connected to each word line and is used to decode the word line selection signal to obtain a third sub-decoding signal XADRO; the second decoding subunit 322 is connected to each bit line and is used to decode the bit line selection signal to obtain a fourth sub-decoding signal YADRO. This embodiment simplifies and facilitates the decoding process of the encoding unit 32 by setting two decoding subunits to decode the word line selection signal and the bit line selection signal respectively.

[0064] Specifically, the first decoding subunit 321 and the second decoding subunit 322 can perform decoding using the same principle. The number of decoding operations in the first decoding subunit 321 is equal to the number of word lines, and the number of decoding operations in the second decoding subunit 322 is equal to the number of bit lines.

[0065] For either the first decoding subunit 321 or the second decoding subunit 322: the decoding subunit includes at least one encoder. Each input terminal of the encoder can be connected to different signal lines (for the encoder in the first decoding subunit 321, these signal lines are word lines; for the encoder in the second decoding subunit 322, these signal lines are bit lines). The encoder generates codes based on the levels of the connected signal lines. It should be noted that, due to the limitation on the number of input terminals, the encoder has a maximum code count limit; for example, the maximum code count is equal to the number of input terminals in the encoder. Therefore, based on the relationship between the number of decoded codes in the decoding subunit and the maximum code count of the encoder, the number of encoders in the decoding subunit can be determined, as explained in detail below.

[0066] In one implementation, optionally, if the number of decoded codes in the decoding subunit is less than or equal to the maximum number of codes in the encoder, then the decoding subunit includes an encoder, and the code output by the encoder serves as the sub-decoded signal output by the decoding subunit. That is, if the number of decoded codes does not exceed the maximum number of codes, setting one encoder is sufficient to meet the decoding requirements of the decoding subunit, and only one encoder can be set in this case.

[0067] In another implementation, optionally, if the number of decoded codes in the decoding subunit is greater than the maximum number of codes in the encoder, then the decoding subunit includes n encoders, where n is the result of dividing the number of decoded codes in the decoding subunit by the maximum number of codes in the encoder and rounding up. That is, when the number of decoded codes exceeds the maximum number of codes, one encoder is no longer sufficient to meet the decoding requirements of the decoding subunit. In this case, two or more encoders are needed. The number of encoders is determined based on the multiple of the number of decoded codes to the maximum number of codes, ensuring that the sum of the maximum number of codes of the n encoders can meet the decoding requirement.

[0068] Based on this, the decoding subunit also needs to include n OR gates and a high-order encoder. Each OR gate corresponds one-to-one with each encoder, and the inputs of each OR gate are connected to the outputs of each encoder; the outputs of each OR gate are connected to the high-order encoder. The encoder output code connected to the selected word line or bit line is used as the low-order address. The OR gate generates an encoder block selection signal based on the encoder output code, and the high-order encoder generates a high-order address based on the encoder block selection signals. The high-order address and the low-order address are concatenated to form the sub-decoding signal output by the decoding subunit.

[0069] For example, the encoder is k-2 k Encoder, with 2 k With one input terminal and k input terminals, it can be based on 2 k The level of each signal line generates a k-bit code. A corresponding OR gate is selected as a k-input, one-output OR gate, with each of the k inputs of the OR gate connected to one of the k outputs of the encoder. Thus, based on the encoder's output code, the OR gate can determine whether any signal lines connected to the encoder have been selected and output the corresponding encoder block selection signal. The number of inputs to the high-order encoder is greater than or equal to the number of OR gates, so that the outputs of each OR gate are connected to different inputs of the high-order encoder. The code output by the high-order encoder based on each encoder block selection signal is used as the high-order address, and the code output by the encoder connected to the selected signal line is used as the low-order address. Concatenating the high-order and low-order addresses yields the complete sub-decoding signal that the inverse decoding subunit should output.

[0070] In summary, in this embodiment of the invention, based on the fundamental condition that only one word line and one bit line will be selected, the decoding level is determined according to the number of decoded bits and the maximum number of codes. When the number of decoded bits does not exceed the maximum number of codes, single-level decoding is sufficient; when the number of decoded bits is greater than the maximum number of codes, hierarchical decoding is used, and the decoded result is obtained by concatenating the high-order address with the low-order address. In this way, the encoding unit 32 can be set according to the size of the storage array 12, simplifying the circuit structure while meeting the decoding number requirement, and satisfying the decoding requirements of memories with storage arrays 12 of various sizes.

[0071] In one specific implementation, optionally, the maximum number of codes that the encoder can implement is defined as 64, that is, the encoder is a 6-64 encoder. For any decoding subunit, when the number of codes is less than or equal to 64, the code obtained by decoding with one encoder can be directly used as the sub-decoding signal; when the number of codes is greater than 64, hierarchical decoding is used. For example, when the number of codes is 8, 16, 32, and 64, hierarchical decoding is not required, and only one encoder is needed; when the number of codes is 128, 256, and 512, hierarchical decoding is required, requiring 2, 4, and 8 encoders respectively, and corresponding OR gates and high-order encoders need to be set; when the number of codes is greater than 512, encoders can be added in the above manner.

[0072] Taking a reverse decoding count of 512 as an example, 8 encoders and 8 OR gates are required. Each encoder has 64 inputs, and each encoder performs 6-64 encoding on the level of the 64 connected signal lines. The encoder output code connected to the selected signal line is used as the low-order address, denoted as A<5:0>. The encoder output code is used by an OR gate to determine whether a signal line is selected, thus outputting 8 encoder block selection signals. The high-order encoder can be a 3-8 priority encoder, which performs 3-8 encoding on the 8 encoder block selection signals and outputs the high-order address, specifically the three high-order address signals, denoted as A<8:6>. The high-order address and the low-order address are then concatenated using combinational logic to obtain the complete sub-decoding signal, denoted as A<8:0>.

[0073] Figure 11 This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 11 In the fourth embodiment, optionally, the decoding module 30 is connected to the first decoding circuit 111. The decoding module 30 is used to decode the row selection line signal XADR and the column selection line signal YADR to obtain the fourth decoded signal AddrO2. The comparison module 40 is used to generate a fourth alarm signal SA4 based on the fourth decoded signal AddrO2 and the read / write access address signal Address.

[0074] In this embodiment, the decoding module 30 extracts the row selection line signal XADR and the column selection line signal YADR for decoding. The comparison module 40 generates a fourth alarm signal SA4 when the fourth decoded signal AddrO2 is inconsistent with the read / write access address signal Address. This is equivalent to verifying the address decoding function of the first decoding circuit 111. The fourth alarm signal SA4 is used to indicate that an error has occurred in the first decoding circuit 111. For example, the fourth decoded signal AddrO2 has the same format as the read / write access address signal Address.

[0075] Figure 12This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 12 Specifically, the decoding module 30 includes a second logic processing unit 34, which is connected to the first decoding circuit 111. The second logic processing unit 34 is used to concatenate the row selection line signal XADR and the column selection line signal YADR to obtain the fourth decoded signal AddrO2. For example, the second logic processing unit 34 uses the same concatenation method as the read / write access address signal Address to concatenate the row selection line signal XADR and the column selection line signal YADR, obtaining the fourth decoded signal AddrO2 with the same format as the read / write access address signal Address.

[0076] The above embodiments exemplify the signals verified by the four verification circuits 100 and their specific implementation methods. It should be noted that in practical applications, one or more verification circuits can be configured according to actual needs. Combining multiple verification circuits facilitates precise location and / or type of decoding errors.

[0077] For example, see Figure 13 The verification circuit described in the first embodiment can be set simultaneously (see...). Figure 13 The first verification circuit 101 in the first embodiment includes a first decryption module 301 and a first comparison module 401, and the verification circuit in the third embodiment (see [reference]). Figure 13 The second verification circuit 102 includes a second inverse decoding module 302 and a second comparison module 402. This allows the fault to be located either in the first decoding circuit 111 or the second decoding circuit 112. It also verifies both the read / write control signal decoding function and the address decoding function of the decoding circuit 11, ensuring verification reliability.

[0078] Alternatively, the verification circuits in the first and second embodiments described above can be set simultaneously, so that the fault can be located to the first decoding circuit 111 or the second decoding circuit 112.

[0079] Alternatively, the verification circuits in the first and fourth embodiments described above can be set simultaneously, so that the fault can be located to the read / write control signal decoding function or the address decoding function of the first decoding circuit 111.

[0080] The above-described combinations of verification circuits are not intended to limit the invention. In other embodiments, other types or numbers of verification circuits may be selected for combination according to actual needs; other combinations will not be described in detail.

[0081] See Figure 14-16Based on the above embodiments, optionally, the memory also includes a RAM control unit 20 and a RAM macro cell 10. The RAM control unit is the core control component of the memory, and a read / write access control circuit 21 is disposed within the RAM control unit 20 to provide control signals; a decoding circuit 11 is disposed within the RAM macro cell 10, and a storage array 12 is also disposed within the RAM macro cell 10.

[0082] Based on this, there are several possible settings for the comparison module 40 and the decoding module 30, which will be explained below.

[0083] In one implementation, optionally, see [link to relevant documentation]. Figure 14 Both the comparison module 40 and the decoding module 30 are located within the RAM control unit 20. This arrangement minimizes the impact on the structure of the RAM macrocell 10, requiring only the configuration of relevant ports and wiring to bring out the signals that need to be verified.

[0084] In another implementation, alternatively, see [link to relevant documentation]. Figure 15 Both the comparison module 40 and the decryption module 30 are housed within the RAM macrocell 10. This arrangement minimizes the impact on the structure of the RAM control unit 20. Since the RAM control unit 20 itself needs to output control signals to the RAM macrocell 10, the wiring to provide control signals to the comparison module 40 can be routed within the RAM macrocell 10. The RAM control unit 20 only needs to additionally configure the relevant ports and wiring for receiving the alarm signal SA.

[0085] In yet another implementation, optionally, see [link to relevant documentation]. Figure 16 The decoding module 30 is located in the RAM macrocell 10, and the comparison module 40 is located in the RAM control unit 20. This arrangement of the read / write access control circuit 21 (which generates and receives control signals) and the comparison module 40 in the same unit, and the decoding circuit 11 (which generates and receives the signal to be verified) and the decoding module 30 in the same unit, facilitates signal processing.

[0086] Based on the above embodiments, optionally, since the decoding circuit 11 decodes the control signal Ctrl and the inverse decoding module 30 inverse decodes the output signal of the decoding circuit 11, both require a certain amount of time. Since the control signal Ctrl can be provided to the decoding circuit 11 and the comparison module 40 simultaneously, the timing of the comparison module 40 receiving the control signal Ctrl and the decoded signal CtrlO may be inconsistent. Therefore, a delay structure can be set to delay the transmission process of the control signal Ctrl to the comparison module 40, so that the delayed signal and the decoded signal CtrlO are transmitted synchronously to the comparison module 40 for comparison, which helps to ensure the reliability of the comparison result. The specific implementation of the delay structure will be described below.

[0087] Figure 17 This is a schematic diagram of the structure of another memory verification circuit provided in an embodiment of the present invention. See also... Figure 17 In one embodiment, the verification circuit 100 may optionally further include a delay module 50, which is connected to the comparison module 40 and receives a control signal Ctrl. The delay module 50 delays the control signal Ctrl for a preset duration before outputting it to the comparison module 40; wherein the preset duration is configured to ensure that the output signal CtrlD and the decoding signal CtrlO of the delay module 50 are transmitted synchronously to the comparison module 40. The comparator module 40 may, for example, output an alarm signal SA when the output signal CtrlD and the decoding signal CtrlO of the delay module 50 are inconsistent.

[0088] This embodiment adjusts the timing of the process of providing the control signal Ctrl to the comparison module 40 by adding a delay module 50. This ensures that the output signal CtrlD and the decoded signal CtrlO of the delay module 50 are transmitted to the comparison module 40 simultaneously for comparison, which helps to guarantee the reliability of the comparison result. For example, the preset duration can be the sum of the decoding processing time of the decoding circuit 11 and the decoding processing time of the decoding module 30; and, when there is also a transmission delay in signal transmission, the preset duration can also include the transmission delay of related signals. In short, the setting of the preset duration must ensure that the output signal CtrlD and the decoded signal CtrlO of the delay module 50 are transmitted to the comparison module 40 simultaneously.

[0089] For example, the delay module 50 can be as follows: Figure 17 The function module shown is independent of the comparison module 40; or, the delay module 50 can also be integrated into the comparison module 40 as a delay function component configured in the comparison module 40 itself.

[0090] In another implementation, alternatively, a delay module may not be provided; instead, delay adjustment can be achieved through timing control. For example, a timing-related trigger signal can be provided to the comparison module 40, triggering the comparison module 40 to perform the comparison under appropriate conditions.

[0091] In summary, the timing adjustment method can be set according to actual needs, and no specific limitations are made here.

[0092] This invention also provides a memory verification method, which is applied to the memory verification circuit provided in any embodiment of this invention and has corresponding beneficial effects. Figure 18 This is a flowchart illustrating an SRAM verification method provided in an embodiment of the present invention. See also... Figure 18 The verification method for this memory includes: S110, the decoding module decodes the output signal of the memory's decoding circuit to obtain the decoded signal.

[0093] S120 The comparison module compares the decoded signal with the control signal received by the decoding circuit and generates an alarm signal based on the comparison result.

[0094] In the memory verification method provided in this embodiment of the invention, the decoding module decodes the output signal of the decoding circuit to obtain the decoded signal, and the comparison module compares the control signal and the decoded signal, and generates an alarm signal based on the comparison result to indicate that an error has occurred in the decoding circuit. This is equivalent to monitoring the decoding circuit by verifying its output signal. By detecting faults in the decoding circuit and issuing timely alarms, the operational reliability of the memory can be effectively improved. Furthermore, when a fault exists in the memory, whether the decoding circuit is faulty can be determined based on whether the comparison module outputs an alarm signal, which helps improve fault diagnosis efficiency.

[0095] It should be noted that in the various embodiments of the memory verification circuit, specific descriptions of verification methods are provided for different verification circuits. These verification methods can all be considered as the memory verification methods provided in the embodiments of the present invention, and repeated content will not be described here.

[0096] This invention also provides a memory, including the verification circuit of the memory provided in any embodiment of this invention, which has corresponding beneficial effects. Figure 19 This is a schematic diagram of another type of memory provided in an embodiment of the present invention. See also... Figure 19For example, the memory 1000 includes a read / write access control circuit 21, a decoding circuit 11, a memory array 12, and a verification circuit 100. The memory array 12 includes multiple memory cells arranged in an array. The read / write access control circuit 21 sends a control signal Ctrl to the decoding circuit 11. The decoding circuit 11 decodes the control signal Ctrl to select the target memory cell specified by the control signal Ctrl in the memory array 12 for the read / write operation indicated by the control signal Ctrl. The verification circuit 100 includes a decoding module 30 and a comparison module 40. The decoding module 30 decodes the output signal of the decoding circuit 11 to obtain a decoded signal CtrlO. The comparison module 40 compares the decoded signal CtrlO with the control signal Ctrl received by the decoding circuit 11 and generates an alarm signal SA based on the comparison result.

[0097] Based on the above embodiments, optionally, the memory 1000 is SRAM (Static Random Access Memory). SRAM has the characteristic of being able to constantly retain data when powered on, and has the advantage of fast read and write speeds. It can be widely used in computers and other electronic devices, and is especially suitable for scenarios requiring fast data access.

[0098] It should be noted that the memory types provided above are not intended to limit the present invention. In other embodiments, the memory may also be a type of memory such as DRAM (Dynamic Random Access Memory) or FLASH (flash memory).

[0099] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is imposed herein.

[0100] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A verification circuit for a memory, characterized in that, include: A decoding module is used to connect to the decoding circuit of the memory and to decode the output signal of the decoding circuit to obtain a decoded signal; A comparison module is connected to the decoding module and is used to compare the decoded signal with the control signal received by the decoding circuit, and generate an alarm signal based on the comparison result.

2. The verification circuit for the memory according to claim 1, characterized in that, The control signals include: read / write control signals and read / write access address signals; The decoding circuit includes: The first decoding circuit is used to generate an internal read / write control signal based on the read / write control signal, and to decode the read / write access address signal to generate row selection line signals and column selection line signals. The second decoding circuit is used to decode the row selection signal to generate a word line selection signal and decode the column selection signal to generate a bit line selection signal according to the control of the internal read / write control signal.

3. The verification circuit for the memory according to claim 2, characterized in that, The decoding module is connected to the first decoding circuit, and the decoding module is used to decode the internal read / write control signal to obtain the first decoded signal. The comparison module is used to generate a first alarm signal based on the first decoded signal and the read / write control signal.

4. The verification circuit for the memory according to claim 2, characterized in that, The inverse decoding module is connected to the second decoding circuit, and the inverse decoding module is used to inverse decode the word line selection signal and the bit line selection signal to obtain the second decoded signal; The comparison module is used to generate a second alarm signal based on the second decoded signal and the read / write control signal.

5. The verification circuit for the memory according to claim 2, characterized in that, The inverse decoding module is connected to the second decoding circuit, and the inverse decoding module is used to inverse decode the word line selection signal and the bit line selection signal to obtain the third decoding signal; The comparison module is used to generate a third alarm signal based on the third decoding signal and the read / write access address signal.

6. The verification circuit for the memory according to claim 2, characterized in that, The inverse decoding module is connected to the first decoding circuit and is used to inverse decode the row selection line signal and the column selection line signal to obtain the fourth decoding signal; The comparison module is used to generate a fourth alarm signal based on the fourth decoding signal and the read / write access address signal.

7. The verification circuit for the memory according to claim 3, characterized in that, The read / write control signal includes a chip select signal and a read / write enable signal; the internal read / write control signal includes an internal chip select signal and an internal read / write enable signal; the first decoding circuit is used to generate the internal chip select signal according to the chip select signal, decode the read / write access address signal to generate the row select line signal and the column select line signal when the internal chip select signal is valid, and generate the internal read / write enable signal according to the internal chip select signal and the read / write enable signal; The decoding module is used to decode the internal chip select signal to obtain a first sub-decoding signal, and to decode the internal read / write enable signal to obtain a second sub-decoding signal. The comparison module is used to generate the first alarm signal based on the first sub-decoding signal, the chip select signal, the second sub-decoding signal, and the read / write enable signal.

8. The verification circuit of the memory according to claim 7, characterized in that, The first decoding circuit includes an input unit, a delay unit, and a read / write control unit; the delay unit is used to generate an internal delay signal, the input unit is used to generate the internal chip select signal according to the chip select signal, the clock signal, and the internal delay signal, and the read / write control unit is used to generate the internal read / write enable signal according to the internal chip select signal and the read / write enable signal; The decoding module includes: a latch, which is connected to the output of the input unit and the output of the read / write control unit, and is connected to the clock signal; the latch is used to latch the internal chip select signal and the internal read / write enable signal, and when the clock signal is at a preset level, outputs the latched internal chip select signal as the first sub-decoding signal and outputs the latched internal read / write enable signal as the second sub-decoding signal.

9. The verification circuit of the memory according to claim 7, characterized in that, The comparison module generates a first result signal based on the first sub-decoding signal and the chip select signal, generates a second result signal based on the second sub-decoding signal and the read / write enable signal, and generates the first alarm signal based on the first result signal and the second result signal.

10. The verification circuit of the memory according to claim 5, characterized in that, The decoding module includes: The encoding unit is used to decode the word line selection signal to obtain a third sub-decoding signal, and to decode the bit line selection signal to obtain a fourth sub-decoding signal. The first logic processing unit is used to concatenate the third sub-decoding signal and the fourth sub-decoding signal to obtain the third decoding signal.

11. The verification circuit for the memory according to claim 10, characterized in that, The memory array includes multiple word lines and multiple bit lines. The word line selection signal includes the level of each word line, and the bit line selection signal includes the level of each bit line. The encoding unit includes: The first decoding subunit is connected to each of the word lines and is used to decode the word line selection signal to obtain the third sub-decoding signal. The second decoding subunit is connected to each bit line and is used to decode the bit line selection signal to obtain the fourth sub-decoding signal.

12. The verification circuit for the memory according to claim 11, characterized in that, The number of decoded codes in the first decoded subunit is equal to the number of word lines, and the number of decoded codes in the second decoded subunit is equal to the number of bit lines. For any one of the first and second decoding subunits: the decoding subunit includes at least one encoder; wherein, If the number of decodes in the decoding subunit is less than or equal to the maximum number of codes in the encoder, then the decoding subunit includes one encoder, and the code output by the encoder is used as the sub-decoding signal output by the decoding subunit. If the number of decoded codes in the decoding subunit is greater than the maximum number of codes in the encoder, then the decoding subunit includes n encoders, n OR gates, and a high-order encoder; where n is the number of decoded codes in the decoding subunit divided by the maximum number of codes in the encoder and rounded up; the input of each OR gate is connected to the output of each encoder, and the output of each OR gate is connected to the high-order encoder; the code output by the encoder connected to the selected word line or bit line is used as the low-order address, the OR gate generates an encoder block selection signal based on the code output by the encoder, the high-order encoder generates a high-order address based on each encoder block selection signal, and the high-order address and the low-order address are concatenated as the sub-decoding signal output by the decoding subunit.

13. The verification circuit for the memory according to claim 6, characterized in that, The decoding module includes: The second logic processing unit is used to concatenate the row selection line signal and the column selection line signal to obtain the fourth decoding signal.

14. The verification circuit of the memory according to any one of claims 1-13, characterized in that, The memory further includes: a RAM control unit and RAM macrocells; the RAM control unit is provided with a read / write access control circuit, which provides the control signals; the decoding circuit is disposed in the RAM macrocells; wherein... Both the comparison module and the decoding module are located in the RAM control unit; Alternatively, both the comparison module and the decoding module can be located within the RAM macrocell; Alternatively, the decoding module may be located in the RAM macrocell, and the comparison module may be located in the RAM control unit.

15. The verification circuit of the memory according to any one of claims 1-13, characterized in that, Also includes: A delay module is connected to the comparison module and receives the control signal; The delay module is used to delay the control signal for a preset duration before outputting it to the comparison module; wherein, the preset duration is configured to ensure that the output signal of the delay module and the decoded signal are transmitted to the comparison module synchronously.

16. A method for verifying a memory, characterized in that, A verification circuit applied to the memory according to any one of claims 1-15; the method includes: The decoding module decodes the output signal of the memory's decoding circuit to obtain the decoded signal; The comparison module compares the decoded signal with the control signal received by the decoding circuit and generates an alarm signal based on the comparison result.

17. A memory, characterized in that, The memory includes a verification circuit according to any one of claims 1-15.

18. The memory according to claim 17, characterized in that, The memory is SRAM.

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