Active neutral-point-clamped three-level inverter, control method and device
By controlling the switching bridge arm and the midpoint clamping transistor, the conduction time of the switching transistors in the active midpoint clamped three-level inverter is balanced, which solves the problem of uneven heating caused by uneven conduction time and reduces the risk of thermal failure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUNGROW POWER SUPPLY CO LTD
- Filing Date
- 2024-10-28
- Publication Date
- 2026-04-28
AI Technical Summary
The control of existing active midpoint clamped three-level inverters results in uneven switching transistor conduction times, leading to uneven heating and a risk of overheating failure.
By controlling the switching bridge arm and the midpoint clamping transistor, the inverter includes levels 0+ and 0- in a single cycle, and alternates between different level transition states in the first and second half of the cycle, thus balancing the conduction time of each switching transistor.
This achieves balanced conduction time of the switching transistors, reduces the risk of thermal failure, avoids severe overheating of a single switching transistor, and protects all switching transistors.
Smart Images
Figure CN121939833A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power electronics technology, specifically to an active neutral-point clamped three-level inverter, its control method, and its device. Background Technology
[0002] An active neutral point clamped three-level inverter (ANPC) has three AC output voltage levels: +1, 0, and -1. The ANPC bridge arms include a first, second, third, and fourth switch connected in series, as well as two clamping switches, namely the fifth and sixth switches.
[0003] In related technologies, the control of ANPC can lead to uneven conduction time of the switching transistors, which may result in uneven heating and pose a risk of overheating failure. Summary of the Invention
[0004] In view of this, this application provides an active midpoint clamped three-level inverter, a control method and device, which can balance the conduction time of the switching transistors and reduce the risk of thermal failure.
[0005] This application provides an active midpoint clamped three-level inverter, comprising: a switch bridge arm, a midpoint clamping transistor, and a controller; the switch bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series; the midpoint clamping transistor includes a fifth switch and a sixth switch; the first end of the fifth switch is connected to the common terminal of the first and second switches, the second end of the fifth switch is connected to the midpoint, the first end of the sixth switch is connected to the midpoint, and the second end of the sixth switch is connected to the common terminal of the third and fourth switches; the controller is used to control the switches of the switch bridge arm and the midpoint clamping transistor, so that the inverter level includes a level 0+ and a level 0- in a single cycle; 0+ refers to the fifth and second switches being turned on, and 0- refers to the sixth and fourth switches being turned on.
[0006] Preferably, the controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the inverter level includes level 0+ and level 0- in the upper half cycle and level 0+ and level 0- in the lower half cycle; or, to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the inverter level includes level 0+ in the upper half cycle and level 0- in the lower half cycle.
[0007] Preferably, the controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the inverter level has a first level transition state in the first half cycle and a second level transition state in the second half cycle. The first level transition state includes +1, 0+, -1, 0+ and +1 in sequence; the second level transition state includes +1, 0-, -1, 0- and +1 in sequence.
[0008] Preferably, the controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the level of the inverter in the first half cycle includes the first level transition state, the third level transition state and the first level transition state in sequence; the third level transition state includes +1, 0+ and +1 in sequence.
[0009] Preferably, the controller is configured to, during the first half-cycle, control the first switch or the sixth switch based on a comparison result of the carrier and the upmodulation wave in the dual modulation wave, wherein the switching state of the fourth switch is complementary to that of the first switch, and the switching state of the sixth switch is complementary to that of the fifth switch; and to control the second switch based on a comparison result of the carrier and the downmodulation wave in the dual modulation wave, wherein the switching state of the third switch is complementary to that of the second switch.
[0010] Preferably, the controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the level of the inverter in the second half cycle includes the second level transition state, the fourth level transition state and the second level transition state in sequence; the fourth level transition state includes 0-, -1 and 0- in sequence.
[0011] Preferably, the controller is configured to, during the second half-cycle, control the second switch transistor according to a comparison result of the carrier wave and the upmodulation wave in the dual modulation wave, wherein the switching state of the third switch transistor is complementary to that of the second switch transistor; and to control the first switch transistor or the sixth switch transistor according to a comparison result of the carrier wave and the downmodulation wave in the dual modulation wave, wherein the switching state of the fourth switch transistor is complementary to that of the first switch transistor, and the switching state of the sixth switch transistor is complementary to that of the fifth switch transistor.
[0012] Preferably, the controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the inverter level has a fifth level transition state in the first half cycle and a sixth level transition state in the second half cycle. The fifth level transition state includes -1, 0+, +1, 0+ and -1 in sequence; the sixth level transition state includes -1, 0-, +1, 0- and -1 in sequence.
[0013] Preferably, the controller is used to control the switching transistors of the switching bridge arm and the midpoint clamping transistor, so that the inverter level in the first half-cycle sequentially includes the fifth level transition state, the seventh level transition state, and the fifth level transition state; the seventh level transition state sequentially includes: 0+, +1, and 0+; the controller is used to control the switching transistors of the switching bridge arm and the midpoint clamping transistor, so that the inverter level in the second half-cycle sequentially includes the sixth level transition state, the eighth level transition state, and the sixth level transition state; the eighth level transition state sequentially includes: -1, 0-, and -1.
[0014] Preferably, the controller is configured to control the fourth and sixth switches to turn off when the second switch is turned on; and to control the first and fifth switches to turn off when the third switch is turned on.
[0015] This application also provides a control method for an active midpoint clamped three-level inverter, the inverter comprising: a switching bridge arm and a midpoint clamping transistor; the switching bridge arm comprises a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor connected in series; the midpoint clamping transistor comprises a fifth switching transistor and a sixth switching transistor; the first end of the fifth switching transistor is connected to the common terminal of the first switching transistor and the second switching transistor, the second end of the fifth switching transistor is connected to the midpoint, the first end of the sixth switching transistor is connected to the midpoint, and the second end of the sixth switching transistor is connected to the common terminal of the third switching transistor and the fourth switching transistor; the method comprises: controlling the switching transistors of the switching bridge arm and the midpoint clamping transistor so that the inverter level includes a level 0+ and a level 0- within a single modulation wave cycle; the 0+ refers to the fifth switching transistor and the second switching transistor being turned on, and the 0- refers to the sixth switching transistor and the fourth switching transistor being turned on.
[0016] Preferably, controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's voltage level include level 0+ and level 0- within a single modulation wave cycle includes: controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's voltage level include level 0+ and level 0- in the first half-cycle and level 0+ and level 0- in the second half-cycle; or, controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's voltage level include level 0+ in the first half-cycle and level 0- in the second half-cycle.
[0017] Preferably, controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's level include level 0+ and level 0- within a single modulation wave cycle includes: controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's level exhibit a first level transition state and a second level transition state, wherein the first level transition state sequentially includes: +1, 0+, -1, 0+, and +1; and the second level transition state sequentially includes: +1, 0-, -1, 0-, and +1.
[0018] Preferably, controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's level exhibit a first level transition state in the first half-cycle includes: controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's level sequentially include the first level transition state, the third level transition state, and the first level transition state in the first half-cycle; the third level transition state sequentially includes: +1, 0+, and +1.
[0019] Preferably, controlling the switching transistors of the switching bridge arm and the midpoint clamping transistor to make the inverter's level sequentially include a first level transition state, a third level transition state, and a first level transition state in the upper half-cycle includes: in the upper half-cycle, controlling the first switching transistor or the sixth switching transistor according to the comparison result of the carrier wave and the upper modulation wave in the dual modulation wave, wherein the switching state of the fourth switching transistor is complementary to that of the first switching transistor, and the switching state of the sixth switching transistor is complementary to that of the fifth switching transistor; controlling the second switching transistor according to the comparison result of the carrier wave and the lower modulation wave in the dual modulation wave, wherein the switching state of the third switching transistor is complementary to that of the second switching transistor.
[0020] Preferably, controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to cause the inverter's level to exhibit a second level transition state in the second half-cycle includes: controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to cause the inverter's level to sequentially include a second level transition state, a fourth level transition state, and a second level transition state in the second half-cycle; the fourth level transition state sequentially includes: 0-, -1, and 0-.
[0021] Preferably, controlling the switching transistors of the switching bridge arm and the midpoint clamping transistor to make the inverter level sequentially include the second level transition state, the fourth level transition state, and the second level transition state in the second half-cycle includes: in the second half-cycle, controlling the second switching transistor according to the comparison result of the carrier wave and the upper modulation wave in the dual modulation wave, wherein the switching state of the third switching transistor is complementary to that of the second switching transistor; controlling the first switching transistor or the sixth switching transistor according to the comparison result of the carrier wave and the lower modulation wave in the dual modulation wave, wherein the switching state of the fourth switching transistor is complementary to that of the first switching transistor, and the switching state of the sixth switching transistor is complementary to that of the fifth switching transistor.
[0022] Preferably, controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's level include level 0+ and level 0- within a single modulation wave cycle includes: controlling the switching transistor of the switching bridge arm and the midpoint clamping transistor to make the inverter's level exhibit a fifth level transition state in the first half of the cycle and a sixth level transition state in the second half of the cycle. The fifth level transition state sequentially includes: -1, 0+, +1, 0+, and -1; the sixth level transition state sequentially includes: -1, 0-, +1, 0-, and -1.
[0023] Preferably, controlling the switching transistors of the switching bridge arm and the midpoint clamping transistor to cause the inverter's voltage level to enter a fifth level transition state in the first half-cycle includes: the controller, used to control the switching transistors of the switching bridge arm and the midpoint clamping transistor, so that the inverter's voltage level in the first half-cycle sequentially includes the fifth level transition state, the seventh level transition state, and the fifth level transition state; the seventh level transition state sequentially includes: 0+, +1, and 0+; controlling the switching transistors of the switching bridge arm and the midpoint clamping transistor to enter a sixth level transition state in the second half-cycle includes: the controller, used to control the switching transistors of the switching bridge arm and the midpoint clamping transistor, so that the inverter's voltage level in the second half-cycle sequentially includes the sixth level transition state, the eighth level transition state, and the sixth level transition state; the eighth level transition state sequentially includes: -1, 0-, and -1.
[0024] Preferably, causing the inverter's voltage level to exhibit a first voltage level transition state and a second voltage level transition state includes: controlling the fourth and sixth switches to turn off when the second switch is turned on; and controlling the first and fifth switches to turn off when the third switch is turned on.
[0025] This application provides a control device, including a processor and a memory, wherein the memory is used to store programs, instructions or code, and the processor is used to execute the programs, instructions or code in the memory to perform the control method described above.
[0026] This application provides a computer-readable storage medium storing a computer program, which is loaded by a processor to execute the control method described above.
[0027] The ANPC provided in this application embodiment has a level 0+ state in the first half cycle and a level 0- state in the second half cycle. Since the fifth and second switches are turned on in the 0+ state and the sixth and third switches are turned on in the 0- state, the sixth switch is not always off. This scheme can achieve a balance in the conduction time of the fifth and sixth switches, and will not result in a situation where one switch overheats severely while another does not, thereby protecting each switch and reducing the risk of thermal failure. Attached Figure Description
[0028] Figure 1A A schematic diagram of an active neutral-point clamped three-level inverter provided in this application embodiment;
[0029] Figure 1B A schematic diagram showing an ANPC with a voltage level of +1 provided in an embodiment of this application;
[0030] Figure 1C A schematic diagram showing an ANPC level of 0 provided in an embodiment of this application;
[0031] Figure 1D A schematic diagram showing an ANPC with a voltage level of -1 provided in an embodiment of this application;
[0032] Figure 2 A schematic diagram of yet another ANPC provided in this application embodiment;
[0033] Figure 3 This application provides a schematic diagram of an ANPC with a voltage level of 0-.
[0034] Figure 4 The waveform diagram of the three-phase original modulation wave of ANPC;
[0035] Figure 5 The waveforms of the maximum and minimum values of the three-phase original modulated wave are shown.
[0036] Figure 6 The waveforms of the maximum and minimum values of the three-phase original modulated wave are shown.
[0037] Figure 7 Waveform diagram of another dual-modulation wave provided in this application;
[0038] Figure 8 Waveform diagrams of the original modulated wave and the dual modulated wave provided in this application;
[0039] Figure 9 A level state diagram of ANPC using dual modulation waves is provided in an embodiment of this application;
[0040] Figure 10 for Figure 9 A schematic diagram of the modulation scheme for region 1;
[0041] Figure 11 for Figure 9 A schematic diagram of the modulation scheme for region 3;
[0042] Figure 12 for Figure 9 A schematic diagram of the modulation scheme for region 4;
[0043] Figure 13 for Figure 9 A schematic diagram of the modulation scheme for region 2;
[0044] Figure 14A Another ANPC level state diagram using dual-modulation waves is provided as an embodiment of this application;
[0045] Figure 14B for Figure 14A A schematic diagram of the modulation scheme for region 1;
[0046] Figure 14C for Figure 14A A schematic diagram of the modulation scheme for region 3;
[0047] Figure 14D for Figure 14A A schematic diagram of the modulation scheme for region 4;
[0048] Figure 14E for Figure 14A A schematic diagram of the modulation scheme for region 2;
[0049] Figure 15 This is a schematic diagram of a control device provided in an embodiment of this application. Detailed Implementation
[0050] To enable those skilled in the art to better understand and implement the technical solutions provided in the embodiments of this application, the topology of the active neutral-point clamped three-level inverter will be described below in conjunction with the accompanying drawings.
[0051] See Figure 1A This figure is a schematic diagram of an active neutral-point clamped three-level inverter provided in an embodiment of this application.
[0052] For ease of description, the following description uses only a single-phase topology of the ANPC. It should be understood that the ANPC can also be three-phase, and the three-phase topology is the same. The active neutral-point clamped three-level inverter provided in this application includes: a switching bridge arm and a neutral-point clamping transistor.
[0053] The switch bridge arm includes a first switch transistor T1, a second switch transistor T2, a third switch transistor T3, and a fourth switch transistor T4 connected in series. The first end of the first switch transistor T1 is connected to the positive DC terminal, the second end of the first switch transistor T1 is connected to the first end of the second switch transistor T2, the second end of the second switch transistor T2 is connected to the first end of the third switch transistor T3, the second end of the third switch transistor T3 is connected to the first end of the fourth switch transistor T4, and the second end of the fourth switch transistor T4 is connected to the negative DC terminal.
[0054] In this configuration, the first terminal of the first capacitor C1 is connected to the positive DC terminal, the second terminal of the first capacitor C1 is connected to the midpoint O (i.e., neutral point O), the first terminal of the second capacitor C2 is connected to the midpoint O, and the second terminal of the second capacitor C2 is connected to the negative DC terminal.
[0055] The midpoint clamping transistors include a fifth switch T5 and a sixth switch T6. The first terminal of the fifth switch T5 is connected to the common terminal of the first switch T1 and the second switch T2, and the second terminal of the fifth switch T5 is connected to the midpoint O. The first terminal of the sixth switch T6 is connected to the midpoint O, and the second terminal of the sixth switch T6 is connected to the common terminal of the third switch T3 and the fourth switch T4. Switches T5-T6 also have anti-parallel diodes, namely D1-D6.
[0056] To facilitate understanding, the three-level circuit is explained below with reference to the accompanying diagram. The three-level circuit includes +1, 0, and -1.
[0057] See Figure 1B The figure is a schematic diagram of an ANPC with a level of +1 provided in an embodiment of this application.
[0058] from Figure 1B It can be seen that when T1 and T2 are on, the ANPC level is +1. If T6 is also on when T1 and T2 are on, then T6 is in a meaningless on-state, with no current flowing through it. This unnecessarily increases the on-time of T6, increasing its losses and heat generation. Moreover, the ANPC's control over T6 increases control complexity and wastes the controller's control logic.
[0059] See Figure 1C The figure is a schematic diagram of an ANPC with a voltage level of 0 provided in an embodiment of this application.
[0060] from Figure 1CIt can be seen that when T5 and T2 are on, the level of ANPC is 0. If T4 is also on when T5 and T2 are on, then T4 is in a meaningless on state, with no current flowing through it. This unnecessarily increases the on-time of T4, increasing its power loss and heat generation.
[0061] See Figure 1D The figure is a schematic diagram of an ANPC with a level of -1 provided in an embodiment of this application.
[0062] from Figure 1D It can be seen that when T3 and T4 are on, the level of ANPC is -1. If T5 is also on when T3 and T4 are on, then T5 is in a meaningless on state, with no current flowing through it. This unnecessarily increases the on-time of T5, increasing its power loss and heat generation.
[0063] As shown in the diagram above, a 0-level signal corresponds only to the 0+ state, not the 0- state. The 0- state means that T6 and T3 are turned on, while other switches are turned off. Furthermore, in traditional technology, T6 is never turned on and hardly flows any current, so it does not heat up. However, T5 operates more frequently, and its losses and heat generation are greater than T6's. Therefore, it is prone to uneven switching losses and heat generation, posing a risk of overheating failure.
[0064] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0065] See Figure 2 This figure is a schematic diagram of another type of ANPC provided in the embodiments of this application.
[0066] In this embodiment of the application, in order to balance the conduction time and power consumption of each switch, the controller controls the switching state of each switch, so that the ANPC operates in the +1, 0+, 0- and -1 level states.
[0067] The active midpoint clamped three-level inverter provided in this application embodiment includes: a switching bridge arm, a midpoint clamping transistor, and a controller 100.
[0068] The switch bridge arm includes a first switch tube T1, a second switch tube T2, a third switch tube T3, and a fourth switch tube T4 connected in series; the midpoint clamping tube includes a fifth switch tube T5 and a sixth switch tube T6; the first end of the fifth switch tube T5 is connected to the common end of the first switch tube T1 and the second switch tube T2, and the second end of the fifth switch tube T5 is connected to the midpoint O; the first end of the sixth switch tube T6 is connected to the midpoint O, and the second end of the sixth switch tube T6 is connected to the common end of the third switch tube T3 and the fourth switch tube T4.
[0069] The controller 100 is used to control the switching transistors and the midpoint clamping transistors of the switching bridge arm, so that the inverter level includes level 0+ and level 0- within a single modulation wave cycle; 0+ means that the fifth switching transistor T5 and the second switching transistor T2 are turned on, and 0- means that the sixth switching transistor T6 and the fourth switching transistor T4 are turned on.
[0070] This application does not specifically limit the exact timing of the occurrence of 0+ and 0-. They can occur simultaneously, or separately in the first and second halves of the cycle. For example, the controller 100 controls the switching transistors and midpoint clamping transistors of the switching bridge arm, so that the inverter's voltage level includes both 0+ and 0- in the first half of the cycle, i.e., the fifth switch T5, the second switch T2, the sixth switch T6, and the fourth switch T4 are simultaneously turned on, while the other switches are turned off. The second half of the cycle includes both 0+ and 0-, i.e., the fifth switch T5, the second switch T2, the sixth switch T6, and the fourth switch T4 are simultaneously turned on, while the other switches are turned off. Alternatively, the controller can control the switching transistors and midpoint clamping transistors of the switching bridge arm, so that the inverter's voltage level includes 0+ in the first half of the cycle and 0- in the second half of the cycle.
[0071] For a better understanding of the 0- state, please refer to [link / reference]. Figure 3 0- means that T6 and T3 are turned on, and all other switches are turned off. In order to balance the conduction time of T5 and T6, the ANPC provided in this application embodiment not only has a level 0+, but also a level 0-.
[0072] The ANPC provided in this application embodiment has a level 0+ state and a level 0- state in a single cycle. Since the fifth and second switches are turned on in the 0+ state and the sixth and third switches are turned on in the 0- state, the sixth switch is not always off. This solution can achieve a balance in the on-time of the fifth and sixth switches, and will not result in a situation where one switch overheats severely while another does not, thereby protecting each switch and reducing the risk of thermal failure.
[0073] To prevent T6 from being in a meaningless conduction state, this application forces T6 to turn off when T2 is on. To prevent T4 from being in a meaningless conduction state, this application forces T4 to turn off when T2 is on. To prevent T5 from being in a meaningless conduction state, this application forces T5 to turn off when T3 is on.
[0074] For ease of description, the following description uses the dual-modulation wave modulation method of the ANPC provided in the embodiment of this application.
[0075] See Figure 4 The figure shows the waveform of the three-phase original modulation wave of ANPC.
[0076] Taking ANPC as an example of a three-phase inverter, Figure 4 The diagram shows the three-phase original modulation waves, which are generally sine waves and can be referred to as the three-phase sinusoidal modulation waves Ua, Ub, and Uc. They can be represented by the following expressions.
[0077] U x (x = a, b, c represent phases A, B, and C)
[0078]
[0079] In the formula, Um represents the phase voltage amplitude, and ω represents the angular frequency. Indicates phase.
[0080] The dual-modulation wave is obtained by taking the maximum and minimum values of the three-phase original modulation wave. To facilitate understanding of the dual-modulation wave, the maximum and minimum values of the three-phase original modulation wave are introduced below.
[0081] See Figure 5 The figure shows the waveforms of the maximum and minimum values of the three-phase original modulated wave.
[0082] Figure 5 The image shown is from Figure 4 The waveforms corresponding to the maximum and minimum values of the three-phase original modulated wave are obtained.
[0083] Three-phase original modulation wave U x The maximum value U in (x = a, b, c) max =Max(U a U b U c ), minimum value U min =Min(U a U b U c ).
[0084] See Figure 6 The figure shows a waveform of a dual-modulation wave provided in this application.
[0085] Dual-modulated waves include up-modulated wave U xpos and downmodulated wave U xneg The upper and lower modulated waves are obtained from the three-phase original modulated waves and their corresponding maximum and minimum values, which can be derived from the minimum value U. min It can also be determined by the maximum value U. max get, Figure 6 The upmodulated wave shown is composed of the three-phase original modulated wave and the minimum value U. min The down-modulated wave is obtained by combining the three-phase original modulated wave and the maximum value U. max You can obtain it using the following expression.
[0086]
[0087] See Figure 7 The figure shows a waveform of another dual-modulation wave provided in this application.
[0088] Figure 7 The upper modulated wave shown is composed of the three-phase original modulated wave and the maximum value U. max The downmodulated wave is obtained by combining the three-phase original modulated wave and the minimum value U. min You can obtain it using the following expression.
[0089]
[0090] For ease of explanation, the following will use... Figure 6 The modulation method provided in this application is illustrated using the dual-modulation wave as an example.
[0091] To facilitate the analysis of the original modulated wave and the dual modulated wave, the original modulated wave, the upmodulated wave, and the downmodulated wave are placed in the same figure.
[0092] See Figure 8 The figure shows the waveforms of the original modulated wave and the dual modulated wave provided in this application.
[0093] Taking phase A as an example, when the original modulation wave U of phase A... a When U ≥ 0, it is called the upper half-cycle region; when U a When <0, it is called the lower half of the cycle region.
[0094] The ANPC provided in this application introduces a division of the upper half-cycle region and the lower half-cycle region based on the original modulation wave.
[0095] For ease of understanding, the following will use... Figure 6 The dual-modulation scheme shown illustrates the level state of the ANPC in this application within one cycle.
[0096] See Figure 9 The figure is a level state diagram of an ANPC using dual modulation waves provided in an embodiment of this application.
[0097] Figure 9 It can be seen that within a cycle, the first half of the cycle is divided into regions 3, 1, and 3. The second half of the cycle is divided into regions 4, 2, and 4.
[0098] use Figure 6 The dual-modulation waveform shown specifically involves controller 110 controlling the switching transistors and midpoint clamping transistors of the switching bridge arm, causing the inverter's voltage level to exhibit a first voltage level transition state in the first half-cycle and a second voltage level transition state in the second half-cycle. The first voltage level transition states sequentially include: +1, 0+, -1, 0+, and +1; the second voltage level transition states sequentially include: +1, 0-, -1, 0-, and +1.
[0099] The first level transition state corresponds to Figure 9 Region 3 in the middle corresponds to the second level transition state. Figure 9 Region 4 in the middle.
[0100] The controller 110 is used to control the switching transistors and the midpoint clamping transistors of the switching bridge arm, so that the inverter level in the first half cycle includes a first level transition state, a third level transition state, and a first level transition state in sequence; the third level transition state includes +1, 0+, and +1 in sequence.
[0101] The third level transition state corresponds to Figure 9 Region 1 in the middle.
[0102] use Figure 6 In the dual-modulation wave mode shown, specifically, the controller 110 is used to control the first switch T1 or the sixth switch T6 in the first half-cycle according to the comparison result of the carrier wave and the up-modulation wave in the dual-modulation wave. The switching state of the fourth switch T4 is complementary to that of the first switch T1, and the switching state of the sixth switch T6 is complementary to that of the fifth switch T5. The controller 110 controls the second switch T2 according to the comparison result of the carrier wave and the down-modulation wave in the dual-modulation wave. The switching state of the third switch T3 is complementary to that of the second switch T2.
[0103] The controller 110 is used to control the switching transistors and the midpoint clamping transistors of the switching bridge arm, so that the inverter level in the second half cycle includes the second level transition state, the fourth level transition state, and the second level transition state in sequence; the fourth level transition state includes 0-, -1, and 0- in sequence.
[0104] The fourth level transition state corresponds to Figure 9 Region 2 in the middle.
[0105] use Figure 6 In the dual-modulation wave mode shown, specifically, the controller 110 is used to control the second switch T2 in the second half-cycle according to the comparison result of the carrier and the upmodulation wave in the dual-modulation wave, and the switching state of the third switch T3 is complementary to that of the second switch T2; and to control the first switch T1 or the sixth switch T6 according to the comparison result of the carrier and the downmodulation wave in the dual-modulation wave, and the switching state of the fourth switch T4 is complementary to that of the first switch T1, and the switching state of the sixth switch T6 is complementary to that of the fifth switch T5.
[0106] The status of the switching transistors in each region is described below with reference to the attached diagram. Figures 10-13 In the diagram, uaneg+1 indicates that the down-modulated wave is shifted up by 1 unit. Since it's inconvenient for the controller to process negative numbers, the down-modulated wave is converted to a positive number for processing. uapos represents the up-modulated wave of phase A. The triangular wave is the carrier wave. The modulated wave is compared with the carrier wave, and the state of each switch is controlled based on the comparison result.
[0107] See Figure 10 The image is Figure 9 A schematic diagram of the modulation method for the corresponding region 1.
[0108] from Figure 10 As can be seen, region 1 includes two voltage levels: +1 (i.e., P) and 0+, corresponding to the third voltage transition state, which is +1, 0+, and +1 in sequence. +1 corresponds to T1 and T2 being turned on while the other switches are turned off. 0+ corresponds to T2 and T5 being turned on while the other switches are turned off.
[0109] See Figure 11 The image is Figure 9 A schematic diagram of the modulation method for the corresponding region 3.
[0110] from Figure 11 As can be seen, region 3 includes three voltage levels: +1, 0+, and -1 (i.e., N), corresponding to the first voltage transition state, namely +1, 0+, -1, 0+, and +1 in sequence. +1 corresponds to T1 and T2 being on while the other switches are off. 0+ corresponds to T2 and T5 being on while the other switches are off. -1 corresponds to T3 and T4 being on while the other switches are off.
[0111] See Figure 12 The image is Figure 9 A schematic diagram of the modulation scheme for region 4.
[0112] from Figure 12 As can be seen, region 4 includes three voltage levels: +1, 0-, and -1, corresponding to the second voltage level transition states, namely +1, 0-, -1, 0-, and +1 in sequence. +1 corresponds to T1 and T2 being on while the other switches are off. 0- corresponds to T3 and T6 being on while the other switches are off. -1 corresponds to T3 and T4 being on while the other switches are off.
[0113] See Figure 13 The image is Figure 9 A schematic diagram of the modulation method for the corresponding region 2.
[0114] from Figure 13 It can be seen that region 2 includes two level states -1 and 0-, corresponding to the fourth level transition state, namely 0-, -1 and 0- in sequence. 0- corresponds to T6 and T3 being turned on and the other switches being turned off. -1 corresponds to T3 and T4 being turned on and the other switches being turned off.
[0115] It should be understood that Figures 9-13 Only Figure 6 The control method shown is based on the dual-modulation wave example. Additionally, it can also utilize... Figure 7 The dual-modulation wave shown is used to modulate the drive signals of each switching transistor. Utilizing... Figure 7When using the dual-modulation wave control shown, specifically, controller 110 controls the switching transistors and midpoint clamping transistors of the switching bridge arm, causing the inverter's level to exhibit a fifth-level transition state in the first half-cycle and a sixth-level transition state in the second half-cycle. The fifth-level transition states sequentially include: -1, 0+, +1, 0+, and -1; the sixth-level transition states sequentially include: -1, 0-, +1, 0-, and -1. The controller controls the switching transistors and midpoint clamping transistors of the switching bridge arm, causing the inverter's level to sequentially include a fifth-level transition state, a seventh-level transition state, and a fifth-level transition state in the first half-cycle; the seventh-level transition state sequentially includes: 0+, +1, and 0+. The controller controls the switching transistors and midpoint clamping transistors of the switching bridge arm, causing the inverter's level to sequentially include a sixth-level transition state, an eighth-level transition state, and a sixth-level transition state in the second half-cycle; the eighth-level transition state sequentially includes: -1, 0-, and -1.
[0116] The following section, with reference to the accompanying diagram, introduces another method for implementing double-adjusted waveforms.
[0117] See Figure 14A This figure is another level state diagram of ANPC using dual modulation waves provided in an embodiment of this application.
[0118] Figure 14A It can be seen that within a cycle, the first half of the cycle is divided into regions 3, 1, and 3. The second half of the cycle is divided into regions 4, 2, and 4.
[0119] See Figure 14B The image is Figure 14A A schematic diagram of the modulation method for the corresponding region 1.
[0120] from Figure 14B As can be seen, region 1 includes two voltage levels, 0+ and +1, corresponding to the seventh voltage level transition states, namely 0+, +1, and 0+. 0+ corresponds to T5 and T2 being on while the other switches are off. +1 corresponds to T2 and T1 being on while the other switches are off.
[0121] See Figure 14C The image is Figure 14A A schematic diagram of the modulation method for the corresponding region 3.
[0122] from Figure 14C As can be seen, region 3 includes three voltage levels: -1, 0+, and +1, corresponding to the fifth voltage level transition state, namely -1, 0+, +1, 0+, and -1 in sequence. -1 corresponds to T3 and T4 being on while the other switches are off. 0+ corresponds to T2 and T5 being on while the other switches are off. +1 corresponds to T1 and T2 being on while the other switches are off.
[0123] See Figure 14D The image is Figure 14A A schematic diagram of the modulation scheme for region 4.
[0124] from Figure 14D As can be seen, region 4 includes three voltage levels: -1, 0-, and +1, corresponding to the sixth voltage level transition state, namely -1, 0-, +1, 0-, and -1 in sequence. -1 corresponds to T3 and T4 being on while the other switches are off. 0- corresponds to T3 and T6 being on while the other switches are off. +1 corresponds to T1 and T2 being on while the other switches are off.
[0125] See Figure 14E The image is Figure 14A A schematic diagram of the modulation method for the corresponding region 2.
[0126] from Figure 14E As can be seen, region 2 includes two voltage levels, 0- and -1, corresponding to the eighth voltage level transition states, namely -1, 0-, and -1. 0- corresponds to T3 and T6 being on while the other switches are off. -1 corresponds to T3 and T4 being on while the other switches are off.
[0127] from Figures 10-14E The conduction status of each switch shown demonstrates that the ANPC provided in this embodiment includes both 0+ and 0- throughout the entire cycle, and there are no switches that conduct without meaning. For example, when T2 is on, T4 and T6 are forcibly turned off. When T3 is on, T1 and T5 are forcibly turned off. This embodiment can achieve balanced conduction of each switch, thereby ensuring even heating of each switch and preventing some switches from remaining off while others conduct for excessively long periods. This reduces the risk of thermal failure caused by uneven heating.
[0128] Based on the active neutral-point clamped three-level inverter provided in the above embodiments, this application also provides a control method for the active neutral-point clamped three-level inverter, which will be described in detail below.
[0129] The control method for an active midpoint clamped three-level inverter provided in this application embodiment includes an inverter comprising: a switch bridge arm and a midpoint clamping transistor; the switch bridge arm comprises a first switch, a second switch, a third switch, and a fourth switch connected in series; the midpoint clamping transistor comprises a fifth switch and a sixth switch; the first end of the fifth switch is connected to the common end of the first and second switches, the second end of the fifth switch is connected to the midpoint, the first end of the sixth switch is connected to the midpoint, and the second end of the sixth switch is connected to the common end of the third and fourth switches;
[0130] The method includes controlling the switching transistors and midpoint clamping transistors of the switching bridge arm so that the inverter level includes level 0+ and level 0- within a single modulation wave cycle; 0+ refers to the fifth and second switching transistors being turned on, and 0- refers to the sixth and fourth switching transistors being turned on.
[0131] The ANPC provided in this application embodiment has a level 0+ state in the first half cycle and a level 0- state in the second half cycle. Since the fifth and second switches are turned on in the 0+ state and the sixth and third switches are turned on in the 0- state, the sixth switch is not always off. This scheme can achieve a balance in the conduction time of the fifth and sixth switches, and will not result in a situation where one switch overheats severely while another does not, thereby protecting each switch and reducing the risk of thermal failure.
[0132] One possible implementation involves controlling the switching transistors and midpoint clamping transistors of the switching bridge arm so that the inverter's voltage level includes both level 0+ and level 0- within a single modulation wave cycle. This includes: controlling the switching transistors and midpoint clamping transistors of the switching bridge arm so that the inverter's voltage level includes both level 0+ and level 0- in the first half-cycle and level 0+ and level 0- in the second half-cycle; or, controlling the switching transistors and midpoint clamping transistors of the switching bridge arm so that the inverter's voltage level includes level 0+ in the first half-cycle and level 0- in the second half-cycle.
[0133] One possible implementation involves controlling the switching transistors and midpoint clamping transistors of the switching bridge arm to make the inverter's voltage level include levels 0+ and 0- within a single modulation wave cycle. This includes controlling the switching transistors and midpoint clamping transistors of the switching bridge arm to cause the inverter's voltage level to exhibit a first voltage level transition state and a second voltage level transition state. The first voltage level transition state sequentially includes: +1, 0+, -1, 0+, and +1; the second voltage level transition state sequentially includes: +1, 0-, -1, 0-, and +1.
[0134] One possible implementation involves controlling the switching transistors and midpoint clamping transistors of the switching bridge arm to cause the inverter's voltage level to transition to a first level transition state in the first half-cycle, including:
[0135] The switching transistors and midpoint clamping transistors of the control switch bridge arm ensure that the inverter's voltage levels in the first half-cycle sequentially include a first voltage level transition state, a third voltage level transition state, and a first voltage level transition state; the third voltage level transition state sequentially includes +1, 0+, and +1.
[0136] One possible implementation involves controlling the switching transistors and midpoint clamping transistors of the switching bridge arm so that the inverter's voltage level sequentially includes a first voltage level transition state, a third voltage level transition state, and a first voltage level transition state in the first half-cycle. This includes: in the first half-cycle, controlling either the first or sixth switching transistor based on the comparison result between the carrier wave and the upmodulation wave in the dual modulation wave, with the fourth switching transistor having a complementary switching state to the first switching transistor, and the sixth switching transistor having a complementary switching state to the fifth switching transistor; and controlling the second switching transistor based on the comparison result between the carrier wave and the downmodulation wave in the dual modulation wave, with the third switching transistor having a complementary switching state to the second switching transistor.
[0137] One possible implementation involves controlling the switching transistors and midpoint clamping transistors of the switching bridge arm to cause the inverter's voltage level to enter a second voltage level transition state in the second half-cycle. This includes controlling the switching transistors and midpoint clamping transistors of the switching bridge arm to cause the inverter's voltage level to sequentially include a second voltage level transition state, a fourth voltage level transition state, and a second voltage level transition state in the second half-cycle. The fourth voltage level transition state sequentially includes: 0-, -1, and 0-.
[0138] One possible implementation involves controlling the switching transistors and midpoint clamping transistors of the switching bridge arm so that the inverter's voltage level sequentially includes a second voltage level transition state, a fourth voltage level transition state, and a second voltage level transition state in the second half-cycle. This includes: in the first half-cycle, controlling the second switching transistor based on the comparison result of the carrier wave and the upper modulation wave in the dual modulation wave, with the third switching transistor having a complementary switching state to the second switching transistor; controlling the first switching transistor or the sixth switching transistor based on the comparison result of the carrier wave and the lower modulation wave in the dual modulation wave, with the fourth switching transistor having a complementary switching state to the first switching transistor, and the sixth switching transistor having a complementary switching state to the fifth switching transistor.
[0139] It should be understood that Figures 9-13 Only Figure 6 The control method shown is based on the dual-modulation wave example. Additionally, it can also utilize... Figure 7 The dual-modulation wave shown is used to modulate the drive signals of each switching transistor. Utilizing... Figure 7When the dual modulation wave is used for control, the switching transistors and midpoint clamping transistors of the control switch bridge arm are used to make the inverter level include level 0+ and level 0- within a single modulation wave cycle. This includes: controlling the switching transistors and midpoint clamping transistors of the control switch bridge arm to make the inverter level have a first level transition state in the first half of the cycle and a second level transition state in the second half of the cycle. The first level transition state includes -1, 0+, +1, 0+ and -1 in sequence; the second level transition state includes -1, 0-, +1, 0- and -1 in sequence. The controller controls the switching transistors and midpoint clamping transistors of the switching bridge arm, ensuring that the inverter's voltage levels in the first half of the cycle sequentially include the fifth level transition state, the seventh level transition state, and the fifth level transition state; the seventh level transition state sequentially includes: 0+, +1, and 0+; the controller also controls the switching transistors and midpoint clamping transistors of the switching bridge arm, ensuring that the inverter's voltage levels in the second half of the cycle sequentially include the sixth level transition state, the eighth level transition state, and the sixth level transition state; the eighth level transition state sequentially includes: -1, 0-, and -1.
[0140] One possible implementation involves causing the inverter's voltage levels to transition between a first voltage level and a second voltage level, including: controlling the fourth and sixth switches to turn off when the second switch is turned on; and controlling the first and fifth switches to turn off when the third switch is turned on.
[0141] In one possible implementation, see Figure 15 The figure is a schematic diagram of a control device provided in an embodiment of this application.
[0142] The control device may include a memory 1011 and a processor 1012. The processor 1012 may be connected to the power converter and can drive the switches in the various power conversion circuits of the power converter. For example... Figure 15 As shown, the memory can be random access memory (RAM), flash memory, read-only memory (ROM), EPROM, non-volatile read-only memory (Electronic Programmable ROM), registers, hard disks, removable disks, etc.
[0143] The memory 1011 can store computer instructions. When the computer instructions stored in the memory 1011 are executed by the processor 1012, the processor 1012 can be used to execute the ANPC control method. The memory 1011 can also store data, such as carrier wave, modulation wave and other information involved in the above embodiments.
[0144] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape) or a semiconductor medium (e.g., solid-state disk (SSD)).
[0145] This application also provides a readable storage medium for storing the methods provided in the above embodiments. Examples include random access memory (RAM), flash memory, read-only memory (ROM), EPROM, non-volatile read-only memory (EPROM), registers, hard disks, removable disks, or any other form of storage medium in the art.
[0146] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the methods disclosed in the embodiments, since they correspond to the product embodiments disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the description of the product embodiments.
[0147] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An active neutral-point clamped three-level inverter, characterized in that, include: Switch bridge arm, midpoint clamp tube, and controller; The switch bridge arm includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube connected in series; the midpoint clamping tube includes a fifth switch tube and a sixth switch tube; the first end of the fifth switch tube is connected to the common end of the first switch tube and the second switch tube, the second end of the fifth switch tube is connected to the midpoint, the first end of the sixth switch tube is connected to the midpoint, and the second end of the sixth switch tube is connected to the common end of the third switch tube and the fourth switch tube; The controller is used to control the switching transistors of the switching bridge arm and the midpoint clamping transistor, so that the inverter level includes level 0+ and level 0- in a single cycle; 0+ means that the fifth switching transistor and the second switching transistor are turned on, and 0- means that the sixth switching transistor and the fourth switching transistor are turned on.
2. The inverter according to claim 1, characterized in that, The controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the inverter level includes level 0+ and level 0- in the upper half cycle and level 0+ and level 0- in the lower half cycle. Alternatively, control the switching transistors of the switching bridge arm and the midpoint clamping transistor so that the inverter's voltage level includes level 0+ in the upper half-cycle and level 0- in the lower half-cycle.
3. The inverter according to claim 1, characterized in that, The controller is used to control the switching transistors of the switching bridge arm and the midpoint clamping transistor, so that the inverter level has a first level transition state in the first half cycle and a second level transition state in the second half cycle. The first level transition state includes +1, 0+, -1, 0+ and +1 in sequence; the second level transition state includes +1, 0-, -1, 0- and +1 in sequence.
4. The inverter according to claim 3, characterized in that, The controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the inverter level in the first half cycle includes the first level transition state, the third level transition state and the first level transition state in sequence. The third level transition states include, in sequence, +1, 0+, and +1.
5. The inverter according to claim 4, characterized in that, The controller is configured to, during the first half-cycle, control either the first or sixth switch based on a comparison result between the carrier and the upmodulation wave in the dual-modulation wave, wherein the switching state of the fourth switch is complementary to that of the first switch, and the switching state of the sixth switch is complementary to that of the fifth switch; and to control the second switch based on a comparison result between the carrier and the downmodulation wave in the dual-modulation wave, wherein the switching state of the third switch is complementary to that of the second switch.
6. The inverter according to claim 3, characterized in that, The controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the inverter level in the second half cycle includes the second level transition state, the fourth level transition state and the second level transition state in sequence; The fourth level transition states include, in sequence, 0-, -1, and 0-.
7. The inverter according to claim 6, characterized in that, The controller is configured to, during the second half-cycle, control the second switch transistor based on a comparison result of the carrier wave and the upmodulation wave in the dual modulation wave, wherein the switching state of the third switch transistor is complementary to that of the second switch transistor; and to control the first switch transistor or the sixth switch transistor based on a comparison result of the carrier wave and the downmodulation wave in the dual modulation wave, wherein the switching state of the fourth switch transistor is complementary to that of the first switch transistor, and the switching state of the sixth switch transistor is complementary to that of the fifth switch transistor.
8. The inverter according to claim 1, characterized in that, The controller is used to control the switching transistors of the switching bridge arm and the midpoint clamping transistor, so that the inverter's level has a fifth level transition state in the first half of the cycle and a sixth level transition state in the second half of the cycle. The fifth level transition state includes -1, 0+, +1, 0+ and -1 in sequence; the sixth level transition state includes -1, 0-, +1, 0- and -1 in sequence.
9. The inverter according to claim 8, characterized in that, The controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the voltage level of the inverter in the first half cycle includes the fifth voltage level transition state, the seventh voltage level transition state and the fifth voltage level transition state in sequence. The seventh level transition states include, in sequence: 0+, +1, and 0+; The controller is used to control the switching transistor of the switching bridge arm and the midpoint clamping transistor, so that the level of the inverter in the second half cycle includes the sixth level transition state, the eighth level transition state and the sixth level transition state in sequence; the eighth level transition state includes -1, 0- and -1 in sequence.
10. The inverter according to any one of claims 1-9, characterized in that, The controller is configured to control the fourth and sixth switches to turn off when the second switch is turned on; and to control the first and fifth switches to turn off when the third switch is turned on.
11. A control method for an active neutral-point clamped three-level inverter, characterized in that, The inverter includes: a switch bridge arm and a midpoint clamping transistor; the switch bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series; the midpoint clamping transistor includes a fifth switch and a sixth switch; the first end of the fifth switch is connected to the common terminal of the first switch and the second switch, the second end of the fifth switch is connected to the midpoint, the first end of the sixth switch is connected to the midpoint, and the second end of the sixth switch is connected to the common terminal of the third switch and the fourth switch; The method includes: The switching transistors of the switching bridge arm and the midpoint clamping transistor are controlled so that the inverter level includes level 0+ and level 0- within a single modulation wave cycle; 0+ means that the fifth switching transistor and the second switching transistor are turned on, and 0- means that the sixth switching transistor and the fourth switching transistor are turned on.
12. The method according to claim 11, characterized in that, The switching transistor controlling the switching bridge arm and the midpoint clamping transistor, such that the inverter's voltage level includes voltage level 0+ and voltage level 0- within a single modulation wave cycle, includes: Control the switching transistor of the switching bridge arm and the midpoint clamping transistor so that the inverter's voltage level includes voltage level 0+ and voltage level 0- in the upper half-cycle and voltage level 0+ and voltage level 0- in the lower half-cycle; or, control the switching transistor of the switching bridge arm and the midpoint clamping transistor so that the inverter's voltage level includes voltage level 0+ in the upper half-cycle and voltage level 0- in the lower half-cycle.
13. The method according to claim 11, characterized in that, The switching transistor controlling the switching bridge arm and the midpoint clamping transistor, such that the inverter's voltage level includes voltage level 0+ and voltage level 0- within a single modulation wave cycle, includes: The switching transistors of the switching bridge arm and the midpoint clamping transistor are controlled to cause the inverter to have a first level transition state and a second level transition state. The first level transition state includes +1, 0+, -1, 0+ and +1 in sequence; the second level transition state includes +1, 0-, -1, 0- and +1 in sequence.
14. The method according to claim 113, characterized in that, The control of the switching transistors of the switching bridge arm and the midpoint clamping transistor to cause the inverter's voltage level to enter a first level transition state in the first half-cycle includes: The switching transistors of the switching bridge arm and the midpoint clamping transistor are controlled so that the inverter's level in the first half-cycle includes the first level transition state, the third level transition state, and the first level transition state in sequence; the third level transition state includes +1, 0+, and +1 in sequence.
15. The method according to claim 14, characterized in that, The switching transistor controlling the switching bridge arm and the midpoint clamping transistor cause the inverter's voltage level to sequentially include a first voltage level transition state, a third voltage level transition state, and the first voltage level transition state in the first half-cycle, including: In the first half-cycle, the first switch or the sixth switch is controlled according to the comparison result of the carrier and the up-modulation wave in the dual-modulation wave, the fourth switch being complementary to the switching state of the first switch, and the sixth switch being complementary to the switching state of the fifth switch; the second switch is controlled according to the comparison result of the carrier and the down-modulation wave in the dual-modulation wave, and the third switch being complementary to the switching state of the second switch.
16. The method according to claim 13, characterized in that, The control of the switching transistors of the switching bridge arm and the midpoint clamping transistor, causing the inverter's voltage level to transition to a second level transition state in the second half-cycle, includes: The switching transistors of the switching bridge arm and the midpoint clamping transistor are controlled so that the inverter's level in the second half-cycle includes the second level transition state, the fourth level transition state, and the second level transition state in sequence; the fourth level transition state includes 0-, -1, and 0- in sequence.
17. The method according to claim 16, characterized in that, The switching transistor controlling the switching bridge arm and the midpoint clamping transistor cause the inverter's voltage level to sequentially include the second voltage level transition state, the fourth voltage level transition state, and the second voltage level transition state in the second half-cycle, including: In the second half-cycle, the second switch is controlled based on the comparison result of the carrier and the upmodulation wave in the dual modulation wave, and the switching state of the third switch is complementary to that of the second switch; the first switch or the sixth switch is controlled based on the comparison result of the carrier and the downmodulation wave in the dual modulation wave, and the switching state of the fourth switch is complementary to that of the first switch, and the switching state of the sixth switch is complementary to that of the fifth switch.
18. The method according to claim 11, characterized in that, The switching transistor controlling the switching bridge arm and the midpoint clamping transistor, such that the inverter's voltage level includes voltage level 0+ and voltage level 0- within a single modulation wave cycle, includes: The switching transistors of the switching bridge arm and the midpoint clamping transistor are controlled so that the inverter's level exhibits a fifth level transition state in the first half-cycle and a sixth level transition state in the second half-cycle. The fifth level transition states sequentially include: -1, 0+, +1, 0+, and -1; the sixth level transition states sequentially include: -1, 0-, +1, 0-, and -1.
19. The method according to claim 18, characterized in that, Controlling the switching transistors of the switching bridge arm and the midpoint clamping transistor to cause the inverter's voltage level to transition to a fifth level in the first half of the cycle includes: The switching transistors of the switching bridge arm and the midpoint clamping transistor are controlled so that the inverter's voltage level in the first half of the cycle includes the fifth voltage level transition state, the seventh voltage level transition state, and the fifth voltage level transition state in sequence; the seventh voltage level transition state includes 0+, +1, and 0+ in sequence. The switching transistor controlling the switching bridge arm and the midpoint clamping transistor enter a sixth-level transition state in the second half-cycle, including: The switching transistors of the switching bridge arm and the midpoint clamping transistor are controlled so that the inverter's level in the second half cycle includes the sixth level transition state, the eighth level transition state, and the sixth level transition state in sequence; the eighth level transition state includes -1, 0-, and -1 in sequence.
20. The method according to any one of claims 11-19, characterized in that, The process of causing the inverter's voltage level to transition to a first voltage level transition state and a second voltage level transition state includes: When the second switch is turned on, the fourth and sixth switches are turned off; when the third switch is turned on, the first and fifth switches are turned off.
21. A control device, characterized in that, It includes a processor and a memory, the memory being used to store programs, instructions, or code, and the processor being used to execute the programs, instructions, or code in the memory to perform the control method as described in any one of claims 11-20.
22. A computer-readable storage medium, characterized in that, The system contains a computer program that is loaded by a processor to execute the control method as described in any one of claims 11-20.