Self-powered gate drive circuit for cascode power device

Abstract

A gate drive circuit is used for controlling on or off of a cascode power device and is provided with a gate drive signal generator and a local power supply. The gate drive signal generator receives an external control signal and accordingly generates a gate drive signal to drive a gate of the cascode power device, the gate drive signal generator being fully powered by a local power source. The local power supply is powered by the original electrical power received from the M point of the cascode power device such that the gate drive circuit is self-powered without being connected to an external power supply. There is no need to install an isolation circuit and an external power supply. Advantageously, elimination of an external power supply and an isolation circuit enables the design of the gate drive circuit to be simplified and more compact.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to U.S. Provisional Patent Application Serial No. 63 / 711,716, filed October 25, 2024, the disclosure of which is incorporated herein by reference in its entirety.

[0002] Abbreviations BTU Boot Unit DC DGND Digital Land DUT (Device Under Test) GaN (Gallium Nitride) GND ground terminal HEMT (High Electron Mobility Transistor) IC Integrated Circuit JFET (Junction Field-Effect Transistor) KS Kelvin Source MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) SiC (Silicon Carbide) V TH Threshold voltage WBG Wide Bandgap Technical Field

[0003] This disclosure generally relates to a gate drive circuit for driving the gate of a semiconductor power device. In particular, this disclosure relates to such a gate drive circuit that is self-powered without being connected to an external power source, thereby simplifying the design of the gate drive circuit. Background Technology

[0004] Power devices based on WBG semiconductors such as GaN and SiC are suitable for next-generation high-efficiency and high-power-density converters, primarily due to their superior characteristics compared to silicon-based counterparts, such as higher operating temperatures, faster switching speeds, and lower specific on-resistance.

[0005] The co-packaged full WBG GaN / SiC cascode device combines highly desirable characteristics for power devices, including: normally-off control mode, high channel mobility, high current handling capability, high voltage blocking capability with avalanche protection, high switching speed, and thermal stability. V TH Reverse conduction characteristics without reverse recovery and high switching speed ( dv / dt With its control capabilities, it becomes an ideal high-voltage power device in high-frequency and high-efficiency power conversion systems [1], [2].

[0006] Each power device requires a gate driver IC and an external power supply system to generate the gate drive signal. For switches... dv / dt and di / dt The significantly improved fast-switching WBG power devices present greater challenges for gate drive system design. During the fast-switching transients, parasitic inductance, especially the common-source inductance, induces significant voltage pulses. These voltage pulses not only impede switching speed but also couple noise from the power circuit to the gate circuit, leading to switching oscillations and false triggering problems.

[0007] KS connection is the most efficient way to minimize common-source inductance, and it is recommended and provided by most commercial WBG power devices. However, KS connection causes the reference ground node of the gate driver IC to be in a floating state. During fast switching transients, high... di / dt Significant voltage pulses (on the order of tens of volts) are induced in the parasitic inductance between the reference digital ground (DGND) of the driver IC (KS) and the ground (GND) of the power device it drives. These induced voltage pulses inject noise into the gate drive circuitry, causing a potential shift in the reference digital ground of the gate driver IC (also known as ground bounce). This ground bounce effect can lead to unintended switching actions, oscillations, degraded switching performance, and even system failure.

[0008] In references [3] and [4], isolated gate drive circuits based on KS nodes are used to drive high-side and low-side devices in a floating state. However, isolated gate drivers require external isolated power supplies, especially isolated DC / DC power modules, which significantly increases design complexity and cost.

[0009] There is an urgent need for a simplified gate drive circuit that can drive floating semiconductor devices without the need for any isolated DC / DC power supply modules. Summary of the Invention

[0010] This disclosure provides a gate driving circuit for driving the gate of a cascode power device by using a gate driving voltage, and controlling the cascode power device to be turned on or off according to an external control signal.

[0011] The gate drive circuit includes a gate drive signal generator and a local power supply. The gate drive signal generator is configured to receive an external control signal and generate a gate drive signal based on the received external control signal. The gate drive signal generator is also configured to be powered entirely by a single power supply. The local power supply serves as this single power supply to power the gate drive signal generator. The local power supply is also configured to be powered by the raw electrical power received from point M of the cascode power device, allowing the gate drive circuit to be self-powered without being connected to an external power supply. As a result, it avoids the need for isolation circuitry to isolate the ground of the external power supply from the ground of the cascode power device to suppress ground bounce.

[0012] This design eliminates the need for an external power supply and the isolation circuit required in traditional solutions to separate the external power supply ground terminal from the ground terminal of the common source cascode power device, thereby reducing system design complexity.

[0013] In some embodiments, the gate drive signal generator includes a gate driver IC and a digital isolator IC. The gate driver IC is used to generate a gate drive signal based on a first control signal. The gate drive signal and the first control signal are referenced to the DGND of the gate driver IC. The digital isolator IC is configured to receive an external control signal and generate a first control signal based on the external control signal, such that the first control signal is electrically isolated from the external control signal to achieve ground isolation.

[0014] In some embodiments, the gate drive signal generator includes a gate driver IC that internally incorporates digital isolation functionality. The gate driver is configured to generate a gate drive signal from an external control signal. In one option, the gate drive signal and the external control signal are referenced to the DGND of the gate driver IC. In another option, the gate driver is further configured to receive and process the external control signal, wherein the external control signal has a differential input signal signal format.

[0015] In some embodiments, the local power supply includes a gate unit (BTU) and a voltage regulator. The BTU is configured to receive raw electrical power from point M of the cascode power device and generate an unregulated power supply voltage from the raw electrical power. The voltage regulator is used to generate a regulated power supply voltage from the unregulated power supply voltage, wherein the regulated power supply voltage is used to power a gate drive signal generator.

[0016] In some embodiments, the voltage regulator is an LDO (Low-dropout regulator).

[0017] In some embodiments, the voltage regulator is selected from switched capacitor converters, buck converters, boost converters, buck-boost converters, and combinations thereof.

[0018] In some embodiments, the BTU includes a diode and one or more capacitors. The one or more capacitors are used to store electrical energy received from point M of the cascode power device, such that the electrical energy can be released from the one or more capacitors to power a gate drive signal generator. The diode is used to prevent the electrical energy stored in the one or more capacitors from flowing back to point M of the cascode power device.

[0019] The diode can be a Schottky barrier diode, a pn junction diode, or a lateral field-effect rectifier.

[0020] Gate driver ICs can be configured to drive high-voltage power devices, including but not limited to cascode power devices. This particular type of cascode power device can be a cascode device formed from GaN and SiC, a cascode device formed from Si and SiC, or a cascode device formed from Si and GaN.

[0021] In some embodiments, the bootstrap unit includes: one or more capacitors for storing electrical energy received from point M of the cascode power device, such that the electrical energy can be released from the one or more capacitors to power the gate drive signal generator; and a semiconductor transistor for preventing the electrical energy stored in the one or more capacitors from flowing back to point M of the cascode power device.

[0022] In some embodiments, the semiconductor transistor is selected from semiconductor transistors, including field-effect transistors, metal-oxide-semiconductor field-effect transistors, Schottky barrier diodes, pn junction diodes, and lateral field-effect rectifiers.

[0023] Other aspects of this disclosure are disclosed as shown in the following embodiments. Attached Figure Description

[0024] Figure 1 shows a schematic diagram of a conventional gate drive circuit.

[0025] Figure 2 A first schematic diagram of a self-powered gate drive circuit as disclosed herein is shown, according to one aspect of this disclosure.

[0026] Figure 3 A second schematic diagram of a self-powered gate drive circuit disclosed according to another aspect of this disclosure is shown.

[0027] Figure 4 The operating principle of the disclosed self-powered gate drive circuit is shown.

[0028] Figure 5A test circuit is shown for characterizing the switching process of a GaN / SiC cascode device when equipped with a disclosed self-powered gate drive circuit and a conventional externally powered gate drive circuit, respectively.

[0029] Figure 6 Photographs of the test board are shown, with the conventional externally powered gate driver and the disclosed self-powered gate driver circuitry respectively.

[0030] Figure 7 The switching waveforms of the GaN / SiC cascode device equipped with a publicly disclosed self-powered gate drive circuit are plotted.

[0031] Figure 8 The switching transient waveforms of the cascode device during the turn-on process are plotted when it is equipped with a self-powered gate drive circuit and a conventional externally powered gate drive circuit, respectively.

[0032] Figure 9 The switching transient waveforms of the cascode device during the turn-off process are plotted when it is equipped with a self-powered gate drive circuit and a conventional externally powered gate drive circuit, respectively.

[0033] Figure 10 The switching losses of GaN / SiC cascode devices at different current levels are plotted when equipped with a self-powered gate drive circuit and a conventional externally powered gate drive circuit, respectively.

[0034] Those skilled in the art will understand that the elements in the figures are shown for simplicity, but are not necessarily displayed to scale. Detailed Implementation

[0035] As used herein, a "cascode power device," or simply "cascode device," is a semiconductor device formed by connecting a high-voltage normally-on (D-mode) power device and a low-voltage normally-off (E-mode) power device in a common-source, common-gate configuration. In a cascode connection, the source of the high-voltage D-mode power device is connected to the drain of the low-voltage E-mode power device. The connection point between the source of the high-voltage D-mode power device and the drain of the low-voltage E-mode power device is referred to herein as the "M-point" or "interconnection point" of the cascode power device. The gate of the high-voltage D-mode power device is connected to the source of the low-voltage E-mode power device to achieve bias.

[0036] Examples of cascode power devices include, but are not limited to: GaN / SiC cascode devices (i.e., GaN-HEMT / SiC-JFET cascode devices), Si / SiC cascode devices (i.e., Si-MOSFET / SiC-JFET cascode devices), and Si / GaN cascode devices (i.e., Si-MOSFET / GaN-HEMT cascode devices). In GaN / SiC cascode devices, normally-on SiC JFETs and normally-off GaN HEMTs are used as high-voltage D-mode power devices and low-voltage E-mode power devices, respectively. Si / SiC and Si / GaN cascode devices employ similar arrangements.

[0037] As used herein, a “bootstrap unit” (BTU) is a bootstrap circuit or a variant thereof used to provide a floating voltage supply generated within the BTU from a primary electrical source. A bootstrap circuit is typically implemented using diodes, capacitors, and resistors. The capacitors in the BTU can be used to store electrical energy received from the primary electrical source, and this stored energy can be released from the capacitors to establish the floating voltage supply. The diodes in the BTU can be used to prevent the electrical energy stored in the capacitors from flowing back to the primary electrical source.

[0038] As used in this article, an "LDO regulator" is a voltage regulator IC designed to maintain a stable output voltage even when the input voltage is only slightly higher than the target output voltage.

[0039] As used in this article, an "isolated DC / DC converter" is an electrical / electronic circuit used to convert voltage between different parts of a system with different ground potentials.

[0040] As used herein, a "digital isolator" is a component that safely transmits digital signals between two circuits by providing electrical isolation to prevent ground loops and high-voltage interference signals. An example of a digital isolator is a high-speed optocoupler.

[0041] This disclosure provides a self-powered gate drive circuit for a cascode power device. The cascode power device can be, but is not limited to, a GaN / SiC cascode power device. The interconnect point (i.e., the M-point) serves as the power source for the gate drive circuit, eliminating the need for an external power supply and one or more isolated DC / DC converter modules, thereby reducing the associated costs, space requirements, and complexity in the manufacturing process of the gate drive circuit. Most importantly, the switching losses of the GaN / SiC cascode device equipped with the self-powered gate drive circuit are very comparable to those of conventional isolated gate drivers, which is beneficial for achieving high-efficiency, high-power-density power converter designs.

[0042] Before disclosing embodiments of this disclosure, the advantages of the disclosed gate drive circuit compared to prior art gate drivers are first outlined. In prior art gate drivers, an external power supply system is used to power isolated gate drivers for high-side and low-side power devices to suppress the effects of ground bounce on the operation of WBG power devices. This disclosure proposes a novel self-powered gate drive circuit capable of drawing power from the interconnect point (i.e., point M) of a cascode power device. This new approach eliminates the need for an external power supply system, thereby enabling a more compact design to improve the power density of the power conversion system. Most importantly, the new design disclosed herein does not increase switching losses, thus not affecting the efficiency of the power conversion system.

[0043] The following will use Figures 1 to 12 as a reference. Figure 10 This disclosure will be explained in detail.

[0044] Figure 1 illustrates a cascode power device 101 driven by a conventional gate drive circuit 100 with an external power supply 104, which provides power to the conventional gate drive circuit 100. An isolated DC / DC module 103 and various other peripheral circuits together constitute a floating power supply, which is regulated by an LDO module 102 and supplied to a digital isolator 105 and its gate driver IC 106. It should be noted that the cascode power device 101 is formed by connecting a high-voltage normally open (D-mode) JFET 151 with a low-voltage normally closed (E-mode) GaN HEMT 152. The point connecting the JFET 151 and the HEMT 142 is point M 150.

[0045] Figure 2 A cascode power device 101 driven by the disclosed self-powered gate drive circuit 200 is shown, which eliminates the need for an external power supply, expensive and bulky isolated DC / DC modules, and various peripheral circuits. The gate drive circuit 200 draws power from the interconnect point 150 (i.e., M-point 150) of the cascode device 101 via the BTU 202 and provides a stable power supply VDD to the digital isolator IC 205 and the gate driver IC 204 via the LDO module 203. It should be noted that any other suitable voltage regulator besides the LDO module 203 can be used to provide VDD. Since the LDO module 203 is referenced to the DGND of the gate drive circuit 200, the generated VDD is also a naturally isolated and floating local power supply voltage. This effectively suppresses ground bounce effects of the gate drive circuit 200.

[0046] Figure 3Another implementation of the disclosed self-powered gate drive circuit 200a is shown. The gate drive circuit 200a draws power from the interconnect point 150 (i.e., M-point 150) of the cascode device 101 via the BTU 202 and provides a stable power supply voltage VDD to the gate driver 204 via the LDO module 203. Since the LDO module 203 is referenced to the DGND of the gate drive circuit 200a, the generated VDD is also a naturally isolated and floating local power supply voltage. This effectively suppresses ground bounce effects.

[0047] Figure 4 The operating principle of the disclosed self-powered gate drive circuit 200 / 200a is illustrated. The most crucial aspect of its operation is drawing power from point M 150 of the cascode device 101 and providing a stable voltage VDD to the gate driver IC 204 and the digital isolator 105 (if present). During the startup phase ( Figure 4 The subgraph (a) and the off state ( Figure 4 During subgraph (c), the normally open characteristic of the high-voltage device (i.e., JFET 151) within the cascode power device 101 pulls the potential of point M 150 high, thereby causing the diode in BTU 202 to... D B 402 is turned on, thus allowing current to flow into the capacitor of BTU 202. C B In 403, and store the charge in the capacitor. C B In 403. Therefore, the capacitor is increased. C B The voltage of 403 is applied, and the LDO module 401 is activated, thereby providing a stable voltage VDD for the gate driver IC and digital isolator IC of the gate drive circuit. During the turn-on phase ( Figure 4 During subgraph (b), when the voltage at point M150 drops to the turn-on voltage (e.g., 0.1V) of the normally closed low-voltage device (i.e., GaN HEMT 152) within the cascode power device 101, the diode... D B 402 enters cutoff mode, and charge is stored in the capacitor. C B Within 403, and via LDO module 401, power is continuously supplied to the gate drive circuits 200 / 200a. During the conduction process, the gate drive circuits 200 / 200a consume several nC of charge, which is the gate charge of the cascode power device 101. Q G The charge is stored in the capacitor. C B Within 403, this leads to the capacitor CB The voltage at 403 drops slightly. During the turn-off process, once the cascode device 101 turns off and the voltage at point M 150 rises above the capacitor... C B The voltage of 403, then the diode D B 402 is re-energized, thereby restoring the consumed charge (i.e. Q G Recharge the capacitor C B In 403, based on the operating principle of the self-powered gate drive circuit 200 / 200a, the capacitor inside BTU 202... C B The capacitance value of 403 should be higher than 100nF to suppress voltage fluctuations during switching.

[0048] Figure 5 A test circuit is shown for characterizing the switching process of a cascode power device 101 equipped with the disclosed self-powered gate drive circuit 200. A 1.2kV GaN-HEMT / SiC-JFET cascode device was selected as the DUT. The drain-source voltage of the DUT was characterized. V DS Drain-source current of DUT I DS The voltage at point M of the DUT V M and the current of the load inductor I L .

[0049] Figure 6 A photograph of a test board is shown for characterizing the switching process of the cascode power device 101 when equipped with a conventional externally powered gate drive circuit 100 and the disclosed self-powered gate drive circuit 200. Because the external power supply and isolated DC / DC module are eliminated, the structure of the test board can be significantly simplified and made more compact when equipped with the self-powered gate drive circuit 200.

[0050] Figure 7 The switching waveforms of the GaN / SiC cascode device equipped with the disclosed self-powered gate drive circuit 200 are plotted. Clearly, when equipped with this circuit, the GaN / SiC cascode power device can successfully achieve turn-on and turn-off under fully controlled conditions.

[0051] Figure 8 and Figure 9The switching transient waveforms and losses of the GaN / SiC cascode device during turn-on and turn-off processes are plotted when equipped with the disclosed self-powered gate drive circuit 200. Clearly, with this circuit, the GaN / SiC cascode power device exhibits switching losses and switching speeds comparable to those of a conventional externally powered gate drive circuit 100.

[0052] Figure 10 The overall switching losses of the GaN / SiC cascode device at different current levels are shown. It demonstrates that, when equipped with the disclosed self-powered gate drive circuit 200, the GaN / SiC cascode device exhibits switching losses comparable to those of a conventional gate drive circuit 100 using an external power supply.

[0053] The embodiments of this disclosure are developed based on the details, examples, applications, etc., of the self-powered gate drive circuit disclosed above, and may include its generalizations and extensions.

[0054] Reference Figure 2 and Figure 3 The main aspect of this disclosure is to provide a gate drive circuit 200 / 200a, which is used to control the common-source common-gate power device 101 to be turned on or off according to an external control signal 280 by applying a gate drive voltage 215 to the gate of the common-source common-gate power device 101.

[0055] Exemplarily, the gate drive circuitry 200 / 200a includes a gate drive signal generator 220 / 220a and a local power supply 210. The gate drive signal generator 220 / 220a is configured to receive an external control signal 280 and generate a gate drive signal 215 based on the received external control signal 280. The gate drive signal generator 200 / 200a is also configured to be powered entirely by a single power supply. The local power supply 210 acts as a single power supply to power the gate drive signal generator 220 / 220a. The local power supply 210 is also configured to be powered by raw electrical power received from point M 150 of the cascode power device 101, such that the gate drive circuitry 200 / 200a is self-powered without connection to an external power supply. As used herein, "raw electrical power received from point M" refers to electrical power received directly from point M. Therefore, there is no need to install isolation circuitry (such as the isolated DC / DC module 103 in the conventional gate drive circuit 100) to isolate the ground terminal of the external power supply from the ground terminal of the cascode power device 101 to suppress ground bounce. Advantageously, eliminating the external power supply and isolation circuitry simplifies and makes the design of the gate drive circuitry of the cascode power device 101 more compact.

[0056] Reference Figure 2In one particular embodiment, the gate drive signal generator 200 includes a gate driver 204 and a digital isolator 205. The gate driver 204 generates a gate drive signal 215 based on a first control signal 214. Both the gate drive signal 215 and the first control signal 214 are referenced to the DGND of the gate driver 204. The digital isolator 205 is configured to receive an external control signal 280 and generate the first control signal 214 based on that external control signal 280, such that the first control signal 214 and the external control signal 280 are electrically isolated from each other to achieve ground isolation. Specifically, the external control signal 280 is referenced to the ground terminal of the cascode power device 101, while the first control signal 214 is referenced to the DGND of the gate driver 204.

[0057] Reference Figure 3 In another specific embodiment, the gate drive signal generator 200a includes a gate driver 204 specifically configured to generate a gate drive signal 215 from an external control signal 280. It should be noted that a digital isolator 205 is not provided in the gate drive signal generator 200a. In one implementation of the gate drive signal generator 200a, due to the absence of the digital isolator 205, both the gate drive signal 215 and the external control signal 280 are referenced to the DGND of the gate driver 204. In another implementation of the gate drive signal generator 200a, specifically for the case where the external control signal 280 is a differential input signal, a digital isolator 205 is also unnecessary since differential input signals do not cause ground bounce. In this specific case, the gate drive signal 215 is referenced to the DGND of the gate driver 204. Furthermore, the gate driver 204 is also configured to receive and process the external control signal 280 in a signal format having differential input signals.

[0058] Other details of the gate drive circuit 200 / 200a are as follows.

[0059] In implementing the gate drive circuit 200 / 200a, preferably, the local power supply 210 includes a BTU 202 and a voltage regulator (also designated 203 for convenience). The BTU 202 is configured to receive raw electrical power from point M 150 of the cascode power device 101 and generate an unregulated supply voltage 231 from this raw electrical power. The voltage regulator 203 is used to generate a regulated supply voltage 232 (VDD) from the unregulated supply voltage 231. The regulated supply voltage 232 is used to power the gate signal generator 220 / 220a.

[0060] The voltage regulator 203 may be an LDO regulator 203. Alternatively, the voltage regulator 203 may be selected from switched capacitor converters, buck converters, boost converters, buck-boost converters, and combinations thereof.

[0061] Typically, BTU 202 includes a diode 241 and one or more capacitors 242. The one or more capacitors 242 store electrical energy received from point M 150 of the cascode power device 101, allowing this energy to be released from the one or more capacitors 242 to power the gate drive signal generator 220 / 220a. Typically, the one or more capacitors 242 are connected in parallel to aggregate their respective capacitance values. Diode 241 prevents the electrical energy stored in the one or more capacitors 242 from flowing back to point M 150 of the cascode power device 101. Therefore, the rated voltage of diode 241 needs to be higher than the maximum voltage at point M 150 of the cascode power device 101. Additionally, an additional resistor can be connected in series with diode 214 to protect it. In implementation, diode 241 can be a Schottky barrier diode, a pn junction diode, or a lateral field-effect rectifier. The diode can also be replaced by a semiconductor transistor, selected from semiconductor transistors, which may include field-effect transistors, metal-oxide-semiconductor field-effect transistors, Schottky barrier diodes, pn junction diodes, and lateral field-effect rectifiers. Alternatively, one or more capacitors 242 in BTU 202 may also be used as input capacitors for LDO module 203.

[0062] As described above, the cascode power device 101 can be a GaN / SiC cascode device, a Si / SiC cascode device, a Si / GaN cascode device, etc. When implementing the gate drive circuit 200 / 200a, the gate driver 204 can be configured to generate a gate drive signal 215, which is suitable for driving the gate of a specific type of cascode power device 101, such as a GaN / SiC cascode device, a Si / SiC cascode device, and a Si / GaN cascode device.

[0063] This disclosure may be embodied in other specific forms without departing from its spirit or essential characteristics. Therefore, the present embodiments should be considered illustrative rather than restrictive in all respects. The scope of the invention is defined by the appended claims rather than the foregoing description, and therefore all modifications falling within the equivalent meaning and scope of the claims should be included within the claims.

[0064] References The following is a list of references occasionally cited in this manual. All publicly available information from these references is incorporated herein by way of citation.

[0065] [1] J. Shu, J. Sun, Z. Zheng and KJ Chen, “Protecting SiC JFET from Gate Overstress in GaN / SiC Cascode Device without Compromising Switching Performance” IEEE Transactions on Power Electronics , pp. 5567–5575, May 2024, doi: 10.1109 / TPEL.2024.3354833.

[0066] [2] J. Shu et al., “Stacked Strongly Coupled GaN / SiC Cascode Device with FastSwitching and Reclaimed Strong dv / dt Control”, IEEE International Electron Devices Meeting (IEDM), San Francisco, California, 2024, pp. 25.1.1-25.1.4, doi: 10.1109 / IEDM50854.2024.10873458.

[0067] [3] Z. Zhang, B. Guo, FF Wang, EA Jones, LM Tolbert and BJ Blalock, “Methodology for Wide Band-Gap Device Dynamic Characterization” IEEE Transactions on Power Electronics Volume 32, Issue 12, pp. 9307–9318, December 2017, doi: 10.1109 / TPEL.2017.2655491.

[0068] [4] J. Shu, J. Sun, Z. Zheng and KJ Chen, “Gate driver design for SiC power MOSFET based on low-voltage GaN HEMT for reducing switching losses and gate protection”, IEEE Transactions on Power Electronics, Vol. 39, No. 5, pp. 5558-5566, May 2024, doi: 10.1109 / TPEL.2024.3353460.

Claims

1. A gate driving circuit, the gate driving circuit being used to drive the gate of a cascode power device by utilizing a gate driving voltage, and to control the on or off of the cascode power device according to an external control signal, the gate driving circuit comprising: A gate drive signal generator is configured to receive the external control signal and generate a gate drive signal based on the received external control signal, wherein the gate drive signal generator is further configured to be powered entirely by a single power supply. as well as A local power supply, which serves as a single power source for powering the gate drive signal generator, is further configured to be powered by raw electrical power received from point M of the cascode power device, such that the gate drive circuit is self-powered without being connected to an external power source. This avoids the need for isolation circuitry to separate the ground of the external power source from the ground of the cascode power device, thereby suppressing ground bounce.

2. The gate driving circuit according to claim 1, wherein, The gate drive signal generator includes: A gate driver, the gate driver being configured to generate the gate drive signal according to a first control signal, wherein the gate drive signal and the first control signal are referenced to the digital ground (DGND) of the gate driver; and A digital isolator configured to receive the external control signal and generate the first control signal based on the external control signal, such that the first control signal is electrically isolated from the external control signal to achieve ground isolation.

3. The gate driving circuit according to claim 1, wherein, The gate drive signal generator includes: A gate driver configured to generate the gate drive signal from the external control signal, wherein the gate drive signal and the external control signal are referenced to the digital ground (DGND) of the gate driver.

4. The gate driving circuit according to claim 1, wherein, The gate drive signal generator includes: A gate driver configured to generate the gate drive signal from the external control signal, the gate drive signal being referenced to the digital ground (DGND) of the gate driver, wherein the gate driver is further configured to receive and process the external control signal, the external control signal being configurable in a signal format having differential input signals.

5. The gate driving circuit according to claim 1, wherein, The local power source includes: A bootstrap unit (BTU) configured to receive raw electrical power from point M of the cascode power device and generate an unregulated supply voltage from the raw electrical power; and A voltage regulator for generating an regulated power supply voltage from the unregulated power supply voltage, the regulated power supply voltage being used to power the gate drive signal generator.

6. The gate driving circuit according to claim 5, wherein, The voltage regulator is a low-dropout linear regulator (LDO).

7. The gate driving circuit according to claim 5, wherein, The voltage regulator is selected from switched capacitor converters, buck converters, boost converters, buck-boost converters, and combinations thereof.

8. The gate driving circuit according to claim 5, wherein, The bootstrap unit includes: One or more capacitors, the one or more capacitors being used to store electrical energy received from point M of the cascode power device, such that the electrical energy can be released from the one or more capacitors to power the gate drive signal generator; and A diode for preventing electrical energy stored in the one or more capacitors from flowing back to point M of the common-source, common-gate power device.

9. The gate driving circuit according to claim 8, wherein, The diode is a Schottky barrier diode, a pn junction diode, or a lateral field-effect rectifier.

10. The gate driving circuit according to claim 2, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a GaN / SiC cascode device.

11. The gate driving circuit according to claim 3, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a GaN / SiC cascode device.

12. The gate driving circuit according to claim 4, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a GaN / SiC cascode device.

13. The gate driving circuit according to claim 2, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a Si / SiC cascode device.

14. The gate driving circuit according to claim 3, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a Si / SiC cascode device.

15. The gate drive circuit according to claim 4, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a Si / SiC cascode device.

16. The gate driving circuit according to claim 2, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a Si / GaN cascode device.

17. The gate drive circuit according to claim 3, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a Si / GaN cascode device.

18. The gate driving circuit according to claim 4, wherein, The gate driver is configured to generate a gate drive signal suitable for driving the gate of a Si / GaN cascode device.

19. The gate driving circuit according to claim 5, wherein, The bootstrap unit includes: One or more capacitors, the one or more capacitors being used to store electrical energy received from point M of the cascode power device, such that the electrical energy can be released from the one or more capacitors to power the gate drive signal generator; and A semiconductor transistor is used to prevent electrical energy stored in the one or more capacitors from flowing back to point M of the common-source cascode power device.

20. The gate drive circuit according to claim 19, wherein, The semiconductor transistor is selected from semiconductor transistors, including field-effect transistors, metal-oxide-semiconductor field-effect transistors, Schottky barrier diodes, pn junction diodes, and lateral field-effect rectifiers.

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