Coding method, hardware accelerator and system on chip

Abstract

The embodiment of the invention provides a coding method, a hardware accelerator and a system on chip, and the method comprises the steps: determining a cardinal number frequency corresponding to each to-be-coded cardinal number obtained by mapping each input symbol through a frequency extraction module in the hardware accelerator; generating a target Huffman tree through a code generation module in the hardware accelerator based on the target sorting result of the cardinal number frequency corresponding to each cardinal number to be coded; and generating a compressed data stream through an encoding module in the hardware accelerator based on a target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. And constructing a Huffman tree structure according to the target sorting result, so that the high-frequency cardinal number corresponds to the short code and the low-frequency cardinal number corresponds to the long code. And dynamically coding the input data stream based on the target Huffman tree to generate a compressed data stream, thereby realizing rapid coding conversion. The whole coding process is efficiently and cooperatively completed in a hardware accelerator, so that the data transmission and software scheduling overhead is reduced, and the data compression speed and performance are improved.

Description

Technical Field

[0001] This invention relates to the field of coding technology, and in particular to a coding method, a hardware accelerator, and a system-on-a-chip. Background Technology

[0002] With the widespread application of information compression technology in data storage and transmission, dynamic Huffman coding, as an adaptive lossless compression algorithm based on dynamically adjusting the coding tree according to the radix frequency, has significant advantages in processing real-time changing data streams. Huffman coding is a lossless data compression method that achieves efficient compression by assigning different lengths of binary codes to different symbols.

[0003] In related technologies, when implementing dynamic Huffman coding algorithms at the software level, standardized compression libraries (such as zlib) can be deployed on the target system using package management tools. During the development phase, when using a high-level programming language for coding, simply including the zlib library header file in the program header file area via preprocessing directives allows for the complete implementation of dynamic Huffman coding and real-time compression of the data stream by calling the series of functions provided by the library, such as deflateInit, deflate, and deflateEnd. However, traditional software-implemented dynamic Huffman coding requires dynamically maintaining the coding tree structure at runtime and frequently performing node insertion, deletion, and coding table update operations. This results in complex tree traversal, node splitting, and merging calculations involved in each coding operation, leading to significant performance overhead. Summary of the Invention

[0004] To overcome the problems existing in related technologies, the present invention provides an encoding method, a hardware accelerator, and a system-on-a-chip.

[0005] In a first aspect, the present invention provides an encoding method applied to a hardware accelerator; the method includes: The frequency extraction module in the hardware accelerator determines the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol. The encoding generation module in the hardware accelerator generates a target Huffman tree based on the target sorting result of the cardinality frequency corresponding to each cardinality to be encoded; the cardinality to be encoded corresponds to a leaf node in the target Huffman tree; The encoding module in the hardware accelerator generates a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. The target encoding result consists of target encoding information corresponding to the target encoding cardinality determined based on the target Huffman tree and an incremental value. The target encoding cardinality and the incremental value are obtained by mapping the symbols to be encoded.

[0006] In a second aspect, the present invention provides a hardware accelerator, which includes a frequency extraction module, a bitonic sorting module, an encoding generation module, and an encoding module. The frequency extraction module is used to determine the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol; The bitonic sorting module is used to perform bitonic sorting on the radix to be encoded according to the radix frequency corresponding to each radix to be encoded, so as to obtain the target sorting result; The encoding generation module is used to generate a target Huffman tree based on the target sorting result of the cardinality frequency corresponding to each cardinality to be encoded; the cardinality to be encoded corresponds to a leaf node in the target Huffman tree; The encoding module is used to generate a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream; the target encoding result consists of target encoding information corresponding to the target encoding cardinality determined based on the target Huffman tree and the incremental value, the target encoding cardinality and the incremental value are obtained by mapping the symbol to be encoded.

[0007] Thirdly, the present invention provides a system-on-a-chip, comprising: a memory, a processor, and a hardware accelerator, the hardware accelerator being configured to implement the steps of the encoding method as described in any of the embodiments of the first aspect above.

[0008] In this embodiment of the invention, the frequency extraction module in the hardware accelerator determines the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol; the encoding generation module in the hardware accelerator generates a target Huffman tree based on the target sorting result of the radix frequencies corresponding to each radix to be encoded; and the encoding module in the hardware accelerator generates a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. Thus, the frequency extraction module in the hardware accelerator can adaptively determine the radix frequency corresponding to each radix to be encoded by the input data, shortening the frequency statistics time and improving processing efficiency. The encoding generation module constructs a Huffman tree structure based on the target sorting result, so that high-frequency radixes correspond to short codes and low-frequency radixes correspond to long codes, achieving efficient compressed representation of the data and improving the compression ratio. The encoding module generates a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. The parallel processing capability of the hardware accelerator enables the encoding module to process multiple radixes simultaneously, achieving fast encoding conversion. The entire encoding process is completed efficiently and collaboratively within the hardware accelerator, reducing data transmission and software scheduling overhead and improving the speed and performance of data compression. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a flowchart of the steps of an encoding method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the workflow of a hardware accelerator provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the architecture of a frequency extraction module provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the process of a sorting module generating a bitonetic sequence according to an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the process of merging bitone sequences by a merging module according to an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the generation process of a target Huffman tree provided in an embodiment of the present invention; Figure 7 This is a structural diagram of a hardware accelerator provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Figure 1 This is a flowchart illustrating the steps of an encoding method provided in an embodiment of the present invention, applied to a hardware accelerator. The hardware accelerator may include a frequency extraction module, a bitonic sorting module, an encoding generation module, and an encoding module. The frequency extraction module extracts the frequency information of each cardinality to be encoded from the input data stream. The bitonic sorting module sorts the frequency information to obtain a target sorting result. The encoding generation module constructs a target Huffman tree based on the target sorting result and generates Huffman codes. The encoding module dynamically encodes the input data stream using the generated Huffman codes.

[0013] The hardware accelerator can communicate with the central processing unit (CPU) and the data bus. The CPU can send initialization signals to the hardware accelerator to configure its operating parameters and modes. The hardware accelerator can interact with the CPU, such as providing status information or requesting further instructions. The hardware accelerator can receive input data streams to be processed and transmit compressed data streams output by the hardware accelerator via the data bus. An exemplary flowchart of the hardware accelerator's workflow can be shown below. Figure 2 As shown.

[0014] like Figure 1 As shown, the method may include: Step 101: Determine the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol through the frequency extraction module in the hardware accelerator.

[0015] In this embodiment of the invention, a frequency extraction module in the hardware accelerator statistically obtains the cardinality frequency corresponding to each cardinality to be encoded. Specifically, the frequency extraction module can be configured to receive an input data stream containing the cardinality to be encoded, and extract the occurrence frequency information of each cardinality to be encoded based on an internally preset frequency statistical logic mechanism for use in subsequent encoding processing. The cardinality to be encoded can be the cardinality after mapping and transformation of the input symbols, such as the encoding cardinality mapped according to a preset mapping table.

[0016] Mapping input symbols yields the cardinality to be encoded and the increment value. In data compression, especially for input data with a large numerical range, directly counting the frequency of each specific value leads to bloated and redundant statistical results, posing challenges for hardware implementation. Therefore, the input symbol values ​​can be divided into multiple numerical intervals, and the frequency of occurrence within each interval can be counted. When a value appears in the input data, it is equivalent to the numerical interval containing that value appearing once. Each numerical interval is remapped to a set of encoding cardins. By counting the frequency of occurrence of these encoding cardins, the number of values ​​to be counted can be greatly reduced, simplifying the statistical process. Furthermore, to represent all values ​​within a numerical interval, multiple bits can be set as additional increments. Due to the uneven division of numerical intervals and the varying number of values ​​within different intervals, the bit width of the additional increments also varies. Based on a pre-designed mapping table, the encoding cardinality and additional increment corresponding to any numerical interval can be determined. This pre-designed mapping table can be a pre-designed data structure that establishes the correspondence between different input symbols in the input data stream and the cardinality and increment value to be encoded.

[0017] The contents of the preset mapping table can be set according to actual conditions. For example, in actual compression, the frequency of values ​​is not entirely the same; smaller values ​​may appear more frequently. Therefore, the division of value ranges in the preset mapping table can be uneven. For example, the preset mapping table can be as follows:

[0018] It is understandable that the encoding base in the above preset mapping table is in binary form.

[0019] According to the preset mapping table, taking the input symbol 17 as an example, the obtained mapping result includes: base 1000, extra increment 000. Taking the input symbol 23 as an example, the obtained mapping result includes: base 1000, extra increment 110.

[0020] Optionally, step 101 may include the following steps: Step 201: Determine the target selection circuit corresponding to the input symbol received by the frequency extraction module through the control register in the frequency extraction module.

[0021] In this embodiment of the invention, the frequency extraction module may include a control register group, a selection circuit array, a statistical register group, and a preset mapping table storage unit. The control register group may be configured to store the base address of the preset mapping table storage unit. The selection circuit array may include N parallel selection circuits (N≥2), each selection circuit being configured with an independent interval comparator. The statistical register group includes N statistical registers, each statistical register establishing a one-to-one correspondence with a selection circuit in the selection circuit array.

[0022] The control register in the frequency extraction module determines the numerical range corresponding to the input symbol, and each numerical range can correspond to a selection circuit. Based on the numerical range corresponding to the input symbol, the target selection circuit corresponding to that numerical range can be determined. Accordingly, the statistical register corresponding to the target selection circuit counts and statistics for each input symbol within that numerical range.

[0023] Step 202: Input the input symbol to the target selection circuit and determine the encoding base corresponding to the input symbol output by the target selection circuit.

[0024] In this embodiment of the invention, the input symbol is input to the corresponding target selection circuit. The target selection circuit determines the encoding base that matches the input symbol based on a preset mapping table, which is then used as the base to be encoded. Simultaneously, the target selection circuit can generate a statistical pulse signal, which triggers the statistical register connected to the target selection circuit to increment its count by 1. That is, each time the target selection circuit outputs the base to be encoded, the value in the statistical register connected to the target selection circuit is incremented by one.

[0025] Step 203: Obtain the target value of the statistical register connected to the target selection circuit, and use it as the base frequency corresponding to the base to be encoded.

[0026] In this embodiment of the invention, the statistical register group can be configured with a parallel read interface, allowing the bitonetic sorting module to read the frequency statistics corresponding to each radix to be encoded. The target value in the statistical register connected to the target selection circuit is obtained as the radix frequency corresponding to the radix to be encoded.

[0027] In this embodiment of the invention, the hardware-accelerated positioning of the input symbol to the target selection circuit is achieved through the collaborative mechanism of the control register and the preset mapping table, avoiding the high latency defect of software traversal search and significantly improving the data processing throughput. At the same time, the direct connection architecture of the selection circuit and the statistical register is adopted to ensure that the radix frequency statistics and the encoding radix output are completed synchronously, eliminating the competition risk brought about by the traditional counter sharing and improving the encoding efficiency to a certain extent.

[0028] For example, Figure 3 A schematic diagram of the architecture of a frequency extraction module is shown, such as... Figure 3 As shown, after the input data, i.e., the input symbol, is input to the frequency extraction module, the encoding base (the base to be encoded) that matches the input symbol is determined based on a preset mapping table, and then input to the corresponding target selection circuit. The target value of the statistical register connected to the target selection circuit is used as the output of the frequency extraction module. The target value of the statistical register is the base frequency corresponding to the base to be encoded.

[0029] Step 102: Using the encoding generation module in the hardware accelerator, a target Huffman tree is generated based on the target sorting result of the cardinality frequency corresponding to each cardinality to be encoded; the cardinality to be encoded corresponds to a leaf node in the target Huffman tree.

[0030] In this embodiment of the invention, after the frequency extraction module determines the cardinality frequency corresponding to each cardinality to be encoded, the encoding generation module in the hardware accelerator generates a target Huffman tree based on the target sorting result of the cardinality frequencies corresponding to each cardinality to be encoded. The target Huffman tree can be a normalized Huffman tree, which is transformed from the initial Huffman tree, and one leaf node in the target Huffman tree corresponds to one cardinality to be encoded. The cardinality to be encoded and its corresponding cardinality frequency information are obtained from the frequency extraction module; the cardinality frequency reflects the frequency of occurrence of the cardinality to be encoded. Based on the cardinality frequencies corresponding to the cardinality to be encoded, the cardinality to be encoded is bitonically sorted to obtain the target sorting result. The target sorting result includes each cardinality to be encoded after the cardinality frequency is monotonically sorted, for example, the cardinality to be encoded is arranged in ascending or descending order of cardinality frequency.

[0031] A Huffman tree is a binary tree structure used for data compression. Its construction principle is that cardinal numbers with higher frequencies are closer to the root node and have shorter encoding lengths; conversely, cardinal numbers with lower frequencies are farther from the root node and have longer encoding lengths. Based on the target sorting result, the initial Huffman tree is constructed step-by-step, starting with the two cardinal numbers with the lowest frequencies. Specifically, the process involves: using the two lowest-frequency cardinal numbers as leaf nodes, creating a new parent node with a frequency equal to the sum of the frequencies of these two leaf nodes; re-sorting the newly created parent node and the remaining cardinal numbers (or already generated parent nodes) according to frequency, and repeating this process until all cardinal numbers to be encoded are included in the Huffman tree, resulting in the initial Huffman tree. Further, to transform the initial Huffman tree into a normalized Huffman tree, initial layer codes can be constructed for each level of the Huffman tree based on the node depth information corresponding to the cardinal numbers to be encoded. Then, using the initial layer codes as a basis, the codes corresponding to the cardinal numbers to be encoded at the same level are incremented by 1 sequentially to construct the normalized Huffman tree, i.e., the target Huffman tree.

[0032] Implementing the encoding process in a hardware accelerator leverages the high parallel computing power and dedicated logic circuitry of the hardware. Compared to software implementation, the hardware encoding generation module can perform comparison and merging operations on multiple nodes simultaneously, significantly reducing the Huffman tree construction time. Furthermore, the Huffman tree structure implemented through a hardware accelerator avoids the overhead of dynamically allocating memory and constructing data structures required in software implementation, improving system stability and reliability.

[0033] Optionally, embodiments of the present invention may include the following steps: Step 301: Using the bitonic sorting module in the hardware accelerator, the radix to be encoded is bitonically sorted according to the radix frequency corresponding to each radix to be encoded, to obtain the target sorting result.

[0034] In this embodiment of the invention, the bitonic sorting module in the hardware accelerator performs bitonic sorting based on the cardinality to be encoded and its corresponding cardinality frequency information obtained from the frequency extraction module.

[0035] Specifically, the sorting submodule in the bitone sorting module receives the cardinality frequencies corresponding to each cardinality to be encoded from the frequency extraction module. Based on these cardinality frequencies, the sorting submodule splits the data and constructs a first monotonic sequence and a second monotonic sequence containing cardinality frequencies with opposite monotonicity, which are then combined to form the initial bitone sequence. This process utilizes the parallel processing capabilities of the hardware circuitry to quickly complete sequence construction. The merging submodule in the bitone sorting module recursively partitions the initial bitone sequence, gradually dividing it into smaller subsequences. During partitioning, the merging submodule uses a hardware comparator to perform cross-segment comparisons of elements at the same position in the subsequences, performing swap operations based on the comparison results to ensure that the data is arranged in an ordered manner according to specific rules within the subsequences. The merging submodule recursively merges the locally sorted subsequences, with each merge further optimizing the overall orderliness of the sequence. As the number of recursions increases, the length of the subsequences gradually decreases until it reaches a preset minimum value (usually 2). At this point, after multiple rounds of recursive partitioning, comparison swapping, and merging operations, the bitone sequence has been transformed into a monotone sequence. The hardware accelerator extracts the permutation information of each cardinality to be encoded from the monotonic sequence, and uses this information to determine the target sorting result.

[0036] In this embodiment of the invention, the target sorting result is obtained by performing bitone sorting according to the radix frequency of the radix to be encoded through the bitone sorting module in the hardware accelerator. Since the hardware accelerator has parallel processing capability, it can compare and exchange multiple radix frequencies at the same time. Compared with the software sorting method of processing one by one, it greatly shortens the sorting time and improves the data processing and sorting efficiency.

[0037] Optionally, step 301 may include the following steps: Step 401: Based on the sorting module in the bitone sorting module, and based on the cardinality frequency corresponding to each cardinality to be encoded, construct a bitone sequence containing a first monotone sequence and a second monotone sequence with opposite cardinality frequencies.

[0038] In this embodiment of the invention, the sorting module is used to output a monotonic sequence based on the cardinality frequency corresponding to each cardinality to be encoded. A bitone sequence is composed of two monotone sequences with opposite cardinality frequencies. By traversing and comparing a set of disordered cardinality frequencies corresponding to the cardinality to be encoded, a cardinality sequence that continuously changes from low frequency to high frequency is determined as the first monotone sequence, and a cardinality sequence that continuously changes from high frequency to low frequency is determined as the second monotone sequence. Then, these two sequences with opposite monotones are merged according to a predetermined rule to construct a bitone sequence containing the characteristic of opposite cardinality frequency monotones. The predetermined rule can be to directly concatenate an ascending monotone sequence with a descending monotone sequence.

[0039] Specifically, assuming there is a set of cardinal numbers to be encoded and their corresponding cardinal frequencies, the sorting module analyzes the frequency data, taking the portion with increasing cardinal frequencies as the first monotonic sequence and the portion with decreasing frequencies as the second monotonic sequence, and then merging the two to form a bitonic sequence. For example, in actual operation, the sorting module uses a specific algorithm to merge two adjacent monotonic sequences with opposite monotonicity into a bitonic sequence and perform preliminary sorting, laying the foundation for subsequent processing. Taking an 8-element cardinal number sequence to be encoded as an example, firstly, two adjacent elements are merged to generate four monotonic sequences with opposite monotonicity. Then, two adjacent sequences of length 2 are merged to generate two bitonic sequences of length 4. Finally, the two bitonic sequences of length 4 with opposite monotonicity are merged to construct the bitonic sequence. The bitonic sequence contains the first monotonic sequence and the second monotonic sequence with opposite monotonicity. For example, taking a sequence of 8 elements as an example, the constructed bitonic sequence can be 2, 4, 6, 8, 7, 5, 3, 1.

[0040] For example, the process of the sorting module generating a bitonic sequence can be as follows: Figure 4 As shown.

[0041] Step 402: Based on the merging module in the bitonic sorting module, the bitonic sequence is recursively divided into subsequences, and the subsequences are recursively merged by cross-segment comparison and exchange to output a monotonic sequence.

[0042] In this embodiment of the invention, the merging module in the bitonic sorting module performs recursive partitioning and merging operations on the constructed bitonic sequence. The merging module divides the bitonic sequence in half according to a certain length, forming multiple subsequences. Within each subsequence and between subsequences, the cardinality frequencies at the same position are compared in parallel through the comparison circuit inside the hardware accelerator. Here, "same position" refers to: assuming a sequence (1…n) is divided in half, and n=2^k, 1 and n / 2+1, 2 and n / 2+2 are at the same position. Based on the comparison results, elements are swapped according to the rules of bitonic sorting to ensure that the orderliness of the cardinality frequencies within each subsequence and between adjacent subsequences is further optimized. For example, in the first round of recursive partitioning, the bitonic sequence is divided into two subsequences of equal length. The cardinality frequencies at the same position in these two subsequences are compared and swapped, causing the larger frequency value to move to one end of the sequence and the smaller frequency value to move to the other end. Then, the processed subsequences are merged again to form a new, more ordered sequence. Next, the new sequence is recursively partitioned and merged, with the length of each subsequence halved each time, until the subsequence length reaches a predetermined minimum (e.g., 2). During this process, the parallel processing capabilities of the hardware accelerator allow for simultaneous comparison and swapping of multiple subsequences, significantly improving sorting efficiency.

[0043] For example, continuing with the ascending merging of a bitonic sequence of 8 elements, during the operation of the hardware accelerator, the merging module first divides the sequence 2, 4, 6, 8, 7, 5, 3, 1 in half, and then performs cross-segment comparison and swap operations. That is, 2 and 7 are compared, the smaller value is placed in position 2, and the larger value is swapped to position 7, and so on, completing the first round of comparison and swapping. The result of the first round of swapping can be 2, 4, 3, 1, 7, 5, 6, 8. Next, the merging module repeats the above comparison and swapping process for these two sequences of length 4, dividing the sequence into 4 groups. The first two groups are then subjected to cross-segment comparison and swap operations, for example, 2 and 3 are compared, 4 and 1 are compared, 7 and 6 are compared, and 5 and 8 are compared. The smaller value is placed before the larger value, and the result of the second round of operations can be 2, 1, 3, 4, 6, 5, 7, 8. As the recursion progresses, the length of the comparison sequence gradually decreases until the length of the comparison sequence is 2, which completes the last round of comparison and swapping, at which point the final sorting result is obtained. The final comparison is equivalent to comparing and swapping the values ​​within the four subsequences in turn, placing the smaller value first and the larger value last. The result of the final comparison can be: 1, 2, 3, 4, 5, 6, 7, 8, which is the target sorting result after ascending order.

[0044] For example, the merging module can merge bitonic sequences as follows: Figure 5 As shown.

[0045] Step 403: Determine the target sorting result based on the arrangement order of each cardinality to be encoded in the monotonic sequence.

[0046] In this embodiment of the invention, after multiple rounds of recursive partitioning and merging operations, the bitone sequence is eventually transformed into a monotone sequence. The hardware accelerator can determine the target sorting result based on the arrangement order of the cardinal numbers to be encoded in this monotone sequence.

[0047] In this embodiment of the invention, by first constructing a bitonetic sequence with opposite cardinality and frequency monotonicity, the data characteristics can be fully utilized, laying the foundation for efficient sorting. Then, by recursively partitioning and merging the bitonetic sequences to output a monotone sequence, an ordered result can be quickly obtained, improving sorting efficiency. Furthermore, implementing the above method in hardware allows the parallel computing capabilities of the hardware to process the sorting and merging operations of the bitonetic sorting module in parallel, accelerating the sorting process. Moreover, since the structure of the hardware accelerator is fixed, unnecessary logical overhead can be reduced, further improving processing speed and enabling rapid determination of the target sorting result.

[0048] Optionally, step 102 may include the following steps: Step 501: Generate an initial Huffman tree based on the target sorting result of the cardinality frequency corresponding to each of the cardins to be encoded.

[0049] In this embodiment of the invention, leaf nodes corresponding to each cardinality to be encoded are created. The weights of the leaf nodes are sorted according to the cardinality frequency, and a priority queue is then created. In each iteration, the two nodes with the smallest and second smallest weights are selected from the priority queue and merged to generate a new merged node, which is then reinserted into the priority queue. This process is repeated until only one node remains in the priority queue, at which point the initial Huffman tree structure is constructed. Simultaneously, based on the initial Huffman tree structure, starting from the root node, leftward branches are encoded as 0, and rightward branches are encoded as 1, until a leaf node is reached. The encoding path of each node in the initial Huffman tree is the initial Huffman code for the cardinality to be encoded corresponding to that node. By constructing the initial Huffman tree according to the cardinality frequency, the initial architecture of the Huffman tree is completed, and the basic connection relationships between the nodes are determined.

[0050] An initial Huffman tree is constructed based on the sorting results. Encoding is performed from the leaf nodes to the root node of the initial Huffman tree. This construction allows cardinal numbers that appear more frequently to be represented by shorter codes, and cardinal numbers that appear less frequently to be represented by longer codes, thereby reducing the overall size of the encoded data and achieving the purpose of data compression.

[0051] Optionally, step 501 may include the following steps: Step 601: For any of the cardinal numbers to be encoded, create a leaf node corresponding to the cardinal number to be encoded and determine the weighted sorting result of the leaf node corresponding to the cardinal number to be encoded based on the target sorting result of the cardinal frequency corresponding to the cardinal number to be encoded.

[0052] In this embodiment of the invention, for each cardinality to be encoded, the encoding generation module creates leaf nodes corresponding to each cardinality. These leaf nodes serve as the basic elements of the Huffman tree, carrying information about the cardinality to be encoded. Simultaneously, the weight ranking of each leaf node is determined based on the target ranking result of the cardinality frequency corresponding to each cardinality to be encoded. For any given cardinality to be encoded, the target ranking result of the cardinality frequency corresponding to that cardinality is the same as the weight ranking of the leaf nodes corresponding to that cardinality.

[0053] Step 602: Create a priority queue containing each leaf node according to the weight sorting results of each leaf node.

[0054] In this embodiment of the invention, based on the weight sorting results of the leaf nodes, the encoding generation module can create a priority queue containing all leaf nodes using a register set. The priority queue is a special queue data structure that automatically adjusts the order of nodes according to their weights, ensuring that the nodes with the smallest and second-smallest weights can be quickly retrieved each time. Simultaneously, an index register stores the index of the queue's least frequent node for quick access to the node with the smallest weight. This hardware-implemented priority queue enables efficient node insertion and popping operations, meeting the requirements of iterative merging.

[0055] Step 603: For any round of iteration, based on the two target nodes with the smallest and second smallest weights in the priority queue, generate a target merge node, and insert the target merge node into the priority queue based on the weights corresponding to the target merge node; the node types of the target node include leaf nodes and merge nodes.

[0056] In this embodiment of the invention, during each iteration of constructing the initial Huffman tree, the encoding generation module obtains the two target nodes with the smallest and second smallest weights from the priority queue through the index register. These two target nodes can be leaf nodes (i.e., the leaf nodes corresponding to the original cardinality to be encoded) or intermediate nodes generated in previous iterations, i.e., merged nodes. Based on the two target nodes, a new merged node is created, and the weight of the merged node is the sum of the weights of the two target nodes. The information of the new node is saved to the corresponding storage unit, and the target merged node is inserted into the priority queue according to the weight of the new target merged node. The information of the new target merged node may include information such as the child node lookup table index, non-child node markers, and the weight of the new node.

[0057] Step 604: If the priority queue contains only one target node, stop the iteration and generate the initial Huffman tree.

[0058] In this embodiment of the invention, when the priority queue contains only one target node, it indicates that all leaf nodes and merged nodes have been integrated, and the iteration stops at this point. The unique node in the priority queue serves as the root node of the initial Huffman tree, thus completing the construction of the initial Huffman tree. Encoding is generated based on the structure of the initial Huffman tree. Starting from the root node of the initial Huffman tree, leftward branches are encoded as 0, rightward branches are encoded as 1, and so on until a leaf node is reached. The encoding path of each node in the initial Huffman tree is the initial Huffman code of the radix to be encoded corresponding to that node.

[0059] In this embodiment of the invention, the importance of high-frequency cardinality is highlighted by determining the weight sorting of leaf nodes based on cardinality frequency. In each iteration, the node with the smallest weight is merged to generate a new target merge node, which is then inserted into the queue. This process gradually builds the tree structure until only one node remains in the priority queue, at which point the iteration stops and the initial Huffman tree is generated. This process ensures that high-frequency cardinality encoding is short and low-frequency cardinality encoding is long in subsequent encoding processes, making the overall encoding more compact, effectively compressing data, improving encoding efficiency, and reducing storage and transmission costs.

[0060] Step 502: For any of the cardinal numbers to be encoded, based on the node depth information corresponding to the cardinal number to be encoded, determine the initial layer encoding corresponding to the level of the cardinal number to be encoded in the initial Huffman tree, and construct the target Huffman tree based on the initial layer encoding.

[0061] In this embodiment of the invention, after constructing the initial Huffman tree, the encoding generation module further analyzes the structural characteristics of the initial Huffman tree based on the node depth information corresponding to the cardinality to be encoded. According to the structural characteristics of the initial Huffman tree, the node depth information corresponding to nodes at the same level in the initial Huffman tree is the same, that is, the number of branches (i.e., encoding length) traversed on the path from the root node to any node at that level is the same. For any cardinality to be encoded, based on the node depth information corresponding to the cardinality to be encoded, the initial layer encoding corresponding to the level of the cardinality to be encoded in the initial Huffman tree can be determined. The node depth information corresponding to the cardinality to be encoded is used to characterize the path length (number of branches) from the leaf node to the root node corresponding to the cardinality to be encoded, that is, the encoding length corresponding to the initial Huffman encoding of the cardinality to be encoded. The node depth information corresponding to the cardinality to be encoded can be obtained from the depth information table. The initial layer encoding can be calculated using the node depth information corresponding to the layer through a preset algorithm. The preset algorithm can be the RFC1951 protocol and the DEFLATE algorithm.

[0062] The initial Huffman tree is optimized and adjusted by constructing initial layer codes for each level and sequentially incrementing the codes corresponding to the cardinality of the same layer by 1 based on the initial layer codes, ultimately constructing the target Huffman tree. For example, assuming a certain level contains two leaf nodes, and the node depth information corresponding to each leaf node is 3, then the initial layer code calculated according to the preset algorithm is 110, and the codes corresponding to the two leaf nodes can be 110 and 111 (i.e., 110+1).

[0063] In the hardware implementation, a set of registers stores the initial layer codes corresponding to each level in a predetermined order and according to rules. Simultaneously, a multiplexer selects the appropriate initial layer code based on the node depth information corresponding to the radix to be encoded. The adder then increments the selected initial layer codes by 1 sequentially to obtain the paradigmatic Huffman code corresponding to the radix to be encoded. For example, after the multiplexer group outputs the selected initial layer code to the adder group, the adder group increments the input initial layer code by 1. For example, suppose the initial layer code for a certain layer is "000". When generating the code for the first radix to be encoded in a layer, "000" is read directly from the register as the code. To generate the code for the second radix, the initial layer code "000" is input to the adder, with "001" (representing an increment operation) as the other input. The adder outputs "001" as the code for the second radix. To generate the code for the third radix, the code "001" from the second radix is ​​input to the adder again, with "001" as the other input. The adder outputs "010" as the code for the third radix, and so on. When performing the increment operation, the adder considers the carry rules of binary encoding to ensure the correctness of the result. After the increment operation is complete, the output of the adder group is the paradigmatic Huffman code of the radix to be encoded.

[0064] In this embodiment of the invention, by generating an initial Huffman tree with initial encoding according to the cardinality frequency, it is possible to ensure that the high-frequency cardinality encoding is short, achieving preliminary compression. Then, based on the node depth information corresponding to the cardinality to be encoded, the initial layer encoding is determined to construct the target Huffman tree, which standardizes the encoding generation rules for the same level. This retains the advantage of traditional Huffman coding in optimizing the encoding length based on frequency, while also making the encoding structure more regular through initial layer encoding, facilitating hardware implementation and decoding, reducing encoding storage space, and improving encoding efficiency and overall performance.

[0065] Step 103: Using the encoding module in the hardware accelerator, a compressed data stream is generated based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream; the target encoding result consists of target encoding information corresponding to the target encoding cardinality determined based on the target Huffman tree and an incremental value, wherein the target encoding cardinality and the incremental value are obtained by mapping the symbols to be encoded. In this embodiment of the invention, the encoding module in the hardware accelerator may integrate logic circuits and storage units related to Huffman coding. For example, the encoding module may include a register set for storing the target Huffman tree structure, and an arithmetic logic unit (ALU) for implementing radix lookup and encoding generation.

[0066] During the dynamic encoding phase, the encoding module first reads the symbols to be encoded one by one from the input data stream. For each read symbol, the target encoding result is determined according to the target Huffman tree. Then, based on the target encoding results corresponding to each symbol, the hardware accelerator integrates them in the order of the input data stream to generate the final compressed data stream.

[0067] Optionally, step 103 may include the following steps: Step 701: For any symbol to be encoded in the input data stream, perform partition mapping on the symbol to be encoded to obtain the target encoding cardinality and increment value corresponding to the symbol to be encoded.

[0068] In this embodiment of the invention, for any symbol to be encoded in the input data stream, the hardware accelerator can perform partition mapping on the symbol to be encoded to obtain the target encoding cardinality and increment value corresponding to the symbol to be encoded.

[0069] Step 702: Based on the target Huffman tree, determine the target coding information corresponding to the target coding cardinality.

[0070] In this embodiment of the invention, based on the constructed target Huffman tree, the hardware accelerator can quickly determine the corresponding target encoding information according to the target encoding cardinality obtained from partition mapping. For example, the correspondence between each encoding cardinality and its corresponding encoding information can be pre-stored in an encoding table. The target encoding information corresponding to the target encoding cardinality is determined by using a lookup table (LUT) in the hardware circuit to store the correspondence between the target encoding cardinality and the target encoding information. In this process, the hardware accelerator can perform parallel lookups on multiple target encoding cardins to obtain the corresponding target encoding information.

[0071] Step 703: Concatenate the target encoding information with the incremental value to obtain the target encoding result corresponding to the symbol to be encoded.

[0072] In this embodiment of the invention, the target encoding information and the incremental value are concatenated according to a preset concatenation rule to obtain the target encoding result corresponding to the symbol to be encoded. The preset concatenation rule may involve placing the target encoding information in the high-order bits and the incremental value in the low-order bits.

[0073] Hardware accelerators can use logic circuits to concatenate target encoded information with incremental values. The logic circuits can combine the target encoded information and incremental values ​​according to preset concatenation rules. For example, a shift-combination operation can be used to shift the incremental value to the appropriate position in the target encoded information, resulting in the concatenated encoded result.

[0074] For example, taking the value 23 as an example, after partitioning and mapping, the value 23 can be mapped to 1000_110, where the target encoding cardinality is 1000 and the increment value is 110. Based on the target Huffman tree, the encoding information corresponding to the target encoding cardinality 1000 can be determined to be 010. Therefore, the encoding result of the value 23 can be 010_110. In this encoding process, the target encoding cardinality is encoded while the increment value remains unchanged, thus obtaining the target encoding result corresponding to the symbol to be encoded.

[0075] Step 704: Based on the target encoding results corresponding to each of the symbols to be encoded, generate a compressed data stream corresponding to the input data stream.

[0076] In this embodiment of the invention, based on the target encoding results corresponding to each symbol to be encoded, the hardware accelerator integrates them in the order of the input data stream to generate the final compressed data stream. The hardware accelerator can then output the integrated compressed data stream to a designated storage device or transmission channel.

[0077] Understandably, the storage format and transmission protocol of the encoded results need to be considered during the integration process. For example, the encoded results can be stored in a byte-aligned manner to facilitate subsequent transmission and processing.

[0078] In this embodiment of the invention, by partitioning and mapping the symbols to be encoded using a preset mapping table, the target encoding cardinality and increment value can be quickly determined, improving initial processing efficiency. Then, the encoding information is determined using a target Huffman tree, and the encoding information is concatenated with the increment value. The encoding length can be optimized based on the cardinality frequency, improving the compression ratio and generating a compressed data stream corresponding to the input data stream, which can reduce data storage and transmission volume to some extent. Simultaneously, with the support of a hardware accelerator, the encoding process can be processed in parallel, shortening the encoding processing time and improving the real-time performance and efficiency of the encoding.

[0079] In summary, in this embodiment of the invention, the frequency extraction module in the hardware accelerator determines the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol; the encoding generation module in the hardware accelerator generates a target Huffman tree based on the target sorting result of the radix frequencies corresponding to each radix to be encoded; and the encoding module in the hardware accelerator generates a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. Thus, the frequency extraction module in the hardware accelerator can adaptively determine the radix frequency corresponding to each radix to be encoded by the input data, shortening the frequency statistics time and improving processing efficiency. The encoding generation module constructs a Huffman tree structure based on the target sorting result, so that high-frequency radixes correspond to short codes and low-frequency radixes correspond to long codes, achieving efficient compressed representation of the data and improving the compression ratio. The encoding module generates a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. The parallel processing capability of the hardware accelerator enables the encoding module to process multiple radixes simultaneously, achieving fast encoding conversion. The entire encoding process is completed efficiently and collaboratively within the hardware accelerator, reducing data transmission and software scheduling overhead and improving the speed and performance of data compression.

[0080] Optionally, embodiments of the present invention may further include the following steps: Step 801: For any round of iteration, add the node association information corresponding to the target merge node to the child node retrieval table.

[0081] In this embodiment of the invention, during any iteration of constructing the initial Huffman tree, after generating a target merge node based on the two target nodes with the smallest and second smallest weights in the priority queue, the node association information corresponding to the target merge node is added to the child node retrieval table. The node association information may include the node identifier information of the target merge node and the node identifier information of the two target nodes involved in generating the target merge node. That is, the relevant information of the two target nodes associated with the target merge node is added to the child node retrieval table. For example, the hardware accelerator can, in parallel, write the node identifier information of the target merge node (such as node number, node type, node weight, etc.), the node identifier information of the two associated target nodes, and the association relationship between the target merge node and the two target nodes (i.e., the two target nodes are downstream nodes of the target merge node) as the node association information corresponding to the target merge node into the corresponding storage unit of the child node retrieval table according to a specific data format.

[0082] Step 802: If the node type of the target node is a leaf node, set the node depth information of the target node in the depth information table to 1.

[0083] In this embodiment of the invention, after generating a target merge node based on the two target nodes with the smallest and second smallest weights in the priority queue, the node depths of the two target nodes are updated. If the target node is a leaf node, its depth is set to 1 and written to the depth information storage unit using its index in the priority queue as the index. For example, when the hardware accelerator determines that the target node is a leaf node, since leaf nodes are the bottom-level nodes of the Huffman tree, their node depth can be set to 1. At this time, the hardware circuit will locate the corresponding storage unit in the depth information table according to the identification information of the target merge node and set the depth value in that storage unit to 1. The depth information table can be a data structure in the hardware accelerator used to store the node depth information of each node.

[0084] Step 803: If the node type of the target node is a merged node type, determine the associated nodes corresponding to the target node based on the child node retrieval table, and increment the node depth information of each associated node in the depth information table by one.

[0085] In this embodiment of the invention, if the target node is not a leaf node, that is, if the node type of the target node is a merged node, then the child node retrieval table is accessed, all associated nodes that are related to the target node are retrieved in the child node retrieval table, and the node depth information of all associated nodes is incremented by 1.

[0086] For example, the hardware accelerator first uses the child node lookup table to query the identification information of the two target nodes (i.e., associated nodes) based on the node association information of the target merging nodes. Then, the hardware circuit accesses the depth information table in parallel based on the node identification information of these associated nodes, reads their current depth values, increments each depth value by 1, and writes it back to the depth information table. For example, if the current depth value of associated node A is 2 and the current depth value of associated node B is 3, the hardware accelerator will read these two values ​​simultaneously, increment them by 1 to obtain 3 and 4 respectively, and then write the updated values ​​back to the corresponding storage unit in the depth information table. This parallel processing method can fully leverage the high-speed computing advantage of the hardware accelerator, shorten the node depth information update time, and improve the efficiency of the entire target Huffman tree construction process.

[0087] In this embodiment of the invention, by constructing and updating the child node retrieval table and the depth information table in real time, parallel and high-speed data processing can be achieved with the support of hardware accelerators, greatly improving the efficiency of coding construction.

[0088] For example, Figure 6 A schematic diagram illustrating the generation process of a target Huffman tree is shown, such as... Figure 6As shown, the priority queue contains multiple leaf nodes sorted according to their respective weights. An index register stores the index of the minimum frequency in the queue for quick access to the two nodes with the lowest and second lowest weights. For an iterative process, the two target nodes with the lowest and second lowest weights are merged to generate a target merged node. The sum of the weights of the two target nodes is used as the target merged node, and it is inserted into the priority queue based on its weight. Simultaneously, the node association information corresponding to the target merged node is added to the child node retrieval table, and the depth information table is updated according to the node types of the two target nodes.

[0089] Figure 7 This is a schematic diagram of the structure of a hardware accelerator provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the hardware accelerator includes a frequency extraction module, a bitonic sorting module, an encoding generation module, and an encoding module; The frequency extraction module 901 is used to determine the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol; The bitone sorting module 902 is used to perform bitone sorting on the radix to be encoded according to the radix frequency corresponding to each radix to be encoded, so as to obtain the target sorting result; The encoding generation module 903 is used to generate a target Huffman tree based on the target sorting result of the cardinality frequency corresponding to each cardinality to be encoded; the cardinality to be encoded corresponds to a leaf node in the target Huffman tree; The encoding module 904 is used to generate a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream; the target encoding result consists of target encoding information corresponding to the target encoding cardinality determined based on the target Huffman tree and the incremental value, the target encoding cardinality and the incremental value are obtained by mapping the symbol to be encoded.

[0090] Optionally, the bitone sorting module 902 is further configured to: Based on the sorting module in the bitone sorting module, a bitone sequence containing a first monotone sequence and a second monotone sequence with opposite monotonicity of the cardinality of the cardinality is constructed based on the cardinality frequency corresponding to each cardinality to be encoded. Based on the merging module in the bitone sorting module, the bitone sequence is recursively divided into subsequences, and the subsequences are recursively merged by cross-segment comparison and exchange to output a monotone sequence. The target sorting result is determined based on the arrangement order of each cardinality to be encoded in the monotonic sequence.

[0091] Optionally, the encoding generation module 903 is further configured to: Based on the target sorting results of the cardinality frequency corresponding to each of the cardins to be encoded, an initial Huffman tree is generated; For any given cardinality to be encoded, based on the node depth information corresponding to the cardinality to be encoded, the initial layer encoding corresponding to the level of the cardinality to be encoded in the initial Huffman tree is determined, and the target Huffman tree is constructed based on the initial layer encoding.

[0092] Optionally, the encoding generation module 903 is further configured to: For any of the cardinal numbers to be encoded, a leaf node corresponding to the cardinal number to be encoded is created, and the weighted sorting result of the leaf node corresponding to the cardinal number to be encoded is determined based on the target sorting result of the cardinal frequency corresponding to the cardinal number to be encoded. Create a priority queue containing each of the leaf nodes according to the weight sorting results of each leaf node; For any round of iteration, a target merge node is generated based on the two target nodes with the smallest and second smallest weights in the priority queue, and the target merge node is inserted into the priority queue based on the weights corresponding to the target merge node; the node types of the target node include leaf nodes and merge nodes; If the priority queue contains only one target node, the iteration stops and the initial Huffman tree is generated.

[0093] Optionally, the encoding generation module 903 is further configured to: For any iteration process, the node association information corresponding to the target merge node is added to the child node retrieval table; If the node type of the target node is a leaf node, the node depth information of the target node in the depth information table is set to 1; If the target node is of the merged node type, the associated nodes corresponding to the target node are determined based on the child node retrieval table, and the node depth information of each associated node in the depth information table is incremented by one.

[0094] Optionally, the encoding module 904 is further configured to: For any symbol to be encoded in the input data stream, perform partition mapping on the symbol to be encoded to obtain the target encoding cardinality and increment value corresponding to the symbol to be encoded; Based on the target Huffman tree, determine the target coding information corresponding to the target coding cardinality; The target encoding information is concatenated with the incremental value to obtain the target encoding result corresponding to the symbol to be encoded; Based on the target encoding results corresponding to each of the symbols to be encoded, a compressed data stream corresponding to the input data stream is generated.

[0095] Optionally, the frequency extraction module 901 includes: The target selection circuit corresponding to the input symbol received by the frequency extraction module is determined by the control register in the frequency extraction module. The input symbol is input to the target selection circuit, and the base number to be encoded corresponding to the input symbol output by the target selection circuit is determined; The target value of the statistical register connected to the target selection circuit is obtained and used as the base frequency corresponding to the base to be encoded.

[0096] This invention provides a hardware accelerator. A frequency extraction module within the hardware accelerator determines the radix frequency corresponding to each radix to be encoded, obtained by mapping each input symbol. An encoding generation module within the hardware accelerator generates a target Huffman tree based on the target sorting result of the radix frequencies corresponding to each radix to be encoded. An encoding module within the hardware accelerator generates a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. Thus, the frequency extraction module in the hardware accelerator can adaptively determine the radix frequency corresponding to each radix to be encoded, shortening the frequency statistics time and improving processing efficiency. The encoding generation module constructs a Huffman tree structure based on the target sorting result, ensuring that high-frequency radixes correspond to short codes and low-frequency radixes correspond to long codes, achieving efficient compressed data representation and improving the compression ratio. The encoding module generates a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. The parallel processing capability of the hardware accelerator allows the encoding module to process multiple radixes simultaneously, achieving fast encoding conversion. The entire encoding process is completed efficiently and collaboratively within the hardware accelerator, reducing data transmission and software scheduling overhead and improving the speed and performance of data compression.

[0097] As the hardware accelerator implementation is basically similar to the method implementation, it is described in a relatively simple way. For relevant details, please refer to the description of the method implementation.

[0098] The present invention also provides a system-on-a-chip, characterized in that it includes: a memory, a processor, and a hardware accelerator, wherein the hardware accelerator is configured to implement the encoding method of the foregoing embodiments.

[0099] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0100] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0101] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0102] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0103] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for performing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0104] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0105] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0106] It should be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device. The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An encoding method, characterized in that, Applied to hardware accelerators; the method includes: The frequency extraction module in the hardware accelerator determines the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol. The encoding generation module in the hardware accelerator generates a target Huffman tree based on the target sorting result of the cardinality frequency corresponding to each cardinality to be encoded; the cardinality to be encoded corresponds to a leaf node in the target Huffman tree; The encoding module in the hardware accelerator generates a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. The target encoding result consists of target encoding information corresponding to the target encoding cardinality determined based on the target Huffman tree and an incremental value. The target encoding cardinality and the incremental value are obtained by mapping the symbols to be encoded.

2. The method according to claim 1, characterized in that, The method further includes: The hardware accelerator uses a bitone sorting module to perform a bitone sort on the radix to be encoded according to the radix frequency corresponding to each radix to be encoded, thereby obtaining the target sorting result.

3. The method according to claim 2, characterized in that, The step of performing a bitonic sort on the cardinal numbers to be encoded according to the cardinal frequency corresponding to each cardinal number to obtain the target sorting result includes: Based on the sorting module in the bitone sorting module, a bitone sequence containing a first monotone sequence and a second monotone sequence with opposite monotonicity of the cardinality of the cardinality is constructed based on the cardinality frequency corresponding to each cardinality to be encoded. Based on the merging module in the bitone sorting module, the bitone sequence is recursively divided into subsequences, and the subsequences are recursively merged by cross-segment comparison and exchange to output a monotone sequence. The target sorting result is determined based on the arrangement order of each cardinality to be encoded in the monotonic sequence.

4. The method according to claim 1, characterized in that, The generation of the target Huffman tree based on the target sorting result of the cardinality frequency corresponding to each of the cardins to be encoded includes: Based on the target sorting results of the cardinality frequency corresponding to each of the cardins to be encoded, an initial Huffman tree is generated; For any given cardinality to be encoded, based on the node depth information corresponding to the cardinality to be encoded, the initial layer encoding corresponding to the level of the cardinality to be encoded in the initial Huffman tree is determined, and the target Huffman tree is constructed based on the initial layer encoding.

5. The method according to claim 4, characterized in that, The initial Huffman tree is generated based on the target sorting result of the cardinality frequency corresponding to each of the cardins to be encoded, including: For any of the cardinal numbers to be encoded, a leaf node corresponding to the cardinal number to be encoded is created, and the weighted sorting result of the leaf node corresponding to the cardinal number to be encoded is determined based on the target sorting result of the cardinal frequency corresponding to the cardinal number to be encoded. Create a priority queue containing each of the leaf nodes according to the weight sorting results of each leaf node; For any round of iteration, a target merge node is generated based on the two target nodes with the smallest and second smallest weights in the priority queue, and the target merge node is inserted into the priority queue based on the weights corresponding to the target merge node; the node types of the target node include leaf nodes and merge nodes; If the priority queue contains only one target node, the iteration stops and the initial Huffman tree is generated.

6. The method according to claim 5, characterized in that, The method further includes: For any iteration process, the node association information corresponding to the target merge node is added to the child node retrieval table; If the node type of the target node is a leaf node, the node depth information of the target node in the depth information table is set to 1; If the target node is of the merged node type, the associated nodes corresponding to the target node are determined based on the child node retrieval table, and the node depth information of each associated node in the depth information table is incremented by one.

7. The method according to claim 1, characterized in that, The process of generating a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream includes: For any symbol to be encoded in the input data stream, perform partition mapping on the symbol to be encoded to obtain the target encoding cardinality and increment value corresponding to the symbol to be encoded; Based on the target Huffman tree, determine the target coding information corresponding to the target coding cardinality; The target encoding information is concatenated with the incremental value to obtain the target encoding result corresponding to the symbol to be encoded; Based on the target encoding results corresponding to each of the symbols to be encoded, a compressed data stream corresponding to the input data stream is generated.

8. The method according to claim 1, characterized in that, The step of determining the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol through the frequency extraction module in the hardware accelerator includes: The target selection circuit corresponding to the input symbol received by the frequency extraction module is determined by the control register in the frequency extraction module. The input symbol is input to the target selection circuit, and the base number to be encoded corresponding to the input symbol output by the target selection circuit is determined; The target value of the statistical register connected to the target selection circuit is obtained and used as the base frequency corresponding to the base to be encoded.

9. A hardware accelerator, characterized in that, The hardware accelerator includes a frequency extraction module, a bitonic sorting module, an encoding generation module, and an encoding module; The frequency extraction module is used to determine the radix frequency corresponding to each radix to be encoded obtained by mapping each input symbol; The bitonic sorting module is used to perform bitonic sorting on the radix to be encoded according to the radix frequency corresponding to each radix to be encoded, so as to obtain the target sorting result; The encoding generation module is used to generate a target Huffman tree based on the target sorting result of the cardinality frequency corresponding to each of the cardins to be encoded. The cardinality to be encoded corresponds to a leaf node in the target Huffman tree; The encoding module is used to generate a compressed data stream based on the target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream; The target encoding result consists of target encoding information corresponding to the target encoding cardinality determined based on the target Huffman tree and an incremental value. The target encoding cardinality and the incremental value are obtained by mapping the symbol to be encoded.

10. A system-on-a-chip, characterized in that, include: A memory, a processor, and a hardware accelerator, the hardware accelerator being configured to implement the steps of the encoding method as described in any one of claims 1 to 8.

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