Method and apparatus for providing demapping system with phase compensation for demapping uplink transmissions

Abstract

The present disclosure relates to methods and apparatus for providing a demapping system with phase compensation for demapping uplink transmissions. In an embodiment, a method is provided, the method comprising: detecting a processing type associated with a received uplink transmission; and when the detected processing type is a first processing type, performing the following: removing a resource unit including a reference signal from the uplink transmission; de-mapping the remaining resource unit layers of the uplink transmission into two or more layers; performing phase compensation on all the layers to generate phase-compensated layers; and soft demapping all the phase compensated layers to produce phase compensated, soft demapped bits.

Description

Case Analysis

[0001] This application is a divisional application of Chinese Patent Application No. 202110192225.1, filed on February 19, 2021, entitled “Method and apparatus for providing a demapping system with phase compensation to demapping uplink transmissions”.

[0002] Cross-references to related applications

[0003] This application is a continuation-in-part (CIP) of U.S. Patent Application No. 16 / 404,029, filed on May 6, 2019, entitled “METHOD AND APPARATUS FOR PROVIDING A DEMAPPING SYSTEM TODEMAP UPLINK TRANSMISSIONS.”

[0004] Application 16 / 404,029 claims priority to U.S. Provisional Application No. 62 / 667,215, filed May 4, 2018, entitled “Method and Apparatus for Providing a Sample Single-Shot Processing Scheme for Data Transmission.” U.S. Provisional Application No. 62 / 667,215, filed May 4, 2018, is incorporated in its entirety by reference to Application 16 / 404,029.

[0005] This application claims priority to U.S. Provisional Application No. 62 / 978,700, filed February 19, 2020, entitled “(Method and Apparatus for Providing a Sample Single-Shot Processing Scheme for Data Transmission),” which is incorporated herein by reference in its entirety. Technical Field

[0006] Exemplary embodiments of the present invention relate to telecommunications networks. More specifically, exemplary embodiments of the present invention relate to using wireless communication networks to receive and process data streams. Background Technology

[0007] With the rapid growth of mobile and remote data access via high-speed communication networks such as LTE, 4G, and 5G cellular services, accurately transmitting and decrypting data streams has become increasingly challenging. High-speed communication networks capable of transmitting information include, but are not limited to, wireless networks, cellular networks, wireless personal area networks (“WPANs”), wireless local area networks (“WLANs”), and wireless metropolitan area networks (“MANs”). While WPANs can be Bluetooth or ZigBee, WLANs can be Wi-Fi networks conforming to the IEEE 802.11 WLAN standard.

[0008] In 5G systems, reference signals can be included in uplink transmissions. These signals are used to estimate channel conditions or for other purposes. However, these signals are mixed with the data, so the reference signals must be taken into account when the data is processed. For example, when processing data received in a resource element, special handling may be needed to skip resource elements that contain reference signals. Even if the reference signal is set to zero or empty, its resource element still needs to be considered when processing the data.

[0009] Therefore, a system is desired that can effectively demap received uplink transmissions while overcoming the shortcomings of conventional systems. Summary of the Invention

[0010] In various exemplary embodiments, methods and apparatuses are provided for a demapping system for efficiently demapping 4G and 5G uplink transmissions. When a first type of processing is used, a reference signal is removed from the received resource element during the uplink transmission before layer demapping. Then, after layer demapping and before descrambling, soft demapping is performed. When a second type of processing is used, the received resource element is despread before the soft demapping process. In this second case, reference signal removal and layer demapping are bypassed. When a third type of processing is used, the received resource element is directly input to the soft mapper, bypassing the despreader. Therefore, the demapping system operates to provide fast and resource-efficient demapping between received uplink transmissions in 4G and 5G wireless networks.

[0011] In one embodiment, a method is provided, comprising: detecting a processing type associated with a received uplink transmission; and when the detected processing type is a first processing type, performing the following operations: removing resource elements containing reference signals from the uplink transmission; demapping the remaining resource element layers of the uplink transmission into two or more layers; and performing soft demapping on the two or more layers to generate soft-demapped data. The method further comprises: descrambling the soft-demapped data to generate descrambled data; and processing the descrambled data to generate uplink control information (UCI).

[0012] In one embodiment, an apparatus is provided, comprising: a detector that detects a processing type associated with a received uplink transmission; and a reference signal (RS) remover that removes resource elements containing reference signals from the uplink transmission when the detected processing type is a first processing type. The apparatus further comprises: a layer demapper that, when the detected processing type is the first processing type, demaps the remaining resource elements of the uplink transmission into two or more layers; and a soft demapper that, when the detected processing type is the first processing type, performs soft demapping on the two or more layers to produce soft-demapped bits.

[0013] In one embodiment, a method is provided, the method comprising: detecting a processing type associated with a received uplink transmission; and when the detected processing type is a first processing type, performing the following operations: removing resource elements containing reference signals from the uplink transmission; demapping the remaining resource element layers of the uplink transmission into two or more layers; performing phase compensation on all layers to generate phase-compensated layers; and performing soft demapping on all phase-compensated layers to generate phase-compensated, soft-demapped bits.

[0014] In one embodiment, an apparatus is provided, comprising: a detector that detects a processing type associated with a received uplink transmission; and a layer demapper that, when the detected processing type is a first processing type, demaps resource elements of the uplink transmission into two or more layers. The apparatus further comprises: a phase compensation circuit that performs phase compensation on all layers; and a soft demapper that, when the detected processing type is the first processing type, performs soft demapping on two or more phase-compensated layers to produce phase-compensated, soft-demapped bits.

[0015] Other features and benefits of exemplary embodiments of the present invention will become apparent from the detailed description, drawings, and claims set forth below. Attached Figure Description

[0016] The exemplary aspects of the invention will be more fully understood through the detailed embodiments and accompanying drawings of the various embodiments of the invention given below. However, these should not be construed as limiting the invention to the specific embodiments, but are merely for explanation and understanding.

[0017] Figure 1 A block diagram of a communication network is shown, in which uplink transmissions from user equipment are demapped by an exemplary embodiment of a demapping system.

[0018] Figure 2 An exemplary embodiment of the understanding mapping system is shown.

[0019] Figure 3 It shows in Figure 2 An exemplary embodiment of the layer demapper used in the demapping system is shown.

[0020] Figure 4 An exemplary method for performing demapping is shown according to an exemplary embodiment of a demapping system.

[0021] Figure 5 It shows in Figure 2 An exemplary embodiment of the phase compensator used in the soft demapper provided in the demapping system is shown.

[0022] Figure 6 It shows in Figure 2 An exemplary embodiment of the software demapper provided in the demapping system is shown.

[0023] Figure 7 An exemplary method for performing I / Q phase compensation is shown for use with... Figure 2 The software demapper provided in the demapping system shown is used together.

[0024] Figure 8 This is a block diagram illustrating an exemplary embodiment of a processing system having a demapping system. Detailed Implementation

[0025] In this document, aspects of the invention are described in the context of methods and apparatus for demapping data received in 5G uplink transmissions.

[0026] The purpose of the following detailed description is to provide an understanding of one or more embodiments of the invention. Those skilled in the art will recognize that the following detailed description is merely illustrative and not intended to be limiting. Other embodiments will readily suggest to those skilled in the art who have benefited from this disclosure and / or description.

[0027] For clarity, not all conventional features of the implementations described herein are shown and described. It should be understood that in the development of any such actual implementation, many implementation-specific decisions may be made to achieve the developer's specific goals (such as compliance with constraints related to the application and business), and these specific goals may differ for different implementations and for different developers. Furthermore, it will be understood that such development work may be complex and time-consuming, but will still be routine engineering work for those skilled in the art who benefit from the embodiments of this disclosure.

[0028] The various embodiments of the invention illustrated in the accompanying drawings may not be drawn to scale. Instead, for clarity, the dimensions of various features may be enlarged or reduced. Additionally, some drawings may be simplified for clarity. Therefore, the drawings may not depict all components of a given device (e.g., apparatus) or method. Throughout the drawings and in the following detailed description, the same reference numerals are used to refer to the same or similar parts.

[0029] The terms “system” or “device” are generally used herein to describe any number of components, elements, subsystems, devices, packet switching elements, packet switches, access switches, routers, networks, modems, base stations, eNBs (eNodeBs), computers and / or communication equipment or mechanical components, or combinations thereof. The term “computer” includes a processor, memory, and bus capable of executing instructions, wherein a computer refers to one or a cluster of computers, personal computers, workstations, mainframes, or combinations thereof.

[0030] IP communication networks, IP networks, or communication networks refer to any type of network with an access network capable of transmitting data over a transmission medium in the form of packets or cells, such as ATM (Asynchronous Transfer Mode) types, such as TCP / IP or UDP / IP types. An ATM cell is the result of decomposing (or segmenting) a data packet (IP type), and those packets (here, IP data packets) include an IP header, a header specific to the transmission medium (e.g., UDP or TCP), and payload data. IP networks can also include satellite networks, DVB-RCS (Digital Video Broadcast-Return Channel System) networks providing internet access via satellite, or SDMB (Digital Multimedia Broadcast Satellite) networks, terrestrial networks, cable (xDSL) networks, or mobile or cellular networks (GPRS / EDGE or UMTS (for MBMS (Multimedia Broadcast / Multicast Service) types, or UMTS evolution known as LTE (Long Term Evolution) or DVB-H (Digital Video Broadcast-Handheld)) or hybrid (satellite and terrestrial) networks.

[0031] Figure 1A block diagram of a communication network 100 is shown, wherein uplink transmissions from user equipment are demapped by an exemplary embodiment of a demapping system (DS) 152. Network 100 includes a packet data network gateway (“P-GW”) 120, two serving gateways (“S-GW”) 121-122, two base stations (or cell sites) 102-104, a server 124, and the Internet 150. P-GW 120 includes various components 140, such as a billing module 142, a subscription module 144, and / or a tracking module 146, to facilitate routing activities between source and destination. It should be noted that the basic concept of the exemplary embodiments of the invention will not change even if one or more boxes (or devices) are added to or removed from diagram 100.

[0032] Network configuration 100 can also be referred to as fourth-generation (“4G”), Long Term Evolution (LTE), fifth-generation (5G), New Radio (NR), or a combination of 4G and 5G cellular network configurations. On one hand, a Mobility Management Entity (MME) 126 is coupled to a base station (or cell site) and an S-GW capable of facilitating data transfer between 4G LTE and 5G. The MME 126 performs various control / management functions, network security, and resource allocation.

[0033] In one example, S-GW 121 or 122, coupled to P-GW 120, MME 126, and base station 102 or 104, can route data packets from base station 102 or eNodeB to P-GW 120 and / or MME 126. The function of S-GW 121 or 122 is to perform anchoring functions for mobility between 3G and 4G devices. S-GW 122 is also capable of performing various network management functions, such as terminating paths, paging idle UEs, storing data, routing information, generating copies, etc.

[0034] The P-GW 120, coupled to the S-GW 121-122 and Internet 150, enables network communication between user equipment (“UE”) and IP-based networks such as Internet 150. The P-GW 120 is used for connectivity, packet filtering, inspection, data usage, billing, or PCRF (Policy and Charging Rules Function) enforcement. The P-GW 120 also provides anchoring functionality for mobility between 4G and 5G packet core networks.

[0035] Base station 102 or 104, also referred to as a cell site, Node B, or eNodeB, includes one or more radio towers 110 or 112. Radio tower 110 or 112 is also coupled to various UEs, such as cellular phones 106, handheld devices 108, tablets, and / or iPad® 107, via wireless communication or channels 137-139. Devices 106-108 can be portable or mobile devices, such as iPhone®, BlackBerry®, Android®, etc. Base station 102 facilitates network communication via radio tower 110 between mobile devices such as UEs 106-107 and the S-GW 121. It should be noted that base stations or cell sites may include additional radio towers and other terrestrial switching circuits.

[0036] To improve efficiency and / or accelerate the extraction of uplink control information received from any user equipment, a demapping system 152 operating according to one of three processing types is provided. In an embodiment, the demapping system 152 applies phase compensation to the received bits as a first stage of the demapping process. When the first type of processing is used, a reference signal is removed from the resource elements of the received uplink transmission before layer demapping. Then, after layer demapping is completed, soft demapping is performed before descrambling. When the second type of processing is used, the received resource elements are despread before the soft demapping process. In this second case, reference signal removal and layer demapping are bypassed. In the third processing type, the received resource elements bypass RE removal, layer demapping, and despreading and are directly input to the soft demapper. A more detailed description of the demapping system 152 is provided below.

[0037] Figure 2 It shows Figure 1 An exemplary detailed embodiment of the demapping system 152 shown. Figure 1 . Figure 2A user equipment (“UE”) 224 with an antenna 228 is shown, which allows wireless communication with a base station 112 via a wireless transmission 226. The UE 224 transmits uplink communication 230 received by a base station front-end (FE) 228, the FE 228 outputting a received symbol 234 including a received reference symbol. In an embodiment, the base station includes a gain normalizer 202, an inverse transform block (IDFT) 204, configuration parameters 222, a demapping system 152, a descrambler 218, and a combiner / extractor 220. In an exemplary embodiment, the demapping system 152 includes a processing detector 208, an RS (reference signal or symbol) remover 210, a layer demapping unit 212, a despreader 214, and a soft demapping unit 216. In an embodiment, the soft demapping unit 216 includes a phase compensation circuit 232 that applies phase compensation to the input I / Q bits. The first stage of the soft demapping process. The output of the soft demapper 216 is input to the descrambler 218, and its output is input to the combiner / extractor 220 that produces the decoded UCI information.

[0038] In an embodiment, the demapping system 154 processes one symbol at a time, which may come from multiple layers of NR, and the demapping system 154 processes the entire subframe or time slot of the layer used for LTE, covering the 1ms transmission time interval (TTI), the 7-OFDM symbol (OS) short TTI, and the 2 / 3-OS TTI. The modulation order can be derived as follows. 1. (π / 2) BPSK for NR 2. QPSK, 16QAM, 64QAM, 256QAM, and (π / 2) BPSK for LTE sub-PRB

[0039] In addition, demapping rules are applied to constellations defined in standards such as LTE (4G) and NR (5G). Configuration parameters (box 222)

[0040] In an embodiment, configuration parameter 222 includes multiple fields, which contain information for... Figure 2 The parameters used in the multiple boxes shown. For example, some configuration parameters in configuration parameter 222 control the operation of gain normalizer 202, IDFT 204, and demapping system 152. In an embodiment, configuration parameter 222 may indicate that gain normalizer 202 and IDFT 204 will be bypassed. Gain normalizer (box 202)

[0041] In this embodiment, gain normalizer 202 performs gain normalization on the received uplink transmission. For example, gain normalizer 202 is suitable for LTE and NR DFT-s-OFDM scenarios. The input samples are normalized per data symbol and per subcarrier as follows, wherein the normalized gain value calculated per symbol is as follows. Gainnorm_out [Ds][sc]= (Gainnorm_in [Ds][sc]) / (Norm_Gain[Ds]) IDFT (box 204)

[0042] The IDFT 204 operation provides an inverse transform to generate a time-domain signal. In this embodiment, IDFT 204 is enabled only for LTE and NR DFT-s-OFDM and LTE sub-PRB. In this embodiment, the input and output are assumed to be 16-bit I and Q values, respectively. The DFT and IDFT operations are defined as follows: as well as

[0043] in . Processing type detector (box 208)

[0044] In an exemplary embodiment, the process type detector 214 detects the type of process to be performed by the system. For example, this information can be detected from configuration parameter 222. In an embodiment, the process type detector 208 operates to detect one of three process types, covering the following system operations. 1. Type 1 - 5G NR DFT-s-OFDM 2. Type 1 - 5G NR CP-OFDM 3. Type 2 - 5G NR PUCCH Format 4 4. Type 3 - 4G LTE DFT-s-OFDM 5. Type 3 - 4G LTE Sub-PRB Allocation RS Remover (Box 210)

[0045] In an embodiment, RS remover 210 operates during Type 1 processing to remove RS resource units from the received data stream to produce a data stream to be input to the layer demapper. For example, the RE positions of RS symbols are identified, and data is rewritten into one or more buffers to remove RS symbols to produce an output containing only data. In an embodiment, Type 1 processing includes RS / DTX removal, layer demapping with an interleaved structure, soft demapping, and descrambling. The benefit of removing RS before layering is that it allows for single-shot descrambling without any interference in a continuous manner, without the need for additional buffering. Layer demapper (box 212)

[0046] Figure 3 An exemplary embodiment of the layer demapper 212 is shown. In this embodiment, multi-layer data (L0-L3) and signal-to-interference-plus-noise ratio (SINR) (L0-L3) from a certain subcarrier are transferred to the layer demapper circuit 302 via a multi-threaded read DMA operation. In this case, as Figure 3 As shown, each thread will point to a memory location in a different layer for a specific symbol. Layer demapping circuit 302 generates demapped data and multiple pSINR reports layer by layer. In this embodiment, for NR, DMRS / PTRS / DTX REs are removed from the information stream before the soft demapping from both I / Q and SINR samples.

[0047] Refer again Figure 2 The additional boxes of the demapping system 152 are described in detail below. Despreader (box 214)

[0048] In this embodiment, despreader 214 provides despreading only for PUCCH Format 4. This involves combining the repeating symbol along the frequency axis after multiplying it by the conjugate of the appropriate extension sequence. The extension sequence index used to correctly combine the information, as well as the extension type, is given by configuration parameter 222. This process is always performed on a total of 12 REs. After despreading, depending on the extension type, the number of REs to be pushed to subsequent boxes is reduced by half or 1 / 4. Before soft demapping, the combined result is averaged and stored as 16 bits. Software demapper (box 216)

[0049] In an embodiment, the soft demodulator 216 includes a phase compensation circuit 232, which acts as a first stage for performing compensation on the received I / Q signals prior to soft demodulation. A detailed description of the phase compensation circuit 232 is provided below. The soft demodulation principle is based on calculating the log-likelihood ratio (LLR) of the bits, which quantifies the level of determinism regarding whether a logic 0 or 1 is present. Under the assumption of Gaussian noise, the LLR for the i-th bit is given as follows: Where c j and c k For the constellation point of the i-th bit, values ​​of 0 and 1 are assigned respectively. Note that for the gray-scale mapping modulation scheme given in [R1], x can be used to represent a single dimension I or Q. The computational complexity increases linearly with the modulation order. To reduce computational complexity, the maximum logarithm (MAP) approximation is used. Note that since the LLR of QPSK has only one term in both the numerator and denominator, this approximation is not necessary for QPSK.

[0050] This approximation is accurate, especially in the high SNR region, and greatly simplifies LLR calculation, avoiding complex exponential and logarithmic operations. Assuming I and Q are the real and imaginary input samples, the soft LLR is defined as follows for (π / 2) BPSK, QPSK, 16QAM, 64QAM, and 256QAM, respectively.

[0051] It should be noted that (π / 2) BPSK is only applicable to NR DFT-s-OFDM and LTE sub-PRB scenarios. This modulation format has two flavors. In the first flavor, the constellation diagram is shifted (π / 2) across subcarriers along the frequency axis. Therefore, the demapper will change the demapping rules from one subcarrier to another in the following order. In the second flavor, the demapping rules remain the same along the frequency axis, and the soft demapper will always use the first rule described below to generate the LLR. This behavior of changing the LLR generation rules across or without frequency cross-frequency ...

[0052] In an embodiment, the soft demapper 216 includes a first minimum function component (“MFC”), a second MFC, a special processing component (“STC”), a subtractor, and / or an LLR generator. The function of the soft demapper 216 is to demap or determine soft bit information associated with received symbols or bitstreams. For example, the soft demapper 216 employs a soft demapping principle based on calculating the log-likelihood ratio (LLR) of a bit, which quantifies the level of certainty about whether the bit is logic 0 or logic 1. To reduce noise and interference, the soft demapper 216 is also capable of discarding one or more unused constellation points associated with the bitstream frequency from the constellation map.

[0053] In one aspect, when a bitstream is identified and requires special processing, the STC is configured to force an infinity value as an input to the first MFC. For example, predefined control signals with a specific set of coding categories (such as ACK (acknowledgment) signals with a set of predefined coding categories) require special processing. In one aspect, one form of special processing is to force an infinity value as an input to the MFC. For example, when a bitstream is identified as an ACK or RI with a predefined coding category, the STC forces an infinity value as an input to both the first and second MFCs. In another case, the STC is configured to determine whether special processing (or a special processing function) is required based on the received bitstream or symbols. In one aspect, 1-bit and 2-bit control signals with predefined coding categories listed in Table 1 require special processing. It should be noted that Table 1 is exemplary, and other configurations are also possible. Table 1

[0054] Table 1 shows six (6) exemplary control signals with predefined coding categories. For the sake of simplicity, the six (6) control signals are renamed or referred to as ACK [1], ACK [2], ACK [3], ACK [4], RI [1], and RI [2], respectively. For example, 1 bit ACK “0” ACK =1” is called ACK [1], and a 1-bit ACK bundle is called ACK [2]. 2-bit ACK “O” ACK =2” is called ACK [3], and a 2-bit ACK bundle is called ACK [3]. Similarly, a 1-bit RI”O RI = 1” is called RI[1], and 2 bits RI“O RI= 2” is called RI [2]. Note that ACK [1] indicates that the ACK control signal uses one (1) bit to indicate its value, and ACK [3] indicates that the ACK control signal uses two (2) bits to indicate its value. ACK bundling reduces the number of ACKs transmitted in a time-division duplex LTE network by using a logical AND operation between ACKs belonging to multiple downlink subframes. Descrambler (box 218)

[0055] Descrambler 218 is configured to generate a descrambled sequence of bit sequences or bit streams. For example, after generating a sequence based on input values, the descrambler determines whether sequence modification is required for a specific category of control information. The bit stream or sequence is then descrambled to produce a descrambled soft bit set. Combiner / Extractor (Box 220)

[0056] Combiner / extractor 220 provides combining and extraction functions to combine descrambled soft bits from descrambler 218 and extract uplink control information (“UCI”).

[0057] Figure 4 An exemplary method 400 for performing demapping according to an exemplary embodiment of a demapping system is shown. For example, method 400 is suitable for use with... Figure 2 The demapping system 152 shown is used together. In various exemplary embodiments, method 400 performs demapping operations for three processing types while reusing the same hardware of demapping system 152, thereby providing fast and efficient demapping for received 4G and 5G uplink transmissions.

[0058] In box 402, uplink transmissions are received in a 4G / 5G communication network. For example, uplink communication in... Figure 2 The signal is received at the front end 228 shown.

[0059] In box 404, perform gain normalization. For example, gain normalization is performed by... Figure 2 The gain normalizer 202 shown is executed.

[0060] In box 406, an inverse Fourier transform is performed to obtain the time-domain signal. For example, this process is performed by... Figure 2 The IDFT box 204 shown is executed.

[0061] In box 408, the type of processing to be performed is determined. For example, descriptions of three processing types are provided above. If the first type of processing is to be performed, the method proceeds to box 410. If the second type of processing is to be performed, the method proceeds to box 420. If the third type of processing is to be performed, the method proceeds to box 414. For example, the operation is performed by... Figure 2The processing type detector 208 shown is executed.

[0062] In box 420, when the processing type is type 2, despreading is performed on the received resource unit. For example, this operation is performed by... Figure 2 The despreader 214 shown is executed. The method then proceeds to block 414.

[0063] When the processing type is type 3, the method proceeds to box 414.

[0064] When the processing type is type 1, perform the following operations.

[0065] In box 410, the reference signal is removed from the received resource unit. For example, the resource unit containing RS / DTX is removed. This operation is performed by... Figure 2 The RS remover 210 shown is executed.

[0066] In box 412, layer demapping is performed. For example, resource units without RS / DTX are layer demapped. This operation is performed by layer demapper 212.

[0067] In box 414, soft demapping is performed. For example, soft demapping 216 soft demaps the bits for each processing type. During processing type 3, soft demapping 216 receives resource units and soft demaps these bits to produce a soft-demapped output. During processing type 2, soft demapping 216 receives despread bits from despreader 214 and soft demaps these bits to produce a soft-demapped output. During processing type 1, soft demapping 216 receives layer-demapped bits from layer demapping 212 and soft demaps these bits to produce a soft-demapped output.

[0068] In box 416, descrambling is performed. For example, descrambler 218 receives soft-demapped bits from soft demapper 216 and generates descrambled bits.

[0069] In box 418, the combination and extraction of UCI information are performed. For example, combiner / extractor 220 receives descrambled bits, combines these bits, and extracts the UCI information.

[0070] Therefore, method 400 operates according to exemplary embodiments to provide demapping. It should be noted that the operation of method 400 can be modified, added to, combined, deleted, rearranged, or otherwise altered within the scope of the embodiments.

[0071] Figure 5 It shows the use of in Figure 2An exemplary embodiment of the phase compensator 232 used in the soft demapper provided in the illustrated demapping system is shown. In this embodiment, the phase compensator 232 is configured to reduce phase noise, particularly in high-frequency wireless communication systems, for better communication quality. In this embodiment, the phase compensator 232 includes a multiplier 502, shift and rounding circuits 504 and 510, saturation circuits 506 and 512, and a phase coefficient calculator 524 for calculating the phase compensation coefficient 508.

[0072] During operation, the phase coefficient calculator 524 calculates the phase compensation coefficient 508. In an embodiment, the calculator 524 receives as... Figure 2 The receiver reference symbol 526, a portion of the received symbol 234 shown, is used as input. The calculator 524 also receives a generated reference symbol 528 internally generated in another circuit of the demapping system 152. The calculator 524 determines the phase difference between the received symbol 234 and the generated symbol 528, and uses this phase difference to calculate a phase compensation coefficient 508, which is a fixed-point complex value expressed in Q14 format. In this embodiment, the calculator 524 calculates up to four phase compensation coefficients for up to four layers.

[0073] Multiplier 502 receives I / Q bits 514, which include a 16-bit value. Multiplier 502 also receives a phase compensation coefficient 508, which also includes 16 bits. The multiplier multiplies its inputs to generate an output 518, which includes 33 bits representing real (Re) and imaginary (Im) values, respectively, which are input to shift and round-off circuits 504 and 510.

[0074] Shift and round circuit 504 receives the Re bit, shifts the Re input right by 14 bits, and rounds the result. The output of shift and round circuit 504 is input to saturation circuit 506. Similarly, shift and round circuit 510 receives the Im bit, shifts the Im input right by 14 bits, and rounds the result. The output of shift and round circuit 510 is input to saturation circuit 512.

[0075] The saturation circuit 506 adjusts the saturation level of the shifted and rounded Re bits. For example, the 16-bit saturation circuit 506 adjusts the saturation level of the shifted and rounded Re bits to maintain the Re value at (2... 15 -1 to -2 15 Within the range of ), then output the saturated adjusted Re bits 520.

[0076] The saturation circuit 512 adjusts the saturation level of the shifted and rounded Im bits. For example, the 16-bit saturation circuit 512 adjusts the saturation level of the shifted and rounded Im bits to maintain the Im value at (2... 15 -1 to -2 15 Within the range of ), the saturated adjusted Im bit 520 is then output. Re bit 520 and Im bit 522 represent the phase-compensated I / Q bits input to the next stage of the soft demapper 216.

[0077] Figure 6 It shows the use of in Figure 2 An exemplary embodiment of a soft demapper 600 used in the illustrated demapping system. In this embodiment, the soft demapper 600 is suitable for use as... Figure 2 The soft demapper 216 is shown. In an embodiment, the soft demapper 600 includes multipliers 602 and 612, shift and round (RND) circuits 604 and 610, an LLR offset circuit 606, and a saturation circuit 608.

[0078] During operation, the soft demapper 600 receives phase-compensated I-bits and Q-bits 520 / 522 and multiplies these signals by a scaled SINR signal. For example, the SINR signal 624 is input to multiplier 612. A modulation (MOD) scaled signal 626 is also input to multiplier 612. The output of multiplier 612 is input to shift and round-down circuit 610, which right-shifts its input by RSFT1 bits and rounds the result. The output of shift and round-down circuit 610 is input to multiplier 602, which also receives phase-compensated I-bits and Q-bits 520 / 522. The output of multiplier 602 is input to shift and round-down circuit 604, which right-shifts its input by RSFT2 bits and rounds the result. The output of shift and round-down circuit 604 is input to LLR offset circuit 606. The bias signal 620 is used to apply a bias, and the resulting output is input to the saturation circuit 608, which adjusts the saturation level of its input signal to generate a phase-compensated, soft-demapped LLR signal 622.

[0079] Figure 7 It shows the use of with Figure 2 The illustrated method 700 is an exemplary method for performing I / Q phase compensation, used in conjunction with a soft demapper 216 provided in the demapping system. For example, method 700 is suitable for use with... Figure 4 The phase compensation circuit 232 shown is used together.

[0080] In box 702, I / Q bits are received at the soft demapper. For example, in Figure 2 The soft demapper shown receives I / Q bits at position 216. For example... Figure 2 As shown, I / Q bits can be received from any of boxes 208, 212, or 214. In this embodiment, I / Q bits are received at the phase compensation circuit 232 of the soft demapper 216.

[0081] In box 704, the phase compensation coefficient is determined. For example, the phase coefficient calculator 524 calculates the compensation coefficient 508 by comparing the phase of the internally generated reference symbol 528 with the received reference symbol 526.

[0082] In box 706, the received I and Q bits are multiplied by the calculated coefficients. For example, multiplier 502 multiplies I / Q bits 514 with phase coefficient 508 to generate real values ​​(Re 33 bits) and imaginary values ​​(Im 33 bits).

[0083] In block 708, the Re value is shifted and rounded. For example, the Re bit is input to shift and round circuit 504, in which the Re bit is right-shifted by 14 bits and then rounded.

[0084] In block 710, the Im value is shifted and rounded. For example, the Im bit is input to shift and rounding circuit 510, in which the Im bit is right-shifted by 14 bits and then rounded.

[0085] In block 712, adjustment of the saturation level of the shifted and rounded Re bits is performed. For example, 16-bit saturation circuit 506 adjusts the saturation level of the shifted and rounded Re bits to maintain the Re value at (2... 15 -1 to -2 15 Within the range of ), then output the saturated adjusted Re bits 520.

[0086] In block 714, adjustment of the saturation level of the shifted and rounded Im bits is performed. For example, the 16-bit saturation circuit 512 adjusts the saturation level of the shifted and rounded Im bits to maintain the Im value at (2... 15 -1 to -2 15 Within the range of ), then output 522 saturated-adjusted Im bits.

[0087] In block 716, soft demapping is performed on the phase-compensated I / Q bits. For example, phase-compensated I / Q bits 520 / 522 are input to soft demapping unit 600 to generate soft-demapped LLR bits 622.

[0088] In box 718, the soft-demapped LLR bits 622 are input to descrambler 218.

[0089] Therefore, method 700 operates according to exemplary embodiments to provide phase-compensated soft demapping. It should be noted that the operation of method 700 can be modified, added to, combined, deleted, rearranged, or otherwise altered within the scope of the embodiments.

[0090] Figure 8 This is a block diagram illustrating a processing system 800 having an exemplary embodiment of a demapping system 830. It will be apparent to those skilled in the art that other alternative computer system architectures may also be employed.

[0091] System 800 includes a processing unit 801, an interface bus 812, and an input / output (“I / O”) unit 820. Processing unit 801 includes a processor 802, main memory 804, a system bus 811, static storage device 806, a bus control unit 805, and mass storage memory 808. Bus 811 is used to transfer information between various components and processor 802 for data processing. Processor 802 can be any of a variety of general-purpose processors, embedded processors, or microprocessors, such as ARM embedded processors, Intel Core™2 Duo, Core™2 Quad, Xeon, Pentium™ microprocessors, AMD family processors, MIPS embedded processors, or proprietary PC™ microprocessors.

[0092] Main memory 804 may include multi-level cache memory for storing frequently used data and instructions. Main memory 804 may be random access memory (RAM), magnetic RAM (MRAM), or flash memory. Static memory 806 may be a read-only memory connected to bus 811 for storing static information and / or instructions. Bus control unit 805 is connected to buses 811-812 and controls which components (e.g., main memory 804 or processor 802) can use the bus. Mass storage memory 808 may be a disk, solid-state drive (“SSD”), optical disk, hard disk drive, floppy disk, optical disk, and / or flash memory for storing large amounts of data.

[0093] In one example, I / O unit 820 includes a display 821, a keyboard 822, a cursor control device 823, a decoder 824, and a communication device 825. The display device 821 can be a liquid crystal display, a flat panel display, a cathode ray tube (“CRT”), a touchscreen display, or other suitable display device. The display 821 projects or displays graphic images or windows. The keyboard 822 can be a conventional alphanumeric input device used to transfer information between computer system 800 and the computer operator. Another type of user input device is the cursor control device 823, such as a mouse, touch mouse, trackball, or other type of cursor used to transfer information between system 800 and the user.

[0094] Communication device 825 is connected to bus 812 for accessing information from a remote computer or server via a wide area network. Communication device 825 may include a modem, router, or network interface device, or other similar devices facilitating communication between computer 800 and the network. In one aspect, communication device 825 is configured to perform wireless functions. Alternatively, demapping system 830 and communication device 825 perform demapping functions according to an embodiment of the invention.

[0095] In one aspect, the demapping system 830 is coupled to bus 811 and configured to demapping received uplink communication as described above to improve overall receiver performance. The demapping system 830 includes hardware, firmware, or a combination of both.

[0096] Although specific embodiments of the invention have been shown and described, it will be apparent to those skilled in the art, based on the teachings herein, that changes and modifications may be made without departing from these exemplary embodiments and their broader aspects. Therefore, the appended claims are intended to encompass within their scope all variations and modifications that fall within the true spirit and scope of these exemplary embodiments of the invention.

Claims

1. A method for providing phase compensation to reduce phase noise, the method comprising: Reference symbols are identified from received symbols via a wireless communication network; The generated reference symbols are obtained from the components of the demapping system; Calculate the phase compensation coefficients based on the reference symbols and the generated reference symbols; as well as Real Re bit values ​​and virtual Im bit values ​​are generated by multiplying the input with the phase compensation coefficient.

2. The method according to claim 1, further comprising: The Re bit value is shifted and rounded to generate a shifted Re bit value, and the saturation level of the shifted Re bit value is adjusted to generate a phase-compensated Re output.

3. The method according to claim 1, further comprising: The Im bit value is shifted and rounded to generate a shifted Im bit value, and the saturation level of the shifted Im bit value is adjusted to generate a phase-compensated Im output.

4. The method according to claim 1, further comprising: Detect the processing type associated with uplink transmission.

5. The method according to claim 1, further comprising: When the first processing type is detected, the resource unit containing the reference signal is removed from the uplink transmission.

6. The method according to claim 1, further comprising: When the first processing type is detected, the remaining resource units of the uplink transmission are demapped into two or more layers.

7. The method according to claim 1, further comprising: When the first processing type is detected, phase compensation is performed on all layers to generate a phase compensation layer.

8. The method according to claim 1, further comprising: When the first processing type is detected, soft demapping is performed on all phase compensation layers to generate phase-compensated soft demapping bits.

9. The method according to claim 1, further comprising: When the second processing type is detected, the received uplink transmission is despread to generate despread real / in-phase I bits and virtual / quadrature Q bits.

10. The method according to claim 1, further comprising: When the second processing type is detected, phase compensation is performed on the despread I bits and Q bits, and soft demapping is performed on the phase-compensated despread I bits and Q bits to generate phase-compensated soft demapping bits.

11. The method of claim 1, further comprising acquiring a modulated MOD scaling signal.

12. The method of claim 11, further comprising multiplying the MOD scaled signal by a scaled signal interference noise ratio (SINR) signal to generate a first result.

13. The method of claim 12 further includes shifting and rounding the first result by a first predefined value to generate a second result.

14. The method of claim 13, further comprising multiplying the second result by the Re output to generate a third result.

15. The method of claim 14, further comprising shifting and rounding in response to the third result to generate a phase-compensated soft demapping log-likelihood ratio (LLR) signal.

16. The method of claim 1, wherein when the detected processing type is a third processing type, the following operations are performed: Perform an inverse discrete Fourier transform (IDFT) on the received uplink transmission to generate an IDFT output with real / in-phase I bits and imaginary / orthogonal Q bits; Phase compensation is performed on the I-bit and the Q-bit to generate phase-compensated I-bit and Q-bit; as well as Soft demapping is performed on the phase-compensated I bits and Q bits to produce phase-compensated soft demapping bits.

17. A method for providing phase compensation to reduce phase noise, the method comprising: Real Re bit values ​​are generated by multiplying the input signal by the phase compensation coefficient; The modulated MOD scaled signal is multiplied by the scaled signal interference noise ratio (SINR) signal to generate the first result; The first result is shifted and rounded using a first predefined value to generate a second result; Multiply the second result by the Re output to generate the third result; as well as The shift and rounding in response to the third result generate a phase-compensated soft demapping log-likelihood ratio (LLR) signal.

18. The method of claim 17, further comprising: Reference symbols are identified from received symbols via a wireless communication network.

19. The method of claim 17, further comprising obtaining the generated reference symbol through a component of the demapping system.

20. The method of claim 17, further comprising calculating a phase compensation coefficient based on a reference symbol and a generated reference symbol.

21. The method of claim 17, further comprising multiplying the input by the phase compensation coefficient to generate Re bit values ​​and imaginary Im bit values.

22. The method of claim 17, further comprising removing the resource unit containing the phase tracking reference signal PTRS.

23. The method of claim 17, further comprising removing the resource unit containing the demodulation reference signal DMRS.

24. The method of claim 17, further comprising removing resource units indicating discontinuous transmission of DTX.

25. The method of claim 17, further comprising receiving uplink transmissions from a user equipment in a fourth-generation 4G or fifth-generation 5G wireless network.

26. An apparatus for providing phase compensation to reduce phase noise, the apparatus comprising: The phase coefficient calculator is configured to calculate the phase compensation coefficient based on the reference symbol and the generated reference symbol. A multiplier, coupled to the phase coefficient calculator, is configured to generate real Re-bit values ​​by multiplying the phase compensation coefficients by the input; A first shift and rounding circuit is coupled to the multiplier and configured to generate a shifted and rounded Re bit value; as well as A saturated circuit is coupled to a first shift and round circuit and is operable to generate a Re output in response to the shifted and rounded Re bit value.

27. The apparatus of claim 26, wherein the multiplier is capable of generating a virtual Im bit value by multiplying the phase compensation coefficient by the input.

28. The apparatus of claim 27, further comprising: The second shift and rounding circuit is configured to generate shifted and rounded Im-bit values.

29. The apparatus of claim 27, further comprising: Another saturation circuit is capable of operating to generate an Im output in response to the shifted and rounded Im bit value.

30. The apparatus of claim 26, further comprising: The detector is configured to detect the processing type associated with received uplink transmissions.

31. The apparatus of claim 26, further comprising a reference signal RS remover configured to remove a resource element containing a reference signal from an uplink transmission.

32. The apparatus of claim 26 further includes a layer demapper operable to demap the remaining resource units of the uplink transmission into two or more layers.

33. The apparatus of claim 26 further includes a soft demapper operable to soft demap two or more phase compensation layers to produce phase-compensated soft demapped bits.

34. The apparatus of claim 26, further comprising a despreader configured to despread a received uplink transmission to produce despread real / in-phase I bits and virtual / quadrature Q bits.

35. The apparatus of claim 26, further comprising: A front-end used to receive uplink transmissions from user equipment in a fourth-generation (4G) or fifth-generation (5G) wireless network.

36. An apparatus for providing phase compensation to reduce phase noise, the apparatus comprising: A component that identifies a reference symbol from a received symbol via a wireless communication network; The components that generate the reference symbols are obtained through the demapping system components; A component that calculates phase compensation coefficients based on the reference symbols and the generated reference symbols; as well as The component generates real Re bit values ​​and virtual Im bit values ​​by multiplying the input with the phase compensation coefficient.

37. The apparatus of claim 36, further comprising: The components for shifting and rounding the Re bit value to generate the shifted Re bit value, and the components for adjusting the saturation level of the shifted Re bit value to generate the phase-compensated Re output.

38. The apparatus of claim 36, further comprising: The component that shifts and rounds the Im bit value to generate the shifted Im bit value; And a component that adjusts the saturation level of the shifted Im bit value to generate a phase-compensated Im output.

39. The apparatus of claim 36 further includes a component for detecting the processing type associated with the uplink transmission.

40. The apparatus of claim 36 further includes a component for generating a phase-compensated soft demapping log-likelihood ratio (LLR) signal in response to shifting and rounding the result.

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