Embedded power module based on multilayer circuit board

Abstract

The invention provides an embedded power module based on a multi-layer circuit board, which belongs to the technical field of power module packaging and comprises a circuit board main body, a first signal wiring layer, a first insulating base material layer, a first power wiring layer, a second insulating base material layer, a second power wiring layer, a third insulating base material layer and a heat conduction layer, the embedded copper block is embedded and mounted at the junction of the third insulating base material layer and the heat conduction layer and is connected with the first power supply wiring layer through a first conductive column; a source electrode of the power chip is connected with the embedded copper block through a solder layer, a drain electrode of the power chip is connected with the second power supply wiring layer through a second conductive column, and a gate-drain driving electrode of the power chip is connected with the first signal wiring layer through a signal interconnection buried hole. The beneficial effects of the invention are that through an integrated packaging structure of the power chip and the multi-layer circuit board, an integrated heat dissipation network and a low-impedance electrode connection structure are adopted, and heat dissipation efficiency and low parasitic parameters are both considered.

Description

Technical Field

[0001] This invention relates to the field of power module packaging technology, and in particular to an embedded power module based on a multilayer circuit board. Background Technology

[0002] As the core component of power electronic systems for power conversion and control, the performance of power modules directly affects the efficiency, reliability, and miniaturization of the entire system. Silicon carbide (SiC) chips offer significant advantages such as a large bandgap, high breakdown electric field strength, high thermal conductivity, and fast switching speed. Compared to traditional silicon-based chips, SiC power chips exhibit superior performance under high voltage, high current, and high temperature conditions, and are therefore widely recognized as the core device for next-generation power modules.

[0003] However, existing silicon carbide power module packaging typically employs a stacked structure of silicon carbide power chip, solder, copper-clad ceramic insulating substrate, solder, and metal substrate. This complex structure, with its numerous intermediate steps, results in high thermal resistance, preventing the full utilization of the high thermal conductivity inherent in the silicon carbide power chip. Insufficient heat dissipation leads to excessively high module operating temperatures and shortens the module's lifespan. Furthermore, in traditional packaging, the chip is connected to a direct-bonded copper (DBC) substrate via wire bonding, resulting in a long power loop path and parasitic inductance reaching 10-20 nH. During high-frequency switching, excessive parasitic inductance can easily generate voltage spikes, causing electrical stress damage to the chip, limiting the high-frequency advantages of the silicon carbide power chip, and affecting the performance and stability of the power module in high-frequency applications. Summary of the Invention

[0004] To address the above technical problems, this invention provides an embedded power module based on a multilayer circuit board.

[0005] The technical problem solved by this invention can be achieved by the following technical solutions:

[0006] An embedded power module based on a multilayer circuit board includes:

[0007] The circuit board body includes a first signal wiring layer, a first insulating substrate layer, a first power wiring layer, a second insulating substrate layer, a second power wiring layer, a third insulating substrate layer, and a heat-conducting layer, which are stacked sequentially from top to bottom.

[0008] An embedded copper block is embedded at the junction of the third insulating substrate layer and the thermally conductive layer, and the embedded copper block is connected to the first power wiring layer through a first conductive post.

[0009] The power chip has its source electrode connected to the upper surface of the embedded copper block via a solder layer, its drain electrode connected to the second power wiring layer via a second conductive post, and its gate-drain drive electrode connected to the first signal wiring layer via a signal interconnect via.

[0010] Preferably, the first power wiring layer is made of copper foil, and at least a portion of the copper foil in the projection area of ​​the power chip has a thickness of 3oz-5oz.

[0011] Preferably, the first insulating substrate layer is made of epoxy resin filled with boron nitride, the amount of boron nitride being 25%-35%, the thermal conductivity of the first insulating substrate layer being greater than 30 W / (m·K), and the glass transition temperature of the first insulating substrate layer being greater than 180°C.

[0012] The second insulating substrate layer is made of epoxy resin filled with boron nitride, the amount of boron nitride being 25%-35%, the thermal conductivity of the second insulating substrate layer being greater than 30 W / (m·K), and the glass transition temperature of the second insulating substrate layer being greater than 180°C.

[0013] The third insulating substrate layer is made of epoxy resin filled with boron nitride, the amount of boron nitride being 25%-35%, the thermal conductivity of the third insulating substrate layer being greater than 30 W / (m·K), and the glass transition temperature of the third insulating substrate layer exceeding 180℃.

[0014] Preferably, the heat-conducting layer is made of a copper and diamond composite material, wherein the volume fraction of diamond is 20%-30%, the thickness of the heat-conducting layer is 0.8mm-1.2mm, and the thermal conductivity of the heat-conducting layer is greater than 400W / (m·K); or

[0015] The thermal conductive layer is made of a copper and aluminum nitride composite material, the thermal conductivity of the thermal conductive layer is greater than 350 W / (m·K), and the temperature resistance of the thermal conductive layer exceeds 500℃.

[0016] Preferably, the embedded copper block is made of oxygen-free copper, and the lower surface of the embedded copper block is fixedly connected to the heat-conducting layer by a pressing process.

[0017] Preferably, the solder layer is a composite solder of nano-silver and copper, wherein the silver content in the composite solder is 60%-70%, the copper nanoparticle size is 50nm-100nm, the thickness of the solder layer is 30-50μm, the shear strength after sintering is not less than 30MPa, the thermal conductivity is not less than 180W / (m·K), and the porosity is not more than 3%.

[0018] Preferably, the second conductive post is made of copper alloy, the diameter of the second conductive post is 0.3mm-0.5mm, the height of the second conductive post is 0.2mm-0.4mm, and the two ends of the second conductive post are respectively welded to the drain electrode and the second power wiring layer, with the resistance at the weld not exceeding 5mΩ;

[0019] The first conductive post is made of copper alloy, with a diameter of 0.4mm-0.6mm and a height of 0.6mm-0.8mm. The two ends of the first conductive post are respectively welded to the embedded copper block and the first power wiring layer, and the resistance at the weld is no greater than 5mΩ.

[0020] The signal interconnect via extends sequentially from the surface of the circuit board body through the first signal wiring layer, the first insulating substrate layer, the first power wiring layer, the second insulating substrate layer, and the second power wiring layer, and connects to the gate-drain drive electrode in the third insulating substrate layer.

[0021] Preferably, the surface of the first conductive post is provided with a second plating layer, the material of the second plating layer is nickel palladium gold, and the thickness of the second plating layer is 0.5μm-1μm;

[0022] The surface of the second conductive post is provided with a third plating layer, the material of which is nickel-palladium-gold, and the thickness of which is 0.5μm-1μm;

[0023] The inner wall of the signal interconnect buried via is provided with a first plating layer, the material of the first plating layer is gold, and the thickness of the first plating layer is 2μm-3μm.

[0024] Preferably, the number of signal interconnect buried vias is 3-4, the positions of the signal interconnect buried vias correspond to the gate electrode and drain electrode of the power chip respectively, and the center-to-center spacing of the signal interconnect buried vias exceeds 0.8mm.

[0025] Preferably, the power chip is a silicon carbide power chip.

[0026] The advantages or beneficial effects of the technical solution of this invention are as follows:

[0027] This invention utilizes an integrated packaging structure that combines a power chip with a multilayer circuit board. The packaging structure employs an integrated heat dissipation network consisting of a first power wiring layer, an embedded copper block, and a thermally conductive layer. Simultaneously, it employs a low-impedance electrode connection structure composed of a first conductive post, a second conductive post, and signal interconnect vias, thus balancing heat dissipation efficiency and low parasitic parameters. Attached Figure Description

[0028] Figure 1This is a cross-sectional view of an embedded power module based on a multilayer circuit board, which is a preferred embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures:

[0030] 1. First signal wiring layer; 2. First insulating substrate layer; 3. First power wiring layer; 4. Second insulating substrate layer; 5. Second power wiring layer; 6. Third insulating substrate layer; 7. Thermal conductive layer; 8. Power chip; 9. Embedded copper block; 10. Second conductive post; 11. First conductive post; 12. Signal interconnect via. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0034] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, an embedded power module based on a multilayer circuit board (MLB) is provided, such as... Figure 1 As shown, it includes:

[0035] The circuit board body includes a first signal wiring layer 1, a first insulating substrate layer 2, a first power wiring layer 3, a second insulating substrate layer 4, a second power wiring layer 5, a third insulating substrate layer 6, and a heat-conducting layer 7, which are stacked sequentially from top to bottom.

[0036] Embedded copper block 9 is embedded at the junction of the third insulating substrate layer 6 and the thermally conductive layer 7;

[0037] The power chip 8 has its source electrode connected to the upper surface of the embedded copper block 9 via a solder layer.

[0038] The low-impedance electrode connection structure includes:

[0039] The second conductive post 10 is connected between the drain electrode of the power chip 8 and the second power wiring layer 5. Furthermore, the material of the second conductive post 10 is copper alloy, the diameter of the second conductive post is 0.3mm-0.5mm, the height of the second conductive post 10 is 0.2mm-0.4mm, and the two ends of the second conductive post 10 are respectively welded to the drain electrode and the second power wiring layer 5, and the resistance at the weld is not greater than 5mΩ.

[0040] The first conductive post 11 is connected between the upper surface of the embedded copper block 9 and the first power wiring layer 3; further, the material of the first conductive post 11 is copper alloy, the diameter of the first conductive post 11 is 0.4mm-0.6mm, the height of the first conductive post 11 is 0.6mm-0.8mm, and the two ends of the first conductive post 11 are respectively welded to the embedded copper block 9 and the first power wiring layer 3, and the resistance at the weld is not greater than 5mΩ;

[0041] The signal interconnect buried via 12 is connected between the gate-drain driving electrode of the power chip 8 and the first signal wiring layer 1; further, the signal interconnect buried via 12 passes through the first signal wiring layer 1, the first insulating substrate layer 2, the first power wiring layer 3, the second insulating substrate layer 4 and the second power wiring layer 5 sequentially from the surface of the circuit board body, and connects to the gate-drain driving electrode in the third insulating substrate layer 6.

[0042] An integrated heat dissipation network includes:

[0043] The thermal conductive layer 7 is made of a copper and diamond composite material, wherein the volume fraction of diamond is 20%-30%, the thickness of the thermal conductive layer 7 is 0.8mm-1.2mm, and the thermal conductivity of the thermal conductive layer 7 is greater than 400W / (m·K).

[0044] The material of the embedded copper block 9 is oxygen-free copper. The lower surface of the embedded copper block 9 is fixedly connected to the heat-conducting layer 7 by a pressing process. In the pressing process, the pressing temperature is 200-220℃ and the pressing pressure is 1.5-2.0MPa. After pressing, the thermal resistance of the joint surface between the embedded copper block 9 and the heat-conducting layer 7 does not exceed 0.1℃ / W.

[0045] The first power wiring layer 3 is made of copper foil, and at least part of the copper foil in the projection area of ​​the power chip 8 has a thickness of 3oz-5oz. Specifically, by locally thickening the copper foil of the power wiring layer to 3-5oz to cover the projection area of ​​the power chip 8, an auxiliary heat dissipation surface is formed.

[0046] Specifically, in this embodiment, the power chip is embedded in a multilayer circuit board (MLB) to form an integrated package structure. The package structure adopts a first power wiring layer 3, an embedded copper block 9, and a thermal conductive layer 7 to form an integrated heat dissipation network. At the same time, a first conductive post 11, a second conductive post 10, and a signal interconnection via 12 are used to form a low-impedance electrode connection structure. Through chip embedding design, integrated heat dissipation network, and low-impedance electrode connection, the technical problems of high thermal resistance and high parasitic parameters in existing packages are solved, while taking into account both heat dissipation efficiency and low parasitic parameters.

[0047] Furthermore, the circuit board body has a stacked structure with 7 to 10 layers, an interlayer alignment error ≤1μm, and an interlayer peel strength ≥1.8N / mm. For example... Figure 1 As shown in the diagram, only the structure of a 7-layer circuit board is displayed. From top to bottom, the layers are: first signal wiring layer 1, first insulating substrate layer 2, first power wiring layer 3, second insulating substrate layer 4, second power wiring layer 5, third insulating substrate layer 6, and thermal conductive layer 7. The first signal wiring layer is used for signal transmission and processing; the insulating substrate layer provides interlayer isolation and circuit protection; the power wiring layer provides a stable power supply to the chip; and the thermal conductive layer 7 uses oxygen-free copper, which has excellent electrical and thermal conductivity, ensuring stable signal transmission and effectively dissipating the heat generated by the chip, ensuring the stability of the module during high-power operation.

[0048] Of course, in practical applications, the number of layers in a multilayer circuit board can be flexibly adjusted according to specific usage requirements. For example, the number of layers can be increased, such as to 8, 9, or 10 layers, to better adapt to different application environments and functional requirements. For instance, if set to 8 layers, it can... Figure 1 The bottom layer of the 7-layer example is further soldered with a metal substrate to embed heat dissipation channels; if it is set to 9 layers, two more layers of driver integrated circuits for driving chips can be designed on the top layer of the 7-layer example; if it is set to 10 layers, two more layers of driver integrated circuits for driving chips can be designed on the top layer of the 7-layer example, and a metal substrate is further soldered on the bottom layer of the 7-layer example to embed heat dissipation channels.

[0049] Furthermore, the first insulating substrate layer 2 is made of epoxy resin filled with boron nitride (BN), with a boron nitride (BN) filling amount of 25%-35%, the thermal conductivity of the first insulating substrate layer 2 is greater than 30 W / (m·K), and the glass transition temperature of the first insulating substrate layer 2 exceeds 180℃.

[0050] The glass transition temperature refers to the temperature at which the glassy state transitions to the elastic state.

[0051] Furthermore, the second insulating substrate layer 4 is made of epoxy resin filled with boron nitride, with a boron nitride filling amount of 25%-35%, the thermal conductivity of the second insulating substrate layer 4 is greater than 30 W / (m·K), and the glass transition temperature of the second insulating substrate layer 4 exceeds 180℃.

[0052] Furthermore, the third insulating substrate layer 6 is made of epoxy resin filled with boron nitride, with a boron nitride filling amount of 25%-35%. The thermal conductivity of the third insulating substrate layer 6 is greater than 30 W / (m·K), and the glass transition temperature of the third insulating substrate layer 6 exceeds 180℃.

[0053] Furthermore, the material of the thermal conductive layer 7 can be replaced with a composite material of copper and aluminum nitride (AlN). The thermal conductivity of the thermal conductive layer 7 is greater than 350W / (m·K), and the temperature resistance of the thermal conductive layer 7 exceeds 500℃, making it suitable for extreme high-power scenarios.

[0054] Furthermore, the solder layer uses a composite solder of nano-silver and copper. The silver content in the composite solder is 60%-70%, the copper nanoparticle size is 50nm-100nm, the thickness of the solder layer is 30-50μm, and the composite solder is coated and then sintered. After sintering, the shear strength of the solder layer is not less than 30MPa, the thermal conductivity of the solder layer is not less than 180W / (m·K), and the porosity of the solder layer does not exceed 3%.

[0055] In this embodiment, the size of the embedded copper block 9 is larger than the size of the power chip 8.

[0056] Furthermore, the surface of the first conductive post 11 is provided with a second plating layer, the material of which is nickel-palladium-gold, and the thickness of which is 0.5μm-1μm.

[0057] Furthermore, the surface of the second conductive post 10 is provided with a third plating layer, the material of which is nickel-palladium-gold, and the thickness of which is 0.5μm-1μm.

[0058] Specifically, in this embodiment, a nickel-palladium-gold layer is plated on the surfaces of the first conductive post 11 and the second conductive post 10. The thickness of the plating layer is 0.5-1μm, and the corrosion resistance meets the requirement of no rust after 1000 hours of salt spray testing.

[0059] Plating a nickel-palladium-gold layer improves the oxidation resistance and weldability of the conductive posts, ensuring their stability during long-term use. The conductive posts are then fixed using laser welding, which offers advantages such as high welding speed and quality. Reliable connections can be achieved with a power of 50W and a welding time of 10ms.

[0060] Furthermore, the inner wall of the signal interconnect buried via 12 is provided with a first plating layer, the material of the first plating layer is gold, and the thickness of the first plating layer is 2μm-3μm.

[0061] Specifically, in this embodiment, a gold layer with a thickness of 2-3 μm is plated on the inner wall of the signal interconnect buried via 12 to achieve direct transmission of the drive signal.

[0062] Furthermore, there are 3-4 signal interconnect buried vias 12, and the positions of the signal interconnect buried vias 12 correspond to the gate electrode and drain electrode of the power chip 8, respectively. The center-to-center spacing of the signal interconnect buried vias 12 exceeds 0.8mm.

[0063] Furthermore, power chip 8 is a silicon carbide power chip.

[0064] Furthermore, the upper surface of the power chip 8 is provided with a passivation layer, which covers the surface of the corresponding electrode on the upper surface of the power chip. The passivation layer is a composite layer of silicon dioxide (SiO2) and silicon nitride (SiN), and the thickness of the passivation layer is 5μm-8μm. The rated voltage of the power chip 8 is greater than 1200V, and the rated current of the power chip 8 is greater than 100A.

[0065] The method for fabricating an embedded power module based on a multilayer circuit board (MLB) according to the present invention includes the following steps:

[0066] Step 1, Multilayer Circuit Board Body Fabrication:

[0067] This embodiment adopts a 7-layer structure, with the layer stacking order from top to bottom being the first signal wiring layer 1, the first insulating substrate layer 2, the first power wiring layer 3, the second insulating substrate layer 4, the second power wiring layer 5, the third insulating substrate layer 6, and the heat-conducting layer 7.

[0068] Step 2, Embedded copper block 9 processing: Embedded copper block 9 is made of oxygen-free copper, and its size is slightly larger than that of the silicon carbide power chip;

[0069] Step 3, fixing the silicon carbide (SiC) power chip 8: A nano-silver-copper composite solder is coated on the upper surface of the embedded copper block 9. This composite solder can reduce the contact resistance between the chip and the copper block and improve heat dissipation efficiency. Then, the source electrode of the silicon carbide power chip is placed downwards in the area where the nano-silver-copper composite solder is coated on the upper surface of the embedded copper block 9. Next, it is placed in a specific sintering environment and sintered at a temperature of 260°C and a pressure of 0.3MPa for 40 minutes to form a combination of silicon carbide power chip 8 and embedded copper block 9.

[0070] Step 4: The assembly of the silicon carbide power chip 8 and the embedded copper block 9 is embedded into the multilayer circuit board body: the lower surface of the embedded copper block is pressed against the thermally conductive layer at a temperature of 210°C and a pressure of 1.8 MPa for 90 minutes. Through the action of high temperature and high pressure, the embedded copper block 9 and the thermally conductive layer 7 will form a tight bond, forming an integrated structure;

[0071] Step 5, Electrode Connection:

[0072] Step 5.1, Preparation of the second conductive post 10: The second conductive post 10 is made of copper alloy, with a diameter of 0.5 mm and a height of 0.3 mm. The surface is plated with nickel-palladium-gold with a thickness of 0.8 μm. The two ends of the second conductive post 10 are connected to the drain electrode on the upper surface of the power chip 8 and the second power wiring layer 5 by laser welding. The laser welding power is 50 W and the welding time is 10 ms.

[0073] Step 5.2, Preparation of the first conductive post 11: The first conductive post 11 is made of copper alloy, with a diameter of 0.4 mm, a height of 0.7 mm, and a surface plating thickness of 0.8 μm of nickel-palladium-gold. The two ends of the first conductive post 11 are connected to the upper surface of the embedded copper block 9 and the first power wiring layer 3 respectively by laser welding. The laser welding power is 50 W and the welding time is 10 ms.

[0074] Step 5.3, signal interconnect buried via 12 processing: The drilling diameter of the signal interconnect buried via 12 is 0.2 mm, and the gold plating layer thickness is 2.5 μm. The buried via penetrates the first signal wiring layer 1 and the gate-drain drive electrode on the upper surface of the silicon carbide power chip 8 to realize signal transmission and control.

[0075] This invention employs a direct heat dissipation path, which consists of the source electrode of the silicon carbide power chip 8, a nano-silver-copper composite solder, an embedded copper block 9, and a thermally conductive layer 7 connected in sequence. The composite solder has a thermal conductivity exceeding 180 W / (m·K), a 20% improvement compared to traditional silver paste. The thermally conductive layer 7 is made of copper-diamond composite material, and its thermal conductivity exceeds 400 W / (m·K), further enhancing heat dissipation efficiency and allowing the high power potential of the silicon carbide power chip to be fully realized.

[0076] The nano-silver-copper composite solder utilizes the dispersed distribution of copper nanoparticles with a particle size of 50-100 nm. On one hand, the amount of silver used is reduced by 30%, resulting in a 30% reduction in production costs compared to pure silver paste, effectively controlling costs. On the other hand, the copper nanoparticles form an antioxidant barrier, with an oxidation weight gain of ≤0.5% at 200℃, compared to 1.8% for pure silver paste. After sintering, the shear strength of the nano-silver-copper composite solder layer exceeds 30 MPa, a 20% improvement over silver paste. In thermal cycling tests (-40℃ to 200℃), the lifespan exceeds 5000 cycles, and the interface contact resistance is ≤3 mΩ, lower than the 5 mΩ of silver paste. This allows the embedded power module of this invention to balance connection reliability and cost advantages.

[0077] The embedded copper block 9 serves as both a source conductor and a heat dissipation carrier for the silicon carbide power chip. Through a dual fixation method of composite solder sintering and pressing, interlayer peeling is avoided, the electrode path is kept below 0.5mm, and the parasitic inductance is below 5nH, achieving synergistic optimization of conductivity reliability and low parasitic characteristics.

[0078] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. An embedded power module based on a multilayer circuit board, characterized in that, include: The circuit board body includes a first signal wiring layer, a first insulating substrate layer, a first power wiring layer, a second insulating substrate layer, a second power wiring layer, a third insulating substrate layer, and a heat-conducting layer, which are stacked sequentially from top to bottom. An embedded copper block is embedded at the junction of the third insulating substrate layer and the thermally conductive layer, and the embedded copper block is connected to the first power wiring layer through a first conductive post. The power chip has its source electrode connected to the upper surface of the embedded copper block via a solder layer, its drain electrode connected to the second power wiring layer via a second conductive post, and its gate-drain drive electrode connected to the first signal wiring layer via a signal interconnect via.

2. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The first power wiring layer is made of copper foil, and at least a portion of the copper foil in the projection area of ​​the power chip has a thickness of 3oz-5oz.

3. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The first insulating substrate layer is made of epoxy resin filled with boron nitride, the amount of boron nitride being 25%-35%, the thermal conductivity of the first insulating substrate layer being greater than 30 W / (m·K), and the glass transition temperature of the first insulating substrate layer being greater than 180°C. The second insulating substrate layer is made of epoxy resin filled with boron nitride, the amount of boron nitride being 25%-35%, the thermal conductivity of the second insulating substrate layer being greater than 30 W / (m·K), and the glass transition temperature of the second insulating substrate layer being greater than 180°C. The third insulating substrate layer is made of epoxy resin filled with boron nitride, the amount of boron nitride being 25%-35%, the thermal conductivity of the third insulating substrate layer being greater than 30 W / (m·K), and the glass transition temperature of the third insulating substrate layer exceeding 180℃.

4. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The heat-conducting layer is made of a copper and diamond composite material, wherein the volume fraction of diamond is 20%-30%, the thickness of the heat-conducting layer is 0.8mm-1.2mm, and the thermal conductivity of the heat-conducting layer is greater than 400W / (m·K); or The thermal conductive layer is made of a copper and aluminum nitride composite material, the thermal conductivity of the thermal conductive layer is greater than 350 W / (m·K), and the temperature resistance of the thermal conductive layer exceeds 500℃.

5. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The embedded copper block is made of oxygen-free copper, and its lower surface is fixedly connected to the heat-conducting layer by a pressing process.

6. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The solder layer uses a composite solder of nano-silver and copper. The silver content in the composite solder is 60%-70%, the copper nanoparticle size is 50nm-100nm, the thickness of the solder layer is 30-50μm, the shear strength after sintering is not less than 30MPa, the thermal conductivity is not less than 180W / (m·K), and the porosity is not more than 3%.

7. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The second conductive post is made of copper alloy, with a diameter of 0.3mm-0.5mm and a height of 0.2mm-0.4mm. The two ends of the second conductive post are respectively welded to the drain electrode and the second power wiring layer, and the resistance at the weld is not greater than 5mΩ. The first conductive post is made of copper alloy, with a diameter of 0.4mm-0.6mm and a height of 0.6mm-0.8mm. The two ends of the first conductive post are respectively welded to the embedded copper block and the first power wiring layer, and the resistance at the weld is no greater than 5mΩ. The signal interconnect via extends sequentially from the surface of the circuit board body through the first signal wiring layer, the first insulating substrate layer, the first power wiring layer, the second insulating substrate layer, and the second power wiring layer, and connects to the gate-drain drive electrode in the third insulating substrate layer.

8. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The surface of the first conductive post is provided with a second plating layer, the material of the second plating layer is nickel palladium gold, and the thickness of the second plating layer is 0.5μm-1μm; The surface of the second conductive post is provided with a third plating layer, the material of which is nickel-palladium-gold, and the thickness of which is 0.5μm-1μm; The inner wall of the signal interconnect buried via is provided with a first plating layer, the material of the first plating layer is gold, and the thickness of the first plating layer is 2μm-3μm.

9. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The number of signal interconnect vias is 3-4, and the positions of the signal interconnect vias correspond to the gate electrode and drain electrode of the power chip, respectively. The center-to-center spacing of the signal interconnect vias exceeds 0.8mm.

10. The embedded power module based on a multilayer circuit board according to claim 1, characterized in that, The power chip is a silicon carbide power chip.

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