Laterally diffused metal oxide semiconductor device and manufacturing method thereof

Abstract

The invention provides a laterally diffused metal oxide semiconductor device and a manufacturing method thereof. The device comprises a substrate; a drift region dielectric layer; the conductive layer pattern comprises auxiliary conductive structures which are arranged at intervals and define gaps; the gap filling medium part is made of a side wall insulating material and is filled in the gap; and a contact hole structure over the gap. According to the method, the sidewall deposition process characteristics are utilized, and narrow polycrystalline silicon gaps are filled with sidewall materials in a self-alignment manner under a miniature process node (such as 55nm BCD), so that a thick medium cushion layer is formed. According to the structure, the problems of filling accumulation and etching residue caused by dependence on a thick silicide barrier layer in the traditional technology are avoided, and the voltage endurance capability and the device reliability of the field plate structure are effectively improved while the logic process is compatible.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a laterally diffused metal-oxide-semiconductor device and its manufacturing method. Background Technology

[0002] LDMOS devices are widely used due to their advantages such as high breakdown voltage, fast switching speed, and easier compatibility with CMOS (Complementary Metal-Oxide-Semiconductor) processes. In power device design, techniques such as reducing the surface electric field (RESURF) and field plate technology are commonly used to alleviate the trade-off between breakdown voltage (BV) and on-resistance.

[0003] Contact field plates (CFPs) are a commonly used structure that utilizes contact holes and an overlying metal layer to optimize the electric field distribution and improve the breakdown voltage performance of devices. To achieve the desired breakdown voltage effect, a dielectric layer with sufficient thickness and mass is typically required beneath the contact holes.

[0004] However, with the continuous advancement of semiconductor process nodes, especially to the 55nm BCD (Bipolar-CMOS-DMOS) process node, in order to be compatible with the logic platform's process and reduce manufacturing costs, it is generally desirable for the SAB (silicide barrier layer) film structure to be shared with the logic platform at the same node. In traditional structural designs, to obtain a high dielectric layer thickness to support the CFP structure, a thicker SAB layer is often relied upon. However, at the 55nm node, device dimensions, especially the polysilicon spacing, are constantly decreasing. This makes it easy for the thick SAB layer to over-accumulate after filling the narrow polysilicon gaps. Consequently, the subsequent SAB etching process cannot fully open the required area, thus affecting the normal formation of silicide and reducing device yield and performance.

[0005] Therefore, how to construct a dielectric filling structure that meets the withstand voltage requirements without relying on a thick SAB layer under advanced process nodes such as 55nm BCD and with reduced polysilicon spacing is a technical problem that urgently needs to be solved in the current LDMOS device manufacturing field. Summary of the Invention

[0006] The technical problem to be solved by this invention is that, under advanced semiconductor process nodes (such as 55nm BCD process), as the polysilicon spacing decreases, traditional contact hole field plate technology is unable to meet the high withstand voltage requirements by increasing the thickness of the silicide barrier layer without generating process defects, resulting in a decrease in device yield and reliability.

[0007] This invention provides a laterally diffused metal-oxide-semiconductor device, comprising:

[0008] Substrate;

[0009] The drift region dielectric layer is located on the substrate;

[0010] A conductive layer pattern is located on the dielectric layer in the drift region. The conductive layer pattern includes at least two spaced auxiliary conductive structures, with a gap defined between the auxiliary conductive structures.

[0011] The gap-filling medium is made of sidewall insulating material and fills the gap;

[0012] An interlayer dielectric layer covers the conductive layer pattern and fills the gaps with dielectric material; a contact hole structure is disposed in the interlayer dielectric layer.

[0013] Preferably, the dielectric layer in the drift region is a silicon oxide layer.

[0014] Preferably, the auxiliary conductive structure is made of polycrystalline silicon.

[0015] Preferably, the gap-filling medium is made of silicon oxide.

[0016] Preferably, the gap-filling medium is a seamless solid structure formed in one piece.

[0017] Preferably, it further includes a silicide barrier layer, which covers the surface of the auxiliary conductive structure and the gap-filling dielectric portion.

[0018] Preferably, the thickness of the silicide barrier layer is the same as the thickness of the silicide barrier layer in the logic device region integrated on the same chip.

[0019] This invention also provides a method for fabricating a laterally diffused metal-oxide-semiconductor device, comprising the following steps:

[0020] Step 1: Provide a substrate, form a drift region dielectric layer on the substrate, and form a conductive layer pattern on the drift region dielectric layer. The conductive layer pattern includes at least two spaced auxiliary conductive structures, with gaps defined between the auxiliary conductive structures.

[0021] Step 2: Deposit the sidewall insulation layer, which covers the auxiliary conductive structure and fills the gaps;

[0022] Step 3: Etch back the sidewall insulation layer, retaining the sidewall insulation material filling the gap to form the gap-filling dielectric section;

[0023] Step 4: Deposit and pattern the barrier layer;

[0024] Step 5: Deposit an interlayer medium layer and form contact hole structures in the interlayer medium layer. The contact hole structures are located above or adjacent to the gaps.

[0025] Preferably, in step one, the material of the dielectric layer in the drift region is silicon oxide.

[0026] Preferably, in step one, the conductive layer pattern is made of polycrystalline silicon.

[0027] Preferably, in step one, the width of the gap is configured to be less than twice the thickness of the sidewall insulation layer deposited in step two, so that the sidewall insulation layer can be clamped and filled in the gap in step two.

[0028] Preferably, in step two, the material of the sidewall insulation layer includes silicon oxide.

[0029] Preferably, in step three, the top surface height of the gap-filling dielectric portion is flush with the top surface height of the auxiliary conductive structure.

[0030] Preferably, in step four, the barrier layer is a silicide barrier layer, which is deposited using the same process steps as the silicide barrier layer in the logic device region on the same chip.

[0031] Preferably, in step four, the thickness of the silicide barrier layer is less than the thickness of the silicide barrier layer required to form a withstand voltage structure for conventional high-voltage devices at the 55nm BCD process node.

[0032] As described above, the laterally diffused metal-oxide semiconductor device and its manufacturing method of the present invention have the following beneficial effects:

[0033] This invention utilizes the pinch-fill effect naturally formed by the sidewall material at small polysilicon gaps to construct a gap-filling dielectric section with sufficient thickness, thereby achieving a thicker dielectric isolation effect with a thinner film process. This structural design cleverly solves the problems of filling voids and etching residues caused by the traditional use of thick silicide barrier layers (SABs) to improve field plate withstand voltage as process nodes shrink and polysilicon spacing decreases. After filling the gaps with sidewalls, the device no longer relies on a thick SAB layer to obtain sufficient insulation thickness below the contact hole structure, effectively reducing the surface electric field at the edges of the auxiliary conductive structure and below the field plate. Without increasing the cost of additional photomasks and maintaining compatibility with logic processes, it significantly improves the breakdown voltage and reliability of the device. Attached Figure Description

[0034] Figure 1 The diagram shown is a flow chart of a laterally diffused metal-oxide-semiconductor device and its fabrication method provided in an embodiment of the present invention.

[0035] Figure 2 The diagram shown is a cross-sectional view of the stacked structure before the formation of the conductive layer pattern in an embodiment of the present invention.

[0036] Figure 3The diagram shown is a cross-sectional view of the device after the formation of the conductive layer pattern and the auxiliary conductive structure according to an embodiment of the present invention.

[0037] Figure 4 The diagram shows a cross-sectional structure of the device after the sidewall insulating layer has been deposited and the gaps have been filled, according to an embodiment of the present invention.

[0038] Figure 5 The diagram shows a cross-sectional structure of the device after etching back the sidewall insulating layer to form a gap-filling dielectric portion, according to an embodiment of the present invention.

[0039] Figure 6 The diagram shows a cross-sectional structure of the device after the barrier layer has been deposited and patterned, according to an embodiment of the present invention.

[0040] Figure 7 The diagram shown is a cross-sectional view of the device after the contact hole structure is formed, according to an embodiment of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] 101. Substrate; 102. Gate oxide layer; 103. Drift region dielectric layer; 104. Conductive material layer; 1041. Auxiliary conductive structure; 1042. Gate structure; 105. Gap filling dielectric portion (sidewall insulating layer); 106. Silicide barrier layer; 107. Contact hole structure. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] This invention proposes a laterally diffused metal-oxide-semiconductor device, as shown in the attached figure. Figure 7 As shown, it includes:

[0045] Substrate 101; Drift region dielectric layer 103, located on substrate 101; Conductive layer pattern, located on drift region dielectric layer 103, the conductive layer pattern including at least two spaced auxiliary conductive structures 1041, the auxiliary conductive structures 1041 defining a gap; Gap-filling dielectric portion 105, made of sidewall insulating material and filling the gap; Interlayer dielectric layer (not shown independently in the figure, usually filling around contact hole 107), covering the conductive layer pattern and gap-filling dielectric portion 105; Contact hole structure 107, disposed in interlayer dielectric layer.

[0046] This technical solution utilizes the inherent deposition characteristics of the sidewall formation process to achieve self-aligned complete filling within a specific polysilicon gap width, thereby constructing a sufficiently thick solid dielectric block, namely the gap-filling dielectric portion 105, between the two auxiliary conductive structures 1041. This structural design cleverly solves the problems of filling voids and etching residues caused by the traditional use of thick silicide barrier layers (SABs) to improve field plate withstand voltage when polysilicon gaps shrink due to process node miniaturization (e.g., 55nm BCD process). After filling the gap with sidewalls, the device no longer relies on a thick SAB layer to obtain sufficient insulation thickness below the contact hole structure 107, effectively reducing the surface electric field at the edge of the auxiliary conductive structure 1041 and below the contact hole structure 107, significantly improving the device's breakdown voltage and yield without increasing additional photomask costs.

[0047] In some embodiments, substrate 101 may include elemental semiconductors, such as silicon (Si) or germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium arsenide phosphide indium (GaInAsP). In other embodiments, substrate 101 may also be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a silicon-on-glass substrate. Various doped regions may be formed in substrate 101, such as N-type wells, P-type wells, deep N-wells, or buried layers formed by ion implantation processes. The formation of these doped regions depends on the specific conductivity type (N-type or P-type LDMOS) designed.

[0048] In some embodiments, the drift region dielectric layer 103 is a silicon oxide layer. As the primary region carrying high voltage, the material of the drift region dielectric layer 103 is not limited to silicon oxide alone, but may also include composite dielectric layers formed from thermally doped silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), carbon-doped silicon oxide, low-k dielectric materials, or combinations thereof. This layer can be formed by dry oxidation, wet oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), flow-through chemical vapor deposition (FCVD), or other suitable deposition processes. The thickness of the drift region dielectric layer 103 is set according to the voltage withstand requirements of the device to prevent vertical breakdown in this region.

[0049] In some embodiments, the auxiliary conductive structure 1041 is made of polycrystalline silicon. The auxiliary conductive structure 1041 is actually part of the gate layer, and its material is not limited to polycrystalline silicon; it can also include amorphous silicon, metallic materials (such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), metal silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), titanium silicide (TiSi), conductive metal oxides), or any combination thereof. The auxiliary conductive structure 1041 not only functions to adjust the electric field but, more importantly, acts as a physical framework, defining the gaps for filling the dielectric. The sidewalls of the auxiliary conductive structure 1041 can be substantially vertical or have a certain tilt angle to adjust the step coverage effect of the sidewall material. The polycrystalline silicon can be in-situ doped during deposition or doped with N-type or P-type impurities after deposition via ion implantation.

[0050] In some embodiments, the gap-filling dielectric portion 105 is made of silicon oxide. The material of the gap-filling dielectric portion 105 is typically chosen to be a dielectric material that is compatible with subsequent processes and has good insulating properties. Besides silicon oxide, it may also include silicon nitride, silicon oxynitride, silicon oxycarbide, spin-coated glass (SOG), oxides formed from tetraethyl orthosilicate (TEOS), high-density plasma (HDP) oxides, or their multilayer stacked structures. The selection of this material should take into account its dielectric constant and interface characteristics with the auxiliary conductive structure 1041.

[0051] In some embodiments, the gap-filling dielectric portion 105 is a one-piece, seamless solid structure. Due to the matched control of the gap width and deposition thickness, the deposited material grows facing each other on the sidewalls of the gap and fuses at the center, eliminating the gaps or voids common in conventional gap filling. This seamless solid structure provides a uniform dielectric constant distribution, avoiding partial discharge or voltage drop problems caused by gas ionization within voids under high electric fields, and provides good mechanical strength to support the upper structure.

[0052] In some embodiments, a silicide barrier layer 106 is further included, which covers a portion of the surface of the auxiliary conductive structure 1041 and the gap-filling dielectric portion 105. The material of the silicide barrier layer 106 (SAB) may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or a hard mask combination of these materials. Figure 7 As shown, the silicide barrier layer 106 is located above the gap-filling medium portion 105 and between the contact hole structures 107, further enhancing the isolation effect and preventing the formation of metal silicides in unwanted areas.

[0053] In some embodiments, the thickness of the silicide barrier layer 106 is consistent with the thickness of the silicide barrier layer in the logic device region integrated on the same chip. This indicates that the LDMOS device is fully compatible with standard logic processes, eliminating the need to adjust the SAB deposition formulation or timing for high-voltage devices, significantly improving process integration flexibility and reducing manufacturing costs.

[0054] This invention also provides a method for fabricating a laterally diffused metal-oxide-semiconductor device, the process flow diagram of which is shown below. Figure 1 As shown, it includes the following steps:

[0055] Step 1: Provide a substrate 101, form a drift region dielectric layer 103 on the substrate 101, and form a conductive layer pattern on the drift region dielectric layer 103. The conductive layer pattern includes at least two spaced auxiliary conductive structures 1041, with a gap defined between the auxiliary conductive structures 1041.

[0056] Figure 2The stacked structure before patterning is shown, including a substrate 101, a gate oxide layer 102, a drift region dielectric layer 103, and an unpatterned conductive material layer 104. Specific steps for forming the substrate 101 include: performing RCA cleaning on the semiconductor wafer to remove organic matter, oxides, and metal ions. The material of the substrate 101 may include elemental semiconductors (such as silicon (Si), germanium (Ge), compound semiconductors (such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), or alloy semiconductors (such as silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), and gallium indium arsenide (GaInAs). Phosphorus, arsenic, or boron ions are implanted using an ion implantation process to form a well region; a field oxide layer (LOCOS) is grown using a thermal oxidation process, or the drift region dielectric layer 103 is formed using a shallow trench isolation (STI) process. The materials of the drift region dielectric layer 103 include, but are not limited to, thermally oxidized silicon, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), carbon-doped silicon oxide, or low-k dielectric materials. The steps for forming the conductive layer pattern include: depositing a conductive material layer 104 using low-pressure chemical vapor deposition (LPCVD). The material of the conductive material layer 104 can be selected from polycrystalline silicon, amorphous silicon, metal materials (aluminum Al, copper Cu, tungsten W, titanium Ti, tantalum Ta, molybdenum Mo), metal nitrides (titanium nitride TiN, tantalum nitride TaN), metal silicides (nickel silicide NiSi, cobalt silicide CoSi, titanium silicide TiSi), or conductive metal oxides; spin-coating photoresist onto the conductive material layer 104, and forming a mask pattern after exposure and development; removing the material not covered by the mask using polycrystalline silicon etching processes such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching. The etching gas can be selected from chlorine (Cl2), hydrogen bromide (HBr), sulfur hexafluoride (SF6), or a combination thereof, thereby forming an auxiliary conductive structure 1041 with specific geometric dimensions and a conventional gate structure 1042, such as... Figure 3 As shown.

[0057] In some embodiments, in step one, the material of the drift region dielectric layer 103 is silicon oxide.

[0058] In some embodiments, in step one, the conductive layer pattern is made of polycrystalline silicon. The polycrystalline silicon layer may be in-situ doped, undoped, or doped by ion implantation after deposition to adjust its work function or conductivity.

[0059] In some embodiments, in step one, the width of the gap is configured to be less than twice the thickness of the sidewall insulating layer subsequently deposited in step two, thereby enabling the sidewall insulating layer to clamp and fill the gap in step two. This is a geometry-based self-aligned filling strategy. Through pre-calculation and simulation, the polysilicon spacing between the auxiliary conductive structures 1041 in the layout is set so that its size is strictly smaller than the convergence critical value of the two sidewall growth. This design ensures that the gap is completely filled during the growth of the subsequently deposited dielectric layer before the top of the gap is sealed, utilizing the characteristics of the deposition process itself to complete the dielectric filling without introducing additional planarization or backfill processes.

[0060] Step 2: Deposit sidewall insulating layer 105. Sidewall insulating layer 105 covers auxiliary conductive structure 1041 and fills the gaps, such as... Figure 4 As shown. This step typically employs a deposition process with good step coverage to ensure no voids are filled at the bottom of the gap. Optional deposition methods include furnace tube chemical vapor deposition, atomic layer deposition (ALD), or subatmospheric pressure chemical vapor deposition (SACVD). Deposition process parameters (such as temperature, pressure, and gas flow rate) are optimized to ensure that the material grows uniformly along the sidewalls of the auxiliary conductive structure 1041 until the entire gap is filled from bottom to top. The material of the sidewall insulating layer 105 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, spin-coated glass (SOG), oxides formed from tetraethyl orthosilicate (TEOS), high-density plasma (HDP) oxides, or multilayer stacked structures thereof.

[0061] In some embodiments, in step two, the sidewall insulation layer 105 is made of silicon oxide. A composite layer of silicon oxide and silicon nitride can also be used, where silicon oxide serves as a backing layer to reduce stress, and silicon nitride serves as the main sidewall layer. If a composite layer is used, the deposition process may include first depositing a thin oxide layer, followed by in-situ or ex-situ deposition of a nitride layer.

[0062] Step 3: Etch back the sidewall insulation layer 105, retaining the sidewall insulation material filling the gap to form the gap-filling dielectric portion, such as... Figure 5 As shown. The back-etching process typically uses anisotropic dry etching, utilizing plasma generated from a mixture of fluorocarbon gases (such as CF4, CHF3, CH2F2, C4F8) and oxygen or argon. The etching process primarily removes the insulating layer from non-perpendicular surfaces. Because the gaps are completely filled with previously deposited material, the ions of the etching gas cannot penetrate deeply into the narrow and filled gaps for effective bombardment, thus preserving the material within the gaps. For example... Figure 5 As shown, conventional sidewalls are formed on the sidewalls of the auxiliary conductive structure 1041, while solid gap-filling dielectric portions are formed within the gaps.

[0063] In some embodiments, in step three, the top surface height of the gap-filling dielectric portion 105 is flush with the top surface height of the auxiliary conductive structure 1041. This structural feature is typically achieved by controlling the over-etching time during the etch-back process.

[0064] Step 4: Deposit and pattern the barrier layer 106, as shown. Figure 6 As shown. After source / drain implantation and annealing activation, a dielectric thin film is deposited as a silicide barrier layer 106 by plasma-enhanced chemical vapor deposition (PECVD). The material of the barrier layer 106 can be selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or a combination thereof. Then, the opening region is defined using a photolithography process, and the barrier layer at the opening is removed by dry etching or wet etching, exposing the active region and gate region where silicide needs to be formed, while retaining the silicide barrier layer 106 covering the interstitial filling dielectric portion 105 and part of the auxiliary conductive structure 1041.

[0065] In some embodiments, in step four, the barrier layer 106 is a silicide barrier layer, which is deposited using the same process steps as the silicide barrier layer in the logic device region on the same chip.

[0066] In some embodiments, in step four, the thickness of the silicide barrier layer 106 is less than the thickness of the silicide barrier layer required to form the withstand voltage structure of a conventional high-voltage device at the 55nm BCD process node. Since the aforementioned steps have already filled the polysilicon gaps using the sidewall insulating layer 105, the silicide barrier layer 106 no longer serves the primary functions of "gap filling" and "medium thickening," but only needs to act as a barrier to the reaction. Therefore, an extremely thin SAB film can be used. A thin SAB layer is not only easy to deposit, but also easier to completely remove during patterned etching, leaving no residue in narrow corners. This completely eliminates the risk of poor contact or open circuits caused by incomplete SAB etching, significantly improving yield.

[0067] Step 5: Deposit an interlayer medium layer and form a contact hole structure 107 in the interlayer medium layer. The contact hole structure 107 is located above or adjacent to the gap, such as... Figure 7As shown. The material of the interlayer dielectric layer (ILD) can include silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), undoped silicon glass (USG), tetraethoxysilane (TEOS) oxide, fluorine-doped silicon glass (FSG), low-k dielectric materials, or combinations thereof. Chemical mechanical polishing (CMP) is typically performed after deposition to planarize the surface. The formation of the contact hole structure 107 includes: using a dual damascene process or a single damascene process; defining the contact hole pattern using photolithography; using dry etching (e.g., using gases such as C4F6, C5F8) to penetrate the interlayer dielectric layer until reaching the underlying conductive region; depositing a barrier metal (e.g., titanium Ti, titanium nitride TiN, tantalum Ta, tantalum nitride TaN) and a filler metal (e.g., tungsten W, copper Cu, aluminum Al, aluminum-copper alloy) within the contact hole; and finally removing excess surface metal by CMP or etching back. The formed contact hole structure 107 not only completes the electrical connection, but the part above the gap also serves as the conductive part of the field plate system. It is isolated from the drift region by the thick gap filling dielectric part 105 and the silicide barrier layer 106 below, thus realizing the electric field modulation function.

[0068] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A laterally diffused metal-oxide-semiconductor device, characterized in that, include: Substrate; A drift region dielectric layer is located on the substrate; A conductive layer pattern is located on the dielectric layer of the drift region. The conductive layer pattern includes at least two spaced auxiliary conductive structures, with a gap defined between the auxiliary conductive structures. The gap-filling medium is made of sidewall insulating material and fills the gap; An interlayer dielectric layer covers the conductive layer pattern and the gap-filling dielectric portion; A contact hole structure is disposed in the interlayer dielectric layer.

2. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The dielectric layer in the drift region is a silicon oxide layer.

3. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The auxiliary conductive structure is made of polycrystalline silicon.

4. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The gap-filling medium is made of silicon oxide.

5. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that: The gap-filling medium is a seamless, integrally formed solid structure.

6. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that: It also includes a silicide barrier layer that covers part of the surface of the auxiliary conductive structure and the gap-filling dielectric portion.

7. The laterally diffused metal-oxide-semiconductor device according to claim 6, characterized in that: The thickness of the silicide barrier layer is the same as the thickness of the silicide barrier layer in the logic device region integrated on the same chip.

8. A method for manufacturing a laterally diffused metal-oxide-semiconductor device, characterized in that, include: Step 1: Provide a substrate, form a drift region dielectric layer on the substrate, and form a conductive layer pattern on the drift region dielectric layer. The conductive layer pattern includes at least two spaced auxiliary conductive structures, with a gap defined between the auxiliary conductive structures. Step 2: Deposit a sidewall insulating layer, which covers the auxiliary conductive structure and fills the gaps; Step 3: Etch back the sidewall insulation layer, retaining the sidewall insulation material filling the gap to form a gap-filling dielectric portion; Step 4: Deposit and pattern the barrier layer; Step 5: Deposit an interlayer medium layer and form a contact hole structure in the interlayer medium layer, the contact hole structure being located above or adjacent to the gap.

9. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 8, characterized in that: In step one, the material of the drift region dielectric layer is silicon oxide.

10. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 8, characterized in that: In step one, the conductive layer pattern is made of polycrystalline silicon.

11. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 8, characterized in that: In step one, the width of the gap is configured to be less than twice the thickness of the sidewall insulation layer deposited in step two, thereby enabling the sidewall insulation layer to clamp and fill the gap in step two.

12. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 8, characterized in that: In step two, the material of the sidewall insulation layer includes silicon oxide.

13. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 8, characterized in that: In step three, the top surface height of the gap-filling dielectric portion is flush with the top surface height of the auxiliary conductive structure.

14. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 8, characterized in that: In step four, the barrier layer is a silicide barrier layer, which is deposited using the same process steps as the silicide barrier layer in the logic device region on the same chip.

15. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 14, characterized in that: In step four, the thickness of the silicide barrier layer is less than the thickness of the silicide barrier layer required to form a withstand voltage structure for conventional high-voltage devices at the 55nm BCD process node.

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