Preparation method of conductive plug and semiconductor chip

Abstract

The invention provides a preparation method of a conductive plug and a semiconductor chip, and belongs to the field of power electronics. The preparation method of the tungsten plug comprises the following steps: preparing an epitaxial wafer, wherein the surface of the epitaxial wafer is provided with a via hole; sputtering a transition metal material into the via hole, and performing ion bombardment on the transition metal material in the via hole to form a transition metal layer; and forming a conductive metal layer on the surface of the transition metal layer to fill the via hole. According to the embodiment of the invention, the problem that the metal film layer formed during the preparation of the tungsten plug is easy to generate more defects can be improved, and the preparation yield of the tungsten plug is improved.

Description

Technical Field

[0001] This disclosure relates to the field of power electronics, and in particular to a method for preparing a conductive plug and a semiconductor chip. Background Technology

[0002] A high electron mobility transistor (HEMT) in semiconductor chips is a field-effect transistor that uses a two-dimensional electron gas formed at a heterojunction interface as a conductive channel. Transistors have advantages such as high electron mobility, high operating frequency, and low noise, and are widely used in various electrical appliances.

[0003] In transistor fabrication, related technologies typically involve fabricating vias on the insulating layer of the transistor and then creating conductive plugs within these vias. These conductive plugs serve as conductive structures, connecting the film layers on both sides of the insulating layer. Tungsten plugs are conductive plugs whose filling material is primarily metallic tungsten. Tungsten plugs possess characteristics such as high melting point, low resistance, resistance to electromigration, and good filling properties, leading to their widespread application.

[0004] In the fabrication of conductive plugs, sputtering is typically used to form multilayered metal films within vias. Insufficient power in the sputtering equipment or improper process parameter settings can easily lead to numerous pores or defects within the formed metal film, thus reducing its density. This is particularly true for tungsten plugs, where decreased density severely impacts subsequent tungsten metal deposition. Summary of the Invention

[0005] This disclosure provides a method for fabricating a conductive plug and a semiconductor chip, which can improve the problem of numerous defects in the metal film layer formed during the fabrication of tungsten plugs and increase the yield of conductive plug fabrication. The technical solution is as follows: On one hand, this disclosure provides a method for preparing a conductive plug, the method comprising: preparing an epitaxial wafer having vias on its surface; sputtering a transition metal material into the vias while simultaneously bombarding the transition metal material in the vias with ions to form a transition metal layer; and forming a conductive metal layer on the surface of the transition metal layer to fill the vias.

[0006] In one implementation of this disclosure, sputtering a transition metal material into the via and simultaneously bombarding the transition metal material within the via with ions to form a transition metal layer includes: injecting argon gas into a reaction chamber; ionizing the argon gas using a DC power supply with a power of 10KW to 20KW; causing the formed argon ions to bombard a titanium target to sputter titanium atoms into the via to form a Ti layer; and using a radio frequency bias power supply with a power of 300W to 400W to control the bombardment of the Ti layer with argon ions.

[0007] In another implementation of this disclosure, when forming the Ti layer, the pressure in the reaction chamber is controlled to be 1 mT to 2 mT, the flow rate of argon gas in the reaction chamber is controlled to be 10 sccm to 20 sccm, the distance between the titanium target and the epitaxial wafer is controlled to be 75 mm to 80 mm, and the growth time is controlled to be 95 s to 130 s.

[0008] In another implementation of this disclosure, after forming the Ti layer, the method further includes: injecting argon and nitrogen into the reaction chamber; ionizing the argon using a DC power supply with a power of 15KW to 25KW; causing the formed argon ions to bombard the titanium target material to sputter titanium atoms onto the surface of the Ti layer, thereby causing the titanium atoms to react with the nitrogen to form a TiN layer; and using a radio frequency bias power supply with a power of 300W to 400W to control the argon ions to bombard the TiN layer.

[0009] In another implementation of this disclosure, when forming the TiN layer, the pressure inside the reaction chamber is controlled to be 7.5 mT to 8.5 mT, the flow rate of argon gas inside the reaction chamber is controlled to be 5 sccm to 15 sccm, the flow rate of nitrogen gas inside the reaction chamber is controlled to be 100 sccm to 200 sccm, the distance between the titanium target and the epitaxial wafer is controlled to be 75 mm to 80 mm, and the growth time is controlled to be 40 s to 60 s.

[0010] In another implementation of this disclosure, the resistivity of the Ti layer is 70 μΩ·cm to 80 μΩ·cm.

[0011] In another implementation of this disclosure, the resistivity of the TiN layer is from 150 μΩ·cm to 250 μΩ·cm.

[0012] In another implementation of this disclosure, the preparation of the epitaxial wafer includes: growing an epitaxial layer on a substrate; forming an insulating dielectric layer on the surface of the epitaxial layer, and forming the via on the surface of the insulating dielectric layer, wherein the diameter of the via is 500 nm to 1000 nm and the depth of the via is 1000 nm to 2000 nm.

[0013] On the other hand, this disclosure provides a semiconductor chip, which includes an epitaxial wafer. The surface of the epitaxial wafer has vias, and a transition metal layer and a conductive metal layer are sequentially stacked in the vias. The transition metal layer is formed by sputtering and subjected to ion bombardment treatment.

[0014] Optionally, the transition metal layer comprises a Ti layer and a TiN layer stacked sequentially, wherein the resistivity of the Ti layer is 70 μΩ·cm to 80 μΩ·cm and the resistivity of the TiN layer is 150 μΩ·cm to 250 μΩ·cm.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The method for preparing a conductive plug provided in this disclosure first prepares an epitaxial wafer with vias. After forming a transition metal layer within the vias by sputtering, an ion bombardment process is introduced to treat the transition metal layer. Subsequently, a conductive metal layer (such as tungsten) is deposited on its surface to fill the vias. Ion bombardment, through the directional bombardment of high-energy ions, provides additional energy to the transition metal layer, promoting surface migration and rearrangement of deposited atoms, effectively reducing porosity and defects, and improving the compactness of the film. Furthermore, the compacted transition metal layer has a more uniform and stable structure, with reduced intrinsic defects (such as vacancies and interstitial atoms) and grain boundary density, providing a higher-quality substrate for the subsequent preparation of the conductive metal layer. Because the highly dense surface can better adsorb reaction precursors, it promotes uniform nucleation of tungsten atoms within the vias, increasing nucleation density and uniformity, thereby avoiding the problem of preferential growth at the via openings and internal voids during via filling. Simultaneously, ion bombardment can also optimize the interface state between the transition metal layer and the subsequent tungsten layer, enhancing adhesion between them through slight surface roughening or activation effects, reducing the risk of delamination. High-quality filling of tungsten plugs in vias was achieved, ensuring the stability and reliability of transistor interconnects. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a method for preparing a conductive plug according to an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a semiconductor chip provided in an embodiment of this disclosure; Figure 3 This is a morphological comparison diagram of a conductive plug provided in an embodiment of this disclosure.

[0018] The markings in the diagram are explained as follows: 10. Epitaxial wafer; 11. Substrate; 12. Buffer layer; 13. Epitaxial layer; 14. Insulating dielectric layer; 100. Via; 20. Transition metal layer; 21. Ti layer; 22. TiN layer; 30. Conductive metal layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0021] Figure 1 This is a flowchart illustrating a method for preparing a conductive plug according to an embodiment of this disclosure. Figure 1 As shown, the preparation method includes: Step S11: Prepare an epitaxial wafer.

[0022] The surface of the epitaxial wafer has vias.

[0023] Step S12: Sputter the transition metal material into the via and simultaneously bombard the transition metal material in the via with ions to form a transition metal layer.

[0024] Step S13: Form a conductive metal layer on the surface of the transition metal layer to fill the via.

[0025] For example, the conductive metal layer may be a tungsten layer, which fills the via to form a tungsten plug.

[0026] The method for preparing a conductive plug provided in this disclosure first prepares an epitaxial wafer with vias. After forming a transition metal layer within the vias by sputtering, an ion bombardment process is introduced to treat the transition metal layer. Subsequently, a conductive metal layer (such as tungsten) is deposited on its surface to fill the vias. Ion bombardment, through the directional bombardment of high-energy ions, provides additional energy to the transition metal layer, promoting surface migration and rearrangement of deposited atoms, effectively reducing porosity and defects, and improving the compactness of the film. Furthermore, the compacted transition metal layer has a more uniform and stable structure, with reduced intrinsic defects (such as vacancies and interstitial atoms) and grain boundary density, providing a higher-quality substrate for the subsequent preparation of the conductive metal layer. Because the highly dense surface can better adsorb reaction precursors, it promotes uniform nucleation of tungsten atoms within the vias, increasing nucleation density and uniformity, thereby avoiding the problem of preferential growth at the via openings and internal voids during via filling. Simultaneously, ion bombardment can also optimize the interface state between the transition metal layer and the subsequent tungsten layer, enhancing adhesion between them through slight surface roughening or activation effects, reducing the risk of delamination. High-quality filling of tungsten plugs in vias was achieved, ensuring the stability and reliability of transistor interconnects.

[0027] Step S11 may include the following steps: The first step is to grow an epitaxial layer on the substrate.

[0028] For example, the epitaxial layer may be the epitaxial layer of a transistor or a light-emitting diode.

[0029] For example, the substrate may be a sapphire substrate or a silicon substrate.

[0030] Taking a transistor as an example, growing an epitaxial layer on a substrate can include growing a buffer layer, a channel layer, and a barrier layer on a silicon substrate.

[0031] Epitaxial growth can be achieved using MOCVD (Metal-organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy).

[0032] Before epitaxial growth, the sapphire substrate is cleaned and then dry-processed in the epitaxial machine. Taking MOCVD as an example, the reaction chamber temperature is controlled at 1050℃, and hydrogen is introduced for 5 to 10 minutes before epitaxial growth is carried out.

[0033] For example, the buffer layer includes AlGaN layers and GaN layers stacked sequentially.

[0034] The thickness of the AlGaN layer ranges from 10 nm to 50 nm. The growth temperature of the AlGaN layer ranges from 500 °C to 700 °C.

[0035] The thickness of the GaN layer is 1 μm to 2 μm. The growth temperature of the GaN layer is 900℃ to 1100℃.

[0036] For example, the channel layer can be a GaN layer.

[0037] As an example, the thickness of the channel layer ranges from 100 nm to 500 nm.

[0038] For example, the barrier layer is an AlGaN layer.

[0039] As an example, the thickness of the barrier layer is 20 nm to 30 nm.

[0040] The second step is to form an insulating dielectric layer on the surface of the epitaxial layer, and then form vias on the surface of the insulating dielectric layer.

[0041] The diameter of the via is 500nm to 1000nm, and the depth of the via is 1000nm to 2000nm.

[0042] For example, the insulating dielectric layer may include at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum nitride layer.

[0043] As an example, the insulating dielectric layer may include a first silicon nitride layer, an aluminum nitride layer, a second silicon nitride layer, and a silicon oxide layer sequentially stacked on the surface of the barrier layer.

[0044] Both the first and second silicon nitride layers can be deposited using metal-organic chemical vapor deposition (MOCVD). SiN layers grown using the Organic Chemical Vapor Deposition (MOCVD) process.

[0045] The silicon dioxide layer can be a silicon dioxide layer prepared using plasma-enhanced chemical vapor deposition (PECVD) technology.

[0046] For example, a titanium nitride barrier layer is inserted between the silicon oxide layer and the second silicon nitride layer.

[0047] The role of the titanium nitride barrier layer inserted between the dielectric layers is to prevent tungsten atoms from diffusing into the surrounding dielectric layers and silicon substrate, thus avoiding device electrical performance degradation or failure. Simultaneously, it also enhances the adhesion between different film layers.

[0048] The third step is to etch the insulating dielectric layer to form vias.

[0049] For example, the silicon oxide layer is etched through by an etching process to form a via that exposes the titanium nitride barrier layer.

[0050] For example, an etching process is used to etch through the insulating dielectric layer to form a via that exposes the barrier layer.

[0051] Optionally, before step S12, the process may further include: treating the via surface with in-situ argon plasma or hydrogen plasma to remove the native oxide layer or organic residue.

[0052] A clean substrate surface can improve the adhesion between the transition metal and the underlying material, while reducing nucleation defects caused by the oxide layer.

[0053] Step S12 may include the following steps: The first step is to inject argon gas into the reaction chamber and use a DC power supply with a power of 10KW to 20KW to ionize the argon gas, so that the argon ions formed bombard the titanium target material to sputter titanium atoms into the vias to form a Ti layer.

[0054] In the above implementation method, a DC power supply of 10KW to 20KW can provide sufficient energy to efficiently ionize argon gas into high-energy argon ions. When these high-energy ions bombard the titanium target, they can effectively sputter titanium atoms and deposit them into the vias to form the initial Ti layer.

[0055] For example, the DC power supply can be 15 kW. The higher DC power ensures sufficient titanium atom flux to meet the basic requirements for via filling, while also helping to improve the deposition rate.

[0056] For example, during the formation of the Ti layer, the pressure within the reaction chamber is controlled to be between 1 mT and 2 mT. This low pressure reduces gas collisions, extends the mean free path of argon ions, ensures that ions bombard the target in a straight line, and improves sputtering atomic energy and deposition orientation.

[0057] For example, during the formation of the Ti layer, the flow rate of argon gas in the reaction chamber is controlled to be between 10 sccm and 20 sccm. Precise control of the amount of reactant gas maintains a stable plasma density, balances the sputtering rate with the chamber environment, and avoids excessive argon gas diluting the plasma.

[0058] For example, when forming the Ti layer, the distance between the titanium target and the epitaxial wafer is controlled to be 75 mm to 80 mm. This appropriate distance ensures that sputtered atoms have sufficient migration time to fill the vias, balancing deposition efficiency and film uniformity while reducing edge effects.

[0059] For example, when forming the Ti layer, the growth time is controlled to be between 95s and 130s. This growth duration ensures that the thickness of the Ti layer is suitable for via filling requirements, avoiding excessively thin vias or excessively thick vias.

[0060] The second step involves using a radio frequency bias power supply with a power of 300W to 400W to control the bombardment of the Ti layer with argon ions.

[0061] The 300W to 400W radio frequency bias power supply induces a stable DC self-bias voltage by applying controllable radio frequency power to the epitaxial wafer, thereby precisely controlling the bombardment energy of argon ions on the Ti layer. During this process, ion bombardment not only enhances the surface migration ability of Ti layer atoms, promoting more uniform diffusion and filling any pores or gaps within the vias, reducing defects and porosity within the film, and improving the compactness of the Ti layer; it also optimizes the interface state between the Ti layer and the subsequent tungsten layer through the kinetic energy of the ions, enhancing their adhesion and preventing delamination.

[0062] For example, the power of the RF bias power supply is 350KW.

[0063] The third step involves injecting argon and nitrogen into the reaction chamber. A DC power supply with a power of 15KW to 25KW is used to ionize the argon gas, causing the argon ions to bombard the titanium target and sputter titanium atoms onto the surface of the Ti layer, where the titanium atoms react with the nitrogen gas to form a TiN layer.

[0064] In the above implementation, a 15KW to 25KW DC power supply is used to ionize argon gas and sputter a titanium target, while nitrogen gas is simultaneously introduced. This allows the sputtered titanium atoms to react chemically with the nitrogen gas, generating a TiN layer in situ. Compared to depositing a Ti layer separately and then introducing a nitriding process, this in-situ reactive sputtering method ensures atomic-level uniform mixing of Ti and N, precisely controls the stoichiometry of TiN, and avoids compositional deviations or interface defects caused by subsequent nitriding processes, thereby forming a dense TiN film with high chemical stability.

[0065] Furthermore, TiN, as a barrier layer with high conductivity and low resistivity, can effectively prevent the diffusion reaction of tungsten during subsequent tungsten deposition, while also improving the oxidation and corrosion resistance of the film.

[0066] Secondly, the introduction of nitrogen gas, which works synergistically with argon gas, not only provides the reaction gas for the formation of TiN, but also allows nitrogen ions to further enhance the surface activation and structural compaction effect of the TiN layer during ion bombardment.

[0067] For example, the DC power supply is 20KW. The power for growing the Ti layer is set to 15KW, which is lower than the 20KW for the TiN layer. This avoids damage to the vias caused by high-power sputtering and facilitates uniform Ti deposition and filling of the vias. Using 20KW for the TiN layer increases the argon ion energy, allowing the titanium atoms to react fully with the nitrogen gas to form a dense TiN layer.

[0068] For example, during the formation of the TiN layer, the pressure within the reaction chamber is controlled to be between 7.5 mT and 8.5 mT. Appropriate pressure balances plasma density and particle energy, promoting efficient migration of Ti and N atoms and optimizing TiN nucleation and growth uniformity.

[0069] For example, when forming the TiN layer, the flow rate of argon gas in the reaction chamber is controlled to be between 5 sccm and 15 sccm. Controlling the argon gas flow rate within this range can maintain a stable plasma environment, ensure stable sputtering of the titanium target, and avoid excessive dilution of the reactive gas.

[0070] For example, during the formation of the TiN layer, the flow rate of nitrogen gas in the reaction chamber is controlled to be between 100 sccm and 200 sccm. The higher nitrogen flow rate ensures a sufficient supply of N atoms, promoting a full reaction between Ti and N.

[0071] For example, when forming the TiN layer, the distance between the titanium target and the epitaxial wafer is controlled to be 75 mm to 80 mm. This appropriate distance balances sputtering atom migration time and deposition efficiency, ensuring uniform TiN coverage of vias and reducing edge effects.

[0072] For example, when forming the TiN layer, the growth time is controlled to be between 40 and 60 seconds. Precise control of the deposition time matches the via filling requirements, forming a TiN layer of suitable thickness, avoiding performance impact from being too thin or too thick.

[0073] The fourth step involves using a radio frequency bias power supply with a power of 300W to 400W to control the bombardment of the TiN layer with argon ions.

[0074] Argon ions were used to bombard the TiN layer using a 300W to 400W radio frequency bias power supply. By applying a stable DC self-bias voltage, argon ions bombarded the TiN surface with controllable energy. This ion bombardment can further improve the density of the TiN layer. Through the kinetic energy transfer of high-energy ions, the deposited Ti and N atoms migrate and rearrange on the surface, filling any possible micropores or gaps, reducing intrinsic defects (such as vacancies and interstitial atoms) and grain boundary density within the film, and forming a more uniform and continuous microstructure.

[0075] For example, the power of the RF bias power supply is 350KW.

[0076] Optionally, the resistivity of the Ti layer is 70 μΩ·cm to 80 μΩ·cm.

[0077] For example, the resistivity of the Ti layer is 73 μΩ·cm.

[0078] Alternatively, the resistivity of the TiN layer is from 150 μΩ·cm to 250 μΩ·cm.

[0079] For example, the resistivity of the TiN layer is 207 μΩ·cm.

[0080] The high density and moderate resistivity of the Ti and TiN layers prepared in this embodiment are beneficial for subsequent tungsten filling. First, the dense Ti / TiN layer structure is compact, and the dense surface can precisely anchor tungsten atoms, promoting a uniform distribution of nucleation sites and avoiding local aggregation or preferential growth at pore edges caused by random nucleation, thus ensuring uniform initiation of tungsten nuclei within the vias. Second, the resistivity of Ti and TiN is within a reasonable range, ensuring that the transition metal layer itself has basic conductivity, reducing the additional burden on the overall interconnect resistance, and suppressing the obstruction of tungsten atom diffusion by defects at the interface through the high density structure, making it easier for tungsten atoms to expand laterally along the dense layer surface and fill vertically, forming a continuous deposition layer. Finally, the high density of the TiN layer can effectively block abnormal diffusion that may occur during subsequent tungsten deposition, while its high hardness can alleviate stress concentration during the via filling process, further improving the integrity and reliability of the via filling.

[0081] Figure 2 This is a schematic diagram of the structure of a semiconductor chip provided in an embodiment of this disclosure. Figure 2 As shown, the semiconductor chip includes an epitaxial wafer 10, the surface of which has a via 100. A transition metal layer 20 and a conductive metal layer 30 are sequentially stacked in the via 100. The transition metal layer 20 is formed by sputtering and subjected to ion bombardment treatment.

[0082] In the fabrication process of the conductive plug provided in this embodiment, after a transition metal layer 20 is formed within the via 100 by sputtering, an ion bombardment process is introduced to treat the transition metal layer 20. Subsequently, a conductive metal layer 30 is deposited on its surface to fill the via 100. The introduction of ion bombardment provides additional energy to the transition metal layer 20 through the directional bombardment of high-energy ions, promoting surface migration and rearrangement of deposited atoms, effectively reducing porosity and defects, and improving the density of the film. Furthermore, the densified transition metal layer 20 has a more uniform and stable structure, with reduced intrinsic defects (such as vacancies and interstitial atoms) and grain boundary density, providing a higher-quality substrate for the subsequent fabrication of the conductive metal layer 30. Because the highly dense surface can better adsorb reaction precursors, it promotes uniform nucleation of tungsten atoms within the via 100, increasing nucleation density and uniformity, thereby avoiding the problem of preferential growth at the via opening and internal voids during filling. Simultaneously, ion bombardment can also optimize the interface state between the transition metal layer 20 and the subsequent tungsten layer, enhancing adhesion between them through slight surface roughening or activation effects, reducing the risk of delamination. High-quality filling of tungsten plugs within vias 100 was achieved, ensuring the stability and reliability of transistor interconnects.

[0083] Optionally, such as Figure 2 As shown, the epitaxial wafer 10 includes a substrate 11, a buffer layer 12, an epitaxial layer 13, and an insulating dielectric layer 14 stacked sequentially.

[0084] For example, the epitaxial layer 13 may be the epitaxial layer 13 of a transistor or a light-emitting diode.

[0085] For example, substrate 11 may be a sapphire substrate or a silicon substrate.

[0086] Taking a transistor as an example, the epitaxial layer 13 may include a channel layer and a barrier layer.

[0087] For example, the buffer layer 12 includes AlGaN layers and GaN layers stacked sequentially.

[0088] The thickness of the AlGaN layer ranges from 10 nm to 50 nm. The growth temperature of the AlGaN layer ranges from 500 °C to 700 °C.

[0089] The thickness of the GaN layer is 1 μm to 2 μm. The growth temperature of the GaN layer is 900℃ to 1100℃.

[0090] For example, the channel layer can be a GaN layer.

[0091] As an example, the thickness of the channel layer ranges from 100 nm to 500 nm.

[0092] For example, the barrier layer is an AlGaN layer.

[0093] As an example, the thickness of the barrier layer is 20 nm to 30 nm.

[0094] For example, the insulating dielectric layer 14 may include at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum nitride layer.

[0095] As an example, the insulating dielectric layer 14 may include a first silicon nitride layer, an aluminum nitride layer, a second silicon nitride layer, and a silicon oxide layer sequentially stacked on the surface of the barrier layer.

[0096] Both the first and second silicon nitride layers can be deposited using metal-organic chemical vapor deposition (MOCVD). SiN layers grown using the Organic Chemical Vapor Deposition (MOCVD) process.

[0097] The silicon dioxide layer can be a silicon dioxide layer prepared using plasma-enhanced chemical vapor deposition (PECVD) technology.

[0098] For example, a titanium nitride barrier layer is inserted between the silicon oxide layer and the second silicon nitride layer.

[0099] The titanium nitride barrier layer inserted between the dielectric layers prevents tungsten atoms from diffusing into the surrounding dielectric layers and silicon substrate 11, thus avoiding device electrical performance degradation or failure. Simultaneously, it also enhances the adhesion between different film layers.

[0100] Optionally, the surface of the insulating dielectric layer 14 has a via 100.

[0101] For example, via 100 exposes a titanium nitride barrier layer, or via 100 exposes a barrier layer.

[0102] Optionally, such as Figure 2 As shown, the transition metal layer 20 includes a Ti layer 21 and a TiN layer 22 stacked sequentially. The resistivity of the Ti layer 21 is 70 μΩ·cm to 80 μΩ·cm, and the resistivity of the TiN layer 22 is 150 μΩ·cm to 250 μΩ·cm.

[0103] For example, the resistivity of Ti layer 21 is 73 μΩ·cm.

[0104] For example, the resistivity of TiN layer 22 is 207 μΩ·cm.

[0105] The high density and moderate resistivity of the Ti layer 21 and TiN layer 22 prepared in this embodiment are beneficial for subsequent tungsten filling. First, the dense structure of the high-density Ti / TiN layer 22 allows for precise anchoring of tungsten atoms on its dense surface, promoting uniform distribution of nucleation sites and avoiding localized aggregation or preferential growth at pore edges caused by random nucleation. This ensures uniform initiation of tungsten nuclei within the via 100. Second, the resistivity of Ti and TiN is within a reasonable range, ensuring that the transition metal layer 20 itself possesses basic conductivity, reducing the additional burden on the overall interconnect resistance. Furthermore, the high density structure suppresses the obstruction of tungsten atom diffusion by defects at the interface, making it easier for tungsten atoms to expand laterally along the dense layer surface and fill vertically, forming a continuous deposition layer. Finally, the high density of the TiN layer 22 effectively blocks abnormal diffusion that may occur during subsequent tungsten deposition, while its high hardness alleviates stress concentration during the via filling process, further improving the integrity and reliability of the via filling.

[0106] Optionally, the transition metal layer 20 may include a multilayer stacked TiN layer 22, wherein the N component content in the TiN layer 22 decreases from the Ti layer 21 to the tungsten layer.

[0107] The N component content can be the percentage of N atoms.

[0108] For example, the N content in the TiN layer 22 near the Ti layer 21 is greater than or equal to 0.3, and the N content in the TiN layer 22 near the tungsten layer is less than or equal to 0.2.

[0109] Among them, TiN with high nitrogen content can enhance barrier properties and inhibit tungsten diffusion, while TiN with low nitrogen content can optimize adhesion to tungsten and reduce interfacial stress.

[0110] Optionally, the surface of the transition metal layer 20 may also be provided with multiple grooves or protrusions arranged at intervals. The relatively rough surface of the transition metal layer 20 can provide more nucleation sites and promote the uniform attachment of tungsten atoms.

[0111] Figure 3 These are comparative morphological images of a conductive plug provided in an embodiment of this disclosure. The left side of the image shows a conductive plug fabricated using related technologies, while the right side shows a conductive plug prepared according to an embodiment of this disclosure. Figure 3 As shown, compared with related technologies, the conductive plug (such as a tungsten plug) prepared in this embodiment has better metal film density and fewer intrinsic defects (such as vacancies and interstitial atoms) inside the film. Furthermore, the high-density surface energy can promote the uniform nucleation of tungsten atoms in the via 100, achieving high-quality filling of the tungsten plug in the via 100 and ensuring the stability and reliability of transistor interconnection.

[0112] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for preparing a conductive plug, characterized in that, The preparation method includes: An epitaxial wafer (10) is prepared, wherein the surface of the epitaxial wafer (10) has a via (100); A transition metal material is sputtered into the via (100), and the transition metal material in the via (100) is simultaneously bombarded with ions to form a transition metal layer (20). A conductive metal layer (30) is formed on the surface of the transition metal layer (20) to fill the via (100).

2. The preparation method according to claim 1, characterized in that, Sputtering a transition metal material into the via (100) and simultaneously bombarding the transition metal material within the via (100) with ions to form a transition metal layer (20) includes: Argon gas is injected into the reaction chamber, and a DC power supply with a power of 10KW to 20KW is used to ionize the argon gas, so that the formed argon ions bombard the titanium target material to sputter titanium atoms into the via (100) to form a Ti layer (21). Argon ions were used to bombard the Ti layer (21) using a radio frequency bias power supply with a power of 300W to 400W.

3. The preparation method according to claim 2, characterized in that, When forming the Ti layer (21), the pressure in the reaction chamber is controlled to be 1 mT to 2 mT, the flow rate of argon gas in the reaction chamber is controlled to be 10 sccm to 20 sccm, the distance between the titanium target and the epitaxial wafer (10) is controlled to be 75 mm to 80 mm, and the growth time is controlled to be 95 s to 130 s.

4. The preparation method according to claim 2, characterized in that, After forming the Ti layer (21), the process further includes: Argon and nitrogen are injected into the reaction chamber. Argon is ionized by a DC power supply with a power of 15KW to 25KW, so that the argon ions formed bombard the titanium target material to sputter titanium atoms onto the surface of the Ti layer (21), so that the titanium atoms react with nitrogen to form a TiN layer (22). Argon ions were used to bombard the TiN layer (22) using a radio frequency bias power supply with a power of 300W to 400W.

5. The preparation method according to claim 4, characterized in that, When forming the TiN layer (22), the pressure in the reaction chamber is controlled to be 7.5 mT to 8.5 mT, the flow rate of argon in the reaction chamber is controlled to be 5 sccm to 15 sccm, the flow rate of nitrogen in the reaction chamber is controlled to be 100 sccm to 200 sccm, the distance between the titanium target and the epitaxial wafer (10) is controlled to be 75 mm to 80 mm, and the growth time is controlled to be 40 s to 60 s.

6. The preparation method according to any one of claims 2 to 5, characterized in that, The resistivity of the Ti layer (21) is 70 μΩ·cm to 80 μΩ·cm.

7. The preparation method according to claim 4 or 5, characterized in that, The resistivity of the TiN layer (22) is from 150 μΩ·cm to 250 μΩ·cm.

8. The preparation method according to any one of claims 1 to 5, characterized in that, The preparation of epitaxial wafers (10) includes: An epitaxial layer (13) is grown on the substrate (11); An insulating dielectric layer (14) is formed on the surface of the epitaxial layer (13), and a via (100) is formed on the surface of the insulating dielectric layer (14). The diameter of the via (100) is 500 nm to 1000 nm, and the depth of the via (100) is 1000 nm to 2000 nm.

9. A semiconductor chip, characterized in that, The semiconductor chip includes an epitaxial wafer (10), the surface of which has a via (100), and a transition metal layer (20) and a conductive metal layer (30) are sequentially stacked in the via (100). The transition metal layer (20) is formed by sputtering and subjected to ion bombardment treatment.

10. The semiconductor chip according to claim 9, characterized in that, The transition metal layer (20) comprises a Ti layer (21) and a TiN layer (22) stacked sequentially, wherein the resistivity of the Ti layer (21) is 70 μΩ·cm to 80 μΩ·cm and the resistivity of the TiN layer (22) is 150 μΩ·cm to 250 μΩ·cm.

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