Board card test tool, test system and test method

Abstract

The invention provides a board card testing tool which comprises a plurality of matrix switches which are divided into at least three layers, the first layer is a matrix switch array composed of a plurality of multi-input and one-output matrix switches, the second layer is a multi-input and one-output matrix switch, and the third layer is a one-input and multi-output matrix switch. The common end of each multi-input one-output matrix switch of the first layer is connected to the input end of the second layer matrix switch, and the common end of the second layer matrix switch is connected to the common end of the third layer matrix switch. The invention further provides a testing system and a testing method adopting the testing tool. According to the invention, a cascade form of at least three layers of matrix switches is designed, a plurality of test channels of a board card to be tested are respectively connected to the corresponding input ends of the test tool through cables, the output ends of the board card to be tested are connected to a detection instrument, a plurality of cables only need to be connected once, the cables do not need to be replaced in the process, the locking degree of each channel is consistent, and the test efficiency is improved. And the test efficiency and the test reliability are improved.

Description

Technical Field

[0001] This application relates to the field of testing electronic circuit boards, specifically to a circuit board testing fixture, testing system, and testing method. Background Technology

[0002] After the superconducting quantum computing room temperature control chassis system is assembled, it needs to undergo a series of tests before being installed and used. To ensure its electronic performance, the radio frequency signals and digital circuits need to be debugged and verified. Currently, the operators connect individual channels of the board under test to individual test instruments via SMA cables, configure parameters in the test cases, and check whether the graphs or values ​​on the instrument meet expectations. Once they do, the next channel is tested, and so on. Because quantum computing boards have many channels, a single AWG (Arbitrary Waveform Generator) control board has 32 channels. The instruments used include power meters, spectrum analyzers, multimeters, and phase noise meters. Testing a single board requires changing cable connections and setting parameters more than a hundred times.

[0003] Existing testing technologies and methods have the following drawbacks: 1. They consume a lot of manpower to replace cables, resulting in low testing efficiency; 2. Frequent cable replacements lead to decreased reliability of board connectors; 3. Inconsistent tightening of channel connections each time can cause testing errors. Summary of the Invention

[0004] The technical problem to be solved by this invention is how to improve testing efficiency and the reliability and consistency of test results.

[0005] The present invention solves the above-mentioned technical problems through the following technical means: a board test fixture, including a plurality of matrix switches, the plurality of matrix switches being divided into at least three layers, the first layer being a matrix switch array composed of multiple multi-input one-output matrix switches, the second layer being a multi-input one-output matrix switch, and the third layer being a one-input multi-output matrix switch, the common terminal of each multi-input one-output matrix switch in the first layer being connected to the input terminal of the matrix switch in the second layer, and the common terminal of the matrix switch in the second layer being connected to the common terminal of the matrix switch in the third layer, forming a matrix switch combination array with multiple inputs and multiple outputs.

[0006] This invention designs a cascaded array of at least three layers of matrix switches to form a matrix switch combination array. To enable continuous testing of multiple channels and multiple test items, the three-layer design is the smallest unit. Multiple test channels of the board under test are connected to the corresponding input terminals of the test fixture via cables, and the output terminals are connected to the testing instrument. Multiple cables only need to be connected once, eliminating the need to replace cables in between, ensuring consistent locking of each channel, improving testing efficiency, and guaranteeing the reliability and consistency of test results.

[0007] As a further optimized technical solution, the matrix switches consist of six switches. The first layer contains four eight-input, one-output matrix switches SP8T_1-SP8T_4, which have 32 input terminals IN_1 to IN_32 externally. The four common terminals are connected to the four input terminals of the four-input, one-output matrix switch SP4T_1 in the second layer. The common terminals of the second layer are connected to the common terminal of the one-input, four-output matrix switch SP4T_2 in the third layer. The third layer has four output terminals OUT_1 to OUT_4, forming a matrix switch combination array with 32 inputs and 4 outputs.

[0008] Currently, the single AWG control board for quantum computing has 32 channels. The instruments used include a power meter, a spectrum analyzer, a multimeter, and a phase noise meter. The 32-input, 4-output matrix switch array meets the board testing requirements of the room temperature control chassis system based on superconducting quantum computing.

[0009] As a further optimized technical solution, the third-layer matrix switch can be swapped with one of the multi-input, one-output matrix switches in the first layer.

[0010] Based on existing testing requirements, this solution allows for the rapid recombination of input and output channels without replacing the hardware.

[0011] As a further optimized technical solution, all input terminals of the matrix switch array can be turned on individually, in which case one output terminal is turned on; or only one input terminal of the matrix switch array can be turned on, in which case all output terminals or one output terminal is turned on.

[0012] By opening each input terminal and one of the output terminals separately, a vertical output comparison test of multi-channel input and single-channel output can be achieved; by opening only one input terminal and opening each output terminal separately, a horizontal comparison test of single-channel input and multi-channel output can be achieved; by opening only one input terminal and one output terminal, crosstalk test between channels can be achieved, thus completing various commonly used test methods for the board. Different test scenarios can be realized by combining the test fixtures of this solution according to actual application needs.

[0013] As a further optimized technical solution, the matrix switch is powered by a power adapter. Each power adapter powers one matrix switch. The power adapter is plugged into a power socket (5), and the input line of the power socket (5) is connected to the power switch (6) through a terminal wire.

[0014] When the power switch (6) supplies power, all matrix switches are powered.

[0015] As a further optimized technical solution, the test fixture also includes a chassis base plate (101), a cover plate (102), a front panel (103), and a rear panel (104). The front panel (103) is provided with an outlet for the matrix switch to the outside. The rear panel (104) is equipped with a power switch (6) and a USB adapter (7). The USB adapter (7) is connected to the USB interface of each matrix switch. Several matrix switches and power sockets (5) are fixed on the base plate (101). The cover plate (102), the front panel (103), and the rear panel (104) are respectively installed on the base plate (101) to form the test chassis shell.

[0016] The test fixture is integrated into a single chassis, making it easy to move and carry. The positions of each component are fixed to prevent loosening after a collision, thus improving the test application scenarios and test accuracy.

[0017] As a further optimized technical solution, the cover plate (102) is provided with an opening above the matrix switch, and a transparent acrylic panel (8) is installed on the opening.

[0018] The status of the indicator lights of the matrix switch inside the chassis during operation can be observed through the transparent acrylic panel (8), thereby timely detection and resolution of faults and improvement of testing efficiency.

[0019] As a further optimized technical solution, the matrix switches are connected by SMA cables, the power adapter is a 12V power adapter, and the multiple multi-input, one-output matrix switches in the first layer can be of the same or different models.

[0020] The present invention also provides a testing system, including the testing fixture, testing computer, and testing instruments described in any of the above embodiments. The testing fixture is connected to the testing computer via a USB cable, and the testing fixture is connected to each testing instrument via an SMA cable. The testing instruments are connected to the testing computer via a network cable.

[0021] This testing system enables rapid testing of circuit boards.

[0022] The present invention also provides a method for testing using the testing fixture described in any of the above-described schemes, comprising the following steps:

[0023] Step 1: Setting up the test environment

[0024] Connect the network port of the test instrument to the test computer via a network cable; power on the board under test and connect it to the test computer via a network cable.

[0025] Step 2: Tooling Connection

[0026] Connect the multiple channels of the board under test to the input terminal of the test fixture in sequence via SMA cable, connect the output terminal of the test fixture to each test instrument, connect the USB interface of the matrix switch on the test fixture to the USB interface of the test computer via USB cable, and provide external power input to the test fixture.

[0027] Step 3: Selection of Test Fixture Path

[0028] Select the appropriate input and output terminals according to the testing requirements;

[0029] Step 4: Output Power Test

[0030] According to the testing requirements, the output power test is performed after the corresponding channel is opened in step three.

[0031] Step 5: Remaining Test Items

[0032] Similar to step four, the tests conducted after the corresponding channels in step three are opened also include: spurious-free dynamic range (SFDR) testing for each channel, output static voltage calibration testing for each channel, phase noise testing for each channel, until all performance tests of the board under test are completed.

[0033] The testing method using this testing fixture can meet the requirements of one-time access testing of multiple inputs and multiple test items without the need for multiple cable replacements, thereby improving testing efficiency and ensuring the reliability and consistency of test results. At the same time, it can enable continuous testing over a longer period of time (such as at night or on holidays) without the need for personnel on duty, saving labor costs. Attached Figure Description

[0034] Figure 1 This is an exploded view of the test fixture according to an embodiment of the present invention;

[0035] Figure 2 This is an overall structural diagram of the test fixture according to an embodiment of the present invention;

[0036] Figure 3 This is a diagram of the matrix switch combination array in the test fixture of this invention embodiment;

[0037] Figure 4 This is another matrix switch combination array diagram of the test fixture in this embodiment of the invention;

[0038] Figure 5 This is a schematic diagram of the connection relationship of the test system according to an embodiment of the present invention;

[0039] Figure 6 This is a flowchart of the testing method according to an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other. Furthermore, the illustrations provided in the following embodiments are merely schematic representations of the basic concept of the invention. The illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex.

[0042] It should be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0043] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0044] Example 1

[0045] The test fixture proposed in this invention is used for testing circuit boards, especially those based on superconducting quantum computing room temperature controlled chassis systems. The test fixture is as follows: Figure 1 As shown, the system includes a chassis base plate 101, a cover plate 102, four 8-in-1-out matrix switches 2 (hereinafter referred to as matrix switches SP8T_1-SP8T_4 respectively), a 4-in-1-out matrix switch 3 (hereinafter referred to as matrix switch SP4T_1), a 1-in-4-out matrix switch 4 (hereinafter referred to as matrix switch SP4T_2), a power adapter (not shown), a power socket 5, a front panel 103, and a rear panel 104.

[0046] The cover plate 102 has a mesh design on both sides for ventilation and heat dissipation. As an optimized technical solution, a rectangular opening is provided on the top of the integrated cover plate 102, and a transparent acrylic panel 8 is installed on the rectangular opening, so that the situation below the cover plate 102 can be observed through the transparent acrylic panel 8. As an optimized technical solution, the cover plate 102 adopts an integrated cover plate, which improves the overall structural strength.

[0047] The four matrix switches SP8T_1-SP8T_4, the two matrix switches SP4T_1 and SP4T_2, and the power socket 5 are fixed to the screw holes reserved on the base plate 101 by bottom screws. The six matrix switches are fixed side by side at the front end of the base plate 101, and the power socket 5 is located at the rear end of the base plate 101.

[0048] The USB adapter 7 and the power switch 6 are installed on the rear panel 104 through the reserved screw holes. Six power adapters are plugged into the power socket 5, and the six power adapters supply power to the six matrix switches respectively. The input line of the power socket 5 is connected to the power switch 6 through the terminal wire. The power switch 6 is a rocker switch.

[0049] The front panel 103 has six circular outlets for the matrix switches to the outside, and the rear panel 104 has holes for installing power switches 6 and six USB adapters 7. The six USB adapters 7 are respectively connected to the USB interfaces USB_1-USB_6 of the six matrix switches.

[0050] The cover plate 102, front panel 103, and rear panel 104 are respectively installed onto the base plate 101 through the pre-drilled screw holes, thus forming a test fixture with a 32-input, 4-output control matrix. Figure 2 The diagram shown is an overall structural diagram of the test fixture.

[0051] As a further optimization, the front panel film 9 is attached to the front panel 103 with its own adhesive backing. Correspondingly, the front panel film 9 also has six circular outlets for the matrix switches to the outside. The transparent acrylic panel 8 is attached to the reserved holes above the integrated cover plate 102 with adhesive backing, which is used to observe the indicator light status of the internal matrix switches SP8T_1-SP8T_4 and matrix switches SP4T_1 and SP4T_2 during operation.

[0052] It should be noted that the core component of this test fixture is the six internal matrix switches, which are connected via SMA cables and arranged in three layers. The first layer contains four matrix switches SP8T_1-SP8T_4, with 32 input terminals (IN_1~IN_32) external to the test fixture. The four common terminals are connected to the four input terminals of the second-layer matrix switch SP4T_1, and the common terminal of the second layer is connected to the common terminal of the third-layer matrix switch SP4T_2. The output terminals (OUT_1~OUT_4) of the third layer connect to external devices and various test instruments to achieve different performance tests. The 32 input terminals and 4 output terminals are connected to different channels of signal input and output via a circular outlet on the front panel 103 of the test fixture. The six matrix switches use DC... The test fixture is powered by 12V. All six 12V power adapters are plugged into the internal power socket 5. Power socket 5 is connected to the power switch 6 on the rear panel 104. When power switch 6 is activated, the six matrix switches are powered by DC 12V. Each of the six matrix switches has a USB interface for connecting to the matrix switch MCU. These USB interfaces are externally connected to the USB adapter 7 on the rear panel 104. Thus, a matrix switch array with 32 inputs and 4 outputs is formed within the test fixture. Figure 3 As shown.

[0053] This design implements a 32-in-4-out test fixture to meet the board testing requirements of a room temperature controlled chassis system based on superconducting quantum computing. It mainly considers the advantages of single-pole multi-throw (8-in-1-out, 1-in-4-out, and 4-in-1-out) matrix switches, such as low cost, simple control, high flexibility in modification, and high testing accuracy.

[0054] Furthermore, based on the use of single-pole multi-throw matrix switches, a three-layer design is adopted as the smallest unit to achieve continuous testing of multiple channels (more than 8 channels) and multiple test items. The design principle is as follows: by designing four 8-input 1-output matrix switches 2 (SP8T_1-SP8T_4), 32 channels can be connected at once. The four common terminals of matrix switches 2 (SP8T_1-SP8T_4) are respectively connected to the four input terminals 2IN_1 to 2IN_4 of matrix switch 3 (SP4T_1). By selecting any channel from IN_1 to IN_32 and connecting it to the common terminal of matrix switch 3 (SP4T_1), a 32-channel single-test-item test scheme is achieved. A matrix switch 4 (SP4T_2) is further added. The common terminal of matrix switch 3 (SP4T_1) is connected to the common terminal of matrix switch 4 (SP4T_2), and the output terminals (OUT_1 to OUT_4) are connected to various test instruments to achieve a 32-channel multi-test-item test scheme.

[0055] As can be seen from the design principles above, if only the first layer is retained and the common terminals of the four matrix switches 2 (SP8T_1-SP8T_4) are connected to four different test instruments, only one test item for every eight channels can be achieved. At least 12 cable replacements would be required, connecting the common terminals of the four matrix switches 2 (SP8T_1-SP8T_4) to the remaining three test instruments. If both the first and second layers are retained, the second layer only has one output connected to a test instrument, allowing only one test item for 32 channels. At least three more cable replacements would be needed, connecting the common terminal of matrix switch 3 (SP4T_1) to the remaining three test instruments. Therefore, to meet the requirement of simultaneous access testing for multiple channel inputs and multiple test items, this solution designs a cascaded configuration of three matrix switches to ensure consistent locking levels across all channels and reduce testing errors.

[0056] With product updates and iterations, especially with the increasing integration of control boards for quantum computing, the number of test channels on a single board will increase (i.e., the number of input channels), and the use of test instruments will also increase (i.e., the number of output channels). By measuring the loss of cables between multiple layers and calculating compensation, the combination of matrix switches can be appropriately changed.

[0057] Optionally, the test fixture designed based on this solution can perform longitudinal output comparison tests of multi-channel input and single-channel output, such as opening input channels IN1-IN32 and output channel OUT1 respectively; it can also perform lateral comparison tests of single-channel input and multi-channel output, such as opening input channel IN1 and output channels OUT1-OUT4 respectively; it can also perform inter-channel crosstalk tests, such as setting the 1 / 2 / 3 channels of the test board to output 5GHz frequency signals, opening only input channel IN2 and output channel OUT2 (connected to an external spectrum analyzer), and observing the fluctuation value of output channel OUT2 after the 5GHz frequency signal of the 1 / 3 channels of the test board is turned off, etc. These are all commonly used test methods for superconducting quantum computing room temperature control chassis system boards, and different test scenarios can be realized by combining the test fixture of this solution according to actual application needs.

[0058] Of course, those skilled in the art will know that with the development of technology, when more or fewer inputs and outputs are required for test fixtures, the number and type of matrix switches in each layer can be adjusted accordingly to adapt to different input and output test scenarios.

[0059] Example 2

[0060] Based on the solution in Example 1, and according to existing testing requirements, the number of input and output channels can be quickly recombined without changing the hardware. For example, the matrix switch SP4T_2 on the third layer can be swapped with the matrix switch SP8T_4 on the first layer. In this case, the matrix switch SP4T_2 becomes a 4-input, 1-output switch, while SP8T_4 becomes a 1-input, 8-output switch, thus realizing a 28-input, 8-output test fixture. Figure 4 As shown.

[0061] Similarly, the test fixture designed based on this scheme can realize longitudinal output comparison tests of multi-channel input and single-channel output, such as opening the input channels IN1-IN28 and the output OUT1 respectively; it can also realize lateral comparison tests of single-channel input and multi-channel output, such as opening the input channel IN1 and the output channels OUT1-OUT8 respectively; it can also realize inter-channel crosstalk tests, such as setting the 1 / 2 / 3 channels of the test board to output 5GHz frequency signals, opening only the input channel IN2 and the output channel OUT2 (connected to an external spectrum analyzer), and observing the fluctuation value of the output of the output channel OUT2 after the 5GHz frequency signal of the 1 / 3 channels of the test board is turned off, etc. These are all commonly used test methods for superconducting quantum computing room temperature control chassis system boards, and different test scenarios can be realized by combining the test fixture of this scheme according to actual application needs.

[0062] Example 3

[0063] This solution further proposes a testing method using the test fixtures of Embodiments 1 and 2, for testing the circuit boards of a superconducting quantum computing room temperature control chassis system. It can traverse multiple performance test items across all test channels and enables continuous testing over extended periods (such as evenings or holidays) without human intervention, saving labor costs. To facilitate a better understanding of the testing method described in this solution for those skilled in the art, a connection diagram is provided. Figure 5 As shown, the test fixture is connected to the test computer via a USB cable. The test computer sends control commands to the MCU modules of each matrix switch. The test fixture is then connected to each test instrument via SMA cables, thus forming a test system. This system controls the connection of input and output terminals, enabling path selection and parameter testing. This solution further elaborates on a clear and complete description of the comparative test of multi-channel input and single-channel output. The test environment connection relationships are as follows: Figure 5 As shown.

[0064] The board testing method in this embodiment includes the following steps:

[0065] Step 1: Setting up the test environment

[0066] according to Figure 1 The assembly test fixture shown is referenced. Figure 5, connect the network port of the test instrument (such as a power meter, spectrum analyzer, multimeter, phase noise meter) to the test computer through a network cable; insert the board under test into the chassis of the superconducting quantum room temperature regulation system and power it on. After being transferred through the chassis of the superconducting quantum room temperature regulation system, the board under test is connected to the test computer using a network cable;

[0067] Step 2: Fixture Connection

[0068] Refer to Figure 5 , connect multiple channels of the board under test to the input end of the test fixture in sequence through SMA cable lines, such as input ends IN_1 to IN_32. Connect the output ends of the test fixture, such as output ends OUT_1 to OUT_4, to a power meter, spectrum analyzer, multimeter, and phase noise meter respectively. Connect the USB adapters 7 that are respectively connected to the USB interfaces of the 6 matrix switches on the test fixture to the USB interfaces of the test computer through USB cables, and externally provide power input to the test fixture; [[ID=⑨]] [[ID=⑩]]

[0069] Step 3: Test Fixture Path Selection

[0070] Combined with Figure 3 and Figure 5 shown, the test computer is connected to USB_1 of the test fixture through the USB interface and issues corresponding instructions. The MCU_1 module of the matrix switch SP8T_1 controls the input end IN_1 and the common end to open. Issue corresponding instructions to the MCU_5 module of the matrix switch SP4T_1 through USB_5 to control the input end 2IN_1 and the common end to open. Issue corresponding instructions to the MCU_6 module of the matrix switch SP4T_2 through USB_6 to control the common end and the output end OUT_1 to open.至此, the input end IN_1 and the output end OUT_1 of the test fixture form a path.同理, refer to the above operations, and 32 * 4 = 128 paths can be selected;

[0071] Step 4: Output Power Test

[0072] The test computer sets the output of channel 1 of the board under test to a fixed power A1 (such as 0 dBm) through the network port, and the test computer opens the path between the input end IN_1 and the output end OUT_1 through the USB interface. The test computer reads the measured value A2 of the power meter connected to the output end OUT_1 through the network cable. Calculate the difference between the set value A1 and the read value A2 through the test computer software. If the error requirement is met, it is judged that the test is qualified, and the path formed by the input end IN_1 and the output end OUT_1 is closed. If the error requirement is not met, the path is reopened for retesting.同理, open the paths between the input ends IN_2 to IN_32 and the output end OUT_1 respectively to complete the output power test of each channel of the board under test;

[0073] Step 5: Remaining Test Items

[0074] Similar to step four, the test computer opens the input terminals IN_1 to IN_32 and the output terminal OUT_2 via the USB interface to complete the spurious-free dynamic range (SFDR) test for each channel; opens the input terminals IN_1 to IN_32 and the output terminal OUT_3 to complete the output static voltage calibration test for each channel; opens the input terminals IN_1 to IN_32 and the output terminal OUT_4 to complete the phase noise test for each channel of the board under test, until all performance tests of the board under test are completed.

Claims

1. A circuit board testing fixture, characterized in that, It includes several matrix switches, which are divided into at least three layers. The first layer is a matrix switch array composed of multiple multi-input, single-output matrix switches. The second layer is a multi-input, single-output matrix switch. The third layer is a single-input, multi-output matrix switch. The common terminal of each multi-input, single-output matrix switch in the first layer is connected to the input terminal of the matrix switch in the second layer. The common terminal of the matrix switch in the second layer is connected to the common terminal of the matrix switch in the third layer, forming a matrix switch combination array with multiple inputs and multiple outputs.

2. The test fixture as described in claim 1, characterized in that, The matrix switches consist of six units. The first layer contains four eight-input, one-output matrix switches SP8T_1-SP8T_4, which have 32 input terminals IN_1 to IN_32. The four common terminals are connected to the four input terminals of the four-input, one-output matrix switch SP4T_1 in the second layer. The common terminals of the second layer are connected to the common terminal of the one-input, four-output matrix switch SP4T_2 in the third layer. The third layer has four output terminals OUT_1 to OUT_4, forming a matrix switch combination array with 32 inputs and 4 outputs.

3. The test fixture as described in claim 1, characterized in that, The third-layer matrix switch can be swapped with one of the multi-input, one-output matrix switches in the first layer.

4. The test fixture as described in claim 1, characterized in that, All input terminals of the matrix switch array can be turned on individually, in which case one output terminal is turned on; or only one input terminal of the matrix switch array can be turned on, in which case all output terminals or one output terminal is turned on.

5. The test fixture as described in claim 1, characterized in that, The matrix switch is powered by a power adapter. Each power adapter powers one matrix switch. The power adapter is plugged into a power socket (5). The input line of the power socket (5) is connected to the power switch (6) through a terminal wire.

6. The test fixture as described in claim 5, characterized in that, It also includes a chassis base plate (101), a cover plate (102), a front panel (103), and a rear panel (104). The front panel (103) has an outlet for the matrix switches to the outside. The rear panel (104) is equipped with a power switch (6) and a USB adapter (7). The USB adapter (7) is connected to the USB interface of each matrix switch. Several matrix switches and power sockets (5) are fixed on the base plate (101). The cover plate (102), the front panel (103), and the rear panel (104) are respectively installed on the base plate (101) to form the test chassis shell.

7. The test fixture as described in claim 6, characterized in that, The cover plate (102) has an opening above the matrix switch, and a transparent acrylic panel (8) is installed on the opening.

8. The test fixture as described in claim 5, characterized in that, The matrix switches are connected by SMA cables, and the power adapter is a 12V power adapter. The multiple multi-input, one-output matrix switches in the first layer can be of the same or different models.

9. A testing system, characterized in that, The test fixture, test computer, and test instruments are as described in any one of claims 1 to 8. The test fixture is connected to the test computer via a USB cable, the test fixture is connected to each test instrument via an SMA cable, and the test instruments are connected to the test computer via a network cable.

10. A method for testing using the testing fixture described in any one of claims 1-8, characterized in that, Includes the following steps: Step 1: Setting up the test environment Connect the network port of the test instrument to the test computer via a network cable; power on the board under test and connect it to the test computer via a network cable. Step 2: Tooling Connection Connect the multiple channels of the board under test to the input terminal of the test fixture in sequence via SMA cable, connect the output terminal of the test fixture to each test instrument, connect the USB interface of the matrix switch on the test fixture to the USB interface of the test computer via USB cable, and provide external power input to the test fixture. Step 3: Selection of Test Fixture Path Select the appropriate input and output terminals according to the testing requirements; Step 4: Output Power Test According to the testing requirements, the output power test is performed after the corresponding channel is opened in step three. Step 5: Remaining Test Items Similar to step four, the tests conducted after the corresponding channels in step three are opened also include: spurious-free dynamic range (SFDR) testing for each channel, output static voltage calibration testing for each channel, phase noise testing for each channel, until all performance tests of the board under test are completed.

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