Chip, chip testing method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a chip, a chip test method, electronic equipment and a storage medium. The chip comprises a vector generation module, a test scan chain and a to-be-tested module, the vector generation module comprises a first selector and a plurality of registers; the first selector and the plurality of registers are sequentially connected in series to form a transmission chain, and the first selector comprises a first input end and a second input end; the first input end is connected with the output end of the transmission chain. The first selector receives an initial vector sequence through a second input end and inputs the initial vector sequence into each register under the condition of receiving a trigger signal, and receives a to-be-transmitted vector through a first input end and sequentially transmits the to-be-transmitted vector into each register under the condition of not receiving the trigger signal; the output end of the transmission chain outputs an aging vector to a test scanning chain of the chip; the to-be-tested module receives the burn-in vector through the test scanning link and operates based on the burn-in vector, so that the burn-in test cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a chip, a chip testing method, an electronic device, and a storage medium. Background Technology

[0002] With the development of integrated circuit technology, chips are becoming increasingly complex. To ensure chip reliability, aging tests are often required. Aging tests involve continuously applying stress to the components in the chip over a certain period of time, causing potential defects inside the components to be exposed early. This facilitates the removal of components that fail prematurely, thereby improving chip reliability.

[0003] Current aging tests are usually implemented through external devices (e.g., aging boards). The external devices generate aging vectors and input them into the chip. However, external devices are often expensive, and aging tests can shorten the lifespan of the external devices, making the cost of aging tests high. Summary of the Invention

[0004] This invention provides a chip, a chip testing method, an electronic device, and a storage medium to solve the problem of high aging test costs.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows: In a first aspect, the present invention provides a chip comprising a vector generation module, a test scan chain, and a module under test; the vector generation module includes a first selector and a plurality of registers; the first selector and the plurality of registers are sequentially connected in series to form a transmission chain, the first selector including a first input terminal and a second input terminal; the first input terminal is connected to the output terminal of the transmission chain; The first selector is configured to receive an initial vector sequence through the second input terminal and input the initial vector sequence into each of the registers when a trigger signal is received, and to receive a vector to be transmitted through the first input terminal and transmit the vector to be transmitted sequentially into each of the registers when the trigger signal is not received. The output end of the transmission chain is used to output the aging vector to the test scan chain of the chip; The module under test is used to receive the refinement vector through the test scan link and run based on the refinement vector.

[0006] Optionally, the module under test includes a counting module; the test scan chain includes at least one scan register and at least one second selector; the second selector includes a third input terminal, a fourth input terminal, a selection terminal, and an output terminal; the third input terminal is connected to the output terminal of the module under test; the fourth input terminal is connected to the output terminal of the transmission chain; the counting module is connected to the selection terminal; the input terminal of the scan register is connected to the output terminal of the second selector. The counting module is used for counting, and outputs a first selection signal when the count value reaches a first preset value; The second selector is configured to receive the output data of the module under test through the third input terminal and input the output data into the scan register when the first selection signal is received, and to receive the data to be transmitted of the test scan chain through the fourth input terminal and input the data to be transmitted of the test scan chain into the scan register when the first selection signal is not received.

[0007] Optionally, after outputting the first selection signal, the counting module is also used to recount and output a second selection signal when the count value reaches a second preset value; the second selection signal is different from the first selection signal.

[0008] Optionally, the chip includes multiple modules under test; the test scan chain includes multiple second selectors and the scan register, with each second selector and each scan register being alternately connected in series to form the test scan chain.

[0009] Optionally, the output of each scan register is connected to the input of each module under test.

[0010] Optionally, the number of data contained in the initial vector sequence is consistent with the number of registers in the transport chain; the initial vector sequence is determined based on a specified inversion rate.

[0011] Optionally, the module under test is a combinational logic circuit of the chip.

[0012] In a second aspect, the present invention provides a chip testing method, the method being applied to a vector generation module in a chip, the chip being the chip described in the first aspect, the method comprising: Upon receiving a trigger signal, an initial vector sequence is received and input into each register of the transmission chain; and if the trigger signal is not received, the vector to be transmitted is sequentially passed to each register of the transmission chain. An aging vector is generated based on the initial vector sequence or the vector to be transmitted, and the aging vector is transmitted to the test scan chain of the chip through the transmission chain. The module under test is used to receive the refinement vector through the test scan link and run based on the refinement vector.

[0013] Thirdly, the present invention provides an electronic device comprising the chip described in the first aspect.

[0014] Fourthly, the present invention provides a readable storage medium that, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the chip testing method described in the second aspect.

[0015] The chip provided in this embodiment of the invention includes a vector generation module, a test scan chain, and a module under test. The vector generation module includes a first selector and multiple registers. The first selector and the multiple registers are sequentially connected to form a transmission chain. The first selector includes a first input terminal and a second input terminal. The first input terminal is connected to the output terminal of the transmission chain. The first selector is used to receive an initial vector sequence through the second input terminal and input the initial vector sequence into each of the registers when a trigger signal is received, and to receive a vector to be transmitted through the first input terminal and sequentially transmit the vector to be transmitted into each of the registers when the trigger signal is not received. The output terminal of the transmission chain is used to output a refined vector to the test scan chain of the chip. The module under test is used to receive the refined vector through the test scan chain and operate based on the refined vector. In this way, the first selector and registers in the vector generation module can generate aging vectors within the chip using the received initial vector sequence and the vector to be transmitted. The aging vectors are then output to the test scan chain via the transmission chain, and the test scan chain in the chip transmits the aging vectors to the module under test. This eliminates the need for third-party testing equipment such as aging boards. The aging vectors can be automatically generated simply by setting the selector and multiple registers, without incurring high costs. This significantly reduces the cost of aging tests while ensuring their automatic execution. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1This is a schematic diagram of the structure of a chip provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a vector generation module provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a test scan chain provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another chip structure provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of the present invention, such as... Figure 1 As shown, the chip includes a vector generation module 11, a test scan chain 13, and a module under test 12; the vector generation module includes a first selector 111 and multiple registers 112; the first selector 111 and the multiple registers 112 are connected in series to form a transmission chain, and the first selector includes a first input terminal and a second input terminal; the first input terminal is connected to the output terminal of the transmission chain.

[0020] The first selector 111 is configured to receive an initial vector sequence through the second input terminal and input the initial vector sequence into each of the registers when a trigger signal is received; and to receive a vector to be transmitted through the first input terminal and sequentially transmit the vector to be transmitted into each of the registers when the trigger signal is not received. The output terminal of the transmission chain is configured to output a refined vector to the test scan chain of the chip.

[0021] The module under test 12 is used to receive the aging vector through the test scan chain 13 and run based on the aging vector.

[0022] The aforementioned module under test refers to the circuit module in the chip that requires aging testing, which can be combinational logic circuits, sequential logic circuits, etc. The aforementioned trigger signal can be a signal indicating the start of the test, which can be sent to the chip by relevant personnel. Specifically, a pre-written signal indicating the start of the test (e.g., 1) can be received in a designated processor register (CPU_REG) on the chip. The first selector in the vector generation module can be connected to this processor register, so that the first selector can receive the trigger signal through the processor register. Specifically, the first selector may also include a selection terminal, through which the first selector can receive the trigger signal.

[0023] The aging vector refers to the data used for aging tests, also known as the aging test vector. The aging vector can be 0 or 1, allowing the module under test (DUT) to receive 0 or 1 signals and trigger corresponding operational logic. By continuously inputting the aging vector into the DUT, the DUT continuously receives 0 or 1 signals, causing the internal logic nodes within the DUT to switch between 0 and 1, achieving effective reversal of internal logic nodes. This allows for rapid simulation of various operating states of the DUT, accelerating its aging process. Furthermore, after the DUT has run based on the aging vector for a certain period, its electrical parameters can be sampled to obtain the aging test results. Alternatively, during the DUT's operation based on the aging vector, the input and output signals of each device within the DUT can be sampled and detected to obtain the aging test results in real time. Different methods for obtaining aging test results can be selected according to actual needs, and this embodiment of the invention does not impose any limitations on this.

[0024] The initial vector sequence mentioned above refers to the data sequence used to generate the refined vector. The vector generation module outputs the refined vector based on the initial vector sequence. The output end of the transport chain can be the target register in the transport chain, which can be used to connect to the input end of the test scan chain. The target register can be any one of the multiple registers mentioned above, for example, it can be the last register, or it can be the second or third register. It can be set according to actual needs, and this embodiment of the invention does not limit it.

[0025] The registers included in the vector generation module can be pre-selected from all registers included in the chip, and the number of registers can be set according to actual needs. This embodiment of the invention does not limit this. Specifically, the first selector mentioned above refers to the MUX. The first selector can receive the trigger signal and the initial vector sequence, and input the initial vector sequence into each register.

[0026] Here, the vector to be transmitted refers to the vector input from the output of the transmission chain to the first input when the first selector does not receive a trigger signal. Specifically, the trigger signal can be an instantaneous signal, meaning that when the first selector receives the trigger signal, it selects to input the initial vector sequence received at the second input into each register. After the trigger signal is immediately turned off, the first selector does not receive a trigger signal at this time, and can choose to use the data received at the first input as the vector to be transmitted, and generate a refined vector based on the vector to be transmitted.

[0027] Furthermore, the output of the transmission chain can output a refined vector based on an initial vector sequence or a vector to be transmitted. Specifically, when the first selector receives a trigger signal, the transmission chain receives the initial vector sequence through the second input, and can then output the initial vector sequence as a refined vector. Conversely, when the first selector does not receive a trigger signal, since the first input is connected to the output of the transmission chain, the data output by the transmission chain can be used as the vector to be transmitted and input to the first input, and can then be output as a refined vector.

[0028] In this system, a first selector and multiple registers are serially connected to form a transmission chain. The first selector serves as the input to the transmission chain, receiving the initial vector sequence. This initial vector sequence can contain multiple data points. The first selector can transmit the initial vector sequence to various registers within the transmission chain, with different registers storing different bits of data from the initial vector sequence. Specifically, the initial vector sequence can be input to the first selector from the Transport Driver Interface (TDI) by the Joint Test Action Group (JTAG) within the chip.

[0029] Figure 2 This is a schematic diagram of the structure of a vector generation module provided in an embodiment of the present invention, such as... Figure 2 As shown, the vector generation module includes a first selector 111 and multiple registers 112, which are serially connected to form a transmission chain. Figure 2 In the `Init_pattern`, the initial vector sequence mentioned above is used as the initial aging vector. This vector can be input to the first selector from the Transport Driver Interface (TDI) by the Joint Test Action Group (JTAG) within the chip. Here, `CLK` is the clock signal, which can be the internal clock of the chip. `SE` represents the trigger signal, which can be controlled by JTAG.

[0030] Specifically, such as Figure 2 As shown, the first selector has two inputs: one input receives the `Init_pattern`, and the other input is connected to the output of the transmission chain. The first selector selects which input to receive data for transmission based on the different `SE` signals received at the selection end.

[0031] For example, in this embodiment of the invention, SE can be set to 1 via JTAG. At this time, the first selector receives a trigger signal, thereby selecting Init_pattern as the data source. That is, the initial vector sequence is received through the second input terminal. Taking the initial vector sequence as 0101 as an example, these four bits of data are... Figure 2 The data is stored in four registers (register, REG). Further, the SE signal can be adjusted to 0, so the first selector does not receive a trigger signal. In this case, the transmission chain can be considered a circular shift register. Correspondingly, the output data simultaneously serves as the input to the first selector. The first selector receives the output data from the first input as the vector to be transmitted, and the output of the transmission chain will continuously alternately output 0s and 1s. For example... Figure 2 As shown, Figure 2 The output of the transmission chain is the register closest to the output end in the transmission chain, and the output of this register is the output of the entire transmission chain.

[0032] The aforementioned test scan chain is pre-built for this chip. Specifically, to facilitate testing, all registers inside the chip can be replaced with scan registers before chip testing, and these scan registers are connected serially to form a test scan chain. The test scan chain is used to receive test data and transfer the test data to the chip's internal components through shifting. Thus, in this embodiment of the invention, the refined vector generated by the vector generation module can be transmitted to the chip's test scan chain, and the refined vector is then transmitted to the module under test via the test scan chain.

[0033] Specifically, the output of the transmission chain in the chip can be connected to the input of the test scan chain, and correspondingly, the output of the test scan chain can be connected to the input of the module under test, thereby realizing the transmission of the aging vector.

[0034] Specifically, the aforementioned vector generation module may also include an inverter. The input of the inverter can be connected to the output of the transmission chain, and the output of the inverter can be connected to the first input of the first selector. Accordingly, when the first selector does not receive a trigger signal, it can invert the vector (0 or 1) output by the transmission chain and input it back to the first input for transmission in the transmission chain. This allows the transmission chain to continuously output 0 and 1 at intervals as a transmission vector to a certain extent.

[0035] Optionally, the module under test is a combinational logic circuit of the chip.

[0036] The aforementioned combinational logic circuits, also known as combinational circuits, are characterized by the fact that their output at any given time depends solely on the input at that moment, regardless of the circuit's previous state. Therefore, combinational logic circuits can be effectively verified through aging tests.

[0037] This allows for automated aging tests on the combinational logic circuits in the chip.

[0038] In summary, the chip provided in this embodiment of the invention includes a vector generation module, a test scan chain, and a module under test. The vector generation module includes a first selector and multiple registers. The first selector and the multiple registers are sequentially connected to form a transmission chain. The first selector includes a first input terminal and a second input terminal. The first input terminal is connected to the output terminal of the transmission chain. The first selector is used to receive an initial vector sequence through the second input terminal and input the initial vector sequence into each of the registers when a trigger signal is received, and to receive a vector to be transmitted through the first input terminal and sequentially transmit the vector to be transmitted into each of the registers when the trigger signal is not received. The output terminal of the transmission chain is used to output a refined vector to the test scan chain of the chip. The module under test is used to receive the refined vector through the test scan chain and operate based on the refined vector. In this way, the first selector and registers in the vector generation module can generate aging vectors within the chip using the received initial vector sequence and the vector to be transmitted. The aging vectors are then output to the test scan chain via the transmission chain, and the test scan chain in the chip transmits the aging vectors to the module under test. This eliminates the need for third-party testing equipment such as aging boards. The aging vectors can be automatically generated simply by setting the selector and multiple registers, without incurring high costs. This significantly reduces the cost of aging tests while ensuring their automatic execution.

[0039] Optionally, the module under test includes a counting module, and the test scan chain includes at least one scan register and at least one second selector; the second selector includes a third input terminal, a fourth input terminal, a selection terminal, and an output terminal; the third input terminal is connected to the output terminal of the module under test; the fourth input terminal is connected to the output terminal of the transmission chain; the counting module is connected to the selection terminal; and the input terminal of the scan register is connected to the output terminal of the second selector.

[0040] The counting module is used for counting, and outputs a first selection signal when the count value reaches a first preset value; the second selector is used to receive the output data of the module under test through the third input terminal when the first selection signal is received, and input the output data into the scan register, and to receive the data to be transmitted of the test scan chain through the fourth input terminal when the first selection signal is not received, and input the data to be transmitted of the test scan chain into the scan register.

[0041] The counting module can be a counter. The first preset value can be pre-set and can be set according to the actual needs of the module under test; this embodiment of the invention does not impose any limitations on this. Accordingly, the counting module can count and output a first selection signal when the count value reaches the first preset value. For example, the first preset value can be set to 2. 20 The counting module starts counting from 0. When the highest bit of the counting module is 1, the counting value of the counting module reaches the first preset value of 2. 20 Then the first selection signal can be output.

[0042] The first selection signal can be a switch signal, which can be 0 or 1, and this embodiment of the invention does not impose any limitation on this. The second selector can be a multiplexer (MUX), which can include two input terminals, namely a third input terminal and a fourth input terminal. The MUX can also include a selection terminal, which can select different input terminals to receive input data according to different signals received by the selection terminal. Further, the counting module can output the first selection signal through its signal output terminal, and correspondingly, the signal output terminal of the counting module can be connected to the selection terminal of the MUX. The output terminal of the second selector is connected to the input terminal of the scan register.

[0043] Furthermore, when the second selector receives the first selection signal, it receives input data through its third input terminal. Since the third input terminal of the second selector is connected to the output terminal of the module under test (DUT), the second selector can receive the output data of the DUT through its third input terminal and further input the received data into the scan register. Correspondingly, when the second selector does not receive the first selection signal, it can receive the data to be transmitted from the test scan chain through its fourth input terminal and input the data to be transmitted from the test scan chain into the scan register.

[0044] The fourth input terminal can be connected to the output terminal of the aforementioned vector generation module. Alternatively, in the case of multiple scan registers, each scan register can correspond to its own second selector. Accordingly, the fourth input terminal of each second selector can be connected to the output terminal of the previous scan register, and the output terminal of each second selector can be connected to the input terminal of the next scan register. The data to be transmitted in the aforementioned test scan chain refers to the refined vector generated by the vector generation module received by the fourth input terminal.

[0045] Specifically, during normal chip operation, the workflow of the module under test (DUT) typically involves two states: shift and capture. Shift refers to receiving input data, while capture refers to outputting data to registers. Current aging testing methods replace the chip's internal registers with scan chain units and incorporate them into the design. During testing, the scan chain, formed by cascading scan chain units, transmits the aging test data to the chip's internals using a shifting method. During this process, test data is not only transmitted within the scan chain units but also passed from the output of the scan chain units to the corresponding combinational logic. Therefore, the current aging testing methods only involve data transmission from scan chain units to combinational logic and from scan chain units to scan chain units; data transmission from combinational logic to scan chain units is not present. In other words, the aging test in related technologies only tests the shift state. That is, the aging vector is only input to the module under test through external devices such as aging boards. The aging vector is only passed to the logic device of the module under test through the test scan chain. There is no situation where the module under test transmits data to the register. However, in the actual operation of the chip, in some functional modes, there may be situations where data is transmitted from the module under test to the register. Therefore, the test method used in related technologies cannot simulate the actual working situation of the module under test, resulting in poor aging test results.

[0046] In this embodiment of the invention, the output terminal of the module under test (DUT) is connected to the scan register in the test scan chain via a second selector. A counting module is installed in the DUT. When the count value of the counting module reaches a first preset value, the second selector receives the output data of the DUT via a third input terminal and inputs the output data into the scan register. Thus, during the aging test of the DUT, the second selector can choose to receive either the output data of the DUT or the output data of the test scan chain based on the count value of the counting module. This allows for automatic switching between shift and capture, simulating the actual working state of the DUT, more closely resembling the real operation of the chip, and ensuring the effectiveness of the aging test.

[0047] Optionally, after outputting the first selection signal, the counting module is also used to recount and output a second selection signal when the count value reaches a second preset value; the second selection signal is different from the first selection signal.

[0048] The aforementioned second preset value can also be pre-set, and can be set according to the testing requirements of the module under test. This embodiment of the invention does not impose any limitations on this. The aforementioned second selection signal refers to a signal different from the first selection signal, and can also be a switching signal. For example, if the first selection signal is 0, then the second selection signal can be 1.

[0049] Specifically, after the counting module outputs the first selection signal, the aging test enters the capture state. At this time, the counting module can restart counting, and when the count value reaches the second preset value, it outputs the second selection signal. If the second selector does not receive the first selection signal, it receives the data to be transmitted from the test scan chain through the fourth input terminal, and the aging test of the module under test re-enters the shift state.

[0050] This invention enables automatic switching between shift and capture by setting a second preset value and having the counting module recount after outputting the first selection signal, and outputting the second selection signal when the count value reaches the second preset value.

[0051] Optionally, in this embodiment of the invention, since the clock of the chip in the shift state is often slow, typically 100 MHz, while the clock of the chip in the capture stage is often fast, in order to ensure the authenticity of the chip verification, after the counting module outputs the first selection signal, this embodiment of the invention can also switch the chip clock to the high-speed clock generated by the phase-locked loop (PLL) in the chip.

[0052] Optionally, the number of data contained in the initial vector sequence is consistent with the number of registers in the transport chain; the initial vector sequence is determined based on a specified inversion rate.

[0053] Specifically, since the data contained in the initial vector sequence needs to be registered through registers in the transfer chain, the number of data contained in the initial vector sequence can be made consistent with the number of registers in the transfer chain, so that all the data in the initial vector sequence can be registered.

[0054] The aforementioned inversion rate refers to the circuit inversion rate, specifically the frequency of signal transitions in a digital circuit, that is, the number of times a signal transitions from a high level (logic "1") to a low level (logic "0") or from a low level to a high level per unit time. For example, based on a transmission chain containing four registers and an initial vector sequence of 0101, the corresponding inversion rate is 50%, meaning that signals 0 and 1 appear alternately on average.

[0055] Furthermore, aging tests may have different test requirements, and correspondingly, the required reversal rate will also be different. The specified reversal rate mentioned above can be set by the user based on the actual test requirements, and this embodiment of the invention does not impose any restrictions on this.

[0056] Optionally, the chip includes multiple modules under test; the test scan chain includes multiple second selectors and the scan register, with each second selector and each scan register being alternately connected in series to form the test scan chain.

[0057] The test scan chain can contain multiple second selectors and scan registers, which are alternately connected in series to form the test scan chain. Correspondingly, the input terminals of each module under test can be connected to the output terminals of the test scan chain, and the output terminals of the module under test can be connected to the input terminals of the test scan chain.

[0058] The output of the aforementioned test scan chain can be the scan register closest to the output in the test scan chain, and the input of the aforementioned test scan chain can be the third input of the second selector closest to the input in the test scan chain.

[0059] This allows each module under test to receive aging vectors through the test scan link. At the same time, the data of the module under test can be output to the register of the test scan link, realizing automatic switching of aging latency, shift and capture for multiple modules under test.

[0060] Optionally, the output of each scan register is connected to the input of each module under test (DUT). Specifically, each DUT can be connected to each scan register via a second selector. In the test scan chain, the output of each scan register is connected to the input of each DUT. The output of each DUT can be connected to the third input of any second selector, the output of the second selector is connected to the input of each scan register, and the output of the scan register can be connected to the input of the next DUT and the fourth input of the next second selector. Further, the input of the DUT can be connected to the output of the previous scan register.

[0061] Figure 3This is a schematic diagram of a test scan chain provided in an embodiment of the present invention, as shown below. Figure 3 As shown, Figure 3 The module under test (DUT) is a combinational logic circuit. The test scan chain includes multiple second selectors 121 and scan registers 122. The second selectors and scan registers are alternately connected in series to form the test scan chain. At the same time, each DUT is connected to one input terminal of each second selector, thereby connecting to each scan register. The output terminal of each scan register is connected to the input terminal of each DUT.

[0062] In this embodiment of the invention, the output terminal of each scan register is connected to the input terminal of each module under test. This ensures that each module under test can switch between shift and capture states during the aging test via the second selector and the scan register.

[0063] Furthermore, Figure 4 This is a schematic diagram of another chip structure provided in an embodiment of the present invention, such as... Figure 4 As shown, the chip includes a vector generation module, a test scan chain, and multiple modules under test (DUTs). The output of the vector generation module is connected to the input of the test scan chain. The output of each scan register in the test scan chain is connected to the input of each DUT. The output of each DUT can be connected to the third input of any second selector. The output of the second selector is connected to the input of each scan register. The output of the scan register can be connected to the input of the next DUT and the fourth input of the next second selector.

[0064] Optionally, embodiments of the present invention also provide a chip testing method, which can be applied to a vector generation module in a chip. The chip can be the chip shown in the above embodiments. Specifically, embodiments of the present invention may include: Upon receiving a trigger signal, an initial vector sequence is received and input into each register of the transmission chain; conversely, if the trigger signal is not received, the vector to be transmitted is sequentially passed to each register of the transmission chain.

[0065] An aging vector is generated based on the initial vector sequence or the vector to be transmitted, and the aging vector is transmitted to the test scan chain of the chip through the transmission chain.

[0066] The vector generation module is used to generate an aging vector based on the initial vector sequence or the vector to be transmitted when a trigger signal is received, and transmits the aging vector to the module under test through the test scan chain, so that the module under test can realize the aging test by running based on the aging vector.

[0067] Specifically, the vector generation module can receive and transmit the initial vector sequence when a trigger signal is received, and output the previously received initial vector sequence as the vector to be transmitted when no trigger signal is received.

[0068] It should be noted that as the complexity of integrated circuits increases, their reliability becomes increasingly prominent. Aging testing is an effective means of eliminating early circuit failures and improving circuit reliability. Aging testing is divided into static aging, dynamic aging, and aging-in-process testing. Among them, dynamic aging can effectively flip the internal nodes of the circuit, making it an effective and feasible testing method. Aging testing mainly applies electrical and thermal stress to integrated circuits and applies an effective aging vector to accelerate the occurrence of failures in potentially defective circuits, thereby improving reliability.

[0069] In related technologies, an external aging board is often used to continuously send aging vectors to the chip while simultaneously heating and pressurizing it. The aging board is programmed with corresponding instructions set in the chip's top-level JTAG module, and then the aging vectors are sent to the TDI interface. Once inside the chip, the vectors undergo shift operations in registers on the scan chain. During this shifting process, the aging vectors enter the combinational logic of the functional modules, causing effective reversal of nodes within the combinational logic circuits. However, aging boards are precision and expensive instruments, and this method undoubtedly shortens their lifespan and increases aging testing costs.

[0070] The chip testing method provided in this invention utilizes a chip comprising a vector generation module, a test scan chain, and a module under test (DUT). The vector generation module receives an initial vector sequence upon receiving a trigger signal and inputs the initial vector sequence into registers of the transmission chain. Conversely, if the trigger signal is not received, it sequentially transmits the vector to be transmitted to each register of the transmission chain. Based on the initial vector sequence or the vector to be transmitted, a aging vector is generated and transmitted to the chip's test scan chain via the transmission chain. The DUT receives the aging vector through the test scan chain and operates based on the aging vector. Thus, the aging vector can be generated internally within the chip using the vector generation module and transmitted to the DUT via the chip's test scan chain, eliminating the need for third-party testing equipment such as aging boards and significantly reducing the cost of aging tests.

[0071] The present invention also provides an electronic device. The chip provided in the embodiments of the present invention can be located in the electronic device, such as a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness device, personal digital assistant, etc.

[0072] The present invention also provides a readable storage medium, wherein when the instructions in the storage medium are executed by the processor of an electronic device, the electronic device is able to perform the chip testing method of the foregoing embodiments.

[0073] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0074] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0075] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0076] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0077] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0078] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for performing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0079] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0080] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0082] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, The chip includes a vector generation module, a test scan chain, and a module under test; the vector generation module includes a first selector and multiple registers; the first selector and the multiple registers are connected in series to form a transmission chain, and the first selector includes a first input terminal and a second input terminal; the first input terminal is connected to the output terminal of the transmission chain; The first selector is configured to receive an initial vector sequence through the second input terminal and input the initial vector sequence into each of the registers when a trigger signal is received, and to receive a vector to be transmitted through the first input terminal and transmit the vector to be transmitted sequentially into each of the registers when the trigger signal is not received. The output end of the transmission chain is used to output the aging vector to the test scan chain of the chip; The module under test is used to receive the refinement vector through the test scan link and run based on the refinement vector.

2. The chip according to claim 1, characterized in that, The module under test includes a counting module; the test scan chain includes at least one scan register and at least one second selector; the second selector includes a third input terminal, a fourth input terminal, a selection terminal, and an output terminal; the third input terminal is connected to the output terminal of the module under test; the fourth input terminal is connected to the output terminal of the transmission chain; the counting module is connected to the selection terminal; the input terminal of the scan register is connected to the output terminal of the second selector. The counting module is used for counting, and outputs a first selection signal when the count value reaches a first preset value; The second selector is configured to receive the output data of the module under test through the third input terminal and input the output data into the scan register when the first selection signal is received, and to receive the data to be transmitted of the test scan chain through the fourth input terminal and input the data to be transmitted of the test scan chain into the scan register when the first selection signal is not received.

3. The chip according to claim 2, characterized in that, After outputting the first selection signal, the counting module is also used to recount, and when the count value reaches the second preset value, it outputs a second selection signal; the second selection signal is different from the first selection signal.

4. The chip according to claim 2, characterized in that, The chip includes multiple modules under test; the test scan chain includes multiple second selectors and the scan register, and each second selector and each scan register are alternately connected in series to form the test scan chain; the input terminal of each module under test is connected to the output terminal of the test scan chain, and the output terminal of each module under test is connected to the input terminal of the test scan chain.

5. The chip according to claim 4, characterized in that, The output of each scan register is connected to the input of each module under test.

6. The chip according to claim 1, characterized in that, The number of data contained in the initial vector sequence is consistent with the number of registers in the transport chain; the initial vector sequence is determined based on a specified inversion rate.

7. The chip according to any one of claims 1-6, characterized in that, The module under test is the combinational logic circuit of the chip.

8. A chip testing method, characterized in that, The method is applied to a vector generation module in a chip, wherein the chip is the chip according to any one of claims 1 to 7, and the method includes: Upon receiving a trigger signal, an initial vector sequence is received and input into each register of the transmission chain; and if the trigger signal is not received, the vector to be transmitted is sequentially passed to each register of the transmission chain. An aging vector is generated based on the initial vector sequence or the vector to be transmitted, and the aging vector is transmitted to the test scan chain of the chip through the transmission chain. The module under test is used to receive the refinement vector through the test scan link and run based on the refinement vector.

9. An electronic device, characterized in that, The electronic device includes the chip according to any one of claims 1 to 7.

10. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the method of claim 8.

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