Hybrid ANPC three-level inverter PWM signal control method and system

Abstract

The invention provides a hybrid ANPC three-level inverter PWM signal control method and system. The method comprises the steps that S1, logic conditions are defined; s2, converting the logic condition and a control signal of an upper-layer control system into an input condition of a PWM signal control function block, judging whether the input condition meets the logic condition or not, and when all the input conditions meet the logic condition, outputting a PWM pulse signal corresponding to a corresponding insulated gate bipolar transistor (IGBT) device; and S3, the pulse signals are fed back to the PWM signal control function block as limiting conditions, the PWM signal control function block evaluates all the input conditions again according to the limiting conditions, and if the input conditions do not meet the logic conditions, the output pulse signals are adjusted until all the input conditions meet the logic conditions again. The IGBT device has the advantages of simple structure, high stability and the like, and the switching state of the IGBT device can be accurately controlled.

Description

Hybrid ANPC Three-Level Inverter PWM Signal Control Method and System Technical Field

[0001] This invention relates to the field of converter control technology, specifically to a PWM signal control method and system for a hybrid ANPC three-level inverter. Background Technology

[0002] With the development of power electronics technology, ANPC three-level inverters have been widely used in various high-power converter applications due to their high efficiency, high voltage utilization, and low harmonic distortion. In recent years, SiC (silicon carbide) semiconductor devices have become an important choice for ANPC three-level inverters due to their excellent high-temperature performance, high breakdown voltage, and high-speed switching characteristics. However, SiC devices are relatively expensive. To reduce costs while maintaining high performance, SiC&Si hybrid ANPC three-level inverters have become a research hotspot.

[0003] One of the main challenges in existing hybrid SiC (silicon carbide) and Si (silicon) ANPC (active neutral point clamped) three-level inverter technology is the switching timing control of IGBT (insulated gate bipolar transistor) devices. In this inverter structure, due to the use of devices made of different materials (Si IGBTs internally and SiC MOSFETs externally as external transistors and clamping transistors), there is a significant difference in switching speed: SiC devices typically switch faster than Si devices. This characteristic necessitates considering both the low-frequency signal requirements of the internal transistor (Si IGBT) and the high-frequency signal requirements of the external transistor and clamping transistor (SiC MOSFET) when designing the switching timing.

[0004] Therefore, the specific technical challenges of existing technologies include:

[0005] 1. How to accurately control the switching sequence of different materials and devices according to the commutation requirements of the inverter topology.

[0006] 2. How to monitor and provide feedback on the switching status of each device in real time to ensure stability during high-speed switching.

[0007] 3. How to avoid potential overvoltage or overcurrent caused by differences in switching speed during the switching process.

[0008] 4. How to overcome the control complexity caused by the performance differences between different components while ensuring system efficiency. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a simple and highly stable PWM signal control method and system for a hybrid ANPC three-level inverter, which can accurately control the switching state of IGBT devices.

[0010] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0011] A PWM signal control method for a hybrid ANPC three-level inverter includes:

[0012] Step S1: Define the logical conditions;

[0013] Define the logic conditions for turning on and off each Insulated Gate Bipolar Transistor (IGBT) device according to the inverter topology control requirements;

[0014] Step S2: Logical condition transformation and judgment;

[0015] The logic conditions and the control signals of the upper control system are converted into the input conditions of the PWM signal control function block, and it is determined whether the input conditions meet the logic conditions. When all input conditions meet the logic conditions, the corresponding PWM pulse signal of the insulated gate bipolar transistor (IGBT) device is output.

[0016] Step S3: Feedback and adjustment of the pulse signal;

[0017] The pulse signal is fed back as a constraint to the PWM signal control function block. The PWM signal control function block re-evaluates all input conditions based on the constraint. If any input condition does not meet the logic condition, the output pulse signal is adjusted until all input conditions meet the logic condition again.

[0018] As a further improvement to the method of the present invention: in step S1, the logic condition includes setting the switching timing of the insulated gate bipolar transistor (IGBT) device:

[0019] When starting the inverter: first turn on the clamping transistor, then turn on the inner transistor, and finally turn on the outer transistor;

[0020] When the inverter is shut down: first turn off the external tube, then turn off the internal tube or clamping tube.

[0021] As a further improvement to the method of the present invention: in step S1, the logical condition further includes:

[0022] Setting dead time: Setting the dead time between the clamping transistor and the outer transistor of the complementary insulated gate bipolar transistor (IGBT);

[0023] Set the minimum pulse width for the insulated gate bipolar transistor (IGBT) to turn on and off;

[0024] Setting interlock conditions includes: setting interlock conditions between the clamping tube and the outer tube, interlock conditions between the inner tube and the outer tube, and interlock conditions between the control signals of the upper control system and the states of each insulated gate bipolar transistor (IGBT) device.

[0025] As a further improvement to the method of the present invention: after setting the minimum pulse width for turn-on and turn-off, the turn-on or turn-off time of the insulated gate bipolar transistor (IGBT) device is calculated. If the turn-on / turn-off time is greater than or equal to the preset minimum turn-on / turn-off time requirement, the original pulse width is output; if the turn-on / turn-off time is less than the preset minimum turn-on / turn-off time requirement, the original pulse is widened to the set minimum turn-on / turn-off pulse width length.

[0026] As a further improvement to the method of the present invention: In step S2, the upper control system includes multiple original pulse signals, and one original pulse corresponds to two pulse signals of the insulated gate bipolar transistor (IGBT) device. When the pulse signals of the IGBT device simultaneously meet the control requirements of the original pulse signals and the switching timing requirements of the IGBT device, the corresponding PWM pulse signal is output.

[0027] As a further improvement to the method of the present invention: in step S3, the adjusted output pulse signal includes:

[0028] When the pulse signal is detected to be inconsistent with the minimum pulse width requirement, the PWM signal control function block adjusts the signal width.

[0029] When the pulse signal is detected to be inconsistent with the dead time requirement, the PWM signal control function block adjusts the signal turn-off time.

[0030] As a further improvement to the method of the present invention: in step S3, when the PWM signal control function block re-evaluates all input conditions, it also includes monitoring the state of other related insulated gate bipolar transistor (IGBT) devices to ensure that the state of all related devices meets the logic conditions.

[0031] The present invention further provides a hybrid ANPC three-level inverter PWM signal control system, including a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the hybrid ANPC three-level inverter PWM signal control method.

[0032] Compared with the prior art, the advantages of the present invention are as follows:

[0033] 1. This invention transforms the topology control requirements of a hybrid ANPC three-level inverter into logical conditions for controlling the turn-on and turn-off of each IGBT device, thereby controlling the PWM signal of each IGBT device to ensure accurate state switching strictly according to the topology requirements. This not only guarantees the absolute safety of IGBT device switching but also improves the stability and reliability of the system.

[0034] 2. This invention monitors the drive pulse signals of IGBT devices and mutually constrains the drive signals of each IGBT device with those of its associated IGBT devices. Simultaneously, it receives feedback signals from the IGBT devices and strictly controls the switching of the devices according to timing requirements to obtain the desired pulse signal output. Through this negative feedback control method, combined with upper-level input control signals, it achieves the switching timing control of IGBT devices in the inverter topology according to commutation requirements. Since the PWM signal of each IGBT device can be reliably controlled, the desired switching states and transitions are obtained, thereby improving the overall reliability, stability, and safety of the inverter control. Attached Figure Description

[0035] Figure 1 is a flowchart of the PWM signal control method for a hybrid ANPC three-level inverter according to an embodiment of the present invention.

[0036] Figure 2 is a schematic diagram of PWM signal control for a single IGBT device according to an embodiment of the present invention.

[0037] Figure 3 is a circuit topology diagram of the hybrid ANPC three-level inverter according to an embodiment of the present invention.

[0038] Figure 4 is a timing diagram of the switching states of the IGBT devices in the hybrid ANPC three-level inverter according to an embodiment of the present invention.

[0039] Figure 5 is a flowchart of the PWM signal control of the T1 IGBT device according to an embodiment of the present invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0041] As shown in Figure 1, this embodiment provides a PWM signal control method for a hybrid ANPC three-level inverter, including:

[0042] Step S1: Define the logical conditions;

[0043] Define the logic conditions for turning on and off each Insulated Gate Bipolar Transistor (IGBT) device according to the inverter topology control requirements.

[0044] In this embodiment, the logic conditions include setting the switching timing of the insulated gate bipolar transistor (IGBT) device:

[0045] When starting the inverter: first turn on the clamping transistor, then turn on the inner transistor, and finally turn on the outer transistor;

[0046] When the inverter is shut down: first turn off the external tube, then turn off the internal tube or clamping tube.

[0047] In this embodiment, the logical conditions also include:

[0048] Setting dead time: Setting the dead time between the clamping transistor and the outer transistor of the complementary insulated gate bipolar transistor (IGBT);

[0049] Set the minimum pulse width for the insulated gate bipolar transistor (IGBT) to turn on and off;

[0050] After setting the minimum pulse width for turn-on and turn-off, the turn-on or turn-off time of the insulated gate bipolar transistor (IGBT) device is calculated. If the turn-on / turn-off time is greater than or equal to the preset minimum turn-on / turn-off time requirement, the original pulse width is output; if the turn-on / turn-off time is less than the preset minimum turn-on / turn-off time requirement, the original pulse is widened to the set minimum turn-on / turn-off pulse width length.

[0051] Setting interlock conditions includes: setting interlock conditions between the clamping tube and the outer tube, interlock conditions between the inner tube and the outer tube, and interlock conditions between the control signals of the upper control system and the states of each insulated gate bipolar transistor (IGBT) device.

[0052] In this embodiment, the safe turn-on and turn-off of the Insulated Gate Bipolar Transistor (IGBT) device are achieved by using minimum turn-on and turn-off pulse widths. Specifically, the turn-on time is calculated when the rising edge of the signal arrives, or the turn-off time is calculated when the falling edge of the signal arrives. If the calculated turn-on or turn-off time is greater than or equal to the minimum pulse width time, the original pulse width is output. If the calculated turn-on or turn-off time is less than the minimum pulse width time, the original pulse is widened to the set minimum pulse width length before output, thereby meeting the output requirements of minimum turn-on / minimum turn-off pulse widths.

[0053] Step S2: Logical condition transformation and judgment;

[0054] The logic conditions and control signals from the upper-level control system are converted into PWM signals to control the input conditions of the function block. It is then determined whether the input conditions meet the logic conditions. When all input conditions meet the logic conditions, the corresponding PWM pulse signal of the insulated gate bipolar transistor (IGBT) is output.

[0055] In this embodiment, the upper-level control system includes multiple raw pulse signals, and one raw pulse corresponds to two pulse signals of the insulated gate bipolar transistor (IGBT) device. When the pulse signal of the IGBT device simultaneously meets the control requirements of the raw pulse signal and the switching timing requirements of the IGBT device, the corresponding PWM pulse signal is output.

[0056] In specific application embodiments, in the SiC&Si hybrid ANPC three-level inverter, the in-phase IGBTs are distinguished by whether they are SiC or Si devices. Taking the inverter topology as an example, the inner IGBT is a Si device, while the outer IGBT and clamping IGBT are SiC devices. Because the switching speed of Si devices is slower than that of SiC devices, and the inverter topology requires the inner IGBT pulse to be a low-frequency signal while the outer IGBT and clamping IGBT pulses are high-frequency signals, according to the topology state switching requirements, the six in-phase IGBT switches must satisfy the interlocking of the IGBT pulses while ensuring the switching sequence of the inner and outer IGBTs and clamping IGBTs in the same bridge arm. The operation is carried out according to the topology rules. Specifically, in the inverter topology, the pulse signals of the six IGBT devices in phase are three original pulse signals controlled by the upper control system. The pulse signals of the six IGBT devices are derived from the three original pulse signals. One original pulse corresponds to two device pulse signals. That is, the device pulse signals must not only meet the control requirements of the original pulses, but also meet the switching timing requirements of the internal and external transistors and the clamping transistors. The output of the device pulse signals is subject to the input of multiple conditions. When all input conditions are met at the same time, the corresponding turn-on or turn-off signal is output.

[0057] Step S3: Feedback and adjustment of the pulse signal;

[0058] The pulse signal is fed back as a constraint to the PWM signal control function block. The PWM signal control function block re-evaluates all input conditions based on the constraint. If any input condition does not meet the logic condition, the output pulse signal is adjusted until all input conditions meet the logic condition again.

[0059] In this embodiment, adjusting the output pulse signal includes:

[0060] When the pulse signal is detected to be inconsistent with the minimum pulse width requirement, the PWM signal control function block adjusts the signal width.

[0061] When the pulse signal is detected to be inconsistent with the dead time requirement, the PWM signal control function block adjusts the signal turn-off time.

[0062] In this embodiment, when re-evaluating all input conditions, the PWM signal control function block also includes monitoring the state of other related insulated gate bipolar transistor (IGBT) devices to ensure that the state of all related devices meets the logic conditions.

[0063] This embodiment uses a negative feedback control method to reliably control the PWM drive signals of each IGBT device. At the same time, it receives the pulse signal form fed back from the output terminal and continuously adjusts the pulse to obtain the final desired PWM signal form.

[0064] As shown in Figure 2, in this embodiment, for the PWM drive signal of a single IGBT device, the conditions for triggering its turn-on and turn-off include multiple input conditions. Through this timing negative feedback control method, the signal state can be switched under different input constraints.

[0065] As shown in Figure 3, this embodiment takes a hybrid ANPC three-level inverter as an example. The timing diagram of the IGBT device switching states is shown in Figure 4. T1 to T6 represent single-phase IGBT devices. T1 and T4 are external transistors, SiC devices, and transmit high-frequency signals. T2 and T3 are internal transistors, Si devices, and transmit low-frequency signals. T5 and T6 are clamping transistors, SiC devices, and transmit high-frequency signals. T1 and T5 are complementary and have a dead time; both are controlled by the same upper-level system control signal. T4 and T6 are complementary and have a dead time; both are controlled by the same upper-level system control signal. T2 and T3 are complementary but do not have a dead time; both are controlled by the same upper-level system control signal. When starting the inverter, the clamping transistors T5 / T6 must be turned on first, followed by the inner transistors T2 / T3, and finally the outer transistors T1 / T4. When shutting down, the outer transistors must be turned off first, followed by the inner transistors and the clamping transistors.

[0066] As shown in Figure 5, in this embodiment, taking transistor T1 in the inverter topology as an example, the PWM signal needs to meet the following input conditions for being turned on and off:

[0067] The input conditions for turning on the PWM signal of transistor T1 are:

[0068] 1) The turn-off time of tube T5 reaches the dead time and remains off (ensuring the dead time requirement between tubes T1 and T5);

[0069] 2) Pipe T2 has been turned on before pipe T1 and has reached the turn-on switching time and continues to be turned on (the inner pipe is turned on before the outer pipe, and this switching time can be adjusted).

[0070] 3) Keep T4 tube off;

[0071] 4) The upper-level control system signal S1 is in the ON state;

[0072] 5) The turn-off pulse width of the PWM signal of transistor T1 is greater than or equal to the minimum turn-off pulse width (ensuring the minimum turn-off pulse width requirement of transistor T1).

[0073] Only when all five conditions mentioned above are met can the turn-on signal of transistor T1 be finally output.

[0074] The input condition for turning off the PWM signal of transistor T1 is:

[0075] 1) T5 tube has been turned off and the turn-off time has reached the dead time and it remains turned off (ensuring the dead time requirement between T1 and T5);

[0076] 2) Pipe T2 is open and remains open (ensuring the inner pipe is shut off later than the outer pipe);

[0077] 3) Keep T4 tube off;

[0078] 4) The upper-level control system signal S1 is in the off state;

[0079] 5) The turn-on pulse width of the PWM signal of transistor T1 is greater than or equal to the minimum turn-on pulse width (ensuring the minimum turn-on pulse width requirement of transistor T1).

[0080] Only when all five conditions mentioned above are met can the turn-off signal of transistor T1 be finally output.

[0081] In this embodiment, the negative feedback control process for the pulse signal is implemented through FPGA software to control the PWM signal of the IGBT device. Similarly, the switching of other IGBT states is also controlled using the above method. This embodiment can achieve PWM signal control of the IGBT under various operating conditions through the negative feedback control method, and strictly follows the circuit topology requirements to switch the device drive signal state, ensuring the absolute safety of the IGBT device switching. It is applicable to various control conditions of hybrid ANPC three-level inverters and has strong applicability. Regardless of whether it is an inverter topology or a four-quadrant topology, this method can be used to achieve precise control of the IGBT device switching state.

[0082] This embodiment also provides a hybrid ANPC three-level inverter PWM signal control system, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute a hybrid ANPC three-level inverter PWM signal control method.

[0083] This embodiment further provides a computer device, including a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to execute the computer program to perform the method described above.

[0084] It is understood that the method described in this embodiment can be executed by a single device, such as a computer or server, or it can be applied to a distributed scenario where multiple devices cooperate to complete the task. In a distributed scenario, one of the multiple devices may execute only one or more steps of the method described in this embodiment, and the multiple devices interact to complete the method. The processor can be implemented using a general-purpose CPU, microprocessor, application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the method described in this embodiment. The memory can be implemented using read-only memory (ROM), random access memory (RAM), static storage devices, and dynamic storage devices. The memory can store the operating system and other applications. When the method described in this embodiment is implemented through software or firmware, the relevant program code is stored in the memory and called and executed by the processor.

[0085] This embodiment further provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method described above.

[0086] Those skilled in the art will understand that the above embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams. These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams, whereby the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams. The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

[0087] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A PWM signal control method for a hybrid ANPC three-level inverter, characterized in that, include: Step S1: Define logic conditions; define the turn-on and turn-off logic conditions for each Insulated Gate Bipolar Transistor (IGBT) device according to the inverter topology control requirements; Step S2: Logic condition conversion and judgment; The logic conditions and the control signals of the upper-level control system are converted into input conditions for the PWM signal control function block, and it is judged whether the input conditions satisfy the logic conditions. When all input conditions satisfy the logic conditions, the corresponding PWM pulse signal of the insulated gate bipolar transistor (IGBT) is output. Step S3: Pulse signal feedback and adjustment; The PWM pulse signal is fed back to the PWM signal control function block as a constraint condition. The PWM signal control function block re-evaluates all input conditions according to the constraint condition. If there is an input condition that does not satisfy the logic conditions, the output pulse signal is adjusted until all input conditions satisfy the logic conditions again.

2. The PWM signal control method for a hybrid ANPC three-level inverter according to claim 1, characterized in that, In step S1, the logic condition includes setting the switching sequence of the insulated gate bipolar transistor (IGBT) device: when the inverter starts up: first turn on the clamping transistor, then turn on the inner transistor, and finally turn on the outer transistor; when the inverter stops: first turn off the outer transistor, and then turn off the inner transistor or the clamping transistor.

3. The PWM signal control method for a hybrid ANPC three-level inverter according to claim 1, characterized in that, In step S1, the logic conditions further include: setting a dead time: setting a dead time between the clamping transistor and the complementary insulated gate bipolar transistor (IGBT) of the outer transistor; setting the minimum pulse width when the IGBT is turned on and off; setting interlocking conditions, including setting interlocking conditions between the clamping transistor and the outer transistor, between the inner transistor and the outer transistor, and between the control signal of the upper control system and the state of each IGBT device.

4. The PWM signal control method for a hybrid ANPC three-level inverter according to claim 3, characterized in that, After setting the minimum pulse width for turn-on and turn-off, the turn-on or turn-off time of the insulated gate bipolar transistor (IGBT) device is calculated. If the turn-on / turn-off time is greater than or equal to the preset minimum turn-on / turn-off time requirement, the original pulse width is output. If the turn-on / turn-off time is less than the preset minimum turn-on / turn-off time requirement, the original pulse will be widened to the set minimum turn-on / turn-off pulse width length.

5. The PWM signal control method for a hybrid ANPC three-level inverter according to claim 1, characterized in that, In step S2, the upper-level control system includes multiple raw pulse signals, and one raw pulse corresponds to two pulse signals of the insulated gate bipolar transistor (IGBT) device. When the pulse signal of the IGBT device simultaneously meets the control requirements of the raw pulse signal and the switching timing requirements of the IGBT device, the corresponding PWM pulse signal is output.

6. The PWM signal control method for a hybrid ANPC three-level inverter according to claim 1, characterized in that, In step S3, adjusting the output pulse signal includes: when the pulse signal is detected to be inconsistent with the minimum pulse width requirement, the PWM signal control function block adjusts the signal width; when the pulse signal is detected to be inconsistent with the dead time requirement, the PWM signal control function block adjusts the signal turn-off time.

7. The PWM signal control method for a hybrid ANPC three-level inverter according to claim 1, characterized in that, In step S3, when the PWM signal control function block re-evaluates all input conditions, it also monitors the state of other related insulated gate bipolar transistor (IGBT) devices to ensure that the state of all related devices meets the logic conditions.

8. A hybrid ANPC three-level inverter PWM signal control system, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to execute the PWM signal control method for the hybrid ANPC three-level inverter according to any one of claims 1 to 7.

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