Inductor architecture, LC resonant circuit and electronic circuit

Abstract

The invention provides an inductor framework, an LC resonance circuit and an electronic circuit. The inductor architecture is applied to an LC resonance circuit, and comprises a first inductor and a second inductor, the structures of which are respectively configured to generate magnetic fluxes in opposite directions when a current passes through the first inductor and the second inductor; and a third inductor configured to be arranged around the first inductor and the second inductor when viewed in a direction perpendicular to the plane of the first inductor, wherein the first inductor and the second inductor are respectively a first tail inductor and a second tail inductor of the LC resonance circuit, and the third inductor is a main inductor of the LC resonance circuit. Through reasonable design of the inductor layout, the tail resonance network of the LC resonance circuit can work under the condition of adjacent arrangement without remarkably influencing the main resonance circuit, so that the performance of the LC resonance circuit is improved, and meanwhile, high integration level and low area occupation are kept.

Description

Technical Field

[0001] This disclosure relates to the fields of integrated circuits and radio frequency circuits, and more specifically, to inductor architectures, LC resonant circuits, and electronic circuits. Background Technology

[0002] In the fields of integrated circuit (IC) and radio frequency (RF) technology, LC resonant circuits, as an important basic circuit structure, are widely used in various electronic circuits such as filters, oscillators, matching networks, and signal tuning. LC resonant circuits are typically composed of an inductor (L) and a capacitor (C), and achieve the selection or suppression of signals at specific frequencies through resonant characteristics, thus playing an irreplaceable role in high-frequency and radio frequency applications.

[0003] In some LC resonant circuit designs, especially on-chip integrated RF circuits, it is often necessary to set up main inductors and tail inductors to meet different resonance requirements or to realize multi-stage resonant structures. However, due to the limited area of ​​integrated circuit chips, inductors usually occupy a large layout space. How to rationally arrange the main inductors and tail inductors within a limited area becomes a key design issue.

[0004] More importantly, electromagnetic coupling exists between inductors. If the layout is not reasonable, the mutual inductance between the main inductor and the tail inductor can lead to resonant frequency shift, decreased quality factor, and even affect the performance stability of the entire circuit. Therefore, optimizing inductor layout and reducing interference between inductors while ensuring circuit performance is a significant technical challenge facing current RF integrated circuit design. Summary of the Invention

[0005] The purpose of this disclosure is to provide a solution that addresses at least one or more of the above-mentioned or other problems. As a non-limiting example, the purpose of this disclosure includes providing an inductor architecture in which, through a rational design of the inductor layout, the tail resonant network of an LC resonant circuit can operate in close proximity without significantly affecting the main resonant circuit, thereby simultaneously achieving stable start-up, low power consumption, good phase noise performance, high integration, and low footprint under low supply voltage conditions.

[0006] In a first aspect of this disclosure, an inductor architecture is provided for use in an LC resonant circuit. The inductor architecture includes: a first inductor and a second inductor, respectively configured to generate magnetic fluxes in opposite directions when current flows through them; and a third inductor, viewed along a direction perpendicular to the plane of the first inductor, configured to surround the first inductor and the second inductor; wherein the first inductor and the second inductor are respectively the first tail inductor and the second tail inductor of the LC resonant circuit, and the third inductor is the main inductor of the LC resonant circuit.

[0007] Optionally, in some examples, the first inductor and the second inductor may each be configured to have an even number of loops, wherein half of the loops are arranged axially or centrally symmetrically with the other half of the loops, and the half of the loops have opposite magnetic flux directions to the other half of the loops.

[0008] Optionally, in some examples, the first inductor and the second inductor may be figure-eight inductors.

[0009] Optionally, in some examples, the first inductor, the second inductor, and the third inductor may be single-turn inductors or multi-turn inductors.

[0010] Optionally, in some examples, the third inductor may be a toroidal inductor.

[0011] Optionally, in some examples, the first inductor and the second inductor may have the same shape and size.

[0012] Optionally, in some examples, the first inductor and the second inductor may have the same shape, and the size of the first inductor may be larger than the size of the second inductor.

[0013] Optionally, in some examples, two of the first inductor, the second inductor, and the third inductor may be arranged in the same metal layer, the other of the first inductor, the second inductor, and the third inductor may be arranged in another metal layer, and the first inductor and the second inductor may be arranged in different metal layers.

[0014] Optionally, in some examples, the first inductor, the second inductor, and the third inductor may be arranged in three adjacent metal layers, and the third inductor may be arranged in the metal layer between the first inductor and the second inductor.

[0015] Optionally, in some examples, the first inductor and the second inductor may have the same current direction during oscillating operation.

[0016] In a second aspect of this disclosure, an LC resonant circuit is provided, comprising: a main resonant circuit configured to include a main inductor and a tunable capacitor; a power supply path configured to include a power supply path and a ground return path; and a tail resonant network disposed in the power supply path of the LC tuning circuit, wherein the tail resonant network includes a first tail inductor connected in series in the power supply path, a second tail inductor connected in series in the ground return path, and a capacitor array connected in parallel between the power supply path and the ground return path; wherein the main inductor, the first tail inductor, and the second tail inductor are configured to have an inductor architecture according to this disclosure.

[0017] Optionally, in some examples, the capacitor array may be a tunable capacitor array and may be configured to adjust the secondary resonant frequency of the tail resonant network.

[0018] Optionally, in some examples, the tunable capacitor array can be configured to be operable such that the secondary resonant point of the tail resonant network is located in a higher-order resonant range above the main oscillation frequency of the main resonant circuit, and covers a frequency range that includes the higher harmonics corresponding to the main oscillation frequency.

[0019] Optionally, in some examples, the tunable capacitor array can be configured to be operable such that the secondary resonant point of the tail resonant network is close to the second harmonic band of the main resonant circuit's main oscillation frequency.

[0020] In a third aspect of this disclosure, an electronic circuit is provided, including an LC resonant circuit according to this disclosure.

[0021] By way of example and not limitation, the advantages provided by this disclosure may include one or more of the following advantages and / or other advantages: 1) By rationally designing the inductor architecture, the tail resonant network can be arranged close to the main resonant circuit without increasing the arrangement spacing, thereby improving the circuit integration within a limited chip area; 2) By ensuring that the two tail inductors in the LC resonant circuit carry currents in the same direction during operation, their magnetic flux coupling directions are aligned, thereby creating a positive mutual inductance between them, which improves the equivalent quality factor of the tail resonant network near its secondary resonance point; and 3) The high equivalent quality factor obtained by the tail resonant network near its secondary resonant point effectively avoids the decrease in quality factor caused by too many inductor turns, thus optimizing inductor performance.

[0022] It should be understood that the technical problems and advantages listed above are merely examples and not limitations of this disclosure. Furthermore, this disclosure is not limited to technical solutions that simultaneously solve all of the above-mentioned technical problems; the technical solutions of this disclosure can be implemented to solve one or more of the above-mentioned or other technical problems, and to provide one or more of the above-mentioned or other advantages. Attached Figure Description

[0023] Figure 1 A schematic circuit diagram of the electronic circuitry of a voltage-controlled oscillator according to the prior art is shown. Figure 2 A schematic diagram of an inductor architecture according to an embodiment of the present disclosure is shown, wherein the magnetic field and current distribution of the main resonant circuit and the adjacent resonant structure are schematically illustrated; Figure 3 A schematic perspective view showing the spatial layout of an inductor architecture according to an embodiment of the present disclosure; Figure 4 A schematic planar layout of an inductor architecture according to an embodiment of the present disclosure is shown; Figure 5 A schematic planar layout of an inductor architecture according to another embodiment of the present disclosure is shown; Figure 6 A schematic planar layout of an inductor architecture according to yet another embodiment of the present disclosure is shown; and Figure 7 A schematic planar layout of an inductor architecture according to another embodiment of the present disclosure is shown. Detailed Implementation

[0024] The present disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments shown in the drawings and described below are merely illustrative and are not intended to limit the present disclosure.

[0025] In the context of this disclosure, unless otherwise specifically stated, ordinal numbers such as "first," "second," etc., are used only to distinguish different elements and not to specify their order.

[0026] Unless otherwise provided, the terminology used in this disclosure shall be interpreted in accordance with the meaning commonly understood by those skilled in the art. The terminology referenced in this disclosure is for the purpose of illustrating the technical solutions only and shall not be construed as limiting the scope of this disclosure.

[0027] Unless otherwise expressly stated, the singular form includes the plural form, and terms such as "comprising" or "including" should be understood as open-ended expressions, including but not limited to the listed elements or steps. Those skilled in the art can reasonably interpret the terms based on the context, and the specific embodiments in the specification should not be construed as the sole limitation of the technical solutions disclosed herein.

[0028] The technical features mentioned in this disclosure can be combined arbitrarily among different embodiments, unless such combinations are technically unrealizable or expressly incompatible with this disclosure.

[0029] In low-power wireless communication and highly integrated SoC products, the LC resonant circuit in the voltage-controlled oscillator typically operates under a low-voltage power supply provided by an on-chip or off-chip DC-DC converter. To reduce system power consumption and minimize power supply noise coupling paths, the supply voltage of the LC resonant circuit is often compressed to approximately 0.4V in engineering.

[0030] Complementary cross-coupled CMOS voltage-controlled oscillators (VCOs) are widely used in engineering due to their current multiplexing characteristics. However, under low supply voltage conditions, the oscillator's start-up margin and oscillation swing are significantly reduced, and it is difficult to introduce common-mode rejection structures such as resistors or current mirrors. This makes it easier for the noise of transconductance devices to upconvert to near the carrier frequency during oscillation, thus degrading phase noise performance. At the same time, the supply ripple and spurious signals introduced by the DC-DC converter are more likely to couple to the oscillation circuit through the supply path, adversely affecting system performance.

[0031] To address these issues, a tail resonant network is typically introduced into the oscillator power supply path in engineering practice to increase the oscillation swing and suppress noise during up-conversion under low supply voltage conditions. However, in highly integrated designs, the tail resonant network often needs to be placed close to the main resonant circuit to save chip area. In this case, the interaction between the main resonant circuit and the tail resonant network becomes unavoidable, potentially causing a shift in the equivalent parameters of the main resonant circuit and a decrease in oscillation stability. Traditional solutions typically mitigate this effect by increasing the placement distance between the main resonant circuit and the tail resonant network, but this significantly increases the chip area, hindering the realization of low-cost products.

[0032] Therefore, ensuring that the influence of the tail resonant network on the main resonant circuit is controlled without increasing the spacing between the components is a key engineering problem in the design of low-voltage voltage-controlled oscillators.

[0033] Figure 1 A schematic circuit diagram of the electronic circuitry of a voltage-controlled oscillator according to the prior art is shown.

[0034] Overall, Figure 1 The voltage-controlled oscillator shown mainly consists of three parts: 1) A complementary cross-coupled active transconductance unit, wherein the transconductance unit is composed of an NMOS transistor 134 and a PMOS transistor 136; 2) Main resonant circuit 106, the main resonant circuit including main inductor 110 and tunable capacitor 112, used to determine the operating frequency of the oscillator; and 3) A tail resonant network 108 is provided in the power supply path of the oscillator. The tail resonant network 108 includes a first tail inductor 120, a second tail inductor 122 and a capacitor array 124 connected thereto.

[0035] Specifically, such as Figure 1As shown, the electronic circuit is an LC resonant circuit 100. The LC resonant circuit 100 includes a first resonant region 102 and a second resonant region 104. The first resonant region includes a first resonant circuit 106 (also referred to as the "main resonant circuit") and a first coupling transistor 134 and a second coupling transistor 136 cross-coupled with the first resonant circuit 106. In one example, the first coupling transistor 134 can be implemented as an N-type coupling transistor (which can be represented as coupling transistor Mn), and the second coupling transistor 136 can be implemented as a P-type coupling transistor (which can be represented as coupling transistor Mp).

[0036] In the first resonant region 102, the first resonant circuit 106 may include a main inductor 110 (which may be represented as a main inductor Lm), a tunable capacitor 112 (which may be represented as a variable capacitor Cv) and a fixed capacitor 114 (which may be represented as a fixed capacitor Cm) connected in parallel.

[0037] The second resonant region 104 includes a second resonant circuit 108 (also referred to as a "tail resonant network"). The second resonant circuit 108 may include a first branch 116 (also referred to as a "power supply path") electrically connected to the first coupling tube 134 and a second branch 118 (also referred to as a "ground return path") electrically connected to the second coupling tube 136. A first tail inductor 120 (which may be represented as tail inductor Ln) is connected in series in the first branch 116, and a second tail inductor (which may be represented as tail inductor Lp) is connected in series in the second branch 118.

[0038] The second resonant circuit 108 further includes a differential capacitor array 124 (which may be represented as a capacitor array Ct) connected in parallel between the first branch 116 and the second branch 118. Optionally, the second resonant circuit 108 may also include a decoupling capacitor 126 (which may be represented as a decoupling capacitor Cd) connected in parallel between the first branch 116 and the second branch 118.

[0039] exist Figure 1 In the example shown, the first resonant region constitutes the main resonant cavity of the voltage-controlled oscillator, responsible for continuously adjusting the clock frequency and providing it to the system. The second resonant region is used to suppress common-mode noise in the first resonant region, utilizing the high impedance generated by resonance to prevent common-mode noise backflow.

[0040] In some examples, the second resonant region provides a unique circuit structure, such as connecting the power supply tail inductor path and the ground tail inductor path through a set of capacitor arrays, near the common source node of the coupled transistors Mn and Mp. Generally, the first resonant region undergoes frequency calibration using software or hardware algorithms to compensate for deviations in the chip's capacitance during mass production; the calibrated control word then maps to the deviation value of the chip's capacitance. The second resonant region, linked to the capacitor array control word of the first resonant region, can change the resonant frequencies of the tail inductors Lp and Ln by adjusting the control word of the tail inductor differential capacitor array Ct, thereby widening the resonant frequency range and effectively suppressing common-mode noise across the entire frequency band.

[0041] In some examples, such as Figure 1 As shown, the differential capacitor array 124 can be arranged near the common source node of the first coupling tube 134 and the second coupling tube 136.

[0042] In some examples, a first tail inductor 120 is arranged on a first branch 116 between a differential capacitor array 124 and a decoupling capacitor 126, and a second tail inductor 122 is arranged on a second branch 118 between a differential capacitor array 124 and a decoupling capacitor 126.

[0043] In some examples, the differential capacitor array 124 includes multiple branches 128a, 128b, etc., connected in parallel between the first branch 116 and the second branch 118, wherein each branch includes at least one switch and at least one capacitor. Figure 1 As shown, branch 128a includes a switch 132 and two capacitors 130.

[0044] In some examples, each of the multiple branches may include at least one of a single NMOS transistor and a single-sided MOM capacitor, a single PMOS transistor and a single-sided MOM capacitor, a single NMOS transistor and a double-sided MOM capacitor, or a single PMOS transistor and a double-sided MOM capacitor.

[0045] In some examples, the coupling coefficient between the first tail inductor 120 and the second tail inductor 122 is configured to be adjusted between 0 and 1 according to the capacitance value of the differential capacitor array 124.

[0046] In some examples, the coupling coefficient between the tail inductors Lp and Ln can be determined based on the system environment and design goals to suppress common-mode noise between the power supply and ground sides through magnetic coupling. Furthermore, the power supply can be provided by an on-chip LDO or an off-chip LDO, and the decoupling capacitor can be a high-Q capacitor to ensure a current loop between the power supply and ground while suppressing the effects of additional parasitic inductance, thus ensuring the accurate resonant frequency of the second resonant region.

[0047] In some examples, the first branch 116 is connected to the power supply, and the second branch 118 is grounded.

[0048] It should be understood that the first resonant circuit may have a PMOS structure, an NMOS structure, a CMOS structure, or other structures.

[0049] In some examples, the LC resonant circuit 100 employs a differential capacitor array placed between the power supply tail inductor path and the ground tail inductor path, near the common source node of the differential coupling transistor of the voltage-controlled oscillator. The two sets of tail inductors can be configured to have a certain coupling coefficient. By adjusting the capacitance value of the differential capacitor array, the second resonant frequency can be adjusted so that the secondary resonant point of the tail resonant network is located in a higher-order resonant range than the main oscillation frequency of the main resonant circuit, covering a frequency range including the higher harmonics corresponding to the main oscillation frequency. In some embodiments, the second resonant frequency can be adjusted to approximately 2 or 4 times the main resonant frequency. Compared to the scheme using two sets of single-ended capacitor arrays, using a differential capacitor array simplifies the process to using only one set of switches and only half the capacitor area. By reducing the parasitic capacitance and resistance of the array, not only is the adjustment range of the second resonant frequency expanded, but the Q value of the second resonant cavity is also improved. Furthermore, this design is easy to implement in a layout, significantly improving area utilization.

[0050] In different application scenarios, the LC resonant circuit 100 can use PMOS, NMOS or CMOS structures as the core architecture of the voltage-controlled oscillator.

[0051] As a non-limiting example of an LC resonant circuit in a voltage-controlled oscillator, reference may be made to, for example, Chinese Patent Publication CN119921682A, the entire text of which is incorporated herein by reference.

[0052] On the other hand, in radio frequency power amplifiers (PAs), LC resonant circuits are typically used in the output matching network to achieve high efficiency and good linearity. However, due to the limited area of ​​integrated circuits, the layout and parasitic effects of on-chip inductors can significantly affect the resonant frequency accuracy and quality factor, thereby impacting the gain and efficiency of the power amplifier. Furthermore, electromagnetic coupling between inductors can lead to resonant offset and increased losses, degrading system performance. Therefore, optimizing the layout of LC resonant circuits within a limited area, reducing parasitic effects, and improving the quality factor is a significant technical challenge in power amplifier design.

[0053] On the other hand, in low-noise amplifiers (LNAs), LC resonant circuits are typically used for input or output matching to achieve low noise figures and high gain. The accuracy and quality factor of the resonant frequency directly affect the noise performance and bandwidth of the LNA. However, parasitic resistance and improper placement of on-chip inductors can lead to increased insertion losses, deteriorated noise figures, and even affected linearity. Furthermore, inductors occupy a large area; achieving high integration while maintaining performance is a key challenge in LNA design.

[0054] In view of the multiple technical challenges in the prior art, the inventors of this application propose an improved inductor architecture, LC resonant circuit, and electronic circuit to solve one or more of the above-mentioned or other technical problems.

[0055] Figure 2 A schematic diagram of an inductor architecture 200 according to an embodiment of the present disclosure is shown, wherein the magnetic field and current distribution of the main resonant circuit and the adjacent resonant structure are schematically shown. Figure 2 The inductor architecture shown is applied to an LC resonant circuit. The following uses... Figure 1 The embodiments of this disclosure are illustrated using the LC resonant circuit shown as an example. However, those skilled in the art should understand that the implementation of this disclosure is not limited thereto, and the inductor architecture of this disclosure can be applied to different LC resonant circuits without departing from the principles of this disclosure.

[0056] like Figure 2 As shown, the inductor architecture 200 includes a first inductor 204 and a second inductor 206, respectively configured to generate magnetic fluxes in opposite directions when current flows through them. The inductor architecture 200 also includes a third inductor 202. Viewed along a direction perpendicular to the plane of the first inductor 204, the third inductor 202 is configured to surround the first inductor 204 and the second inductor 206. In embodiments of this disclosure, the first inductor 204 and the second inductor 206 are respectively the first tail inductor and the second tail inductor of an LC resonant circuit, and the third inductor 202 is the main inductor of the LC resonant circuit. As a non-limiting example, the third inductor 202 could be... Figure 1The LC resonant circuit 100 shown has a main inductor 110, while the first inductor 204 and the second inductor 206 can be the first tail inductor 120 and the second tail inductor 122 of the LC resonant circuit 100, respectively. In this manner, the present disclosure provides a compact inductor layout, allowing the main inductor and tail inductor to be arranged adjacent to each other within a limited chip area, while significantly reducing electromagnetic coupling effects between inductors and minimizing resonant frequency shift and quality factor degradation caused by mutual inductance. Through this layout design, the tail resonant network can maintain independent resonant characteristics even when close to the main resonant circuit, without significantly interfering with the main resonant circuit. In the context of this disclosure, the terms "third inductor" and "main inductor" are used interchangeably, as are the terms "first inductor," "second inductor," and "tail inductor."

[0057] In some embodiments, the first inductor 204 and the second inductor 206 are each configured to have an even number of loops, wherein half of the loops are arranged axially or centrally symmetrically with the other half of the loops, and the half of the loops have opposite magnetic flux directions to the other half of the loops. In this way, by customizing the tail inductor structure, the magnetic flux generated by the tail inductor when energized can be at least partially canceled, preferably substantially canceled, so that the equivalent magnetic field of the tail resonant network in the LC resonant circuit forms a mutually canceling distribution characteristic in space during oscillation operation, thereby reducing the impact on its adjacent resonant structures.

[0058] In some embodiments, the first inductor 204 and the second inductor 206 can be figure-eight inductors. In this way, the tail inductor can employ a symmetrical arrangement of at least two inductor sub-circuits in a figure-eight shape, such that their magnetic flux directions are opposite in the operating state to achieve a distribution characteristic of mutually canceling magnetic fields. For example... Figure 2 As shown, the magnetic flux directions of loops 202a and 202b in the first inductor 204 are opposite, and similarly, the magnetic flux directions of the two loops (unlabeled) in the second inductor 206 are also opposite. Therefore, the influence of their magnetic fields on the tail inductor can be minimized. It should be understood that the tail inductor of this disclosure is not limited to a figure-eight structure, and can adopt an equivalent magnetic field symmetry structure or a geometric structure with magnetic field symmetry cancellation characteristics, without departing from the scope of this disclosure.

[0059] In some embodiments, when viewed along a direction perpendicular to the plane of the first inductor 204, the third inductor 202 is arranged in a surrounding manner outside the first inductor 204 and the second inductor 206. This surrounding arrangement makes the third inductor 202 substantially symmetrical in spatial position with respect to the individual loops (e.g., loops 202a and 202b) of the first inductor 204, and when viewed along a direction perpendicular to the plane of the first inductor 204, the third inductor 202 does not pass through the first inductor 204. Therefore, the magnetic field coupling effect of the third inductor 202 on the individual loops of the first inductor 204 is substantially consistent in direction and intensity, thereby causing its overall equivalent magnetic field effect on the first inductor 204 to cancel each other out or significantly weaken. The magnetic field coupling relationship of the third inductor 202 to the second inductor 206 is similar to that of the first inductor 204, and will not be described again here.

[0060] In some embodiments, the current directions of the first inductor 204 and the second inductor 206 may be consistent during oscillation operation. For example... Figure 1 As shown, arrows A1, A2, A3, A4, and A5 indicate the current direction from the input terminal 214 to the output terminal 216 of the first inductor 204 at a certain moment during the oscillating operation. Arrows B1, B2, B3, B4, and B5 indicate the current direction from the input terminal 218 to the output terminal 220 of the second inductor 206 at the same moment during the oscillating operation.

[0061] In this way, the current directions of the first inductor 204 and the second inductor 206 are aligned during oscillating operation, and a controlled positive mutual inductance is formed by controlling this current direction. The resulting positive mutual inductance can improve the equivalent quality factor of the tail resonant network near its secondary resonant point without adding additional inductor components or significantly increasing the inductor area. It should be understood that the controlled positive mutual inductance causes the magnetic fields of the two tail inductors to mutually reinforce each other, increasing the equivalent inductance value of the tail resonant network, thereby improving the energy storage capacity and quality factor (Q value) of the resonant circuit without increasing the area.

[0062] In some embodiments, the third inductor 202 may be a toroidal inductor. Those skilled in the art will understand that a toroidal inductor may include, but is not limited to, a ring, a polygon, or other irregular shapes, and these variations should not be construed as departing from the scope of this disclosure.

[0063] In some embodiments, the positive mutual inductance is formed by aligning the winding direction of the first inductor 204 and the second inductor 206 and arranging them opposite each other so that their magnetic flux coupling directions are the same.

[0064] like Figure 2As shown, by designing the tail inductor geometry (figure-eight shape), the tail resonant network can exhibit a distribution characteristic where the equivalent magnetic fields cancel each other out in space during operation, thereby reducing its magnetic coupling sensitivity with adjacent structures. Figure 2 In the layout shown, the main inductor is located outside the tail inductor, and its equivalent quality factor dominates the overall oscillation performance. Therefore, there is no need to adopt an 8-shaped layout, thus avoiding the negative impact of the 8-shaped structure on the equivalent quality factor.

[0065] In addition, such as Figure 2 As shown, by placing the main inductor around the two tail inductors, a compact structure can be achieved within a limited space, reducing circuit area footprint and making it suitable for miniaturization design requirements. In practice, the position of the main inductor is relatively fixed, while the position of the tail inductors is more flexible. Therefore, the tail inductors can be arranged within the area surrounded by the main inductor, thus achieving a compact layout without increasing the chip area.

[0066] Meanwhile, the enclosed structure reduces electromagnetic leakage from the tail inductor. Compared to the main inductor, the tail inductor is more prone to frequency conflicts with other RF devices during operation. By designing the tail inductor into an 8-shaped structure, partial magnetic field cancellation can be achieved, thereby reducing the radiation effect of the tail inductor itself. Furthermore, placing the tail inductor within the enclosed area of ​​the main inductor enhances the isolation effect from external devices, reduces the mutual influence between the tail inductor and external circuits, and achieves better electromagnetic compatibility and system stability. Those skilled in the art should understand that various modifications, substitutions, and improvements can be made based on this disclosure without departing from the spirit and scope of protection of this disclosure. For example, the shape, size, material, arrangement, and circuit connection method of the inductor can be adjusted according to specific application requirements; the parameters of the resonant network can also be optimized through different design methods. These modifications and improvements should all be considered to fall within the scope of protection of this disclosure.

[0067] Figure 3 A schematic perspective view showing the spatial layout of an inductor architecture 300 according to an embodiment of the present disclosure is provided. Figure 3 In the example shown, the first inductor 304, the third inductor 302, and the second inductor 306 can be arranged in three adjacent metal layers P1, P2, and P3, and the third inductor 302 can be arranged in the metal layer P2 between the first inductor 304 and the second inductor 306.

[0068] In this way, the vertical spacing between different metal layers weakens the magnetic field coupling between the main inductor and the tail inductor, reducing the planar coupling effect between inductors and minimizing the impact of mutual inductance on the resonant frequency and Q value. Furthermore, by utilizing the vertical space, multiple inductors can be compactly arranged within a limited chip area without needing to be spaced apart on the same plane. Moreover, with the main inductor located in the middle layer and the tail inductors on the upper and lower layers, the magnetic field distribution is more balanced, helping to reduce interference to surrounding circuits. Layered arrangement reduces the direct metal proximity area between inductors, lowers parasitic capacitance, and improves high-frequency performance.

[0069] In some embodiments, two of the first inductor 304, the second inductor 306, and the third inductor 302 are arranged in the same metal layer, the other of the first inductor 304, the second inductor 306, and the third inductor 302 is arranged in another metal layer, and the first inductor 304 and the second inductor 306 are arranged in different metal layers. This approach provides a more flexible process implementation for the inductor architecture of this disclosure.

[0070] like Figure 3 As shown, when the tail inductance in the tail resonant network is set to cancel each other out, other resonant or power supply related structures can be arranged around it without significantly affecting the equivalent parameters of the tail resonant network.

[0071] Figures 4 to 7 Various planar layouts of the inductor architecture of this disclosure are shown in different embodiments.

[0072] Figure 4 A schematic planar layout of an inductor architecture 400 according to an embodiment of the present disclosure is shown.

[0073] exist Figure 4 In the illustrated embodiment, the first inductor (i.e., the tail inductor) 404 is a single-turn inductor. Specifically, the first inductor 404 is a figure-eight shaped inductor composed of a single-turn conductor and including a first loop 404a and a second loop 404b. Figure 4 As shown, the first loop 404a and the second loop 404b have opposite magnetic flux directions.

[0074] exist Figure 4 In the illustrated embodiment, the first inductor 404 and the second inductor (not shown) can have the same shape and size. Therefore, from... Figure 4 Viewed from the perspective of the planar layout diagram, the second inductor is located below the first inductor 404 and is completely blocked by the first inductor 404, thus not being in the... Figure 4 As shown in the diagram, the first inductor 404 and the second inductor (not shown) are connected to the capacitor array 408.

[0075] In some embodiments, the dimensions of the first inductor and the second inductor may also be different.

[0076] Figure 5 A schematic planar layout of an inductor architecture 500 according to yet another embodiment of the present disclosure is shown.

[0077] exist Figure 5 In the illustrated embodiment, the first inductor (i.e., the tail inductor) 504 is a multi-turn inductor. For example... Figure 5 As shown, the first inductor 504 has two turns of trace to form nested first loop 504a and second loop 504b, as well as nested third loop 504c and fourth loop 504d. In this way, a larger inductance value can be provided for the tail inductor within the same area. Those skilled in the art will understand that, although... Figure 5 The first inductor 504 shown is a two-turn inductor, but embodiments of this disclosure are not limited to this. Depending on the application scenario and engineering requirements, more or fewer than two turns of the tail inductor can be selected without departing from the scope of this disclosure. Furthermore, it should be understood that multiple turns of inductor may lead to an increase in parasitic resistance and capacitance, which may affect the Q value. Therefore, a trade-off needs to be made regarding the number of inductor turns in engineering. In addition, Figure 5 Only the first inductor 504 is shown, and the second inductor located below it is not shown. Figure 5 The first inductor 504 and the second inductor (not shown) are connected to the capacitor array 508, which will not be described in detail here.

[0078] Figure 6 A schematic planar layout of an inductor architecture 600 according to another embodiment of the present disclosure is shown. Similar to the embodiments described above, Figure 6 The inductor architecture 600 shown includes a first inductor 604, a second inductor (not shown), and a third inductor 602, with the first inductor 604 and the second inductor (not shown) connected to a capacitor array 608. Furthermore, the first inductor 604 is also formed as a figure-eight inductor and includes a first loop 604a and a second loop 604b having opposite magnetic flux directions. Unlike the embodiments described above, in... Figure 6 In the illustrated inductor architecture 600, the input terminal 614 and output terminal 616 of the first inductor 604 extend from the middle of the figure-eight tail inductor rather than from its ends. Those skilled in the art will understand that in the inductor architecture according to this disclosure, the input and output terminals of the inductor may be configured in the same or different ways as shown in the embodiments without departing from the scope of this disclosure.

[0079] Figure 7 A schematic planar layout of an inductor architecture 700 according to yet another embodiment of the present disclosure is shown. Similar to the embodiments described above, Figure 7The illustrated inductor architecture 700 includes a first inductor 704, a second inductor (not shown), and a third inductor 702, with the first inductor 704 and the second inductor (not shown) connected to a capacitor array 708. Furthermore, the first inductor 704 is also formed as a figure-eight inductor and includes a first loop 704a and a second loop 704b with opposite magnetic flux directions. Unlike the embodiments described above, in... Figure 7 In the illustrated inductor architecture 700, the third inductor 702 includes double-turn traces forming nested first loops 702a and 702b. In some embodiments, the main inductor may employ a double-turn structure. By increasing the number of turns, a double-turn main inductor can provide a higher inductance value under the same area or volume conditions, helping to meet application scenarios with high inductance requirements. Furthermore, the double-turn structure improves current distribution to some extent, reduces single-turn current density, and reduces localized heat generation. However, those skilled in the art will understand that the design of a double-turn main inductor may introduce additional parasitic resistance and capacitance, thereby affecting the quality factor (Q value) and reducing filtering or resonant performance. Simultaneously, the double-turn structure increases wiring complexity and manufacturing cost, and may introduce changes in electromagnetic coupling paths, requiring comprehensive trade-offs in engineering design. This disclosure is not limited to a double-turn structure; the number of turns of the main inductor can be adjusted according to application requirements without departing from the scope of this disclosure.

[0080] In a preferred embodiment of this disclosure, a single-turn main inductor is used to avoid the limitations of complex multi-turn main inductor layouts.

[0081] In another aspect of this disclosure, an LC resonant circuit is provided. For example, see reference... Figure 1 The LC resonant circuit 100 shown is an example. Figure 1 As shown, the LC resonant circuit 100 includes a main resonant circuit 106 configured to include a main inductor 110 and a tunable capacitor 112; a power supply path configured to include a power supply path 116 and a ground return path 118; and a tail resonant network 108 arranged in the power supply path of the LC tuning circuit, wherein the tail resonant network 108 includes a first tail inductor 120 connected in series in the power supply path 116, a second tail inductor 122 connected in series in the ground return path 118, and a capacitor array 124 connected in parallel between the power supply path 116 and the ground return path 118; wherein the main inductor 110, the first tail inductor 120, and the second tail inductor 122 are configured to have an inductor architecture according to the present disclosure.

[0082] In some embodiments, the capacitor array 124 may be a tunable capacitor array and may be configured to adjust the secondary resonant frequency of the tail resonant network 108.

[0083] In some embodiments, the tunable capacitor array may be configured to be operable such that the secondary resonant point of the tail resonant network 108 is located in a higher resonant range than the main oscillation frequency of the main resonant circuit 106, and covers a frequency range including the higher harmonics corresponding to the main oscillation frequency.

[0084] In some embodiments, the tunable capacitor array can be configured to operate such that the second resonant point of the tail resonant network 108 is close to the second harmonic band of the main resonant frequency of the main resonant circuit 106. Utilizing the higher equivalent quality factor obtained by the tail resonant network near its second resonant point effectively avoids the quality factor degradation caused by excessive inductor turns, thereby optimizing inductor performance.

[0085] In the embodiments of this disclosure, the first tail inductor 120 and the second tail inductor 122 are integrally arranged in the surrounding area of ​​the main resonant circuit 106, forming a secondary resonant network 108 for the power supply path without increasing the distance between them. The secondary resonant network 108 for the power supply path refers to the second resonant circuit 108 formed by the first tail inductor 120, the second tail inductor 122, and the capacitor array 124 on the oscillator power supply path.

[0086] In this way, in the embodiments of this disclosure, through the characteristic design of the tail resonant network 108, the main resonant circuit 106 can be arranged close together without causing a significant shift in the equivalent resonant frequency and oscillation conditions of the tail resonant network 108.

[0087] In some embodiments, the characteristic design of the tail resonant network 108 includes: ensuring that the first tail inductor 120 and the second tail inductor 122 exhibit a spatial distribution where their equivalent magnetic fields cancel each other out during operation, thereby reducing magnetic coupling with adjacent resonant structures. In embodiments where the LC resonant circuit 100 is an oscillator, the variation in the equivalent resonant frequency and oscillation conditions of the tail resonant network is within a tolerable range relative to the oscillator's tuning range and design start-up margin, thus not causing significant shifts in the equivalent resonant frequency and oscillation conditions.

[0088] In some embodiments, the main resonant circuit can be designed and configured according to the oscillation frequency range required by the target application. The main resonant circuit includes a main inductor and a tunable capacitor array connected thereto. By adjusting the tunable capacitor array, the main resonant circuit can cover the target oscillation frequency range. Simultaneously, the dimensions of the complementary cross-coupled transconductance units are configured according to the resonant frequency of the main resonant circuit and the required start-up margin to meet the oscillation conditions of the oscillator within the target frequency range.

[0089] After the main resonant circuit is designed, the tail resonant network can be arranged in the vicinity of the main resonant circuit. The tail resonant network includes a first tail inductor and a second tail inductor. The main inductor covers the area around the first and second tail inductors on a plane, and the first and second tail inductors form a secondary resonant circuit for the power supply path, taking into account the parasitic parameters of the transconductance unit. In a preferred embodiment, the first and second tail inductors adopt an 8-shaped or equivalent symmetrical structure to achieve the magnetic field cancellation characteristic. The equivalent magnetic field symmetrical structure may also include multi-loop symmetrical inductors or other layout structures that can achieve partial magnetic field cancellation in the operating state.

[0090] Since the secondary resonant frequency of the tail resonant network is affected by the tail inductor parameters and related parasitic parameters, a capacitor tuning array can be set between the first and second tail inductors to adjust the secondary resonant frequency. By adjusting this capacitor tuning array, the secondary resonant point of the tail resonant network is located in a higher-order resonant range than the oscillation frequency of the main resonant circuit, and covers the frequency range containing the higher harmonics corresponding to the main oscillation frequency. In a preferred embodiment, the resonant point is located in a harmonic frequency band (2f) close to twice the main resonant frequency (f), thereby obtaining a higher equivalent impedance near the secondary resonant point.

[0091] In some embodiments, by aligning the first and second tail inductors (with the same current direction) and arranging them opposite each other so that their magnetic flux coupling directions are the same, the two tail inductors form a positive mutual inductance in the operating state. The magnitude of this positive mutual inductance can be adjusted by the relative spacing, overlap area, or interlayer position of the two inductors.

[0092] In embodiments of this disclosure, the tail resonant network exhibits a high equivalent quality factor near its second resonant frequency, which helps to reduce the impact of transconductance unit noise upconverting to the target oscillation frequency via the second resonant frequency path, thereby improving the phase noise performance of the oscillator. Simultaneously, this tail resonant network can achieve the above effects without increasing the arrangement distance from the main resonant circuit, and without increasing the chip area. In this way, in some embodiments, the inductor architecture of this disclosure enables the LC resonant circuit to maintain a low footprint while improving performance.

[0093] In another aspect of this disclosure, an electronic circuit is provided that includes an LC resonant circuit according to this disclosure. It should be understood that, although referenced above... Figure 1 The LC resonant circuit in the voltage-controlled oscillator shown illustrates the principles of this disclosure, but the implementation of this disclosure is not limited thereto. Those skilled in the art can apply the principles of this disclosure to power amplifiers, low-noise amplifiers, and other electronic circuits in integrated circuits and radio frequency circuits without departing from the scope of this disclosure.

[0094] While various embodiments of various aspects of this disclosure have been described for the purposes of this disclosure, they should not be construed as limiting the teachings of this disclosure to these embodiments. Features disclosed in one specific embodiment are not limited to that embodiment, but can be combined with features disclosed in different embodiments. For example, one or more features and / or functions according to the scheme described in one embodiment can also be applied individually, in combination, or holistically to another embodiment. Furthermore, various embodiments of various aspects of this disclosure can be implemented independently or in different combinations. Those skilled in the art will understand that many more possible alternative implementations and variations exist, and various changes and modifications can be made to the above structure without departing from the protection scope of this disclosure.

Claims

1. An inductor architecture for use in an LC resonant circuit, the inductor architecture comprising: The first inductor and the second inductor are respectively configured such that they generate magnetic fluxes in opposite directions when current flows through them; as well as The third inductor, when viewed along a direction perpendicular to the plane of the first inductor, is configured to surround the first inductor and the second inductor; The first inductor and the second inductor are the first tail inductor and the second tail inductor of the LC resonant circuit, respectively, and the third inductor is the main inductor of the LC resonant circuit.

2. The inductor architecture according to claim 1, characterized in that, The first inductor and the second inductor are each configured to have an even number of loops, wherein half of the loops are arranged axially or centrally symmetrically with the other half of the loops, and the half of the loops have opposite magnetic flux directions to the other half of the loops.

3. The inductor architecture according to claim 2, characterized in that, The first inductor and the second inductor are figure-eight inductors.

4. The inductor architecture according to claim 1, characterized in that, The first inductor, the second inductor, and the third inductor are single-turn or multi-turn inductors.

5. The inductor architecture according to claim 1, characterized in that, The third inductor is a toroidal inductor.

6. The inductor architecture according to claim 1, characterized in that, The first inductor and the second inductor have the same shape and size.

7. The inductor architecture according to claim 1, characterized in that, The first inductor and the second inductor have the same shape, and the size of the first inductor is larger than the size of the second inductor.

8. The inductor architecture according to claim 1, characterized in that, Two of the first inductor, the second inductor, and the third inductor are arranged in the same metal layer, the other of the first inductor, the second inductor, and the third inductor is arranged in another metal layer, and the first inductor and the second inductor are arranged in different metal layers.

9. The inductor architecture according to claim 1, characterized in that, The first inductor, the second inductor, and the third inductor are arranged in three adjacent metal layers, and the third inductor is arranged in the metal layer between the first inductor and the second inductor.

10. The inductor architecture according to claim 1, characterized in that, The current directions of the first inductor and the second inductor are the same when they are in oscillating operation.

11. An LC resonant circuit, comprising: The main resonant circuit is configured to include a main inductor and a tunable capacitor. The power supply path is configured to include a power supply path and a ground return path; as well as A tail resonant network is arranged in the power supply path of the LC tuning circuit, and the tail resonant network includes a first tail inductor connected in series in the power supply path, a second tail inductor connected in series in the ground return path, and a capacitor array connected in parallel between the power supply path and the ground return path. The main inductor, the first tail inductor, and the second tail inductor are configured to have The inductor architecture according to any one of claims 1 to 10.

12. The LC resonant circuit according to claim 11, characterized in that, The capacitor array is a tunable capacitor array, configured to adjust the secondary resonant frequency of the tail resonant network.

13. The LC resonant circuit according to claim 12, characterized in that, The tunable capacitor array is configured to be operable such that the secondary resonant point of the tail resonant network is located in a higher-order resonant range than the main oscillation frequency of the main resonant circuit, and covers a frequency range that includes the higher-order harmonics corresponding to the main oscillation frequency.

14. The LC resonant circuit according to claim 12, characterized in that, The tunable capacitor array is configured to be operable such that the secondary resonant point of the tail resonant network is close to the second harmonic band of the main resonant circuit's main oscillation frequency.

15. An electronic circuit comprising an LC resonant circuit according to any one of claims 11 to 14.

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