Low-insertion-loss high-harmonic-suppression LTCC duplexer equivalent circuit for WiFi and duplexer thereof

Abstract

The invention discloses a low-insertion-loss high-harmonic-suppression LTCC (Low Temperature Co-fired Ceramic) duplexer equivalent circuit for WiFi (Wireless Fidelity) and a duplexer thereof, and relates to a low-insertion-loss high-harmonic-suppression LTCC duplexer equivalent circuit for WiFi and a duplexer thereof, which are based on an LTCC (Low Temperature Co-fired Ceramic) technology and adopt lumped parameter model design to realize the special electrical performance requirements of the low-insertion-loss high-harmonic-suppression LTCC duplexer for WiFi. The frequency divider effectively achieves the frequency division function of low-frequency signals and high-frequency signals, has the advantages of being low in loss, high in harmonic suppression, high in isolation, high in reliability, low in cost, good in consistency, suitable for large-scale production and the like, and further adapts to the development trend of integration and miniaturization of new electronic components.

Description

Technical Field

[0001] This invention discloses a low insertion loss, high harmonic suppression LTCC duplexer for WiFi, which can be used for wireless connections in 5G, 4G mobile communication devices, tablets, and various other communication devices. Background Technology

[0002] Low-temperature co-fired ceramic (LTCC) technology emerged in the 1980s. Its core principle involves co-firing multiple layers of ceramic green bodies with a highly conductive metal (such as silver) at a relatively low temperature of approximately 900°C, forming a high-density three-dimensional interconnect structure. Initially developed to meet the stringent requirements of military electronics for miniaturization, high reliability, and high-frequency characteristics, this technology has now become a key technology for achieving advanced electronic packaging and integration, renowned for its excellent dielectric properties, thermal stability, and process compatibility.

[0003] Building upon this technology, the field of radio frequency (RF) components has witnessed a revolution in high integration. Traditional discrete RF components struggle to meet the miniaturization demands of modern systems, while LTCC (Low-Temperature Compressed Carbide) technology allows filters, couplers, antennas, and passive components to be embedded within multi-layered structures, integrating them into compact front-end modules. This has enabled the widespread application of related products in fields such as wireless communication (4G / 5G), satellite navigation, and automotive electronics. Their low loss, high quality factor, and excellent thermal management and electromagnetic shielding performance continue to drive the evolution of high-frequency systems towards higher performance and smaller size. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides an equivalent circuit for a low insertion loss, high harmonic suppression (LTCC) duplexer used in WiFi. The equivalent circuit includes a first common port, a second common port, and a third common port. A first link connects the first and second common ports, and a second link connects the second and third common ports. The first link includes a first inductor L1, a second inductor L2, and a third inductor L3 connected in series. A grounding capacitor C1 is provided between the first inductor L1 and the second inductor L2, and a grounding capacitor C2 is provided between the second inductor L2 and the third inductor L3. This first link outputs a low-frequency signal in the 2.4GHz band. The second link includes a high-frequency... The system includes a high-pass filter and a low-pass filter. The high-pass filter consists of a grounded fifth inductor L5 and capacitors C3, C4, and C5. Capacitors C3 and C4 are connected in series and then in parallel with C5. A grounded fifth inductor L5 is located between capacitors C3 and C4. The low-pass filter consists of a fourth inductor L4 and capacitors C6, C7, and C8. Capacitor C6 is connected in parallel with the fourth inductor L4 for resonance. A grounded capacitor C7 is located between capacitors C4 and C6. A grounded capacitor C8 is located between capacitor C6 and the third common terminal. A grounded sixth inductor L6 is located at the common terminal of the fifth inductor L5, capacitors C7 and C8. This second link outputs high-frequency signals in the 5.15-7.25 GHz band.

[0005] This invention also provides a duplexer that implements the equivalent circuit of the low insertion loss, high harmonic suppression (LTCC) duplexer for WiFi. The duplexer includes a body, ground ports P1, P2, and P3, a low-frequency input / output port P4, a ground port P5, and a high-frequency input / output port P6 disposed on the body, and a stacked circuit structure disposed inside the body. The stacked circuit structure includes... The first layer is a first metal planar conductor printed on a ceramic dielectric substrate. The first metal planar conductor is connected to the grounding port P1, grounding port P3 and grounding port P5 of the product through the first post, the second post and the third post, respectively, and is connected to the fifth first metal planar conductor and the third second metal planar conductor through the fourth post and the twelfth post, respectively. The second layer consists of three mutually insulated second-layer first metal planar conductors, second-layer second metal planar conductors, and third-layer third metal planar conductors printed on the ceramic dielectric substrate. The second-layer first metal planar conductor is connected to the high-frequency input / output port P6 and the fifth-layer second metal planar conductor via the sixth and seventh posts, respectively. The second-layer second metal planar conductor is connected to the third-layer first metal planar conductor via the eighth post. The second-layer third metal planar conductor is connected to the seventh-layer third metal planar conductor via the ninth post. The third layer consists of two mutually insulated first metal planar conductors and second metal planar conductors printed on the ceramic dielectric substrate. The first metal planar conductor is connected to the second metal planar conductor and the first metal planar conductor through the tenth and eleventh post, respectively. The second metal planar conductor is connected to the first metal planar conductor through the twelfth post. The fourth layer is a first metal planar conductor printed on a ceramic dielectric substrate; the first metal planar conductor is connected to the second metal planar conductor of the seventh layer through a thirteenth point post. The fifth layer consists of three mutually insulated fifth-layer first metal planar conductors, fifth-layer second metal planar conductors, and fifth-layer third metal planar conductors printed on the ceramic dielectric substrate. The fifth-layer first metal planar conductor is connected to the first-layer first metal planar conductor and the sixth-layer first metal planar conductor via the fourth and fifteenth posts, respectively. The fifth-layer second metal planar conductor is connected to the second-layer insulated metal planar conductor and the ninth-layer second metal planar conductor via the seventh and sixteenth posts, respectively. The fifth-layer third metal planar conductor is connected to the low-frequency input / output port P4 and the sixth-layer second metal planar conductor via the thirtieth and seventeenth posts, respectively. The sixth layer consists of two mutually insulated first and second metal planar conductors printed on a ceramic dielectric substrate. The first metal planar conductor is connected to the first metal planar conductor of the fifth layer and the first metal planar conductor of the seventh layer via posts at the fifteenth and eighteenth points, respectively. The second metal planar conductor is connected to the third metal planar conductor of the fifth layer and the second metal planar conductor of the seventh layer via posts at the seventeenth and nineteenth points, respectively. The seventh layer consists of three mutually insulated first, second, and third metal planar conductors printed on a ceramic dielectric substrate. The first metal planar conductor is connected to the first metal planar conductor of the sixth and ninth layers via posts at the eighteenth and twentieth points, respectively. The second metal planar conductor is connected to the first metal planar conductor of the fourth, sixth, and eleventh layers via posts at the thirteenth, nineteenth, and twenty-first points, respectively. The third metal planar conductor is connected to the third metal planar conductor of the second and ninth layers via posts at the ninth and twenty-second points, respectively. The eighth layer has a first metal planar conductor printed on the ceramic dielectric substrate; the first metal planar conductor of the eighth layer is connected to the common port P2 and the third metal planar conductor of the eleventh layer through the fourteenth post and the twenty-third post, respectively. On the ninth layer, three mutually insulated first, second, and third metal planar conductors are printed on the ceramic dielectric substrate. The first metal planar conductor is connected to the first metal planar conductor of the seventh and eleventh layers through the twentieth and twenty-fourth posts, respectively. The second metal planar conductor is connected to the second metal planar conductor of the fifth and tenth layers through the sixteenth and twenty-fifth posts, respectively. The third metal planar conductor is connected to the third metal planar conductor of the seventh, tenth, and tenth layers through the twenty-second, twenty-sixth, and twenty-seventh posts, respectively. The tenth layer consists of three mutually insulated planar metal conductors: a first planar metal conductor, a second planar metal conductor, and a third planar metal conductor. The first planar metal conductor is connected to the first planar metal conductor of the third layer and the second planar metal conductor of the ninth layer via posts 11 and 25, respectively. The second planar metal conductor is connected to the third planar metal conductor of the ninth layer and the third planar metal conductor of the eleventh layer via posts 26 and 29, respectively. The third planar metal conductor is connected to the third planar metal conductor of the ninth layer and the second planar metal conductor of the eleventh layer via posts 27 and 28, respectively. The eleventh layer consists of three mutually insulated first, second, and third metal planar conductors printed on the ceramic dielectric substrate. The first metal planar conductor is connected to the first metal planar conductor of the ninth layer via the twenty-fourth post. The second metal planar conductor is connected to the second metal planar conductor of the seventh layer and the third metal planar conductor of the tenth layer via the twenty-first and twenty-eighth posts, respectively. The second metal planar conductor is connected to the first metal planar conductor of the eighth layer and the second metal planar conductor of the tenth layer via the twenty-third and twenty-ninth posts, respectively.

[0006] This invention is based on LTCC (Low Temperature Co-fired Ceramic) technology and uses a lumped parameter model to design and achieve the special electrical performance requirements of a low insertion loss, high harmonic suppression LTCC duplexer for WiFi. This invention effectively realizes the frequency division function for low-frequency and high-frequency signals, and has advantages such as low loss, high harmonic suppression, high isolation, high reliability, low cost, excellent consistency, and suitability for large-scale production. Furthermore, it adapts to the new trend of electronic component integration and miniaturization. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the equivalent circuit of the low insertion loss, high harmonic suppression LTCC duplexer for WiFi in this invention. Figure 2This is a three-dimensional schematic diagram of the appearance and structure of the low insertion loss, high harmonic suppression LTCC duplexer for WiFi of the present invention; Figure 3 This is a schematic diagram of the internal structure of the low insertion loss, high harmonic suppression LTCC duplexer for WiFi in this invention. Figure 4 This is a schematic diagram of the first layer circuit planar structure of the present invention; Figure 5 This is a schematic diagram of the second-layer circuit planar structure of the present invention; Figure 6 This is a schematic diagram of the third-layer circuit planar structure of the present invention; Figure 7 This is a schematic diagram of the fourth layer circuit planar structure of the present invention; Figure 8 This is a schematic diagram of the fifth layer circuit planar structure of the present invention; Figure 9 This is a schematic diagram of the sixth layer circuit planar structure of the present invention; Figure 10 This is a schematic diagram of the seventh layer circuit planar structure of the present invention; Figure 11 This is a schematic diagram of the eighth layer circuit planar structure of the present invention; Figure 12 This is a schematic diagram of the ninth layer circuit planar structure of the present invention; Figure 13 This is a schematic diagram of the tenth layer circuit planar structure of the present invention; Figure 14 This is a schematic diagram of the eleventh layer circuit planar structure of the present invention; Figure 15 The electrical characteristic curve of the low insertion loss, high harmonic suppression LTCC duplexer for WiFi in this invention is shown. Detailed Implementation

[0008] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0009] This invention provides a low-insertion-loss, high-harmonic-suppression LTCC duplexer for WiFi. This duplexer employs a special structure with lumped parameters, consisting of a low-pass filter and a band-pass filter. The low-pass filter primarily separates low-frequency signals from the WiFi 2.4GHz band, while the band-pass filter primarily separates high-frequency signals from the WiFi 6GHz band. This duplexer offers advantages such as low loss, high harmonic suppression, and high isolation. The technical solution adopted by this invention to solve its technical problem is: a low-insertion-loss, high-harmonic-suppression LTCC duplexer for WiFi, comprising a substrate, terminals disposed on the outside of the substrate, and a circuit layer disposed inside the substrate. The circuit layer inside the substrate has a stacked structure.

[0010] Figure 1This is the equivalent circuit diagram of a low insertion loss, high harmonic suppression (LTCC) duplexer for WiFi. Taking a signal input from common port ① as an example: After entering through the first common port ①, the signal outputs through the second common port ②. This first link consists of a third-order low-pass filter, separating the low-frequency signal in the 2.4GHz band. After entering through the first common port ①, the signal outputs through the third common port ③. This second link is a band-pass filter, separating the high-frequency signal in the 5.15-7.25GHz band. The band-pass filter in the high-frequency path consists of a high-pass filter and a low-pass filter. The high-pass filter is composed of inductor L5 and capacitors C3, C4, and C5. Capacitors C3 and C4 are connected in series and then in parallel with C5. This configuration effectively improves the suppression performance of the high-pass filter. The low-pass filter is composed of inductor L4 and capacitors C6, C7, and C8. Capacitor C6 resonates in parallel with inductor L4, creating a resonant zero at high frequencies, further improving suppression performance. The sixth inductor, L6, is a series-grounded inductor, which effectively improves the suppression performance of the high-frequency third common port ③ in the low-frequency band.

[0011] The first common port ① constitutes the common port of the duplexer, the second common port ② is the low-frequency input / output port, and the third common port ③ is the high-frequency input / output port.

[0012] Figure 2 This is the appearance structure of a low insertion loss, high harmonic suppression LTCC duplexer for WiFi. P1, P3, and P5 are grounding ports, P2 is the common port of the chip duplexer, P4 is the low-frequency input / output port, and P6 is the high-frequency input / output port.

[0013] WiFi uses the internal structure of a low-insertion-loss, high-harmonic-suppression LTCC duplexer, such as... Figure 3 As shown, the circuit structure is distributed inside the ceramic substrate. The circuit structure has a total of eleven layers.

[0014] The first layer, such as Figure 4 As shown, a first layer of first metal planar conductor 1 is printed on a ceramic dielectric substrate. The first layer of first metal planar conductor 1 is the ground plane of the product, and is connected to the ground port P1, ground port P3 and ground port P5 of the product through the first post 2, the second post 3 and the third post 4, and is connected to the fifth layer of first metal planar conductor 18 and the third layer of second metal planar conductor 13 through the fourth post 21 and the twelfth post 15, respectively. The first layer of first metal planar conductor 1, together with the first post 2, the second post 3 and the third post 4, constitutes the sixth grounding inductor L6.

[0015] The second layer consists of three mutually insulated second-layer first metal planar conductors 5, 6, and 7 on a ceramic dielectric substrate. The second-layer first metal planar conductor 5 is connected to the high-frequency input / output port P6 and the fifth-layer second metal planar conductor 19 via the sixth post 8 and the seventh post 9, respectively. The second-layer second metal planar conductor 6 is connected to the third-layer first metal planar conductor 12 via the eighth post 10. The second-layer third metal planar conductor 7 is connected to the seventh-layer third metal planar conductor 31 via the ninth post 11. The second-layer first metal planar conductor 5, the second-layer second metal planar conductor 6, and the first-layer first metal planar conductor 1 form two grounding capacitors C8 and C7 for the high-frequency path, respectively.

[0016] The third layer consists of two mutually insulated third-layer first metal planar conductors 12 and 13 printed on a ceramic dielectric substrate. The third-layer first metal planar conductor 12 is connected to the second-layer second metal planar conductor 6 and the tenth-layer first metal planar conductor 45 via the tenth post 10 and the eleventh post 14, respectively. The third-layer second metal planar conductor 13 is connected to the first-layer first metal planar conductor 1 via the twelfth post 15. The third-layer first metal planar conductor 12 and the second-layer first metal planar conductor 5 form an interstage coupling capacitor C6 for a high-frequency path, and the third-layer second metal planar conductor 13, the first-layer first metal planar conductor 1, and the second-layer third metal planar conductor 7 form a grounding capacitor C1 for a low-frequency path.

[0017] The fourth layer has a first metal planar conductor 16 printed on the ceramic dielectric substrate; the first metal planar conductor 16 is connected to the second metal planar conductor 30 of the seventh layer through the thirteenth point post 17; the first metal planar conductor 16 and the first metal planar conductor 1 form a grounding capacitor C2 for a low-frequency path.

[0018] The fifth layer consists of three mutually insulated fifth-layer first metal planar conductors 18, 19, and 20 printed on a ceramic dielectric substrate. The fifth-layer first metal planar conductor 18 is connected to the first-layer first metal planar conductor 1 and the sixth-layer first metal planar conductor 25 via the fourth post 21 and the fifteenth post 22, respectively. The fifth-layer second metal planar conductor 19 is connected to the second-layer insulated metal planar conductor 5 and the ninth-layer second metal planar conductor 39 via the seventh post 9 and the sixteenth post 23, respectively. The fifth-layer third metal planar conductor 20 is connected to the low-frequency input / output port P4 and the sixth-layer second metal planar conductor 26 via the thirtieth post 53 and the seventeenth post 24, respectively.

[0019] The sixth layer consists of two mutually insulated first metal planar conductors 25 and second metal planar conductors 26 printed on a ceramic dielectric substrate. The first metal planar conductor 25 is connected to the first metal planar conductor 18 of the fifth layer and the first metal planar conductor 29 of the seventh layer via the fifteenth post 22 and the eighteenth post 27, respectively; the second metal planar conductor 26 is connected to the third metal planar conductor 20 of the fifth layer and the second metal planar conductor 30 of the seventh layer via the seventeenth post 24 and the nineteenth post 28, respectively.

[0020] The seventh layer consists of three mutually insulated first metal planar conductors 29, 30, and 31 printed on a ceramic dielectric substrate. The first metal planar conductor 29 is connected to the first metal planar conductor 25 of the sixth layer and the first metal planar conductor 38 of the ninth layer via the eighteenth post 27 and the twentieth post 32, respectively. The second metal planar conductor 30 is connected to the first metal planar conductor 16 of the fourth layer, the second metal planar conductor 26 of the sixth layer, and the second metal planar conductor 51 of the eleventh layer via the thirteenth post 17, the nineteenth post 28, and the twenty-first post 33, respectively. The third metal planar conductor 31 is connected to the third metal planar conductor 7 of the second layer and the third metal planar conductor 40 of the ninth layer via the ninth post 11 and the twenty-second post 34, respectively. The fifth layer first metal planar conductor 18, the sixth layer first metal planar conductor 25, the seventh layer first metal planar conductor 29, together with the fourth point post 21, the fifteenth point post 22, and the eighteenth point post 27, constitute the high-frequency grounding fifth inductor L5; the fifth layer third metal planar conductor 20, the sixth layer second metal planar conductor 26, the seventh layer second metal planar conductor 30, together with the fifteenth point post 22, the seventeenth point post 24, and the nineteenth point post 28, constitute the low-frequency interstage third inductor L3.

[0021] The eighth layer has an eighth layer first metal planar conductor 35 printed on the ceramic dielectric substrate. The eighth layer first metal planar conductor 35 is connected to the common port P2 and the eleventh layer third metal planar conductor 52 through the fourteenth point post 36 and the twenty-third point post 37, respectively.

[0022] The ninth layer comprises three mutually insulated first metal planar conductors 38, 39, and 40 printed on a ceramic dielectric substrate. The first metal planar conductor 38 is connected to the first metal planar conductor 29 (seventh layer) and the first metal planar conductor 50 (eleventh layer) via posts 32 (twentieth point) and 41 (twenty-fourth point), respectively. The second metal planar conductor 39 is connected to the second metal planar conductor 19 (fifth layer) and the first metal planar conductor 45 (tenth layer) via posts 23 (sixteenth point) and 42 (twenty-fifth point), respectively. The third metal planar conductor 40 is connected to the third metal planar conductor 31 (seventh layer), the second metal planar conductor 46 (tenth layer), and the third metal planar conductor 47 (tenth layer) via posts 34 (twenty-second point), 43 (twenty-sixth point), and 44 (twenty-seventh point). The first metal planar conductor 38 and the first metal planar conductor 35 form the interstage capacitance C3 of the high-frequency path.

[0023] The tenth layer consists of three mutually insulated planar metal conductors: a first planar metal conductor 45, a second planar metal conductor 46, and a third planar metal conductor 47. The first planar metal conductor 45 is connected to the first planar metal conductor 12 of the third layer and the second planar metal conductor 39 of the ninth layer via posts 11 and 42, respectively. The second planar metal conductor 46 is connected to the third planar metal conductor 40 of the ninth layer and the third planar metal conductor 52 of the eleventh layer via posts 43 and 48, respectively. The third planar metal conductor 47 is connected to the third planar metal conductor 40 of the ninth layer and the second planar metal conductor 51 of the eleventh layer via posts 44 and 49, respectively. The first planar metal conductor 45, the first planar metal conductor 38, and the first planar metal conductor 50 of the eleventh layer form the interstage capacitance C4 of the high-frequency path.

[0024] In the eleventh layer, three mutually insulated first metal planar conductors 50, 51, and 52 are printed on the ceramic dielectric substrate. The first metal planar conductor 50 is connected to the first metal planar conductor 38 of the ninth layer via the twenty-fourth post 41; the second metal planar conductor 51 is connected to the second metal planar conductor 30 of the seventh layer and the third metal planar conductor 47 of the tenth layer via the twenty-first post 33 and the twenty-eighth post 49, respectively; and the second metal planar conductor 51 is connected to the first metal planar conductor 35 of the eighth layer and the second metal planar conductor 46 of the tenth layer via the twenty-third post 37 and the twenty-ninth post 48, respectively. The third metal planar conductor 52 and the first metal planar conductor 45 of the tenth layer form the interstage capacitance C5 of the high-frequency path. The fifth layer second metal planar conductor 19, the ninth layer second metal planar conductor 39, the tenth layer first metal planar conductor 45, together with the seventh point post 9, the sixteenth point post 23, and the twenty-fifth point post 42, constitute the high-frequency interstage coupling fourth inductor L4; the ninth layer third metal planar conductor 40, the tenth layer second metal planar conductor 46, the eleventh layer third metal planar conductor 52, together with the twenty-sixth point post 43 and the twenty-ninth point post 48, constitute the low-frequency interstage first inductor L1; the tenth layer third metal planar conductor 47, the eleventh layer second metal planar conductor 51, together with the twenty-first point post 33, the twenty-seventh point post 44, and the twenty-eighth point post 49, constitute the low-frequency interstage second inductor L2.

Claims

1. An equivalent circuit for a low insertion loss, high harmonic suppression (LTCC) duplexer used in WiFi, the equivalent circuit comprising a first common port, a second common port, and a third common port, wherein the first common port and the second common port form a first link, and the second common port and the third common port form a second link, characterized in that... The first link includes a first inductor L1, a second inductor L2, and a third inductor L3 connected in series. A grounding capacitor C1 is provided between the first inductor L1 and the second inductor L2, and a grounding capacitor C2 is provided between the second inductor L2 and the third inductor L3. This first link outputs a low-frequency signal in the 2.4GHz band. The second link includes a high-pass filter and a low-pass filter connected in series. The high-pass filter is composed of a grounded fifth inductor L5 and capacitors C3, C4, and C5. Capacitors C3 and C4... After being connected in series, they are connected in parallel with C5. A fifth inductor L5 is grounded between capacitors C3 and C4. The low-pass filter is composed of a fourth inductor L4 and capacitors C6, C7, and C8. Capacitor C6 is connected in parallel with the fourth inductor L4 for resonance. A grounded capacitor C7 is connected between capacitors C4 and C6. A grounded capacitor C8 is connected between capacitor C6 and the third common terminal. A sixth inductor L6 is grounded at the common terminal of the fifth inductor L5, capacitors C7 and C8. This second link outputs high-frequency signals in the 5.15-7.25GHz band.

2. A duplexer that implements the equivalent circuit of the low insertion loss, high harmonic suppression LTCC duplexer for WiFi as described in claim 1, characterized in that, The duplexer includes a body, grounding ports P1, P2, and P3, a low-frequency input / output port P4, a grounding port P5, and a high-frequency input / output port P6 disposed on the body, and a stacked circuit structure disposed inside the body. The stacked circuit structure includes... The first layer is a first metal planar conductor printed on a ceramic dielectric substrate. The first metal planar conductor is connected to the grounding port P1, grounding port P3 and grounding port P5 of the product through the first post, the second post and the third post, respectively, and is connected to the fifth first metal planar conductor and the third second metal planar conductor through the fourth post and the twelfth post, respectively. The second layer consists of three mutually insulated second-layer first metal planar conductors, second-layer second metal planar conductors, and third-layer third metal planar conductors printed on the ceramic dielectric substrate. The second-layer first metal planar conductor is connected to the high-frequency input / output port P6 and the fifth-layer second metal planar conductor via the sixth and seventh posts, respectively. The second-layer second metal planar conductor is connected to the third-layer first metal planar conductor via the eighth post. The second-layer third metal planar conductor is connected to the seventh-layer third metal planar conductor via the ninth post. The third layer consists of two mutually insulated first metal planar conductors and second metal planar conductors printed on the ceramic dielectric substrate. The first metal planar conductor is connected to the second metal planar conductor and the first metal planar conductor through the tenth and eleventh post, respectively. The second metal planar conductor is connected to the first metal planar conductor through the twelfth post. The fourth layer is a first metal planar conductor printed on a ceramic dielectric substrate; the first metal planar conductor is connected to the second metal planar conductor of the seventh layer through a thirteenth point post. The fifth layer consists of three mutually insulated fifth-layer first metal planar conductors, fifth-layer second metal planar conductors, and fifth-layer third metal planar conductors printed on the ceramic dielectric substrate. The fifth-layer first metal planar conductor is connected to the first-layer first metal planar conductor and the sixth-layer first metal planar conductor via the fourth and fifteenth posts, respectively. The fifth-layer second metal planar conductor is connected to the second-layer insulated metal planar conductor and the ninth-layer second metal planar conductor via the seventh and sixteenth posts, respectively. The fifth-layer third metal planar conductor is connected to the low-frequency input / output port P4 and the sixth-layer second metal planar conductor via the thirtieth and seventeenth posts, respectively. The sixth layer consists of two mutually insulated sixth-layer first metal planar conductors and sixth-layer second metal planar conductors printed on a ceramic dielectric substrate. The sixth layer first metal planar conductor is connected to the fifth layer first metal planar conductor and the seventh layer first metal planar conductor through the fifteenth point post and the eighteenth point post, respectively; the sixth layer second metal planar conductor is connected to the fifth layer third metal planar conductor and the seventh layer second metal planar conductor through the seventeenth point post and the nineteenth point post, respectively. The seventh layer consists of three mutually insulated seventh-layer first metal planar conductors, seventh-layer second metal planar conductors, and seventh-layer third metal planar conductors printed on a ceramic dielectric substrate. The seventh layer first metal planar conductor is connected to the sixth layer first metal planar conductor and the ninth layer first metal planar conductor through the eighteenth and twentieth posts, respectively; the seventh layer second metal planar conductor is connected to the fourth layer first metal planar conductor, the sixth layer second metal planar conductor, and the eleventh layer second metal planar conductor through the thirteenth, nineteenth, and twenty-first posts, respectively; the seventh layer third metal planar conductor is connected to the second layer third metal planar conductor and the ninth layer third metal planar conductor through the ninth and twenty-second posts, respectively. The eighth layer has a first metal planar conductor printed on the ceramic dielectric substrate; the first metal planar conductor of the eighth layer is connected to the common port P2 and the third metal planar conductor of the eleventh layer through the fourteenth post and the twenty-third post, respectively. The ninth layer consists of three mutually insulated first, second, and third metal planar conductors printed on a ceramic dielectric substrate. The ninth layer first metal planar conductor is connected to the seventh layer first metal planar conductor and the eleventh layer first metal planar conductor through the twentieth and twenty-fourth posts, respectively; the ninth layer second metal planar conductor is connected to the fifth layer second metal planar conductor and the tenth layer first metal planar conductor through the sixteenth and twenty-fifth posts, respectively; the ninth layer third metal planar conductor is connected to the seventh layer third metal planar conductor, the tenth layer second metal planar conductor, and the tenth layer third metal planar conductor through the twenty-second, twenty-sixth, and twenty-seventh posts, respectively. The tenth layer consists of three mutually insulated planar metal conductors: a first planar metal conductor, a second planar metal conductor, and a third planar metal conductor. The first planar metal conductor is connected to the first planar metal conductor of the third layer and the second planar metal conductor of the ninth layer via posts 11 and 25, respectively. The second planar metal conductor is connected to the third planar metal conductor of the ninth layer and the third planar metal conductor of the eleventh layer via posts 26 and 29, respectively. The third planar metal conductor is connected to the third planar metal conductor of the ninth layer and the second planar metal conductor of the eleventh layer via posts 27 and 28, respectively. The eleventh layer consists of three mutually insulated first, second, and third metal planar conductors printed on the ceramic dielectric substrate. The first metal planar conductor is connected to the first metal planar conductor of the ninth layer via the twenty-fourth post. The second metal planar conductor is connected to the second metal planar conductor of the seventh layer and the third metal planar conductor of the tenth layer via the twenty-first and twenty-eighth posts, respectively. The second metal planar conductor is connected to the first metal planar conductor of the eighth layer and the second metal planar conductor of the tenth layer via the twenty-third and twenty-ninth posts, respectively.

Images