Chip

Abstract

A chip includes a configuration pin, an internal pull-up resistor, an internal pull-down resistor, a logic level detection circuit, and a configuration detection circuit. The configuration pin is electrically connected with the reference voltage end through the external resistor. The configuration detection circuit is used for connecting an input end of a logic level detection circuit (the logic level detection circuit can be a digital logic buffer, a comparator or other circuit which can be used for detecting a logic level) to a configuration pin, and is also used for carrying out the following steps. And disconnecting the internal pull-up resistor and the internal pull-down resistor from the configuration pin, so that the logic level detection circuit outputs a zeroth detection logic value. The internal pull-up resistor and the internal pull-down resistor are sequentially connected with the configuration pin, so that the logic level detection circuit outputs a plurality of detection logic values. A configuration vector is determined according to the zeroth detection logic value and the plurality of detection logic values.

Description

Technical Field

[0001] This case relates to a chip, and more particularly to a chip that can be configured with vector programming via a single pin. Background Technology

[0002] Application-specific integrated circuits often employ multi-bit vector configurations using two or more pins, which increases chip size and material costs. Therefore, providing a chip that addresses these issues is a crucial topic in this field. Summary of the Invention

[0003] This disclosure provides a chip. The chip includes a configuration pin, internal pull-up resistors, internal pull-down resistors, a logic level detection circuit, and a configuration detection circuit. The logic level detection circuit may be a digital logic buffer, a comparator, or other circuitry used to detect a logic level or a voltage level equivalent to that logic value. The configuration pin is electrically connected to a reference voltage terminal via an external resistor. The configuration detection circuit is electrically connected to the configuration pin, the internal pull-up resistors, the internal pull-down resistors, and the logic level detection circuit, wherein the configuration detection circuit is used to connect the input of the logic level detection circuit to the configuration pin, and wherein the configuration detection circuit is also used to perform the following steps: Disconnecting the internal pull-up resistors and the internal pull-down resistors from the configuration pin, so that the logic level detection circuit outputs a zeroth detected logic value. Sequentially connecting the internal pull-up resistors and the internal pull-down resistors to the configuration pin, so that the logic level detection circuit outputs a plurality of detected logic values. Determining a configuration vector based on the zeroth detected logic value and the plurality of detected logic values.

[0004] This disclosure provides a chip. The chip includes a configuration pin, internal pull-up resistors, internal pull-down resistors, a logic level detection circuit, and a configuration detection circuit. The configuration detection circuit is electrically connected to the logic level detection circuit, the internal pull-up resistors, and the internal pull-down resistors, wherein the internal pull-up resistors and internal pull-down resistors are variable resistors, and wherein the configuration detection circuit is used to perform the following steps: progressively adjusting the resistance values ​​of the internal pull-up resistors and internal pull-down resistors to a plurality of preset resistance values, sequentially connecting the internal pull-up resistors and internal pull-down resistors to the configuration pin at the plurality of preset resistance values, so that the digital logic level detection circuit outputs the plurality of detected logic values, and determines a configuration vector based on the plurality of detected logic values.

[0005] In summary, the chip disclosed in this document can be configured through a single configuration pin, thereby reducing the number of pins on the chip. Attached Figure Description

[0006] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0007] Figure 1 This is a schematic diagram of a configuration detection system according to an embodiment of the present disclosure.

[0008] Figures 2A to 2D This is a schematic diagram illustrating the vector detection operation of a chip supporting a two-bit configuration according to some embodiments of this disclosure.

[0009] Figure 3 This is a schematic diagram showing the resistance values ​​of the internal pull-up resistor, internal pull-down resistor, and external resistor of a configuration detection system supporting two-bit configuration according to some embodiments of this disclosure.

[0010] Figures 4A to 4B This is a schematic diagram illustrating the vector detection operation of a chip supporting multi-bit configuration according to some embodiments of this disclosure.

[0011] Figure 5 This is a schematic diagram showing the resistance values ​​of the internal pull-up resistor, internal pull-down resistor, and external resistor of a configuration detection system supporting multi-bit configuration according to some embodiments of this disclosure.

[0012] Figure 6 This is a flowchart of a method for detecting the configuration vector of a chip according to some embodiments of this disclosure. Detailed Implementation

[0013] Please see Figure 1 , Figure 1 This is a schematic diagram of a configuration detection system 100 according to an embodiment of this disclosure. Figure 1 As shown, the configuration detection system 100 includes a chip 110, an external resistor Rext1, and / or Rext0. In some embodiments, the chip 110 is an integrated circuit. In some embodiments, the chip 110 is an application-specific integrated circuit or other logic integrated circuit, and this invention is not limited thereto. In some embodiments, function selection, chip startup, address selection, clock configuration, or other actions or functions are performed via the configuration pin 102 of the chip 110. In some embodiments, function selection can select different functions or mode configurations via the configuration pin 102. In some embodiments, chip startup is performed by starting or resetting the chip 110 via the configuration pin 102. In some embodiments, address selection is performed by selecting an address or identifier via the configuration pin 102. In some embodiments, clock configuration is performed by selecting different clock sources or clock frequencies via the configuration pin 102. In some embodiments, the chip 110 has a configuration pin 102, and the chip 110 can perform two-bit or multi-bit vector configuration via a single configuration pin 102.

[0014] In some embodiments, chip 110 is configured by connecting an external pull-up resistor (e.g., external resistor Rext1) or an external pull-down resistor (e.g., external resistor Rext0) to configuration pin 102. In some embodiments, the reference voltage terminal VDD... ext1 The voltage (e.g., 3.3 volts) is higher than the reference voltage terminal VDD. ext0 The voltage (e.g., 0 volts) can be electrically connected to the reference voltage terminal VDD. ext1 The external resistor Rext1 is considered as an external pull-up resistor and is electrically connected to the reference voltage terminal VDD. ext0 The external resistor Rext0 is considered a pull-down resistor. In some embodiments, the reference voltage terminal VDD ext1 The voltage is 3.3 volts, and the reference voltage terminal VDD ext0 The voltage is 0 volts. In some embodiments, by connecting an external resistor Rext1 or Rext0 to configuration pin 102, and by detecting the interval (e.g., the upper and lower bounds of the interval / boundary) covering the resistance value of the external resistor Rext1 or Rext0, the configuration vector is determined based on the interval of the resistance value of the external resistor Rext1 or Rext0, thereby configuring the function or behavior of chip 110.

[0015] Chip 110 includes configuration detection circuitry 120, internal pull-up resistor R1, internal pull-down resistor R0, output driver 124, switches S0, S1, S2, and S3, and logic level detection circuitry 126. In some embodiments, the internal pull-up resistor R1 is electrically connected to the reference voltage terminal VDD. int1 And between the configuration detection circuit 120, and the internal pull-down resistor R0 is electrically connected to the reference voltage terminal VDD. int0 And between the configuration detection circuit 120 and the configuration detection circuit 120. In some embodiments, the output driver 124 may be implemented by other circuitry that would create a resistive load on the configuration pin 102, and this is not limited thereto. In some embodiments, the logic level detection circuit 126 may be a digital logic buffer, a comparator, or other circuitry that can be used to detect logic levels, and this is not limited thereto. In some embodiments, during the initial setting (configuration vector detection) phase, the configuration detection circuit 120 determines the logic level based on the detected logic value V at each step. LL (For example, high or low logic) to determine the configuration vector. In some embodiments, during initial setup (configuration vector detection), the configuration detection circuit 120 disconnects the output driver 124 from the configuration pin 102 and connects the input of the logic level detection circuit 126 to the configuration pin 102, so that the logic level detection circuit 126 detects the potential of the configuration pin 102 and outputs a detection logic value V. LL (For example, the zeroth detection logic value).

[0016] In some embodiments, during initial setup (configuration vector detection), the configuration detection circuit 120 controls the connection between the internal pull-up resistor R1 and the internal pull-down resistor R0 and the configuration pin 102. In some embodiments, during initial setup (configuration vector detection), the configuration detection circuit 120 sequentially connects the internal pull-up resistor R1 and the internal pull-down resistor R0 to the configuration pin 102, so that the logic level detection circuit 126 detects the potential of the configuration pin 102 and outputs a detection logic value V. LL (For example, multiple detection logic values), and then determine the configuration vector based on the output of the logic level detection circuit 126.

[0017] In some embodiments, the configuration detection circuit 120 includes logic circuit 122, which controls switches S0, S1, S2, and S3. In some embodiments, the configuration detection circuit 120 further includes switches S0, S1, and S3. In some embodiments, switch S0 is electrically connected between an internal pull-down resistor R0 and a configuration pin 102. In some embodiments, switch S0 is used to receive a control signal EN_R0 to turn on or off according to the control signal EN_R0. In some embodiments, switch S0 connects or disconnects the internal pull-down resistor R0 from the configuration pin 102 according to the control signal EN_R0. In some embodiments, logic circuit 122 may be implemented using combinational logic circuit and / or sequential logic circuit. In some embodiments, logic circuit 122 is electrically connected to the internal pull-up resistor R1, the internal pull-down resistor R0, the control terminals of switches S0-S3, and the output terminal of logic level detection circuit 126. In some embodiments, logic circuit 122 is used to generate and provide control signals EN_R1, EN_R0, EN_OD and EN_LB to the control terminals of switches S0 to S3, so as to control switches S0 to S3 to be turned on or off respectively.

[0018] In some embodiments, switch S1 is electrically connected between internal pull-up resistor R1 and configuration pin 102. In some embodiments, switch S1 is used to receive control signal EN_R1 to turn on or off according to control signal EN_R1. In some embodiments, switch S1 connects or disconnects internal pull-up resistor R1 from configuration pin 102 according to control signal EN_R1.

[0019] In some embodiments, switch S2 is electrically connected between the output terminal of output driver 124 and configuration pin 102. In some embodiments, switch S2 is used to receive control signal EN_OD to turn on or off according to control signal EN_OD. In some embodiments, switch S2 connects or disconnects the output terminal of output driver 124 from configuration pin 102 according to control signal EN_OD. In some embodiments, during idle period, switch S2 connects or disconnects the output terminal of output driver 124 from configuration pin 102 according to control signal EN_OD; and during initial setting (configuration vector detection), switch S2 disconnects the output terminal of output driver 124 from configuration pin 102 according to control signal EN_OD.

[0020] In some embodiments, switch S3 is electrically connected between the input of logic level detection circuit 126 and configuration pin 102. In some embodiments, switch S3 is used to receive control signal EN_LB to turn on or off according to control signal EN_LB. In some embodiments, switch S3 connects or disconnects the input of logic level detection circuit 126 from configuration pin 102 according to control signal EN_LB. In some embodiments, during idle period, switch S3 disconnects the input of logic level detection circuit 126 from configuration pin 102 according to control signal EN_LB; and during initial setting (configuration vector detection), switch S3 connects the input of logic level detection circuit 126 to configuration pin 102 according to control signal EN_LB.

[0021] In some embodiments, the internal pull-up resistor R1 and the internal pull-down resistor R0 are variable resistors, and the logic circuit 122 is used to generate and provide control signals ADJ_R1 and ADJ_R0 to the internal pull-up resistor R1 and the internal pull-down resistor R0, respectively, to control the resistance values ​​of the internal pull-up resistor R1 and the internal pull-down resistor R0.

[0022] In some embodiments, the logic level detection circuit 126 outputs a detection logic value V based on the potential of the configuration pin 102. LL The logic circuit 122 is connected to the logic level detection circuit 126 so that the logic circuit 122 determines the configuration vector based on the output of the logic level detection circuit 126.

[0023] Please see Figures 2A to 2D , Figures 2A to 2D This is a schematic diagram illustrating vector detection operations 200, 201, 210, and 211 of a chip 110 supporting a two-bit configuration according to some embodiments of this disclosure. In some embodiments, Figures 2A to 2D Chip 110 corresponds to Figure 1 Chip 110. (The last part appears to be incomplete and possibly refers to a different chip or component.) Figures 2A to 2DIn some embodiments, chip 110 is adapted for a 2-bit pin strapping configuration. In some embodiments, the 2-bit pin strapping configuration allows four configurations (e.g.,

[00] ,

[01] ,

[10] , and

[11] ).

[0024] In the two-bit configuration embodiment, the resistance value R1 of the internal pull-up resistor R1 of chip 110 is R R1 and the resistance value R of the internal pull-down resistor R0 R0 It can be fixed to the resistance value R A In some embodiments, the configuration vector is a one- or two-bit configuration vector that depends on the resistance value of the external resistor and the voltage at a reference voltage terminal connected to the external resistor. Figures 2A to 2D In some embodiments, the resistance values ​​of the external resistors Rext00, Rext01, Rext10, and Rext11 are each selected from two given resistance values ​​(e.g., 1 kΩ and 128 kΩ), and the resistance values ​​of the internal pull-down resistor R0 and the internal pull-up resistor R1 are within the range of the two given resistance values. In some embodiments, in a two-bit configuration, Figure 2A The external resistor Rext00 shown and Figure 2C Each of the external resistors Rext10 shown is an external pull-down resistor, corresponding to the external resistor Rext0, and Figure 2B The external resistor Rext01 shown and Figure 2D Each of the external resistors Rext11 shown is an external pull-up resistor, corresponding to external resistor Rext1. In some embodiments, the resistance value R of external resistor Rext00 is... 00 and the resistance value R of the external resistor Rext01 01 It can be made from a resistance value R. A A given resistance value is implemented, and the resistance value R of the external resistor Rext10 is... 10 and the resistance value R of the external resistor Rext11 11 It can be made from a resistance value greater than R. A Another given resistance value is implemented. Thus, the resistance value of the external resistor connected to the configuration pin 102 of the detection chip 110 is greater than or less than the resistance value R. A And the external resistor is electrically connected to the reference voltage terminal VDD. ext1 External pull-up resistor or electrical connection to the reference voltage terminal VDD ext0 An external pull-down resistor can be used to detect a two-bit configuration vector (e.g.,

[00] ,

[01] ,

[10] , or

[11] ).

[0025] like Figure 2AAs shown, in vector detection operation 200, the external resistor Rext00 electrically connects the configuration pin 102 of chip 110 to the reference voltage terminal VDD. ext0 In some embodiments, the vector detection operation 200 can configure the vector configuration chip 110 in a

[00] configuration.

[0026] In the zeroth step of vector detection operation 200, switches S0 and S1 disconnect the internal pull-down resistor R0 and internal pull-up resistor R1 from the configuration pin 102, since the external resistor Rext00 connects the configuration pin 102 to the reference voltage terminal VDD. ext0 (For example, 0 volts), the potential of configuration pin 102 is pulled down (external resistor Rext00 can be considered as an external pull-down resistor), and logic level detection circuit 126 outputs the zeroth detection logic value. When external resistor Rext00 is an external pull-down resistor, the zeroth detection logic value is a low logic level L. L .

[0027] In the first step of vector detection operation 200, switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, and switch S1 pulls the internal pull-up resistor R1 (whose resistance value R) back up. R1 The resistance value R A It is connected to configuration pin 102, due to the resistance value R of external resistor Rext00. 00 Less than the resistance value R A Furthermore, the external resistor Rext00 connects the configuration pin 102 to the reference voltage terminal VDD. ext0 (For example, 0 volts), the potential of configuration pin 102 is pulled down, and logic level detection circuit 126 outputs a first detection logic value (for example, low logic level L). L ).

[0028] In the second step of vector detection operation 200, switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, and switch S0 pulls the internal pull-down resistor R0 (whose resistance value R) to the configuration pin 102. R0 The resistance value R A When connected to configuration pin 102, external resistor Rext00 connects configuration pin 102 to the reference voltage terminal VDD. ext0 (For example, 0 volts), together with the internal pull-down resistor R0, provides the pull-down function, so the potential of the configuration pin 102 is pulled down, and the logic level detection circuit 126 outputs the second detection logic value (for example, low logic level L). L ).

[0029] In some embodiments, if the external resistor Rext00 is an external pull-down resistor and the resistance value R of the external resistor Rext00 is... 00 Less than the resistance value RA Through the zeroth to the second step of the vector detection operation 200, logic circuit 122 can obtain the triplet (L L L L L L ),like Figure 2A As shown. In some embodiments, the triplet (L L L L L L The configuration vector is defined as a first binary value, for example, 00. In some embodiments, the first binary value represents that the external resistor Rext00 is an external pull-down resistor and that the external resistor Rext00 has a first given resistance value, wherein the first given resistance value is less than the resistance values ​​of the internal pull-up resistor R1 and the internal pull-down resistor R0 (e.g., resistance value R). A ).

[0030] like Figure 2B As shown, in vector detection operation 201, the external resistor Rext01 electrically connects the configuration pin 102 of chip 110 to the reference voltage terminal VDD. ext1 In some embodiments, the vector detection operation 201 can configure the chip 110 with a configuration vector of

[01] .

[0031] In the zeroth step of vector detection operation 201, switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102, since the external resistor Rext01 connects the configuration pin 102 to the reference voltage terminal VDD. ext1 (For example, 3.3 volts), the potential of configuration pin 102 is pulled up (external resistor Rext01 can be considered as an external pull-up resistor), and logic level detection circuit 126 outputs the zeroth detection logic value. When external resistor Rext01 is an external pull-up resistor, the zeroth detection logic value is a high logic level L. H .

[0032] In the first step of vector detection operation 201, switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, and switch S1 pulls the internal pull-up resistor R1 (whose resistance value R) back up. R1 The resistance value R A When connected to configuration pin 102, external resistor Rext01 connects configuration pin 102 to the reference voltage terminal VDD. ext1 (For example, 3.3 volts), together with the internal pull-up resistor R1, provides a pull-up function, so the potential of the configuration pin 102 is pulled up, and the logic level detection circuit 126 outputs the first detection logic value (for example, high logic level L). H ).

[0033] In the second step of vector detection operation 201, switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, and switch S0 pulls the internal pull-down resistor R0 (whose resistance value R) to the configuration pin 102. R0 The resistance value R A It is connected to configuration pin 102, due to the resistance value R of external resistor Rext01. 01 Less than the resistance value R A Furthermore, the external resistor Rext01 connects the configuration pin 102 to the reference voltage terminal VDD. ext1 (For example, 3.3 volts), the potential of configuration pin 102 is pulled up, and logic level detection circuit 126 outputs a second detection logic value (for example, high logic level L). H ).

[0034] In some embodiments, if the external resistor Rext01 is an external pull-up resistor and the resistance value R of the external resistor Rext01 is... 01 Less than the resistance value R A Through the zeroth to the second step of vector detection operation 201, logic circuit 122 can obtain triples (L... H L H L H ),like Figure 2B As shown. In some embodiments, the triplet (L H L H L H The configuration vector is defined as a second binary value, for example, 01. In some embodiments, the second binary value represents that the external resistor Rext01 is an external pull-up resistor and that the external resistor Rext01 has a first given resistance value, wherein the first given resistance value is less than the resistance values ​​of the internal pull-up resistor R1 and the internal pull-down resistor R0 (e.g., resistance value R...). A ).

[0035] like Figure 2C As shown, in vector detection operation 210, external resistor Rext10 electrically connects the configuration pin 102 of chip 110 to the reference voltage terminal VDD. ext0 In some embodiments, the vector detection operation 210 can configure the chip 110 with a configuration vector of

[10] .

[0036] In the zeroth step of vector detection operation 210, switches S0 and S1 disconnect the internal pull-down resistor R0 and internal pull-up resistor R1 from the configuration pin 102, since the external resistor Rext10 connects the configuration pin 102 to the reference voltage terminal VDD. ext0(For example, 0 volts), the potential of configuration pin 102 is pulled down (external resistor Rext10 can be regarded as an external pull-down resistor), and logic level detection circuit 126 outputs the zeroth detection logic value (for example, low logic level L). L ).

[0037] In the first step of vector detection operation 210, switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, and switch S1 pulls the internal pull-up resistor R1 (whose resistance value R) back up. R1 The resistance value R A It is connected to configuration pin 102, due to the resistance value R. A The resistance value R is less than the external resistance Rext10. 10 Furthermore, the internal pull-up resistor R1 connects the configuration pin 102 to the reference voltage terminal VDD. int1 (For example, 3.3 volts), the potential of configuration pin 102 is pulled up, and logic level detection circuit 126 outputs a first detection logic value (for example, high logic level L). H ).

[0038] In the second step of vector detection operation 210, switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, and switch S0 pulls the internal pull-down resistor R0 (whose resistance value R) to the configuration pin 102. R0 The resistance value R A When connected to configuration pin 102, external resistor Rext10 connects configuration pin 102 to the reference voltage terminal VDD. ext0 (For example, 0 volts), the configuration pin 102 is connected to the reference voltage terminal VDD via an internal pull-down resistor R0. int0 (For example, 0 volts), so the potential of configuration pin 102 is pulled down together, and logic level detection circuit 126 outputs a second detection logic value (for example, low logic level L). L ).

[0039] In some embodiments, if the external resistor Rext10 is an external pull-down resistor and the resistance value R of the external resistor Rext10 is... 10 Greater than the resistance value R A Through the zeroth to the second step of vector detection operation 210, logic circuit 122 can obtain triples (L... L L H L L ),like Figure 2C As shown. In some embodiments, the triplet (L L L H L LThe configuration vector is defined as a third binary value, for example, 10. In some embodiments, the third binary value represents that the external resistor Rext10 is an external pull-down resistor and that the external resistor Rext10 has a second given resistance value, wherein the second given resistance value is greater than the resistance values ​​of the internal pull-up resistor R1 and the internal pull-down resistor R0 (e.g., resistance value R...). A ).

[0040] like Figure 2D As shown, in vector detection operation 211, the external resistor Rext11 electrically connects the configuration pin 102 of chip 110 to the reference voltage terminal VDD. ext1 In some embodiments, the vector detection operation 211 can configure the chip 110 with the configuration vector of

[11] .

[0041] In the zeroth step of vector detection operation 211, switches S0 and S1 disconnect the internal pull-down resistor R0 and internal pull-up resistor R1 from the configuration pin 102, since the external resistor Rext11 connects the configuration pin 102 to the reference voltage terminal VDD. ext1 (For example, 3.3 volts), the potential of configuration pin 102 is pulled up (external resistor Rext11 can be regarded as an external pull-up resistor), and logic level detection circuit 126 outputs the zeroth detection logic value (for example, high logic level L). H ).

[0042] In the first step of vector detection operation 211, switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, and switch S1 pulls the internal pull-up resistor R1 (whose resistance value R) back up. R1 The resistance value R A When connected to configuration pin 102, external resistor Rext11 connects configuration pin 102 to the reference voltage terminal VDD. ext1 (For example, 3.3 volts), and the internal pull-up resistor R1 connects the configuration pin 102 to the reference voltage terminal VDD. int1 (For example, 3.3 volts), so the potential of configuration pin 102 is pulled up together, and logic level detection circuit 126 outputs the first detection logic value (for example, high logic level L). H ).

[0043] In the second step of vector detection operation 210, switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, and switch S0 pulls the internal pull-down resistor R0 (whose resistance value R) to the configuration pin 102. R0 The resistance value R A It is connected to configuration pin 102, due to the resistance value R. A The resistance value R is less than the external resistance Rext11. 11The internal pull-down resistor R0 connects the configuration pin 102 to the reference voltage terminal VDD. int0 (For example, 0 volts), the potential of configuration pin 102 is pulled down, and logic level detection circuit 126 outputs a second detection logic value (for example, low logic level L). L ).

[0044] In some embodiments, if the external resistor Rext11 is an external pull-up resistor and the resistance value R of the external resistor Rext11 is... 11 Greater than the resistance value R A Through the zeroth to the second step of vector detection operation 211, logic circuit 122 can obtain triples (L... H L H L L ),like Figure 2D As shown. In some embodiments, the triplet (L H L H L L The configuration vector is defined as a fourth binary value, for example, 11. In some embodiments, the fourth binary value represents that the external resistor Rext11 is an external pull-up resistor and that the external resistor Rext11 has a second given resistance value, wherein the second given resistance value is greater than the resistance values ​​of the internal pull-up resistor R1 and the internal pull-down resistor R0 (e.g., resistance value R...). A ).

[0045] Thus, triples can be obtained through vector detection operations 200, 201, 210 or 211, and binary values ​​can be obtained based on the triples, thereby configuring chip 110 with a two-bit configuration vector.

[0046] Please see Figures 1 to 3 , Figure 3 This is a schematic diagram showing the resistance values ​​of the internal pull-up resistor R1, the internal pull-down resistor R0, and the external resistor Rext1 or Rext0 of a configuration detection system 100 supporting two-bit configuration according to some embodiments of this disclosure. In some embodiments, the resistance value of the internal pull-up resistor R1 is R... R1 and the resistance value R of the internal pull-down resistor R0 R0 Fixed to the resistance value R A And the resistance value R A It can be implemented with 32 kΩ. In some embodiments, the external resistor Rext1 is an external pull-up resistor (e.g., Figure 2B as well as Figure 2D The external resistors Rext01 and Rext11), and the external resistor Rext0 is an external pull-down resistor (e.g., Figure 2A as well as Figure 2CThe external resistors Rext00 and Rext10). In some embodiments, the resistance value R of the external resistor Rext00 is... 00 and the resistance value R of the external resistor Rext01 01 It is less than the resistance value R A The given resistance value (e.g., 1 kΩ) is implemented, and the resistance value R of the external resistor Rext10 is... 10 and the resistance value R of the external resistor Rext11 11 It is greater than the resistance value R A Implemented with a given resistance value (e.g., 128 kΩ).

[0047] In some embodiments, based on Figure 1 , Figures 2A to 2D as well as Figure 3 The two-bit configuration vectors obtained by the vector detection operations 200, 201, 210, and 211 can be represented by the following Table 1.

[0048]

[0049] Table 1

[0050] Please see Figure 4A as well as Figure 4B , Figures 4A to 4B This is a schematic diagram of vector detection operations 400a and 400b of a chip 110 supporting multi-bit configurations according to some embodiments of this disclosure. In some embodiments, Figure 4A as well as Figure 4B Chip 110 is suitable for multi-bit pin strapping configuration. In some embodiments, the multi-bit pin strapping configuration allows at least eight configurations of three bits (e.g.,

[000] ,

[001] ,

[010] ,

[011] ,

[100] ,

[101] ,

[110] , and

[111] ).

[0051] In the multi-bit configuration embodiment, the internal pull-up resistor R1 and internal pull-down resistor R0 of chip 110 are variable resistors, and the resistance value R of the internal pull-up resistor R1 is... R1 and the resistance value R of the internal pull-down resistor R0 R0 The resistance can be adjusted to multiple preset values. In some embodiments, the configuration vector is a multi-bit configuration vector that depends on the resistance value of the external resistor and the voltage at a reference voltage terminal connected to the external resistor. Figures 4A to 4BIn some embodiments, the resistance values ​​of the external resistors Rpd and Rpu are selected from a plurality of given resistance values, wherein the plurality of given resistance values ​​are 250 ohms, 4 kiloohms, 64 kiloohms, and 1 megaohm. In some embodiments, the resistance values ​​of the external resistors Rpd and Rpu are selected from a plurality of given resistance value ranges, wherein the plurality of preset resistance values ​​and the plurality of given resistance value ranges are interleaved, and wherein the upper limit of the largest of the plurality of given resistance value ranges is less than the largest of the plurality of preset resistance values. In some embodiments, the center values ​​of the plurality of given resistance value ranges are 250 ohms, 4 kiloohms, 64 kiloohms, and 1 megaohm, respectively. In some embodiments, Figure 4A The external resistance Rpd corresponds to Figure 1 The external resistor Rext0, and Figure 4B The external resistance Rpu corresponds to Figure 1 The external resistor Rext1. Thus, by detecting whether the resistance value of the external resistor connected to the configuration pin 102 of chip 110 is greater than or less than the preset resistance value of the plurality of internal pull-up or pull-down resistors, and whether the external resistor is an external pull-up resistor or an external pull-down resistor, a multi-bit configuration vector can be generated.

[0052] like Figure 4A As shown, in vector detection operation 400a, the external resistor Rpd electrically connects the configuration pin 102 of chip 110 to the reference voltage terminal VDD. ext0 In some embodiments, the vector detection operation 400a can configure the chip 110 with a configuration vector of any of

[000] ,

[010] ,

[100] and

[110] .

[0053] In the zeroth step of the vector detection operation 400a, switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102, since the external resistor Rpd connects the configuration pin 102 to the reference voltage terminal VDD. ext0 (For example, 0 volts), the potential of configuration pin 102 is pulled down (external resistor Rpd can be regarded as an external pull-down resistor), and the logic level detection circuit 126 outputs a low logic level L. L .

[0054] In some embodiments, when switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102, and the logic level detection circuit 126 outputs a low logic level L... LWhen the external resistor connected to the configuration pin 102 is identified as an external pull-down resistor, the configuration vector can be determined based on the adjusted resistance value of the internal pull-up resistor R1 in subsequent operations. Therefore, the connection between the internal pull-up resistor R1 and the configuration pin 102 can be maintained in subsequent operations, while the connection between the internal pull-down resistor R0 and the configuration pin 102 can be maintained as open.

[0055] In some embodiments, when switch S1 connects the internal pull-up resistor R1 to configuration pin 102 and switch S0 disconnects the internal pull-down resistor R0 from configuration pin 102, if the resistance value R of the internal pull-up resistor R1 is R R1 The resistance value R is less than the external resistance Rpd. Rpd The preset resistance value R A1 When the potential of configuration pin 102 is pulled up, the logic level detection circuit 126 outputs a high logic level L. H .

[0056] Next, the resistance value R of the internal pull-up resistor R1 is increased. R1 Adjust to the preset resistance value R A2 If the preset resistance value R A2 The resistance value R is less than the external resistance Rpd. Rpd When the potential of configuration pin 102 is pulled up, the logic level detection circuit 126 outputs a high logic level L. H .

[0057] In some embodiments, the resistance value R of the internal pull-up resistor R1 is... R1 Gradually adjust / increase the resistance value to R using multiple preset resistance values. An Until the logic level detection circuit 126 outputs a low logic level L L In some embodiments, the logic level detection circuit 126 outputs a low logic level L. L Represents the resistance value R An Greater than the external resistance R pd resistance value R Rpd This pulls down the potential of configuration pin 102.

[0058] Thus, if the external resistor Rpd is an external pull-down resistor, through vector detection operation 400a, logic circuit 122 can obtain the corresponding (n+1) tuple (L L L H ...L H L L Configuration vectors, such as Figure 4A As shown. In some embodiments, the resistance value R is adjusted according to the internal pull-up resistor R1 corresponding to the (n+1)th tuple / logic level. An Then the resistance value R of the external resistor Rpd can be obtained. RpdThe interval in which it is located (e.g., the upper and lower bounds of the interval / boundary), and thus based on the external resistance R. pd resistance value R Rpd The interval in which the configuration vector is located is used to configure the function or behavior of chip 110. In some embodiments, based on Figure 4A The multi-bit configuration vector obtained by the vector detection operation 400a can be represented by the following Table 2.

[0059]

[0060] Table 2

[0061] In some embodiments, the resistance values ​​1kΩ, 16kΩ, 256kΩ, and 4MΩ are the resistance values ​​R of the external pull-down resistors. Rpd The given resistance values ​​are 250Ω, 4kΩ, 64kΩ and 1MΩ with upper limits.

[0062] like Figure 4B As shown, in the vector detection operation 400b, the external resistor Rpu electrically connects the configuration pin 102 of chip 110 to the reference voltage terminal VDD. ext1 In some embodiments, the vector detection operation 400b can configure the chip 110 with a configuration vector of any of

[001] ,

[011] ,

[101] and

[111] .

[0063] In the zeroth step of the vector detection operation 400b, switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102, since the external resistor Rpu connects the configuration pin 102 to the reference voltage terminal VDD. ext1 (For example, 3.3 volts), the potential of configuration pin 102 is pulled up (external resistor Rpu can be regarded as an external pull-up resistor), and logic level detection circuit 126 outputs a high logic level L. H .

[0064] In some embodiments, when switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102, and the logic level detection circuit 126 outputs a high logic level L... H When the external resistor connected to the configuration pin 102 is identified as an external pull-up resistor, the configuration vector can be determined based on the adjusted resistance value of the internal pull-down resistor R0 in subsequent operations. Therefore, the connection between the internal pull-down resistor R0 and the configuration pin 102 can be maintained in subsequent operations, while the connection between the internal pull-up resistor R1 and the configuration pin 102 can be maintained as open.

[0065] In some embodiments, when switch S0 connects the internal pull-down resistor R0 to configuration pin 102 and switch S1 disconnects the internal pull-up resistor R1 from configuration pin 102, if the resistance value R of the internal pull-down resistor R0 is... R0 The resistance value R is less than the external resistance Rpu. Rpu The preset resistance value R A1 When the potential of configuration pin 102 is pulled down, the logic level detection circuit 126 outputs a low logic level L. L .

[0066] Next, the resistance value R of the internal pull-down resistor R0 is... R0 Adjust to the preset resistance value R A2 If the preset resistance value R A2 The resistance value R of the external resistor Rpu is less than the resistance value R of the external resistor Rpu. Rpu When the potential of configuration pin 102 is pulled down, the logic level detection circuit 126 outputs a low logic level L. L .

[0067] In some embodiments, the resistance value R of the internal pull-down resistor R0 is... R0 Gradually adjust / increase the resistance value to R using multiple preset resistance values. An Until the logic level detection circuit 126 outputs a high logic level L H In some embodiments, the logic level detection circuit 126 outputs a high logic level L. H Represents the resistance value R An The resistance value R of the external resistor Rpu is greater than the resistance value R. Rpu This pulls up the potential of configuration pin 102.

[0068] Thus, if the external resistor Rpu is an external pull-up resistor, through vector detection operation 400b, logic circuit 122 can obtain the corresponding (n+1) tuple (L H L L ...L L L H Configuration vectors, such as Figure 4B As shown. In some embodiments, the resistance value R is adjusted according to the internal pull-down resistor R0 corresponding to the (n+1)th tuple / logic level. An Then the resistance value R of the external resistor Rpu can be obtained. Rpu The interval in which the resistance value of the external resistor Rpu is located (e.g., the upper and lower bounds of the interval / boundary) is determined, thereby determining the configuration vector based on the interval in which the resistance value of the external resistor Rpu is located, and then configuring the function or behavior of the chip 110. In some embodiments, based on Figure 4B The multi-bit configuration vector obtained by the vector detection operation 400b can be represented by the following Table 3.

[0069]

[0070] Table 3

[0071] In some embodiments, the resistance values ​​1kΩ, 16kΩ, 256kΩ, and 4MΩ are the upper bounds of the given resistance values ​​250Ω, 4kΩ, 64kΩ, and 1MΩ, respectively, where any one of the given resistance values ​​250Ω, 4kΩ, 64kΩ, and 1MΩ can be the resistance value R of the external pull-up resistor. Rpu Thus, the multi-bit configuration vector can be obtained based on Tables 2 and 3 above.

[0072] In some embodiments, the detection circuit 120 is further configured to gradually adjust the resistance value R of the internal pull-up resistor R1. R1 and the resistance value R of the internal pull-down resistor R0 R0 Up to multiple preset resistance values ​​(e.g., preset resistance value R) A1 ~R An The internal pull-up resistor R1 and internal pull-down resistor R0 are sequentially connected to the configuration pin 102 under the multiple preset resistor values, so that the logic level detection circuit 126 outputs the multiple detection logic values, and determines the configuration vector based on the multiple detection logic values ​​(and the zeroth detection logic value). In some embodiments, if the configuration pin 102 is connected to an external resistor Rpd, the output of the logic level detection circuit 126 can be represented by Table 4 below based on the above method.

[0073]

[0074] Table 4

[0075] In some embodiments, if pin 102 is configured to be connected to an external resistor Rpu, the output of the logic level detection circuit 126 can be represented by Table 5 below based on the above method.

[0076]

[0077]

[0078] Table 5

[0079] In some implementations, when the external resistor is disconnected from configuration pin 102 (i.e., configuration pin 102 is not connected to any external resistor) and configuration pin 102 is a floating pin, configuration detection circuit 120 determines that the configuration vector is a preset value based on the plurality of detection logic values. For example, if configuration pin 102 is not connected to any external resistor, the resistance value of configuration pin 102 is infinitely large, exceeding the largest of the preset resistance values ​​of internal pull-up resistor R1 and / or internal pull-down resistor R0. In this case, the output of logic level detection circuit 126 can be represented by Table 6 below.

[0080]

[0081]

[0082] Table 6

[0083] Thus, by not connecting any external resistors to configuration pin 102, a larger set of configuration vectors (e.g., preset values) can be configured, thereby reducing material costs.

[0084] Please see Figure 1 , Figures 4A to 4B as well as Figure 5 , Figure 5 The resistance value R of the internal pull-up resistor R1 of the configuration detection system 100 supporting multi-bit configuration according to some embodiments of this disclosure is... R1 The resistance value R of the internal pull-down resistor R0 R0 And the resistance value R of the external resistor Rpu Rpu and external resistance R pd resistance value R Rpd A schematic diagram is shown. In some embodiments, the internal pull-up resistor R1 and the internal pull-down resistor R0 are variable resistors. In some embodiments, the resistance value R of the internal pull-up resistor R1 is... R1 It can be maintained at a fixed value or change over time. In some embodiments, the resistance value R of the internal pull-up resistor R1 is... R1 It is a variable, and the variable can be multiple preset resistance values ​​R. A1 ~R A4 At least one of them. In some embodiments, the resistance value R of the internal pull-up resistor R1 is... R1 The resistance value can be changed within a range between a minimum value and a maximum value, the range of which includes multiple preset resistance values ​​R. A1 ~R A4 In some embodiments, the resistance value R of the internal pull-down resistor R0 is... R0 It can be maintained at a fixed value or change over time. In some embodiments, the resistance value R of the internal pull-down resistor R0 is... R0 It is a variable, and the variable can be multiple preset resistance values ​​R. A1 ~R A4 At least one of them. In some embodiments, the resistance value R of the internal pull-down resistor R0 is... R0 The resistance value can be changed within a range between a minimum value and a maximum value, the range of which includes multiple preset resistance values ​​R. A1 ~R A4 In some embodiments, the external resistor Rext1 is an external pull-up resistor (e.g., Figure 4B The external resistor Rpu), and the external resistor Rext0 is an external pull-down resistor (e.g., Figure 4AThe external resistor Rpd). In some embodiments, the resistance value R of the external resistor Rpu is... Rpu It is selected from a plurality of given resistance values, and each of these given resistance values ​​is selected from a corresponding range of given resistance values ​​(e.g., ...). Figure 5 (The numerical range shown is within the dashed box). In some embodiments, the resistance value Rpd of the external resistor is... Rpd It is selected from a plurality of given resistance values, and each of these given resistance values ​​is selected from a corresponding range of given resistance values ​​(e.g., ...). Figure 5 The numerical range shown in the dashed box. In some embodiments, the multiple given resistance values ​​(e.g., 250 ohms, 4K ohms, 64K ohms, and 1M ohms), and the multiple given resistance value ranges (e.g., ... Figure 5 The numerical range shown in the dashed box is interleaved with the aforementioned preset resistance value, so that the preset resistance value can become the boundary of the given resistance value (e.g., the upper and / or lower boundary of the boundary / interval).

[0085] Please see Figure 6 , Figure 6 This is a flowchart of a method 600 for detecting the configuration vector of chip 110 according to some embodiments of the present disclosure. In some embodiments, the detection method 600 includes steps S610 to S660. In some embodiments, steps S610 to S660 may be performed by a configuration detection circuit 120. In some embodiments, the configuration detection circuit 120 may perform steps S610 to S660 via hardware and / or software, and this invention is not limited thereto.

[0086] In step S610, during the idle period, a control signal is provided according to the function mode.

[0087] In step S620, during the initial setup, the output driver is disconnected from the configuration pin, and the logic level detection circuit is connected to the configuration pin.

[0088] In step S630, the resistance value of the internal resistor is set or adjusted, and the connection between the internal resistor and the configuration pin is set or adjusted.

[0089] In step S640, the detection logic value corresponding to the potential of the configuration pin is detected and recorded.

[0090] In step S650, determine whether sufficient information has been collected to determine the configuration vector. If yes, proceed to step S660; otherwise, proceed to step S630.

[0091] In step S660, the configuration vector is latched.

[0092] In summary, the chip 110 disclosed herein can be configured with a two-bit or multi-bit configuration vector via a single configuration pin 102, thereby reducing the number of chip pins and lowering material costs.

[0093] In a multi-bit configuration embodiment, if the internal pull-up resistor R1 of chip 110 is absent or disconnected, this condition is electrically equivalent to the resistance value R of the internal pull-up resistor R1. R1 Extremely large (or infinitely large). At this time, the resistance value R of the internal pull-down resistor R0 is... R0 The external resistor Rext1 corresponds to Figure 4B The resistor Rpu is tested, and referring to the steps / operations in the embodiments described in Table 3 above, the results shown in Table 7 below can be obtained. At this time, the external resistor Rext0 is not needed, and the resistance value of the external resistor Rext0 is equivalent to a maximum (or infinite). A binary configuration can still be obtained under this condition. Therefore, the absence of the internal pull-up resistor R1 and the external resistor Rext0 is a special case and within the scope of this invention.

[0094]

[0095] Table 7

[0096] In a multi-bit configuration embodiment, if the internal pull-down resistor R0 of chip 110 is absent or disconnected, this condition is electrically equivalent to the resistance value R of the internal pull-down resistor R0. R0 Extremely large (or infinitely large). At this time, the resistance value R of the internal pull-up resistor R1 is extremely large. R1 When paired with an external resistor Rext0, it corresponds to Figure 4A The resistor Rpd is tested, and referring to the steps / operations in the embodiments related to Table 2 above, the results shown in Table 8 below can be obtained. At this time, the external resistor Rext1 is not needed, and the resistance value of the external resistor Rext1 is equivalent to a maximum (or infinite). A binary configuration can still be obtained under this condition. Therefore, the absence of the internal pull-down resistor R0 and the external resistor Rext1 is a special case and within the scope of this invention.

[0097]

[0098] Table 8

[0099] Although in the embodiments disclosed herein, the configuration detection circuit 120 can control the switch S3 to be connected or disconnected, connecting the input terminal of the logic level detection circuit 126 to the configuration pin 102, or disconnecting the input terminal of the logic level detection circuit 126 from the configuration pin 102, in practice, depending on the requirements, it can be designed so that the input terminal of the logic level detection circuit 126 is always connected to the configuration pin 102. In this case, the circuit controlling the switch S3 does not exist, or the switch S3 is always connected. In this case, the configuration detection circuit 120 does not need to control the connection or disconnection of the switch S3, and it does not hinder configuration detection. Therefore, in the embodiments disclosed herein, the description of the existence and function of the switch S3, and the description of the configuration detection circuit 120 controlling the switch S3, are not intended to limit this disclosure.

[0100] Although in the embodiments disclosed herein, the configuration detection circuit 120 can control the switch S2 to be connected or disconnected, thereby connecting or disconnecting the output terminal of the output driver 124 from the configuration pin 102, in practice, depending on the definition and functional requirements of the configuration pin 102, the output driver 124 or other circuits that would create a resistive load on the configuration pin 102 may not exist, or the output terminal of the output driver 124 may be designed to always be disconnected from the configuration pin 102. In this case, the configuration detection circuit 120 does not need to control the connection or disconnection of the switch S2, and this does not hinder configuration detection. Therefore, in the embodiments disclosed herein, the description of the existence and function of the output driver 124 and the switch S2, and the description of the configuration detection circuit 120 controlling the switch S2, are not intended to limit this disclosure.

[0101] Referring to the description of the vector detection operation 400a in the foregoing embodiment, when the resistance value of the internal pull-up resistor R1 is R R1 Equal to the maximum preset resistance value R A4 At that time, the resistance value R of the internal pull-up resistor R1 is... R1 For each given resistance value greater than the external resistance Rpd, the logic level detection circuit 126 outputs a low logic level L. L When the external resistor connected to the configuration pin 102 is determined to be an external pull-down resistor, the internal pull-up resistor R1 is set to the maximum preset resistance value. When this maximum preset resistance value is greater than each given resistance value of the external resistor Rpd, the output of the logic level detection circuit 126 is equivalent to the result of step zero, as shown in Table 9 below.

[0102]

[0103] Table 9

[0104] Referring to the description of the vector detection operation 400b in the foregoing embodiment, when the resistance value R of the internal pull-down resistor R0 is R R0 Equal to the maximum preset resistance value R A4At that time, the resistance value R of the internal pull-down resistor R0 is... R0 For each given resistance value greater than the external resistor Rpu, the logic level detection circuit 126 outputs a high logic level L. H When the external resistor connected to the configuration pin 102 is determined to be an external pull-up resistor, the internal pull-down resistor R0 is set to the maximum preset resistance value. When this maximum preset resistance value is greater than each given resistance value of the external resistor Rpu, the output of the logic level detection circuit 126 is equivalent to the result of step zero, as shown in Table 10 below.

[0105]

[0106]

[0107] Table 10

[0108] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the art may make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0109] [Symbol Explanation]

[0110] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying symbols are explained as follows:

[0111] 100: Configure the detection system

[0112] 102: Configuration pin

[0113] 110: Chip

[0114] 120: Configure detection circuit

[0115] 122: Logic Circuits

[0116] 124: Output Driver

[0117] 126: Logic Level Detection Circuit

[0118] 200,201,210,211,400a,400b: Vector detection operation

[0119] 600: Detection Method

[0120] R0, R1, Rpd, Rpu: Resistors

[0121] S0, S1, S2, S3: Switches

[0122] V LL :Detect logical value

[0123] L H High logic level

[0124] L L Low logic level

[0125] ADJ_R0, ADJ_R1: Control signals

[0126] EN_R0, EN_R1, EN_OD, EN_LB: control signal

[0127] VDD int1 VDD ext1 VDD int0 VDD ext0 Reference voltage terminal

[0128] Rext0, Rext1: External resistors

[0129] Rext00, Rext01, Rext10, Rext11: External resistors

[0130] R R1 ,R R0 ,R A ,R 00 ,R 01 ,R 10 ,R 11 Resistance value

[0131] R A1 ,R A2 ,R A3 ,R A4 ,R An ,R pd ,R pu ,R Rpd ,R Rpu Resistance value

[0132] S610, S620, S630, S640, S650, S660: Steps.

Claims

1. A chip comprising: A configuration pin is electrically connected to a reference voltage terminal via an external resistor; One internal pull-up resistor; One internal pull-down resistor; A logic level detection circuit; and A configuration detection circuit is electrically connected to the configuration pin, the internal pull-up resistor, the internal pull-down resistor, and the logic level detection circuit, wherein, The configuration detection circuit is used to connect the input of the logic level detection circuit to the configuration pin, and the configuration detection circuit is further used to: Disconnect the internal pull-up resistor and the internal pull-down resistor from the configuration pin so that the logic level detection circuit outputs a zeroth detection logic value. The internal pull-up resistor and the internal pull-down resistor are connected sequentially to the configuration pin to cause the logic level detection circuit to output multiple detection logic values; and A configuration vector is determined based on the zeroth detection logic value and the plurality of detection logic values.

2. The chip according to claim 1, wherein, The resistance value of the external resistor is selected from one of two given resistance values, and the resistance value of the internal pull-up resistor or the internal pull-down resistor is within the range of the two given resistance values.

3. The chip according to claim 1, wherein, The configuration vector is a two-bit configuration vector that depends on the resistance value of the external resistor and the voltage at the reference voltage terminal.

4. The chip according to claim 3, wherein, The detection circuit in this configuration is also used for: Connect the internal pull-up resistor to the configuration pin to cause the logic level detection circuit to output a first detection logic value; and Connect the internal pull-down resistor to the configuration pin to cause the logic level detection circuit to output a second detection logic value, wherein... If the zeroth detection logic value, the first detection logic value, and the second detection logic value are, in sequence, a low logic level, a low logic level, and a low logic level, then the configuration vector is a first binary value. If the zeroth detection logic value, the first detection logic value, and the second detection logic value are, in sequence, a high logic level, a high logic level, and a high logic level, then the configuration vector is a second binary value. If the zeroth detection logic value, the first detection logic value, and the second detection logic value are, in sequence, the low logic level, the high logic level, and the low logic level, then the configuration vector is a third binary value; and If the zeroth detection logic value, the first detection logic value, and the second detection logic value are, in sequence, the high logic level, the high logic level, and the low logic level, the configuration vector is a fourth binary value.

5. The chip according to claim 4, wherein: The first binary value represents that the external resistor is an external pull-down resistor and the external resistor has a first given resistance value, wherein the first given resistance value is less than the resistance value of the internal pull-up resistor and the internal pull-down resistor. The second binary value represents that the external resistor is an external pull-up resistor and that the external resistor has the first given resistance value; The third binary value represents that the external resistor is the external pull-down resistor and that the external resistor has a second given resistance value, wherein the second given resistance value is greater than the resistance values ​​of the internal pull-up resistor and the internal pull-down resistor; and The fourth binary value represents that the external resistor is the external pull-up resistor and that the external resistor has the second given resistance value.

6. The chip according to claim 1, wherein, The internal pull-up resistor and the internal pull-down resistor are variable resistors, and the configuration detection circuit is further used to: The internal pull-up resistor and the internal pull-down resistor are gradually adjusted to multiple preset resistance values. Under these multiple preset resistance values, the internal pull-up resistor and the internal pull-down resistor are sequentially connected to the configuration pin so that the logic level detection circuit outputs the multiple detection logic values ​​and determines the configuration vector based on the multiple detection logic values.

7. The chip according to claim 6, wherein, The configuration vector is a multi-bit configuration vector that depends on a resistance value of the external resistor and a voltage at the reference voltage terminal.

8. The chip according to claim 7, wherein, The resistance value of the external resistor is selected from a plurality of given resistance value ranges, wherein the plurality of preset resistance values ​​and the plurality of given resistance value ranges are interleaved, and wherein the upper limit of the largest of the plurality of given resistance value ranges is less than the largest of the plurality of preset resistance values.

9. A chip comprising: A configuration pin is electrically connected to a reference voltage terminal via an external resistor; One internal pull-up resistor; One internal pull-down resistor; A logic level detection circuit; and A detection circuit is configured to electrically connect the logic level detection circuit, the internal pull-up resistor, and the internal pull-down resistor, wherein, The internal pull-up resistor and the internal pull-down resistor are variable resistors, and the configuration detection circuit is used to: The internal pull-up resistor and the internal pull-down resistor are gradually adjusted to multiple preset resistance values. Under these multiple preset resistance values, the internal pull-up resistor and the internal pull-down resistor are sequentially connected to the configuration pin so that the digital logic level detection circuit outputs multiple detection logic values ​​and determines a configuration vector based on the multiple detection logic values.

10. The chip according to claim 9, wherein, The resistance value of the external resistor is selected from a plurality of given resistance values, wherein the values ​​of the plurality of preset resistance values ​​and the plurality of given resistance values ​​are interleaved, and wherein the largest of the plurality of given resistance values ​​is smaller than the largest of the plurality of preset resistance values.

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