A finite field modular operation acceleration implementation method for a RISC-V processor

By constructing an unsaturated multi-limb representation model and a delayed carry propagation mechanism on a RISC-V processor, the finite field operation of the SQIsign algorithm is optimized, solving the performance bottleneck of the RISC-V processor when executing the SQIsign algorithm, and achieving efficient acceleration of finite field operation and quantum security.

CN121966834BActive Publication Date: 2026-06-19NANJING UNIV OF POSTS & TELECOMM
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Patent Information

Application Number
CN202610420142.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-04-01
Publication Date
2026-06-19
Estimated Expiration
2046-04-01

AI Technical Summary

Technical Problem

Existing RISC-V processors suffer from performance bottlenecks when performing finite field operations using the SQIsign algorithm, especially in operations such as modular addition, modular subtraction, modular multiplication, and modular squaring. They lack dedicated instruction support for arithmetic operations in finite fields with extremely large bit widths, resulting in low computational efficiency and making it difficult to scale up applications in scenarios with high real-time requirements.

Method used

By constructing a non-saturated multi-limb representation model in the 64-bit general-purpose registers of the RISC-V processor, a fixed mapping relationship between data limbs and registers is established. Combining a delayed carry propagation mechanism and a unified modular reduction path planning, an instruction scheduling strategy that interleaves computation and memory access is designed to ensure that data resides in registers during the operation cycle. Carry propagation and modular reduction are completed through a branchless instruction sequence, thereby optimizing register resource allocation and instruction scheduling.

Benefits of technology

While maintaining constant-time execution characteristics, it significantly improves computational efficiency, reduces memory accesses, enhances resistance to timing side-channel attacks, and has good compatibility and portability, achieving a computational speedup of several times compared to existing implementations.

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Abstract

A method for accelerating finite-field modular arithmetic on RISC-V processors is disclosed. The method includes: 1. Constructing a non-saturated multi-limb representation model of finite-field elements in the processor's 64-bit general-purpose registers; 2. Designing an instruction scheduling strategy that interleaves computation and memory access based on the execution latency characteristics of multiplication instructions in the RISC-V processor; 3. Employing a latency correction mechanism within the general-purpose registers to decouple carry propagation and modular reduction path scheduling; 4. For modular square operations, constructing an instruction-level reduction path within the processor's instruction set environment, and implementing cross-limb carry processing through logical shift instructions and unsigned comparison instructions; 5. Utilizing the redundant bit width of the non-saturated representation, implementing a latency accumulation and mask correction mechanism for modular addition and subtraction operations at the register level. This invention achieves a computational speedup several times greater than existing implementations by optimizing processor register resources and instruction scheduling without altering the original mathematical structure of cryptographic algorithms.
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