Circuit board structure and manufacturing method thereof

Abstract

The invention discloses a circuit board structure and a manufacturing method thereof. The circuit board structure includes a substrate, a via, and a first photosensitized dielectric layer. The substrate has a through hole. The guide hole is arranged in the through hole of the substrate and comprises a guide hole metal layer. The first photosensitized dielectric layer is disposed between the substrate and the via.

Description

Circuit board structure and manufacturing method Technical Field

[0001] This disclosure relates to circuit board structures, and in particular to circuit board structures having photosensitive dielectric layers and methods for manufacturing the same. Background Technology

[0002] As the semiconductor industry evolves to achieve highly integrated packaging, wafer pioneers have entered the 3-nanometer generation, and industry leaders have begun to lay out production processes below 3 nanometers. However, peripheral packaging products (such as packaging substrates) also need to keep up with the demands of semiconductor miniaturization. Substrate manufacturers have made many efforts in this regard, but current substrate product designs are subject to limitations in packaging processes due to their multi-layered structure. For example, during packaging bonding, thermal processes are often used to bond the substrate and the chip. However, because the substrate structure is multi-layered, the stress between different materials within the substrate cannot be balanced after heating, leading to warping of the finished substrate. Or, during substrate production, warping can cause difficulties in subsequent circuit miniaturization (fine lines have high requirements for flatness). To address the aforementioned issues, the industry is moving towards adding an interposer between the carrier and the chip to act as a bridge for bonding. To overcome the problems encountered with previous carriers, manufacturers are selecting materials with thermal expansion coefficients close to those of the chip. As we know, the main material of a chip is silicon, and although glass differs in appearance from a chip due to its different crystal structure, its main component is also silicon. Therefore, the material compatibility between these two materials after heating is better than that between the chip and the carrier. Thus, glass circuit boards are the first choice for packaging interposers. In addition, due to the transparency of glass itself, it already has a place in commercial applications (such as displays, optoelectronics, and green energy (solar energy) industries). Therefore, the layout of functional circuits on glass products is an inevitable trend. Summary of the Invention

[0003] In some embodiments, a circuit board structure is provided. The circuit board structure includes a substrate, vias, through-holes, and a first photosensitive dielectric layer. The substrate has through-holes. The vias are disposed in the through-holes of the substrate and include a via metal layer. The first photosensitive dielectric layer is disposed between the substrate and the via.

[0004] In some embodiments, a method for manufacturing a circuit board structure is provided. The method for manufacturing a circuit board structure includes: providing a substrate having a through-hole through the substrate; forming a first photosensitive dielectric layer on at least a portion of the sidewalls of the through-hole; and forming a via in the through-hole, wherein the first photosensitive dielectric layer is located between the substrate and the via.

[0005] The circuit board structure and manufacturing method disclosed herein can be applied to various electronic devices. To make the features and advantages of this disclosure more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0006] The viewpoints of the embodiments of this disclosure will be better understood through the following detailed description in conjunction with the accompanying drawings. It is worth noting that, by convention, some features may not be drawn to scale. In fact, the dimensions of different features may be increased or decreased for clarity of description.

[0007] Figure 1A is a side view of a circuit board structure employing resin-filled vias according to some embodiments of the present disclosure.

[0008] Figure 1B is a side view of a circuit board structure employing electroplated plugged vias according to some embodiments of the present disclosure.

[0009] Figure 2 is a side view of a circuit board structure with a via metal having a lateral protrusion according to some embodiments of the present disclosure.

[0010] Figures 3A-3I, 3J-1 and 3K-1 are side views in the manufacturing process of a circuit board structure employing resin-filled vias according to some embodiments of the present disclosure.

[0011] Figures 3A-3I, 3J-2 and 3K-2 are side views in the manufacturing process of a circuit board structure employing electroplated plugged vias according to some embodiments of the present disclosure.

[0012] Figures 4A-4I are side views in process of a circuit board structure with a via metal having a lateral protrusion according to some embodiments of the present disclosure.

[0013] The reference numerals in the attached figures are explained as follows:

[0014] 100: Circuit board structure

[0015] 102: Substrate

[0016] 104: Photosensitive dielectric layer

[0017] 1041: First photosensitive dielectric layer

[0018] 1042: Second photosensitive dielectric layer

[0019] 106: Through hole

[0020] 108: Through-hole metal layer

[0021] 110: Line Layer

[0022] 1101: Front-side circuit layer

[0023] 1102: Backside Circuit Layer

[0024] 1101-1, 1102-1: First Line Section

[0025] 1101-2, 1102-2: Second Line Section

[0026] 112: (Through-sealing) Dielectric layer

[0027] 114: Guide hole

[0028] 1141: Front guide hole

[0029] 1142: Back blind hole

[0030] 116: Weld pad layer

[0031] 1161: Front weld pad

[0032] 1162: Backside solder pad

[0033] 118: Green paint layer

[0034] 1181: Front green paint layer

[0035] 1182: Green paint layer on the back

[0036] 120: Dry film layer

[0037] 1201: Front Dry Film Layer

[0038] 1202: Backside dry film layer

[0039] 122: Guide hole

[0040] 200: Circuit Board Structure

[0041] 300: Circuit Board Structure

[0042] FS: Front side of substrate

[0043] BS: Back side of substrate

[0044] X: X direction

[0045] Y: Y direction

[0046] Z: Z direction

[0047] C: Center of through hole

[0048] S: Spacing

[0049] LS: Light Detailed Implementation

[0050] The apparatus of various embodiments of this disclosure is described in detail below. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of this disclosure. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of this disclosure. Of course, these are merely examples and not for limiting the scope of this disclosure. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of this disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this disclosure and does not represent any relationship between the different embodiments and / or structures discussed.

[0051] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that element (or those elements), nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, a first element in the specification may be a second element in the claims.

[0052] In some embodiments of this disclosure, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding connection and bonding may also include situations where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect electrical connection means.

[0053] It should be understood that, without departing from the spirit of this disclosure, components in multiple different embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0054] In the following text, when a material is referred to as having "photo-imageable property", it refers to the property of a material that undergoes a qualitative change (e.g., curing) in the portion exposed to light after a suitable light irradiation process (e.g., exposure process).

[0055] This disclosure provides a circuit board structure and a method for manufacturing the same. The circuit board structure provided in this disclosure has a photo-imageable dielectric layer disposed between the vias and the substrate. Specifically, in some embodiments of the circuit board structure disclosed in this disclosure, the photo-imageable dielectric layer is disposed between the via metal layer and the substrate. With this configuration, the material properties of the photo-imageable dielectric layer provide better adhesion between the via metal layer and the substrate (e.g., as a liner between the via metal layer and the substrate).

[0056] Furthermore, in some embodiments of this disclosure, a photosensitive dielectric layer is used as a mask for the patterned via metal layer, providing greater flexibility in the fabrication process of the patterned via metal layer.

[0057] Figure 1A is a side view of a circuit board structure employing resin-filled vias according to some embodiments of the present disclosure. For purposes of brevity and illustration, only a portion of the circuit board structure is illustrated in the following figures. In practice, the circuit board structure illustrated below may include more or fewer components without departing from the spirit of the present disclosure.

[0058] Please refer to Figure 1A. In some embodiments, the circuit board structure 100 includes a substrate 102, a photo-imageable dielectric layer 104, a via 106, a via metal layer 108, a circuit layer 110, a plug dielectric layer 112, a blind via 114, and a via 122. In some embodiments, the photo-imageable dielectric layer 104 includes a first photo-imageable dielectric layer 1041 and a second photo-imageable dielectric layer 1042. In some embodiments, the circuit board structure 100 can be configured such that the via 122 (or via structure 122) is formed in the via 106 and includes the via metal layer 108. The descriptions of each of the above components will be presented below.

[0059] In some embodiments, the material of the substrate 102 may include a suitable insulating material, such as bismaleimide triazine resin, paper phenolic resin, composite epoxy, polyimide (PI) resin, glass, or a combination thereof. For example, the substrate 102 may include a prepreg, which is a material obtained by impregnating resin with insulating paper, glass fiber, or other fibrous materials. In one embodiment, the substrate 102 is the aforementioned light-transmitting glass substrate.

[0060] Please refer to Figure 1A. The substrate 102 has a through-hole 106. A first photosensitive dielectric layer 1041 is disposed on the sidewall of the through-hole 106. In some embodiments, the first photosensitive dielectric layer 1041 is disposed on the sidewall of the through-hole 106 and further embedded in the substrate 102.

[0061] Specifically, in some embodiments, the first photosensitive dielectric layer 1041 may be selected from suitable photosensitive insulating materials, such as polybenzoxazole (PBO), polyimide (e.g., photosensitive polyimide (PSPI)), benzocyclobutene (BCB), Ajinomoto build-up film (ABF), and other organic materials, but this disclosure is not limited thereto.

[0062] Please refer to FIG1A. A via metal layer 108 of the circuit board structure 100 is disposed in the through-hole 106. In some embodiments, the via metal layer 108 may be disposed on the sidewall of the through-hole 106 and may selectively extend to the front FS and back BS of the substrate 102, as shown in FIG1A. The via metal layer 108 serves as a conductive layer for electrically connecting components (not shown) disposed on the front FS and back BS of the substrate 102. Therefore, the configuration of the circuit board structure 100 can be considered as having vias 122 (or via structure 122) formed in the through-hole 106 and including the via metal layer 108.

[0063] In some embodiments, the material of the via metal layer 108 may be a suitable conductive material, such as aluminum (Al), copper (Cu), alloys thereof or compounds thereof, or other suitable metallic materials or combinations thereof, but this disclosure is not limited thereto. For example, the via metal layer 108 may include copper foil, such as brass, phosphor bronze, beryllium alloy, or oxygen-free copper.

[0064] Please refer to Figure 1A. In the circuit board structure 100, a first photosensitive dielectric layer 1041 is disposed between the substrate 102 and the via metal layer 108 (via 122). Specifically, in the configuration of the circuit board structure 100, the first photosensitive dielectric layer 1041 is disposed on at least a portion of the sidewall of the via 106 and directly contacts the via metal layer 108 and the substrate 102. In this configuration, the first photosensitive dielectric layer 1041 (e.g., as an adhesive layer or liner) increases the adhesion between the via metal layer 108 and the substrate 102. This is because the surface of the first photosensitive dielectric layer 1041 is easier to roughen than the surfaces of the substrate 102 and the via metal layer 108.

[0065] Conversely, in a configuration where the via metal layer 108 directly contacts the substrate 102 via the sidewall of the via 106 without any first photosensitive dielectric layer 1041 in between, since the substrate 102 is typically a rigid material used to support the structure (e.g., glass), the contact interface between it and the via metal layer 108 is prone to insufficient indirect adhesion due to material property mismatch (e.g., glass versus metal). In such an embodiment, the first photosensitive dielectric layer 1041 is the aforementioned insulating material that has photosensitive properties and good adhesion.

[0066] Please refer to Figure 1A. A circuit layer 110 and a second photosensitive dielectric layer 1042 are disposed on the front FS and back BS of the substrate 102. Specifically, the circuit layer 110 includes front circuit layers 1101 (1101-1, 1101-2) and back circuit layers 1102 (1102-1, 1102-2), each disposed in the area defined by the second photosensitive dielectric layer 1042 on the front FS and back BS of the substrate 102. In other words, the second photosensitive dielectric layer 1042 is disposed between adjacent circuit layers 110 on the front FS and back BS of the substrate 102. Generally, the circuit layer 110 is used to electrically connect the via metal layer 108 to the front FS and back BS of the substrate 102. Therefore, although the front circuit layer 1101 and back circuit layer 1102 of the circuit layer 110 are shown as separate portions in Figure 1A, these portions can actually be electrically connected to each other.

[0067] In some embodiments, the second photosensitive dielectric layer 1042 may be an illustrative material similar to that listed above with respect to the first photosensitive dielectric layer 1041, and the material of the circuit layer 110 may be at least the same as or similar to the conductive material of the aforementioned via metal layer 108. The material of the circuit layer 110 may also be, for example, silver (Ag), tin (Sn), nickel (Ni), chromium (Cr), titanium (Ti), lead (Pb), gold (Au), tungsten (W), or other suitable metal materials. The material of the circuit layer 110 may be copper, and the material of the second photosensitive dielectric layer 1042 may be the same as or different from that of the first photosensitive dielectric layer 1041, and may be an insulating material.

[0068] Please refer to FIG1A. In some embodiments, the front circuit layer 1101 and the back circuit layer 1102 of the circuit layer 110 each include a first circuit portion 1101-1, 1102-1 adjacent to the via 122 (more precisely, the via metal layer 108 adjacent to the via 122) and a second circuit portion 1101-2, 1102-2 not adjacent to the via 122 (not adjacent to the via metal layer 108 of the via 122). In some embodiments, the first circuit portions 1101-1, 1102-1 directly contact the first photosensitive dielectric layer 1041. More specifically, in some embodiments, the first circuit portions 1101-1, 1102-1 cover the opposite ends of the first photosensitive dielectric layer 1041 and partially cover the sidewalls of the first photosensitive dielectric layer 1041, as shown in FIG1A. In this configuration, due to the material properties of the first photosensitive dielectric layer 1041 (e.g., it is softer than the material of the core layer 102), the first line portions 1101-1 and 1102-1 can be more securely disposed at the position adjacent to the via metal layer 108 via the first photosensitive dielectric layer 1041, thereby increasing the conductive structural strength of the circuit board structure. Furthermore, since the first line portions 1101-1 and 1102-1 are respectively the portions in the front circuit layer 1101 and the back circuit layer 1102 that transmit electrical signals out of the via metal layer 108, the more secure placement of the first line portions 1101-1 and 1102-1 ensures the structural strength of the via metal layer 108 (i.e., ensures that 1101-1 and 1102-1 are in contact with 108), which improves the electrical signal transmission quality in the circuit board structure 100.

[0069] Please refer to Figure 1A. In some embodiments, a dielectric layer 112 is disposed on the front side FS and the back side BS of the substrate 102. In this configuration, the dielectric layer 112 of the circuit board structure 100 fills the portion of the via 106 that is not filled by the via metal layer 108. The dielectric layer 112 is a resin insulating material, and the via 122 may be a resin plug structure.

[0070] In some embodiments, the material of the dielectric layer 112 may be, for example, paper phenolic resin, composite epoxy resin, polyimide resin, resin polymer, ABF film (Ajinomoto Build-up Film), polyphenylene (PPE), polypropylene (PP), or other suitable insulating materials or combinations thereof.

[0071] Please refer to Figure 1A. In some embodiments, a blind hole 114 is disposed in the portions of the dielectric layer 112 located on the front side FS and the back side BS of the substrate 102 and is electrically connected to the circuit layer 110. The blind hole 114 includes a front blind hole 1141 disposed in the front side FS portion of the substrate 102 and a back blind hole 1142 disposed in the back side BS portion of the substrate 102. The blind hole 114 can be made of the same or similar conductive material as the aforementioned via metal layer 108 or circuit layer 110, which will not be described again here.

[0072] Please refer to Figure 1A. In some embodiments, a bonding pad 116 is disposed on and electrically connected to the via 114. The bonding pad 116 includes a front bonding pad 1161 disposed on the front side FS of the substrate 102 and a back bonding pad 1162 disposed on the back side BS of the substrate 102. In some embodiments, the bonding pad 116 may be a conductive material that is the same as or similar to the aforementioned via metal layer 108 or circuit layer 110, which will not be described again here.

[0073] Please refer to Figure 1A. In some embodiments, a green paint layer 118 is disposed on the dielectric layer 112 and exposes a portion of the solder pad layer 116. The green paint layer 118 includes a front green paint layer 1181 disposed on the front side FS of the substrate 102 and a back green paint layer 1182 disposed on the back side BS of the substrate 102. The green paint layer 118 can serve as a solder resist layer to protect the solder pad layer 116 and its vias 114 near the substrate 102 from oxidation or short-circuiting. The green paint layer 118 can be, for example, an ultraviolet-cured green paint, a thermosetting green paint, a similar material, or a combination thereof.

[0074] Figure 1B is a side view of a circuit board structure employing electroplated plugged vias according to some embodiments of the present disclosure. The embodiment illustrated in Figure 1B is substantially the same as the embodiment illustrated in Figure 1A above. The difference is that in the embodiment illustrated in Figure 1B, the via metal layer 108 completely fills the through-hole 106. Hereinafter, other embodiments of the present disclosure will be described in conjunction with Figure 1B. Unless specifically mentioned otherwise, components in the following figures (including Figure 1B and the following figures) that are the same as the component symbols in Figure 1A represent the same or similar components and may include at least the same or similar materials as those in the foregoing embodiments. For the sake of brevity, these will not be described again.

[0075] Please refer to Figure 1B. In some embodiments, the via metal layer 108 of the circuit board structure 200 completely fills the via 106 and directly contacts the first photosensitive dielectric layer 1041 to configure the via 122 as an electroplated plug. In the embodiment illustrated in Figure 1B, the dielectric layer 112, the blind via 114, and the solder pad layer 116 above the front FS and back BS of the substrate 102 can be considered as an add-on structure. Although Figure 1B shows only one add-on structure on the front FS and back BS of the substrate 102, this disclosure is not limited thereto. In fact, any number of add-on structures can be provided between the front FS and back BS of the substrate 102 and the green paint layer 118 according to design requirements.

[0076] Figure 2 is a side view of a circuit board structure with a via metal having a lateral protrusion according to some embodiments of the present disclosure. For simplicity and illustrative purposes, Figure 2 shows only a portion of the circuit board structure. It should be understood that additional components and structures mentioned in Figures 1A and 1B can be added to the embodiments illustrated in Figure 2 without departing from the spirit of the invention. For example, in some embodiments, a dielectric layer 112, a blind via 114, a solder pad layer 116, and a green paint layer 118 can be further formed on the embodiment of Figure 2, wherein the dielectric layer 112 fills the via 106 to form a resin-filled via configuration similar to that of the embodiment of Figure 1A. Alternatively, in other embodiments, the via metal layer 108 can be configured on the embodiment of Figure 2 to completely fill the via 106 to form an electroplated via configuration similar to that of the embodiment of Figure 1B. The addition of these additional configurations and components based on the embodiments of Figure 2 is covered by the claims expressly set forth in this disclosure.

[0077] Please refer to Figure 2. In some embodiments, the first photosensitive dielectric layer 1041 disposed on the sidewall of the via 106 can be used as a patterned masking layer to configure the via metal layer 108 as having a plurality of lateral protrusions 1081 and a longitudinal base 1082. It is worth noting that, in such embodiments, due to the photosensitive nature of the first photosensitive dielectric layer 1041, a patterned via metal layer 108 can be formed in the lateral direction of the substrate 102 (e.g., along the X direction shown in Figure 2) (details will be described later). In such embodiments, the substrate 102 is a light-transmitting material among the materials listed above, such as a glass fiber substrate.

[0078] Please refer to Figure 2. In some embodiments, the lateral protrusions 1081 of the via metal layer 108 are spaced apart between the first photosensitive dielectric layers 1041 and extend laterally through the first photosensitive dielectric layers 1041 toward the sidewall of the substrate 102 (e.g., along the X direction shown in Figure 2). In some embodiments, the lateral protrusions 1081 of the via metal layer 108 extend more laterally into the substrate 102. In some embodiments, the spacing S between the lateral protrusions 1081 can be defined according to the first photosensitive dielectric layer 1041 (described later).

[0079] Please refer to Figure 2. The longitudinal base 1082 of the via metal layer 108 is disposed on the side of the lateral protrusion 1081 near the center C of the through hole 106. The longitudinal base 1082 is continuously disposed along the longitudinal direction of the sidewall of the through hole 106 (e.g., along the Z direction shown in Figure 2) and is connected to the lateral protrusion 1081. The configuration of the via metal layer 108 having the lateral protrusion 1081 and the longitudinal base 1082 increases the contact area between the via metal layer 108 and the first photosensitive dielectric layer 1041, which further improves the adhesion between the via metal layer 108 and the substrate 102, and further increases the benefits (e.g., the degree of increase in adhesion) brought about by the placement of the first photosensitive dielectric layer 1041 between the via metal layer 108 and the substrate 102.

[0080] Figures 3A-3I, 3J-1, and 3K-1 are side views of a circuit board structure employing resin-filled vias according to some embodiments of the present disclosure during the manufacturing process. The manufacturing process of the aforementioned circuit board structure 100 employing resin-filled vias will be described below in conjunction with Figures 3A-3I, 3J-1, and 3K-1. Not all process steps of the circuit board structure may be described below for illustrative purposes. Those skilled in the art will understand that process steps known in the art can be added before, between, or after the following process steps without departing from the spirit of the present disclosure.

[0081] Referring to FIG3A. In some embodiments, the step of forming the circuit board structure 100 includes providing a substrate 102 and forming a through hole 106 through the substrate 102. The through hole 106 may be formed in the substrate 102 by means of, for example, mechanical drilling, laser drilling, other suitable methods or combinations thereof, but this disclosure is not limited thereto.

[0082] Referring to Figure 3B, following the steps shown in Figure 3A, a photosensitive material 104' is formed on the front side FS, the back side BS, and in the via 106 of the substrate 102. The photosensitive material 104' can be any of the materials listed above regarding the first photosensitive dielectric layer 1041, and will not be described again here.

[0083] Referring to Figure 3C, following the steps shown in Figure 3B, the photosensitive material 104' is subjected to an exposure process to cure the photosensitive material 104' into a photosensitive dielectric layer 104. In some embodiments, the exposure process can be, for example, a laser imaging or general imaging process. Subsequently, the portion of the photosensitive dielectric layer 104 located on the front side FS and back side BS of the substrate 102 is removed, leaving the portion of the photosensitive dielectric layer 104 located in the via 106. The portion of the photosensitive dielectric layer 104 retained in the via 106 will be partially removed in a subsequent process to form a first photosensitive dielectric layer 1041. In some embodiments, the removal of the photosensitive dielectric layer 104 can be, for example, a plasma process.

[0084] Referring to Figures 3D and 3E. Continuing from the steps shown in Figure 3C, in some embodiments, a photosensitive material 104' is formed on the front side FS and back side BS of the substrate 102, and is exposed and developed to form a patterned second photosensitive dielectric layer 1042.

[0085] Referring to Figure 3F. Continuing from the steps shown in Figure 3E, in some embodiments, the second photosensitive dielectric layer 1042 on the front side FS and back side BS of the substrate 102 is used as a mask to etch the substrate 102. The etching method of the substrate 102 can be an etching process that etches the substrate 102 but does not etch (or substantially does not etch) the second photosensitive dielectric layer 1042.

[0086] Referring to Figure 3G. Continuing from the steps shown in Figure 3F, in some embodiments, a circuit layer 110 is formed in the portion of the substrate 102 removed according to the pattern of the second photosensitive dielectric layer 1042. A front circuit layer 1101 of the circuit layer 110 is formed on the front side FS of the substrate 102, and a back circuit layer 1102 of the circuit layer 110 is formed on the back side BS of the substrate 102. The front circuit layer 1101 and the back circuit layer 1102 are formed between the second photosensitive dielectric layer 1042. The circuit layer 110 can be formed by, for example, electroplating, electroless plating, sputtering, lamination, coating, or a combination thereof.

[0087] Referring to Figure 3H, following the steps shown in Figure 3G, in some embodiments, a drilling process is performed to remove a portion of the photosensitive dielectric layer 104 and a portion of the circuit layer 110 adjacent to the dielectric layer 104. In some embodiments, the drilling process can be, for example, mechanical drilling, laser drilling, other suitable methods, or a combination thereof. After the drilling process, the remaining portion of the photosensitive dielectric layer 104 forms the first photosensitive dielectric layer 1041, and the remaining portion of the circuit layer 110 adjacent to the dielectric layer 104 forms the first circuit portions 1101-1 and 1102-1. In other words, the first photosensitive dielectric layer 1041 is disposed on at least a portion of the sidewall of the via 106, and the first circuit portions 1101-1 and 1102-1 of the circuit layer 110 adjacent to the first photosensitive dielectric layer 1041 directly contact the first photosensitive dielectric layer 1041. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), may be performed before the drilling process to make the top surface of the circuit layer 110 flush with the top surface of the second photosensitive dielectric layer 1042.

[0088] Referring to FIG3I, following the steps shown in FIG3H, in some embodiments, a dry film layer 120 is formed on the front side FS and the back side BS of the substrate 102. Specifically, a front dry film layer 1201 is formed on the front side FS of the substrate 102 and a back dry film layer 1202 is formed on the back side BS of the substrate 102. In some embodiments, the dry film layer 120 may be a dry film photoresist known in the art, but this disclosure is not limited thereto.

[0089] Referring to Figure 3J-1, continuing the steps shown in Figure 3I, in some embodiments, a via metal layer 108 is formed on the portion of the substrate 102 exposed by the dry film layer 120. In some embodiments, the via metal layer 108 covers a portion of the front side FS and the back side BS of the substrate 102 and directly contacts the first photosensitive dielectric layer 1041. In such embodiments, the via metal layer 108 does not completely fill the via 106.

[0090] In some embodiments, the method of forming the via metal layer 108 may be, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process (e.g., sputtering), an electroplating process, a coating process, an electroless electroplating process, other suitable processes, or a combination thereof.

[0091] Referring to Figure 3K-1, following the steps shown in Figure 3J-1, a (via-plugging) dielectric layer 112 is formed on the front FS and back BS of the substrate 102 and in the vias 106 by lamination or coating to form a resin-plugged via configuration. Blind holes 114 (including front blind holes 1141 and back blind holes 1142), solder pad layers 116 (including front solder pad layers 1161 and back solder pad layers 1162), and green paint layers 118 (including front green paint layers 1181 and back green paint layers 1182) are formed using processes known in the art to form a circuit board structure. For the sake of brevity, the formation processes of the above components are not described in detail here.

[0092] Referring to Figure 3K-2, similar to the steps shown in Figure 3K-1, after forming the via metal layer 108, a dielectric layer 112, blind vias 114 (including front blind via 1141 and back blind via 1142), a solder pad layer 116 (including front solder pad 1161 and back solder pad 1162), and a green paint layer 118 (including front green paint layer 1181 and back green paint layer 1182) are formed to form the circuit board structure 200. The difference from the example in Figure 3K-1 is that, in this embodiment, the dielectric layer 112 is not filled into the via 106, but is formed on the second photosensitive dielectric layer 1042 and covers the portion of the via metal layer 108 that extends beyond the via 106, as shown in Figure 3K-2.

[0093] Figures 4A-4I are side views in process of a circuit board structure with lateral protrusions in the via metal layer according to some embodiments of the present disclosure. The manufacturing process of the aforementioned circuit board structure 300 (e.g., Figure 2) with lateral protrusions in the via metal layer will be described below with reference to Figures 4A-4I. For the sake of brevity, the process steps similar to those described above will only be briefly mentioned and not described in detail.

[0094] Referring to Figures 4A and 4B, a photosensitive material 104' is formed on the front side FS, the back side BS, and in the through-hole 106 of the substrate 102.

[0095] Referring to FIG4C, in some embodiments, the photosensitive material 104' undergoes an exposure process. In this embodiment, the light source LS (or light beam LS) in the exposure process laterally passes through the substrate 102 and irradiates the portion of the photosensitive material 104' located on the sidewall of the via 106. The portion of the photosensitive material 104' exposed by the light source LS is cured into a photosensitive dielectric layer 104. Specifically, the photosensitive dielectric layer 104 has multiple discontinuous longitudinal segments. In such embodiments, the substrate 102 is a light-transmitting material among the aforementioned materials, such as a glass fiber substrate.

[0096] It is worth noting that in such an embodiment, a light-transmitting substrate 102 is used and a photosensitive material 104' is used as a patterning mask, so that the light source LS can pass through the side of the substrate 102 to pattern the photosensitive material 104' (e.g., after partial exposure, it has cured and uncured portions), which provides greater design flexibility for the subsequent definition of the via metal layer 108.

[0097] Referring to Figure 4D, following the process steps of Figure 4C, the uncured portion of the photosensitive material 104' is removed, while the cured portion 104 of the photosensitive material 104' is retained, thereby forming a patterned first photosensitive dielectric layer 1041 on the sidewall of the via 106. As shown in Figure 4D, the first photosensitive dielectric layer 1041 has multiple discontinuous longitudinal segments that define multiple exposed portions on the sidewall of the via 106.

[0098] Referring to Figures 4E and 4F, continuing the process steps of Figure 4D, the sidewalls of the via 106 are etched using the first photosensitive dielectric layer 1041 as an etching mask. On the exposed portions of the sidewalls of the via 106, a via metal layer 108 is formed by electroplating or coating. As shown in Figure 4F, the via metal layer 108 has multiple lateral protrusions 1081, which are spaced apart from each other via longitudinal sections of the first photosensitive dielectric layer 1041. In some embodiments, the spacing S between the lateral protrusions 1081 can be controlled by adjusting the spacing between the longitudinal sections of the first photosensitive dielectric layer 1041 by adjusting the exposure time (e.g., by adjusting the light emission position during exposure).

[0099] Referring to Figures 4G and 4H, etching or drilling processes can be performed to appropriately enlarge the through-hole 106. Subsequently, a longitudinal base 1082 of the via metal layer 108 is formed in the through-hole 106 by electroplating. In some embodiments, the longitudinal base 1082 of the via metal layer 108 extends longitudinally continuously and connects to the lateral protrusions 1081 of the via metal layer 108.

[0100] Referring to Figure 4I. In some embodiments, the process steps of Figure 4H, for example, those of Figure 3D described above, can be followed to form the second photosensitive dielectric layer 1042. Moreover, it is understood that in some embodiments, the process steps of Figures 3D to 3J-1 and 3K-1 described above can be further followed to form the circuit board structure 300. For the sake of brevity, these will not be described again here.

[0101] In summary, this disclosure provides a circuit board structure and its manufacturing method. The circuit board structure has a first photosensitive dielectric layer disposed between a substrate and a via (via metal layer). The first photosensitive dielectric layer enhances the adhesion between the substrate and the via metal layer (e.g., serving as an adhesive layer or substrate), thereby improving the strength of the conductive structure of the circuit board. Furthermore, the circuit layer of the circuit board structure is more firmly disposed adjacent to the via metal layer via the first photosensitive dielectric layer, ensuring direct contact between the circuit layer and the via metal layer, thus increasing the electrical signal transmission quality of the circuit board structure.

[0102] Furthermore, the circuit board structure provided in this disclosure employs a photosensitive material (photosensitive dielectric layer) as a mask for the patterned via metal layer. By combining the transparent substrate and the photosensitive material in the circuit board structure, greater design flexibility is provided for the patterned via metal layer. Therefore, the circuit board structure and manufacturing method of this disclosure effectively solve some structural strength and electrical connection reliability issues in existing circuit board structures.

[0103] The foregoing outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments of this disclosure to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure.

Claims

1. A circuit board structure, comprising: A substrate having a through hole; a via disposed in the through hole and including a via metal layer; And a first photosensitive dielectric layer is disposed on at least a portion of the sidewall of the via and directly contacts the via metal layer and the substrate.

2. The circuit board structure as described in claim 1, wherein the via is a resin plug.

3. The circuit board structure as described in claim 1, wherein the via is an electroplated plug hole.

4. The circuit board structure as described in claim 1, further comprising: Multiple circuit layers are disposed on a front side and a back side of the substrate; And a second photosensitive dielectric layer, disposed between adjacent line layers.

5. The circuit board structure of claim 4, wherein the circuit layer has a first circuit portion adjacent to the via and a second circuit portion not adjacent to the via, and wherein the first circuit portion directly contacts the first photosensitive dielectric layer.

6. The circuit board structure of claim 5, wherein the first line portion covers the opposite ends of the first photosensitive dielectric layer and partially covers the sidewalls of the first photosensitive dielectric layer.

7. The circuit board structure of claim 1, wherein the via metal layer further comprises: A longitudinal base is continuously disposed along the sidewall of the through hole; and a plurality of transverse protrusions are connected to the longitudinal base and extend laterally through the first photosensitive dielectric layer toward the sidewall of the substrate.

8. The circuit board structure of claim 7, wherein the plurality of lateral protrusions extend laterally into the substrate.

9. The circuit board structure as claimed in claim 1, wherein the substrate is a glass substrate.

10. A method for manufacturing a circuit board structure, comprising: A substrate is provided having a through hole through which the substrate passes; A first photosensitive dielectric layer is formed on at least a portion of the sidewall of the via and directly contacts a via metal layer in the via and the substrate. The method includes forming a via in the via, wherein the first photosensitive dielectric layer is located between the substrate and the via; forming a plurality of circuit layers on a front side and a back side of the substrate; and forming a second photosensitive dielectric layer between adjacent circuit layers.

11. The method for manufacturing a circuit board structure as claimed in claim 10, wherein the step of forming the via includes: A via metal layer is formed in the via, wherein the via metal layer covers the sidewall of the via and connects a front side and a back side of the substrate.

12. The method for manufacturing a circuit board structure as claimed in claim 11, wherein the step of forming the via further comprises: After the via metal layer is formed, a plug dielectric layer is formed in the via.

13. The method for manufacturing a circuit board structure as claimed in claim 10, wherein the step of forming the first photosensitive dielectric layer includes: A photosensitizing material is formed in the through-hole; And perform a patterning process on the photosensitive material to form the first photosensitive dielectric layer on the sidewall of the via, wherein the first photosensitive dielectric layer has a plurality of discontinuous longitudinal segments, and wherein the plurality of longitudinal segments define a plurality of exposed portions on the sidewall of the via.

14. The method for manufacturing a circuit board structure as claimed in claim 13, wherein the step of performing the patterning process on the photosensitive material includes: A light source is provided that passes laterally through the side of the substrate and illuminates the photosensitive material on the sidewall of the via to expose a portion of the photosensitive material. And remove the unexposed portion of the photosensitive material to form the first photosensitive dielectric layer on the sidewall of the via.

15. The method for manufacturing a circuit board structure as claimed in claim 13, wherein the step of forming the via includes: Multiple lateral protrusions of a via metal layer are formed on the multiple exposed portions of the sidewall of the via, wherein the multiple lateral protrusions are spaced apart from each other via the multiple longitudinal segments of the first photosensitive dielectric layer; And a longitudinal base forming the via metal layer in the via, the longitudinal base extending continuously and connecting the plurality of transverse protrusions.

16. The method of manufacturing a circuit board structure as claimed in claim 10, wherein the circuit layer has a first circuit portion adjacent to the via and a second circuit portion not adjacent to the via, and wherein the first circuit portion is in direct contact with the first photosensitive dielectric layer.

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