Josephson junction manufacturing method, superconducting quantum chip and quantum computer

Abstract

The invention discloses a Josephson junction manufacturing method, a superconducting quantum chip and a quantum computer, and belongs to the technical field of quantum chip preparation processes. The manufacturing method of the Josephson junction comprises the following steps: forming a first superconducting metal layer, an insulating layer and a second superconducting metal layer which are stacked in sequence on the surface of a substrate in a film coating manner; etching the second superconducting metal layer to form a top electrode region and a top bonding pad region which are communicated with each other and have a first preset size; the insulating layer and the first superconducting metal layer are etched, so that a barrier layer of a second preset size is formed on the insulating layer, and a bottom electrode area and a bottom bonding pad area of the second preset size are formed on the first superconducting metal layer; the top electrode region, the barrier layer, and the bottom electrode region overlap in a direction perpendicular to the surface to form a junction region of the Josephson junction. By means of the in-situ coating and etching mode, the Josephson junction can be lower in loss and better in performance, the preparation process can be compatible with traditional mass production semiconductor equipment, and the mass production process is facilitated.

Description

Technical Field

[0001] This application belongs to the field of quantum chip fabrication technology, and in particular relates to a method for manufacturing a Josephson junction, a superconducting quantum chip, and a quantum computer. Background Technology

[0002] Josephson junctions are a key component of core devices in superconducting quantum computing, offering unique advantages such as stability, reliability, ease of design, and scalability in quantum control and measurement. As a superconducting quantum device with nonlinear and dissipation-free characteristics, the Josephson junction provides a stable and reliable hardware foundation for quantum computing. This structure, with its superconducting properties, opens the door to exploring the quantum world, making quantum computing possible.

[0003] The Josephson junction structure consists of two superconductors sandwiching a nanoscale insulating layer. The traditional fabrication process mainly involves preparing the first superconducting metal layer through a single oblique evaporation, forming an insulating oxide layer on the surface of the first superconducting metal layer through a controlled oxidation process, and then preparing the second superconducting metal layer through oblique evaporation to form the Josephson junction.

[0004] However, the Josephson junction prepared using the traditional oblique evaporation process has an unstable oxide layer formed by the oxidation process, resulting in high losses and thus affecting the performance of the quantum chip. Summary of the Invention

[0005] The purpose of this application is to provide a method for manufacturing Josephson junctions, a superconducting quantum chip, and a quantum computer. This addresses the shortcomings of existing technologies that typically employ oblique evaporation processes to fabricate Josephson junctions. Oblique evaporation results in unstable oxide layers due to oxidation processes, leading to significant losses and impacting quantum chip performance. Furthermore, the distribution of photoresist with multiple Josephson junction patterns etched on the wafer surface exhibits non-negligible angular errors relative to the evaporation source, potentially causing inconsistent linewidths within the same batch of Josephson junctions and failing to meet testing requirements. This application primarily utilizes an in-situ deposition process to fabricate Josephson junctions, resulting in lower losses, improved performance, and compatibility with traditional mass production semiconductor equipment, facilitating mass production implementation.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a Josephson junction, comprising:

[0007] A first superconducting metal layer, an insulating layer, and a second superconducting metal layer are sequentially stacked on the substrate surface by film deposition.

[0008] The second superconducting metal layer is etched to form a connected top electrode region and a top pad region with a first preset size;

[0009] The insulating layer and the first superconducting metal layer are etched such that the insulating layer forms a barrier layer of a second preset size, and the first superconducting metal layer forms a bottom electrode region and a bottom pad region of a second preset size; wherein, in a direction perpendicular to the surface, the top electrode region, the barrier layer, and the bottom electrode region overlap to form a junction region of a Josephson junction.

[0010] Preferably, the method for etching the second superconducting metal layer to form a connected top electrode region and a top pad region with a first preset size includes:

[0011] A photoresist layer with a first blank area is formed on the surface of the second superconducting metal layer away from the substrate; the first blank area exposes a portion of the second superconducting metal layer.

[0012] The second superconducting metal layer located in the first blank area is etched away, so that the second superconducting metal layer forms a connected top electrode region and a top pad region with a first preset size;

[0013] Remove the photoresist layer.

[0014] Preferably, the method for forming a barrier layer, a bottom electrode region, and a bottom pad region of a second predetermined size by etching the insulating layer and the first superconducting metal layer includes:

[0015] A photoresist layer with a second blank area is formed on the surface of the insulating layer opposite to the substrate; the second blank area exposes a portion of the insulating layer.

[0016] The insulating layer and the first superconducting metal layer are removed by etching in the second blank area;

[0017] Remove the photoresist layer;

[0018] Etching removes a portion of the insulating layer and a portion of the first superconducting metal layer in the region opposite to the substrate of the top electrode region, so that the insulating layer forms the barrier layer and the first superconducting metal layer forms a connected bottom electrode region and bottom pad region.

[0019] Preferably, the method for etching away a portion of the insulating layer and a portion of the first superconducting metal layer in the region opposite to the substrate includes:

[0020] A photoresist layer is formed on the surface of the region away from the first superconducting metal layer, the insulating layer, and the top electrode region away from the substrate;

[0021] The photoresist layer is photolithographically etched to form a window; the window exposes a portion of the top electrode region and a portion of the substrate.

[0022] The insulating layer and the first superconducting metal layer located within the window are etched through the window using an etching solution, such that the insulating layer forms a barrier layer and a first support layer separated by a channel, and the first superconducting metal layer forms a bottom electrode region and a second support layer separated by a channel.

[0023] Remove the photoresist layer.

[0024] Preferably, the material of the first superconducting layer is aluminum;

[0025] The etching solution is a mixed solution comprising phosphoric acid, acetic acid and nitric acid.

[0026] Preferably, the material of the second superconducting metal layer is one of tantalum, niobium, titanium nitride, and titanium nitride niobium.

[0027] This application also provides a superconducting quantum chip, comprising:

[0028] Josephson knots manufactured by the aforementioned manufacturing method;

[0029] The top pad is electrically connected to the end of the top electrode region that is furthest from the junction region;

[0030] The bottom pad is electrically connected to the end of the bottom electrode region furthest from the junction region.

[0031] Preferably, the top pad is integrally formed with the top electrode region;

[0032] And / or, the bottom pad is integrally formed with the bottom electrode region.

[0033] Preferably, the size of the top pad region is larger than the size of the top electrode region;

[0034] And / or, the size of the bottom pad region is larger than the size of the bottom electrode region.

[0035] This application also provides a quantum computer, comprising:

[0036] The aforementioned superconducting quantum chip.

[0037] Compared with existing technologies, this application firstly deposits a first superconducting metal layer, an insulating layer, and a second superconducting metal layer on the substrate surface by coating. Then, the top electrode is formed by etching the second superconducting metal layer. Finally, the insulating layer and the second superconducting metal layer are etched to form a barrier layer and a bottom electrode, respectively. Ultimately, the top electrode, barrier layer, and bottom electrode partially overlap to form a Josephson junction, and the overlapping region is the junction region of the Josephson junction. This method can result in lower Josephson junction loss and better performance, and the fabrication process is compatible with traditional mass production semiconductor equipment, which is beneficial for mass production processes. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the steps in the Josephson junction manufacturing method provided in the embodiments of this application;

[0039] Figure 2 A top view of the Josephson knot provided in an embodiment of this application;

[0040] Figure 3 A schematic diagram of the etching of the second superconducting metal layer provided in an embodiment of this application;

[0041] Figure 4 A schematic diagram of the top electrode region and top pad region formed by etching, provided in an embodiment of this application;

[0042] Figure 5 A schematic diagram of the etched insulating layer and the first superconducting metal layer provided in an embodiment of this application;

[0043] Figure 6 A front view of photoresist formed before forming an insulating layer, a first support layer, a bottom electrode region, and a second support layer, provided in an embodiment of this application;

[0044] Figure 7 This is a top view of the photoresist formed before forming the insulating layer, the first support layer, the bottom electrode region, and the second support layer, as provided in an embodiment of this application.

[0045] Explanation of reference numerals in the attached figures: 1 - substrate, 2 - first superconducting metal layer, 21 - bottom electrode region, 22 - bottom pad region, 23 - second support layer, 3 - insulating layer, 31 - barrier layer, 32 - first support layer, 4 - second superconducting metal layer, 41 - top electrode region, 42 - top pad region. Detailed Implementation

[0046] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0047] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0048] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0050] In the fields of quantum computing and quantum chips, the Josephson junction is a key superconducting electronic component that enables quantum current tunneling between two superconductors. The Josephson junction plays a crucial role in qubits, providing the foundation for the design and implementation of superconducting qubits. A Josephson junction consists of two superconductors weakly connected by an insulating thin film. This structure allows superconducting electron pairs (Cooper pairs) to tunnel from one superconductor to another via quantum tunneling, a phenomenon known as the Josephson effect.

[0051] In the traditional fabrication process of superconducting quantum chips, a first superconducting layer is typically prepared on a substrate using aluminum. Then, an alumina layer (barrier layer) is prepared by uniformly diffusing high-purity oxygen onto the aluminum surface. Finally, a second superconducting layer is formed on the barrier layer to create a Josephson junction. However, the barrier layer formed by this oxidation method is often not ideal and has several drawbacks, such as incomplete oxidation, difficulty in thickness control, and the formation of amorphous alumina material.

[0052] In the fabrication process of Josephson junctions, the diffusion rate of the bottom superconducting layer decreases with increasing diffusion depth during oxidation, resulting in a non-linear relationship between oxidation time and oxide layer thickness. This makes it difficult to control the thickness of the barrier layer. Furthermore, current oblique evaporation processes have high requirements for coating directionality, leading to poor uniformity when the coating area is large. This makes it impossible to complete multi-wafer coating and large-size wafer coating in one go. Therefore, traditional semiconductor mass production processes can hardly support oblique evaporation, resulting in low fabrication efficiency of Josephson junctions.

[0053] Please refer to Figure 1 This invention provides a method for manufacturing a Josephson knot, comprising:

[0054] S1: A first superconducting metal layer 2, an insulating layer 3, and a second superconducting metal layer 4 are sequentially stacked on the surface of substrate 1 by means of film deposition.

[0055] S2: Etch the second superconducting metal layer 4 to form a connected top electrode region 41 and a top pad region 42 with a first preset size;

[0056] S3: Etch the insulating layer 3 and the first superconducting metal layer 2, so that the insulating layer 3 forms a barrier layer 31 of a second preset size, and the first superconducting metal layer 2 forms a bottom electrode region 21 and a bottom pad region 22 of a second preset size.

[0057] In the direction of the first superconducting metal layer 2 formed on the vertical substrate 1 (or the stacking direction of the first superconducting layer, the insulating layer 3, and the second superconducting metal layer 4), the top electrode region 41, the barrier layer 31, and the bottom electrode region 21 partially overlap to form a Josephson junction region.

[0058] Regarding the first superconducting metal layer 2, the insulating layer 3, and the second superconducting metal layer 4 sequentially stacked as shown in step S1, the first superconducting metal layer 2 can be made of aluminum, for example. In this Josephson junction fabrication process, a 100 nm aluminum film can be formed on the surface of the substrate 1 by sputtering.

[0059] Sputter coating is a physical vapor deposition technique that uses charged particles to bombard a target material, causing the target atoms or molecules to escape and deposit on a substrate material to form a thin film.

[0060] The first superconducting metal layer 2, the insulating layer 3, and the second superconducting metal layer 4 are stacked and in close contact with each other. Specifically, aluminum films are deposited on the surface of substrate 1 using magnetron sputtering. First, aluminum is placed as a target material in a sputtering chamber, and an environment composed of argon plasma is created within it. Under the action of a DC or AC power supply, argon gas is excited to form plasma, and argon ions in the plasma are accelerated and bombard the aluminum target material, causing aluminum atoms to be sputtered from the target surface and form corresponding aluminum films on substrate 1. In this process, by precisely controlling sputtering parameters such as power, gas flow rate, and sputtering time, a 100 nm aluminum film is obtained on substrate 1. This method can produce uniform and dense films. The other insulating layer 3 and the second superconducting metal layer 4 can also be deposited using the same method or other suitable techniques.

[0061] After the first superconducting metal layer 2 is prepared, an insulating layer 3 thin film, such as an aluminum oxide thin film (AL2O3), is deposited in situ using a film deposition method. In this step, the thickness of the insulating layer 3 can be set according to the preset room temperature resistance of the Josephson junction, thereby meeting the requirements for setting its room temperature resistance.

[0062] After the insulating layer 3 is prepared, a second superconducting metal layer 4 is formed by in-situ deposition using a film deposition method. The material of the second superconducting metal layer 4 can be selected from tantalum, niobium, titanium nitride, and titanium nitride-niobium. For example, a 100 nm tantalum film is selected as the second superconducting metal layer 4.

[0063] Further, the second superconducting metal layer 4 located at the top layer is etched, and its shape, including the top electrode region 41 and the top pad region 42, must be preserved according to preset conditions. For example, RIE dry etching (reactive ion etching) can be used to process the second superconducting metal layer 4. The active substances in the plasma are used to selectively etch the metallic material of the second superconducting metal layer 4, causing a chemical reaction or physical bombardment with the material surface, thereby removing excess portions of the second superconducting metal layer 4. For example, F-based gas can be used for etching without damaging the insulating layer 3 and the first superconducting metal layer 2.

[0064] Then, the insulating layer 3 and the first superconducting metal layer 2 are partially removed by wet etching using an etchant with lateral characteristics. This results in the insulating layer 3 forming a barrier layer 31 of a second preset size, and the first superconducting metal layer 2 forming a bottom electrode region 21 and a pad region of the second preset size. It is worth noting that a crucial parameter of the Josephson junction is its room-temperature resistance, which depends on the thickness and area of ​​the barrier layer 31. In this embodiment, the junction area of ​​the Josephson junction depends on the linewidth of the etched top electrode region 41, barrier layer 31, and bottom electrode region 21. The resistance of the Josephson junction can be controlled by precisely controlling the area of ​​the junction region during the fabrication process. Figure 2 As shown, the first preset size and the second preset size are matched so that the top electrode region 41, the barrier layer 31 and the bottom electrode region 21 partially overlap in the direction perpendicular to the surface of the substrate 1 to form the junction region of the Josephson junction.

[0065] In one embodiment of this application, a method is provided for etching a second superconducting metal layer 4 to form a connected top electrode region 41 and a top pad region 42 having a first predetermined size. This method includes:

[0066] Step 1: A photoresist layer with a first blank area is formed on the surface of the second superconducting metal layer 4 facing away from the substrate 1; the first blank area exposes a portion of the second superconducting metal layer 4;

[0067] Step 2: Etch away the second superconducting metal layer 4 located in the first blank area, so that the second superconducting metal layer 4 forms the top electrode region 41 and the top pad region 42 with a first preset size.

[0068] The third step is to remove the photoresist layer.

[0069] First, a uniform photoresist layer is spin-coated onto the surface of the second superconducting metal layer 4 facing away from the substrate 1. Then, a first blank area is formed in the photoresist layer through exposure, development, and etching. Here, the portions of the second superconducting metal layer 4 that are blocked by the photoresist layer include the top electrode region 41 and the top pad region 42. Figure 3 and Figure 4 As shown, the second superconducting metal layer 4 located on the top layer is etched according to the aforementioned method, using a process such as RIE dry etching, so that the remaining part of the second superconducting metal layer 4 after etching is the top electrode region 41 and the top pad region 42. Finally, the excess photoresist layer is removed.

[0070] Please refer to Figure 5 In one embodiment of this application, a method is provided for etching an insulating layer 3 and a first superconducting metal layer 2 to form a barrier layer 31 of a second predetermined size, a bottom electrode region 21, and a bottom pad region 22. This method includes:

[0071] Step 1: A photoresist layer with a second blank area is formed on the surface of the insulating layer 3 facing away from the substrate 1; the second blank area exposes a portion of the insulating layer 3;

[0072] Step 2: Remove the insulating layer 3 and the first superconducting metal layer 2 by etching the second blank area;

[0073] Step 3: Remove the photoresist layer;

[0074] Step 4: Etch away a portion of the insulating layer 3 and a portion of the first superconducting metal layer 2 in the area opposite to the top electrode region 41 and the substrate 1, so that the insulating layer 3 forms the barrier layer 31 and the first superconducting metal layer 2 forms a connected bottom electrode region 21 and bottom pad region 22.

[0075] First, a photoresist layer with a second blank area is formed on the insulating layer 3. This photoresist layer abuts against the end of the top electrode region 41 away from the top pad region 42, and is used to protect part of the insulating layer 3 and the first superconducting metal layer 2. Then, the insulating layer 3 and the first superconducting metal layer 2 located below the second superconducting metal layer 4 are etched using the lateral characteristics of the etching solution.

[0076] Then the photoresist layer is removed, and a portion of the insulating layer 3 and a portion of the first superconducting metal layer 2 in the area opposite to the top electrode region 41 and the substrate 1 are etched again to form a barrier layer 31, a bottom electrode region 21, and a bottom pad region 22; so that the orthographic projections of the top electrode region 41, the barrier layer 31, and the bottom electrode region 21 on the surface of the substrate 1 intersect only partially, and this intersecting region is defined as the junction region of the Josephson junction.

[0077] Please refer to Figure 6 and Figure 7 This embodiment also provides a method for etching away a portion of the insulating layer 3 and a portion of the first superconducting metal layer 2 in the region opposite to the substrate 1 in the top electrode region 41. This method includes:

[0078] Step 1: A photoresist layer is formed on the surface of the region away from the first superconducting metal layer 2, the insulating layer 3, and the top electrode region 41 away from the substrate 1;

[0079] Step 2: Photolithography is used to form a window in the photoresist layer; the window exposes a portion of the top electrode region 41 and a portion of the substrate 1;

[0080] Step 3: Use etching solution to etch the insulating layer 3 and the first superconducting metal layer 2 located in the window through the window, so that the insulating layer 3 forms a barrier layer 31 and a first support layer 32 separated by the channel, and the first superconducting metal layer 2 forms a bottom electrode region 21 and a second support layer 23 separated by the channel.

[0081] Step 4: Remove the photoresist layer.

[0082] Since the area to be etched away is between the first superconducting metal layer 2 and the substrate 1, it is difficult to directly remove it using methods such as RIE dry etching. A photoresist layer is used to completely cover all devices on the surface of substrate 1, and a window is formed in the photoresist layer by photolithography, exposing part of the top electrode region 41 and part of substrate 1. Then, using an etchant corresponding to the materials of the first superconducting metal layer 2 and the insulating layer 3, the etchant enters the region between the second superconducting metal layer 4 and substrate 1 through the window, and wet etching is performed on the insulating layer 3 and the first superconducting metal layer 2 in this region, so that the insulating layer 3 forms a barrier layer 31 and a first support layer 32 separated by a channel, and the first superconducting metal layer 2 forms a bottom electrode region 21 and a second support layer 23 separated by a channel. It is worth noting that the etchant used to etch the insulating layer 3 and the first superconducting metal layer 2 will not have a significant negative impact on the second superconducting metal layer 4, such as etching. The first support layer 32 and the second support layer 23 are located in the space between the top electrode region 41 and the top pad region 42 and substrate 1, and are used to support the top electrode region 41 and the top pad region 42 to prevent collapse.

[0083] Specifically, the material of the first superconducting layer is aluminum; the etching solution is then selected as a mixed solution including phosphoric acid, acetic acid and nitric acid.

[0084] Using aluminum as the superconducting material for Josephson junctions has significant advantages. Through atomic layer deposition (ALD), an Al₂O₃ barrier layer 31 can be grown layer by layer on the metal surface, ultimately fabricating a Josephson junction with a sandwich structure, which is advantageous for the embodiments of this application. Furthermore, aluminum oxide (Al₂O₃) possesses excellent barrier properties, suitable for Cooper pair tunneling processes; therefore, Al₂O₃ is also frequently used as the material for the barrier layer 31.

[0085] Aluminum, as a superconducting material, is highly compatible with existing microelectronic processing technologies. This allows it to be used even on existing semiconductor production lines to manufacture superconducting quantum devices, fully utilizing its uniformity, stability, and excellent superconducting properties.

[0086] When the material of the first superconducting layer is aluminum, the etching solution used in this embodiment is a mixture of phosphoric acid, acetic acid, and nitric acid in a ratio of approximately 7:2:1. This is an important wet etching technique with good etching effect. The ratio of each solution in the etching solution is continuously determined through experimental research and optimization to ensure optimal etching effect when etching the aluminum film. Phosphoric acid acts as the main etchant in the etching solution, effectively corroding the aluminum film surface. Nitric acid, as a strong oxidant, enhances the activity of the etching solution to promote the etching reaction; its ratio is mainly determined based on the required etching rate and selectivity. Acetic acid helps adjust the pH of the etching solution and also participates in the etching reaction, removing metal ions generated during the etching process and preventing metal ion deposition that could affect the etching effect.

[0087] Specifically, the etching rate of the aforementioned etching solution on the aluminum film at 25°C is about 1 nm / s. This rate is relatively stable, so the etching depth can be precisely controlled by adjusting the etching time and the concentration of the etching solution. This is undoubtedly an excellent condition for determining the etching depth, and can prevent over-etching or under-etching in actual etching processes.

[0088] In some cases, the aforementioned etching solution mainly etches the aluminum film without reacting with other materials such as Ta (tantalum) and TiN (titanium nitride). When the material of the second superconducting layer is one of the above materials, this selective etching characteristic is very important, as it can protect the second superconducting layer from the effects of the etching process of other layers, thereby ensuring the integrity of the quantum device.

[0089] In the embodiments of this application, the material of the second superconducting metal layer 4 is not limited, and the material may be, for example, one of tantalum, niobium, titanium nitride, and titanium nitride niobium.

[0090] In superconducting quantum chips, Josephson junctions are used to realize qubits, the fundamental building blocks of quantum computing. Superconducting quantum chips utilize the properties of Josephson junctions to control and read out qubits. For example, by changing the parameters of the Josephson junction and the external magnetic field, the state of the qubits can be precisely manipulated to achieve quantum gate operations.

[0091] Josephson junctions are also used to construct qubits. For example, a qubit is a Josephson junction manufactured by the aforementioned method, consisting of two electrodes connected in parallel with a capacitor. This structure makes the energy levels of the Josephson junction insensitive to fluctuations in ambient charge, thus providing a longer coherence time.

[0092] Furthermore, superconducting quantum chips often include multiple qubits, with adjacent qubits directly coupled through capacitance or inductance, and SQUIDs are introduced to enable frequency tunability of the qubits. Additionally, superconducting qubits generally employ a dispersive readout method, where the qubit is dispersively coupled to a readout resonant cavity, and the readout signal is amplified through a Josephson junction parametric amplifier to improve readout fidelity and speed.

[0093] In one embodiment of this application, a superconducting quantum chip is provided, comprising: a Josephson junction manufactured by the aforementioned method for manufacturing a Josephson junction, a top pad, and a bottom pad. The top pad is manufactured in the aforementioned top pad region 42 and electrically connected to the end of the top electrode region 41 away from the junction region; the bottom pad is manufactured in the aforementioned bottom pad region 22 and electrically connected to the end of the bottom electrode region 21 away from the junction region.

[0094] The pads at both ends of the Josephson junction electrodes are crucial in superconducting quantum chips. For example, as connection points between the electrodes and external circuits, the pads allow current to flow into and out of the Josephson junction, which is essential for controlling the superconducting current in the Josephson junction and manipulating qubits. Furthermore, the pads help protect the Josephson junction from external environmental influences, thereby improving the performance and stability of the superconducting circuitry.

[0095] Furthermore, the top pad and top electrode region 41 are integrally formed; and / or, the bottom pad and bottom electrode region 21 are integrally formed. This integral forming technology of pads and Josephson junction electrodes plays a crucial role in the fabrication of superconducting quantum chips. It not only improves device integration and electrical performance but also enhances mechanical stability, simplifies the manufacturing process, and increases production efficiency. This design approach allows for denser device placement, reduces the impact of resistance and parasitic capacitance, thereby optimizing electrical characteristics. Simultaneously, the integrated structure improves device stability under temperature and mechanical stress, reduces production costs, and provides greater design flexibility for different application requirements, playing a vital role in improving the overall performance of superconducting quantum chips and advancing quantum technology.

[0096] Specifically, the size of the top pad region 42 is larger than the size of the top electrode region 41; and / or, the size of the bottom pad region 22 is larger than the size of the bottom electrode region 21. As the connection path between the Josephson junction and external circuits, the pads need to establish a good electrical connection. Larger pads, compared to nanoscale Josephson junction electrodes, provide a larger contact area, thereby reducing contact resistance and ensuring the reliability of the electrical connection. Furthermore, during manufacturing, there may be alignment errors between the electrodes and pads of the Josephson junction; that is, the pads and electrodes may not be perfectly aligned. Larger pads provide a certain tolerance, ensuring the effectiveness of the connection between the pads and electrodes even with slight alignment deviations.

[0097] In one embodiment of this application, a quantum computer is also provided, which is at least provided with the superconducting quantum chip described in the embodiments of this application, wherein magnetic flux control signal lines and pulse modulation lines are formed on the qubits to realize control, readout and other element structures.

[0098] It is understood that the manipulation and reading device uses the magnetic flux modulation signal on the magnetic flux modulation signal line to adjust the frequency of the superconducting quantum bit to the operating frequency. At this time, a quantum state control signal is applied through the pulse modulation line to control the quantum state of the superconducting quantum bit in its initial state, and the quantum state of the controlled superconducting quantum bit is read using a readout resonant cavity. It should be noted that the superconducting quantum chip set in the quantum computer has a similar structure to the superconducting quantum chip in the above-described embodiment and has the same beneficial effects as the superconducting quantum chip and embodiment described above, so it will not be described again. For technical details not disclosed in the quantum computer embodiments of this application, those skilled in the art should refer to the description of the Josephson junction and superconducting quantum chip structure described above, and for the sake of brevity, they will not be described again here.

[0099] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0100] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for manufacturing a Josephson knot, characterized in that, include: A first superconducting metal layer (2), an insulating layer (3), and a second superconducting metal layer (4) are sequentially stacked on the surface of a substrate (1) by means of film deposition. The second superconducting metal layer (4) is etched to form a connected top electrode region (41) and a top pad region (42) with a first preset size; The insulating layer (3) and the first superconducting metal layer (2) are etched such that the insulating layer (3) forms a barrier layer (31) of a second preset size, and the first superconducting metal layer (2) forms a bottom electrode region (21) and a bottom pad region (22) of a second preset size; wherein, in a direction perpendicular to the surface, the top electrode region (41), the barrier layer (31) and the bottom electrode region (21) overlap to form a junction region of a Josephson junction.

2. The method for manufacturing a Josephson knot according to claim 1, characterized in that, The method for etching the second superconducting metal layer (4) to form a connected top electrode region (41) and a top pad region (42) with a first preset size includes: A photoresist layer with a first blank area is formed on the surface of the second superconducting metal layer (4) facing away from the substrate (1); the first blank area exposes a portion of the second superconducting metal layer (4); The second superconducting metal layer (4) located in the first blank area is etched away, so that the second superconducting metal layer (4) forms a connected top electrode region (41) and a top pad region (42) with a first preset size; Remove the photoresist layer.

3. The method for manufacturing a Josephson knot according to claim 1, characterized in that, The method for forming a barrier layer (31), a bottom electrode region (21), and a bottom pad region (22) of a second predetermined size in the etched insulating layer (3) and the first superconducting metal layer (2) includes: A second blank area photoresist layer is formed on the surface of the insulating layer (3) facing away from the substrate (1); the second blank area exposes a portion of the insulating layer (3); The insulating layer (3) and the first superconducting metal layer (2) are removed by etching in the second blank area; Remove the photoresist layer; Etching removes a portion of the insulating layer (3) and a portion of the first superconducting metal layer (2) in the region opposite to the top electrode region (41) and the substrate (1), so that the insulating layer (3) forms the barrier layer (31) and the first superconducting metal layer (2) forms a connected bottom electrode region (21) and bottom pad region (22).

4. The method for manufacturing a Josephson knot according to claim 3, characterized in that, The method for etching away a portion of the insulating layer (3) and a portion of the first superconducting metal layer (2) in the region opposite to the top electrode region (41) and the substrate (1) includes: A photoresist layer is formed on the surface of the region away from the first superconducting metal layer (2), the insulating layer (3), and the top electrode region (41) away from the substrate (1); The photoresist layer is photolithographically etched to form a window; the window exposes a portion of the top electrode region (41) and a portion of the substrate (1); The insulating layer (3) and the first superconducting metal layer (2) located within the window are etched through the window using an etching solution, so that the insulating layer (3) forms a barrier layer (31) and a first support layer (32) separated by a channel, and the first superconducting metal layer (2) forms a bottom electrode region (21) and a second support layer (23) separated by a channel. Remove the photoresist layer.

5. The method for manufacturing a Josephson knot according to claim 4, characterized in that, The material of the first superconducting layer is aluminum; The etching solution is a mixed solution comprising phosphoric acid, acetic acid and nitric acid.

6. The method for manufacturing a Josephson knot according to any one of claims 1-5, characterized in that, The material of the second superconducting metal layer (4) is one of tantalum, niobium, titanium nitride, and titanium nitride niobium.

7. A superconducting quantum chip, characterized in that, include: Josephson knots manufactured by the manufacturing method according to any one of claims 1-6; The top pad is electrically connected to the end of the top electrode region (41) away from the junction region; The bottom pad is electrically connected to the end of the bottom electrode region (21) away from the junction region.

8. The superconducting quantum chip according to claim 7, characterized in that, The top pad is integrally formed with the top electrode region (41); And / or, the bottom pad is integrally formed with the bottom electrode region (21).

9. The superconducting quantum chip according to claim 7 or 8, characterized in that, The size of the top pad region (42) is larger than the size of the top electrode region (41); And / or, the size of the bottom pad region (22) is larger than the size of the bottom electrode region (21).

10. A quantum computer, characterized in that, include: The superconducting quantum chip according to any one of claims 7-9.

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