Manufacturing method of superconducting quantum device and superconducting quantum device

Abstract

The invention provides a manufacturing method of a superconducting quantum device and the superconducting quantum device. The manufacturing method comprises the steps that a Josephson junction is formed on a substrate, and a lower superconducting layer of the Josephson junction extends out of a barrier layer and an upper superconducting layer of the Josephson junction in the transverse direction; forming a resistance layer on the substrate, wherein the resistance layer is separated from the Josephson junction in the transverse direction; forming an insulating layer on the substrate to cover the Josephson junction and the resistive layer; forming through holes in the insulating layer, wherein the through holes comprise a first through hole for exposing the upper superconducting layer, a second through hole for exposing the lower superconducting layer and a third through hole for exposing the resistive layer; and forming a lead layer on the insulating layer in which the through holes are formed, the lead layer including a portion filled in the first through hole, the second through hole, and the third through hole and continuously extending between the second through hole and the third through hole to electrically connect the lower superconducting layer and the resistive layer of the Josephson junction.

Description

Fabrication methods of superconducting quantum devices and superconducting quantum devices Technical Field

[0001] This disclosure relates to the field of superconducting electronics technology, and more specifically to a method for manufacturing a superconducting quantum device and the superconducting quantum device itself. Background Technology

[0002] A Josephson junction is a quantum device consisting of two superconducting layers separated by an extremely thin insulating barrier layer. Electron pairs in the superconductors tunnel through the barrier layer using the quantum tunneling effect, generating a dissipationless superconducting current. As one of the core components in superconducting electronics, the Josephson junction is widely used in various superconducting quantum devices. Currently, in the fabrication of Josephson junctions, to effectively bridge the resistance layer, the conductive layer connecting the Josephson junction and the resistive layer is typically etched using a tilted etching process. This results in a steep slope in the conductive layer's morphology, increasing the inductance deviation. Simultaneously, a resistive layer of a certain thickness needs to be deposited to ensure a good connection between the resistive and conductive layers. Furthermore, before the resistive layer is bridged, particle beam bombardment is often used to remove oxides from the conductive layer's surface, which increases the functional requirements of the manufacturing equipment. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a method for manufacturing a superconducting quantum device and the superconducting quantum device.

[0004] According to a first aspect of this disclosure, a method for fabricating a superconducting quantum device is provided. The method includes: forming a Josephson junction on a substrate, wherein a lower superconducting layer of the Josephson junction extends laterally beyond a barrier layer and an upper superconducting layer of the Josephson junction; forming a resistive layer on the substrate, the resistive layer being laterally spaced from the Josephson junction; forming an insulating layer on the substrate to cover the Josephson junction and the resistive layer; forming vias in the insulating layer, the vias including a first via exposing the upper superconducting layer, a second via exposing the lower superconducting layer, and a third via exposing the resistive layer; and forming a conductive layer on the insulating layer with the vias, the conductive layer including portions filling the first, second, and third vias and extending continuously between the second and third vias to electrically connect the lower superconducting layer and the resistive layer of the Josephson junction.

[0005] According to embodiments of this disclosure, a conductive layer is formed on an insulating layer with vias, including etching the conductive layer, the etching process being determined based on the inductance requirements of the conductive layer.

[0006] According to embodiments of this disclosure, forming a Josephson junction on a substrate includes: sequentially forming a first preconducting superconducting layer, a preconducting barrier layer, and a second preconducting superconducting layer on the substrate; etching the second preconducting superconducting layer to form an upper superconducting layer, thereby defining a junction region; performing anodic oxidation to repair damage caused to the preconducting barrier layer, the first preconducting superconducting layer, and the upper superconducting layer during the etching process; etching the preconducting barrier layer to form a barrier layer, the barrier layer extending laterally beyond the upper superconducting layer; and etching the first preconducting superconducting layer to form a lower superconducting layer.

[0007] According to embodiments of this disclosure, after anodizing, an oxide layer is formed on the sidewalls of the upper superconducting layer, the upper and lower surfaces of the pre-barrier layer, and the portion of the pre-barrier layer that extends laterally beyond the upper superconducting layer.

[0008] According to embodiments of the present disclosure, an insulating layer is formed on a substrate using a conformal deposition method to cover the Josephson junction and the resistive layer. The conformal deposition includes plasma-enhanced chemical vapor deposition.

[0009] According to embodiments of this disclosure, before forming a conductive layer on an insulating layer with vias, the manufacturing method further includes removing residual insulating layers on the lower superconducting layer, upper superconducting layer, and resistive layer within the vias.

[0010] According to embodiments of this disclosure, the lower superconducting layer and the upper superconducting layer comprise any one of niobium or other superconducting materials, and the barrier layer comprises a mixture of aluminum and alumina.

[0011] According to embodiments of this disclosure, the thickness of the lower superconducting layer and the upper superconducting layer ranges from 50 nm to 400 nm, and the thickness of the barrier layer ranges from 2 nm to 20 nm.

[0012] According to a second aspect of this disclosure, a superconducting quantum device is provided, comprising a substrate and a Josephson junction, a resistive layer, an insulating layer, and a conductive layer on the substrate. The lower superconducting layer of the Josephson junction extends laterally beyond the barrier layer and the upper superconducting layer of the Josephson junction. The resistive layer is laterally spaced from the Josephson junction. The insulating layer is located on the Josephson junction and the resistive layer and has vias, including a first via exposing the upper superconducting layer, a second via exposing the lower superconducting layer, and a third via exposing the resistive layer. The conductive layer is located on the insulating layer and includes portions filling the first, second, and third vias and extending continuously between the second and third vias to electrically connect the resistive layer and the lower superconducting layer of the Josephson junction.

[0013] According to embodiments of this disclosure, the superconducting quantum device further includes an oxide layer located on the sidewalls of the upper superconducting layer, on the upper and lower surfaces of the barrier layer, and on a portion of the barrier layer extending laterally beyond the upper superconducting layer.

[0014] According to embodiments of this disclosure, a method for manufacturing a superconducting quantum device is provided. This method moves the fabrication process of the resistive layer before the deposition process of the conductive layer, thereby enhancing the selectivity of the conductive layer etching process. This allows it to be applied to superconducting quantum devices with high requirements for the perpendicularity of the conductive layer, improving the inductance accuracy of the device and reducing the impact of residual photoresist caused by the photolithography process on the overlap resistance in subsequent resistive layer deposition methods. Simultaneously, this method reduces limitations on the resistive layer thickness, thereby lowering production costs, increasing device integration, and avoiding the process of using particle beam bombardment to remove oxides from the conductive layer surface, thus reducing the functional requirements of the equipment. Attached Figure Description

[0015] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 schematically illustrates a flowchart of a method for manufacturing a superconducting quantum device according to an embodiment of the present disclosure;

[0017] Figure 2 schematically illustrates the structure of forming a first preconducting layer, a preconducting barrier layer, and a second preconducting layer in a manufacturing method according to an embodiment of the present disclosure.

[0018] Figure 3 schematically illustrates the structure of the defined junction region in the manufacturing method according to an embodiment of the present disclosure;

[0019] Figure 4 schematically illustrates a structural diagram of anodizing performed in a manufacturing method according to an embodiment of the present disclosure;

[0020] Figure 5 schematically illustrates a structural diagram of forming a barrier layer in a manufacturing method according to an embodiment of the present disclosure;

[0021] Figure 6 schematically illustrates a structural diagram of forming a lower superconducting layer in a manufacturing method according to an embodiment of the present disclosure;

[0022] Figure 7 schematically illustrates the structure of the deposited resistive layer in the manufacturing method according to an embodiment of the present disclosure;

[0023] Figure 8 schematically illustrates a structural diagram of forming an insulating layer in a manufacturing method according to an embodiment of the present disclosure;

[0024] Figure 9 schematically illustrates a structural diagram of a through-hole formed in a manufacturing method according to an embodiment of the present disclosure;

[0025] Figure 10 schematically illustrates the structure of a superconducting quantum device according to an embodiment of the present disclosure. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0027] The endpoints and any values ​​of the ranges disclosed in this disclosure are not limited to the precise ranges or values, and such ranges or values ​​should be understood to include values ​​close to such ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be regarded as specifically disclosed in this disclosure.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0029] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0030] In the description of this disclosure, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the subsystem or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0031] Similarly, to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present disclosure. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0032] A Josephson junction is a quantum device formed by two superconducting layers separated by an extremely thin insulating barrier layer. When a superconducting current passes through it, superconducting electron pairs can tunnel through the barrier layer, producing macroscopic quantum effects. Josephson junctions are widely used in superconducting quantum interference devices, such as superconducting quantum interference devices, ultrafast single-flux quantum qubits, flux qubits, qubit couplers, traveling-wave parametric amplifiers, Josephson parametric amplifiers, qubit readout cavities, on-chip microwave sources, and on-chip circulators. Currently, in the fabrication of Josephson junctions, to effectively bridge the resistance, the conductive layer connecting the Josephson junction and the resistive layer is typically etched using a tilted etching process, resulting in a steep slope in the conductive layer's morphology. This increases the inductance deviation of the conductive layer. Simultaneously, a resistive layer of a certain thickness needs to be deposited to ensure a good connection between the resistive layer and the conductive layer. Furthermore, before bridging the resistance in the conductive layer, an additional power supply device is often required to bombard the conductive layer with a particle beam to remove oxides from the surface of the conductive layer, further increasing the requirements for the manufacturing equipment.

[0033] In view of this, embodiments of the present disclosure provide a method for manufacturing a superconducting quantum device and a superconducting quantum device. This method advances the manufacturing process of the resistive layer, thereby enhancing the selectivity of the etching process for the conductive layer, which can be arbitrarily selected according to device requirements, such as tilted etching or vertical etching. Furthermore, this manufacturing method reduces limitations on the thickness of the resistive layer, lowers production costs, and avoids the particle beam backsputtering process before resistive layer deposition, as well as the contact problems between the conductive layer and the resistive layer caused by the backsputtering process, thus reducing the functional requirements of the coating equipment.

[0034] Figure 1 schematically illustrates a flowchart of a method for manufacturing a superconducting quantum device according to an embodiment of the present disclosure.

[0035] As shown in FIG1, the manufacturing method of this embodiment may include operations S101 to S105.

[0036] In operation S101, a Josephson junction is formed on the substrate, with the lower superconducting layer of the Josephson junction extending laterally beyond the barrier layer and the upper superconducting layer of the Josephson junction.

[0037] In operation S102, a resistive layer is formed on the substrate, the resistive layer being laterally spaced from the Josephson junction.

[0038] In operation S103, an insulating layer is formed on the substrate to cover the Josephson junction and the resistive layer.

[0039] In operation S104, through holes are formed in the insulating layer. The through holes include a first through hole exposing the upper superconducting layer, a second through hole exposing the lower superconducting layer, and a third through hole exposing the resistive layer.

[0040] In operation S105, a conductive layer is formed on the insulating layer with through holes. The conductive layer includes portions that fill the first through hole, the second through hole, and the third through hole, and that extend continuously between the second through hole and the third through hole, to electrically connect the lower superconducting layer and the resistive layer of the Josephson junction.

[0041] According to embodiments of this disclosure, a method for manufacturing a superconducting quantum device is provided. This method moves the manufacturing process of the resistive layer before the deposition of the conductive layer, thereby enhancing the selectivity of the conductive layer etching process. This allows it to be applied to superconducting quantum devices with high requirements for the perpendicularity of the conductive layer, improving the inductance accuracy of the device and reducing the impact of residual photoresist caused by the photolithography process on the overlap resistance in subsequent resistive layer deposition methods. Simultaneously, this method reduces limitations on the thickness of the resistive layer, thereby lowering production costs, increasing device integration, and avoiding the process of using particle beam bombardment to remove oxides from the conductive layer surface, thus reducing the functional requirements of the equipment.

[0042] Forming a conductive layer on an insulating layer with vias involves etching the conductive layer. The etching process can be determined based on the inductance requirements of the conductive layer. Etching processes can include tilting etching or perpendicular etching. Tilting etching of the conductive layer requires high process control; different etching angles at different locations can lead to uneven inductance distribution in the device, and deviations in the geometric dimensions of the conductive layer can also cause the inductance value to deviate from the design value, resulting in increased inductance deviation of the device.

[0043] According to embodiments of this disclosure, the etching process for the conductive layer can be determined based on the inductance requirements of the conductive layer, which is beneficial for manufacturing devices with specific inductance requirements for the conductive layer. Using a vertical etching process for the conductive layer can improve the inductance accuracy of the conductive layer.

[0044] The following description, based on schematic diagrams of the structures obtained during the fabrication of superconducting quantum devices according to embodiments of this disclosure, and in conjunction with Figures 2-10, illustrates the fabrication method of embodiments of this disclosure. It should be noted that this disclosure can be presented in various forms, and some examples will be described below. In the following description, various material selections are involved. Material selection considers not only its functionality but also etching selectivity. In the following description, desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following mentions etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, such etching can be selective, and the material layer can possess etching selectivity relative to other layers exposed to the same etching formulation.

[0045] Figures 2 through 10 schematically illustrate the structural diagrams of each stage in the method for manufacturing a superconducting quantum device according to embodiments of the present disclosure.

[0046] As shown in Figure 2, a substrate 1 can be provided. For example, substrate 1 may include high-resistivity silicon oxide, etc. Pre-treatment operations such as cleaning can be performed on substrate 1. First, a first pre-superconducting layer 21 can be formed on substrate 1 by deposition. The first pre-superconducting layer 21 may include any of niobium or other superconducting materials. The thickness of the first pre-superconducting layer 21 may include 50 nm to 400 nm. Next, a metal layer can be deposited on the first pre-superconducting layer 21 and oxidized to form a pre-barrier layer 31. The metal layer may include aluminum, and the pre-barrier layer 31 may include a mixture of aluminum and aluminum oxide. The oxidation time and gas pressure can be determined based on the device current density requirements. The thickness of the pre-barrier layer 31 may include 2 nm to 20 nm. Subsequently, a second pre-superconducting layer 41 can be deposited on the pre-barrier layer 31. The second pre-superconducting layer 41 may include any of niobium or other superconducting materials. The thickness of the second pre-superconducting layer 41 may include 50 nm to 400 nm.

[0047] During the deposition process, the film stress of the first preconducting layer 21 and the second preconducting layer 41 can be controlled between -300 MPa and 200 MPa, the roughness is less than 3 nm, the residual resistivity is not less than 3.5 ohm-meters, and the transition temperature is not less than 9 K.

[0048] As shown in Figure 3, the second pre-superconducting layer 41 can be etched to form the upper superconducting layer 4, thereby defining the junction region. A patterned first photoresist layer 42 can be formed on the second pre-superconducting layer 41. The first photoresist layer 42 may include positive photoresist. The exposure method in the patterning process can be ultraviolet contact exposure or laser direct writing, etc. The second pre-superconducting layer 41 can be etched using reactive ion etching (RIE) and inductively coupled plasma (ICP) processes to form the upper superconducting layer 4. During the etching process, methods such as endpoint detection marking can be used to stop the etching at the point where the pre-barrier layer 31 is exposed.

[0049] As shown in Figure 4, anodizing can be performed to repair damage caused to the preparatory barrier layer 31, the first preparatory superconducting layer 21, and the upper superconducting layer 4 during the etching process. After anodizing, oxide layers can be formed on the sidewalls of the upper superconducting layer 4, the upper and lower surfaces of the preparatory barrier layer 31, and the portion of the preparatory barrier layer 31 extending laterally beyond the upper superconducting layer 4. A first oxide layer 5 can be formed on the portion of the preparatory barrier layer 31 extending laterally beyond the upper superconducting layer 4. A second oxide layer 6 can be formed on the sidewalls of the upper superconducting layer 4 and the upper and lower surfaces of the preparatory barrier layer 31. In a specific embodiment, if the first preparatory superconducting layer 21, the preparatory barrier layer 31, and the upper superconducting layer 4 are a mixture of niobium, aluminum, and aluminum oxide, and niobium, respectively, the first oxide layer 5 may include aluminum oxide, and the second oxide layer 6 may include niobium oxide.

[0050] The electrolyte for anodizing can be a mixture of ammonium pentaborate, ethylene glycol, and deionized water. The degree of oxidation can depend on the damage to the pre-determination barrier layer 31, the first pre-determination superconducting layer 21, and the upper superconducting layer 4 during etching. After anodizing, the first photoresist layer 42 can be removed by ultrasonic treatment with acetone, isopropanol, and deionized water in sequence, followed by drying.

[0051] As shown in Figure 5, a patterned second photoresist layer 43 can be formed on the upper superconducting layer 4. The second photoresist layer 43 extends laterally beyond the upper superconducting layer 4 to prevent damage to the junction region during subsequent etching. The second photoresist layer 43 may include positive photoresist. The exposure method in the patterning process can be ultraviolet contact exposure or laser direct writing, etc. Ion beam etching (IBE) can be used to etch the pre-determination barrier layer 31 along the sidewalls of the second photoresist layer 43 to form the barrier layer 3, which extends laterally beyond the upper superconducting layer 4. In this process, part of the first oxide layer 5 and the second oxide layer 6 on the upper and lower surfaces of the first oxide layer 5 can be retained in the region of the pre-determination barrier layer 31. The second photoresist layer 43 is removed after etching.

[0052] As shown in Figure 6, the first pre-conducting layer 21 can be etched to form the lower superconducting layer 2. This process can be performed using the same method as for forming the upper superconducting layer 4 to form the lower superconducting layer 2, which extends laterally beyond the barrier layer 3 and the upper superconducting layer 4. After etching, the photoresist is removed.

[0053] Thus, a Josephson junction 7 comprising a lower superconducting layer 2, a barrier layer 3, and an upper superconducting layer 4 is formed on substrate 1.

[0054] The lower superconducting layer 2 and the upper superconducting layer 4 may comprise niobium or any other superconducting material. The thickness of the lower superconducting layer 2 and the upper superconducting layer 4 may range from 50 nm to 400 nm, for example, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, etc. The barrier layer 3 may comprise a mixture of aluminum and alumina. The thickness of the barrier layer 3 may range from 2 nm to 20 nm, for example, 2 nm, 5 nm, 10 nm, 15 nm, 20 nm, etc.

[0055] As shown in Figure 7, a resistive layer 8 can be formed on the substrate 1. The resistive layer 8 can be spaced apart from the Josephson junction 7 in the lateral direction. The resistive layer 8 may include PdAu, etc. To increase the adhesion between the resistive layer 8 and the substrate 1, a metal Ti can be deposited on the substrate 1 as an adhesion layer (not shown in Figure 7). This process can utilize negative photoresist to form the photolithographic pattern of the resistive layer 8, followed by the removal of the negative photoresist.

[0056] As shown in Figure 8, an insulating layer 9 can be formed on substrate 1 using conformal deposition to cover the Josephson junction 7 and resistive layer 8. Conformal deposition can include inductively coupled plasma chemical vapor deposition (ICP-CVD). The thickness of the conformal deposition can be greater than the thickness difference between the lower and upper superconducting layers of the Josephson junction 7. For example, if the upper superconducting layer is 50 nm thick and the lower superconducting layer is 400 nm thick, the thickness of the conformal deposition can be 360 ​​nm.

[0057] As shown in Figure 9, vias can be formed on the insulating layer 9 using RIE and ICP processes, including a first via 91 exposing the upper superconducting layer 4, a second via 92 exposing the lower superconducting layer 2, and a third via 93 exposing the resistive layer 8. During the etching process, an endpoint detection marker method can be used to stop the etching of the first via 91, the second via 92, and the third via 93 at the point where the upper superconducting layer 4, the lower superconducting layer 2, and the resistive layer 8 are exposed, respectively.

[0058] After the insulating layer 9 with through holes is formed, the first through hole 91, the second through hole 92 and the third through hole 93 can be processed by an radio frequency source to remove the insulating layer 9 remaining on the lower superconducting layer 2, the upper superconducting layer 4 and the resistive layer 8 inside the through holes.

[0059] As shown in Figure 10, a conductive layer material can be deposited on the insulating layer 9 with vias. The conductive layer material may include niobium, etc. A patterned positive photoresist can be formed on the conductive layer material. The exposure method in the patterning process may be ultraviolet contact exposure or laser direct writing, etc. The conductive layer material can be etched using RIE and ICP processes to form the conductive layer 10. The conductive layer 10 may include a first portion 101 filled in the first via 91 and connected to the upper superconducting layer 4 of the Josephson junction 7, a second portion 102 filled in the second via 92 and the third via 93 and continuously extending between the second via 92 and the third via 93 to electrically connect the lower superconducting layer 2 and the resistive layer 8 of the Josephson junction 7, and a third portion 103 filled in the third via 93 and connected to the resistive layer 8, thereby realizing the electrical connection between the Josephson junction 7 and the resistive layer 8.

[0060] According to embodiments of this disclosure, the manufacturing method shifts the manufacturing process of the resistive layer 8 forward, thereby enhancing the selectivity of the etching process for the conductive layer 10. This allows for arbitrary selection based on device requirements, such as tilted etching or vertical etching. Furthermore, this manufacturing method reduces the particle beam backsputtering process prior to the deposition of the resistive layer 8, avoiding contact problems between the conductive layer 10 and the resistive layer 8 caused by the backsputtering process, and also reducing the functional requirements of the coating equipment.

[0061] Referring again to FIG. 10, the superconducting quantum device of the present disclosure embodiment can be fabricated using the above-described manufacturing method. The superconducting quantum device may include a substrate 1 and a Josephson junction 7, a resistive layer 8, an insulating layer 9, and a conductive layer 10 on the substrate 1. The lower superconducting layer 2 of the Josephson junction 7 may extend laterally beyond the barrier layer 3 and the upper superconducting layer 4 of the Josephson junction 7. The resistive layer 8 may be laterally spaced from the Josephson junction 7. The insulating layer 9 may be located on the Josephson junction 7 and the resistive layer 8 and have vias. The vias may include a first via 91 exposing the upper superconducting layer 4, a second via 92 exposing the lower superconducting layer 2, and a third via 93 exposing the resistive layer 8. The conductive layer 10 is located on the insulating layer 9 and may include portions filling the first via 91, the second via 92, and the third via 93, and extending continuously between the second via 92 and the third via 93, to electrically connect the resistive layer 8 and the lower superconducting layer 2 of the Josephson junction 7.

[0062] In a specific embodiment, the superconducting quantum device may further include an oxide layer. The oxide layer may include a first oxide layer 5 located on the barrier layer 3 extending laterally into the upper superconducting layer 4, and a second oxide layer 6 located on the sidewalls of the upper superconducting layer 4 and on the upper and lower surfaces of the barrier layer.

[0063] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0064] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a superconducting quantum device, characterized in that, include: A Josephson junction is formed on a substrate, wherein the lower superconducting layer of the Josephson junction extends laterally beyond the barrier layer and the upper superconducting layer of the Josephson junction; a resistive layer is formed on the substrate, which is laterally spaced from the Josephson junction; an insulating layer is formed on the substrate to cover the Josephson junction and the resistive layer; vias are formed in the insulating layer, the vias including a first via exposing the upper superconducting layer, a second via exposing the lower superconducting layer, and a third via exposing the resistive layer; and a conductive layer is formed on the insulating layer in which the vias are formed, the conductive layer including portions filling the first via, the second via, and the third via, and extending continuously between the second via and the third via, to electrically connect the lower superconducting layer and the resistive layer of the Josephson junction.

2. The manufacturing method according to claim 1, characterized in that, The process of forming a conductive layer on the insulating layer in which the via is formed includes etching the conductive layer, wherein the etching process is determined based on the inductance requirements of the conductive layer.

3. The manufacturing method according to claim 1, characterized in that, The formation of a Josephson junction on a substrate includes: sequentially forming a first pre-superconducting layer, a pre-barrier layer, and a second pre-superconducting layer on the substrate; etching the second pre-superconducting layer to form the upper superconducting layer, thereby defining the junction region; performing anodic oxidation to repair damage caused to the pre-barrier layer, the first pre-superconducting layer, and the upper superconducting layer during the etching process; etching the pre-barrier layer to form the barrier layer, the barrier layer extending laterally beyond the upper superconducting layer; and etching the first pre-superconducting layer to form the lower superconducting layer.

4. The manufacturing method according to claim 3, characterized in that, After the anodizing is performed, an oxide layer is formed on the sidewalls of the upper superconducting layer, the upper and lower surfaces of the pre-barrier layer, and the portion of the pre-barrier layer that extends laterally beyond the upper superconducting layer.

5. The manufacturing method according to claim 1, characterized in that, An insulating layer is formed on the substrate using a conformal deposition method to cover the Josephson junction and the resistive layer, the conformal deposition including plasma-enhanced chemical vapor deposition.

6. The manufacturing method according to claim 1, characterized in that, Before forming a conductive layer on the insulating layer in which the through-hole is formed, the manufacturing method further includes: removing the insulating layer remaining in the through-hole on the lower superconducting layer, the upper superconducting layer and the resistive layer.

7. The manufacturing method according to claim 1, characterized in that, The lower superconducting layer and the upper superconducting layer comprise any one of niobium or other superconducting materials, and the barrier layer comprises a mixture of aluminum and alumina.

8. The manufacturing method according to claim 1, characterized in that, The thickness of the lower superconducting layer and the upper superconducting layer ranges from 50 nm to 400 nm, and the thickness of the barrier layer ranges from 2 nm to 20 nm.

9. A superconducting quantum device, characterized in that, include: A substrate; a Josephson junction on the substrate, wherein a lower superconducting layer of the Josephson junction extends laterally beyond a barrier layer and an upper superconducting layer of the Josephson junction; a resistive layer on the substrate, the resistive layer being laterally spaced from the Josephson junction; an insulating layer on the Josephson junction and the resistive layer, the insulating layer having vias, the vias including a first via exposing the upper superconducting layer, a second via exposing the lower superconducting layer, and a third via exposing the resistive layer; and a conductive layer on the insulating layer, the conductive layer including portions filling the first via, the second via, and the third via, and extending continuously between the second via and the third via, to electrically connect the resistive layer and the lower superconducting layer of the Josephson junction.

10. The superconducting quantum device according to claim 9, characterized in that, The superconducting quantum device further includes an oxide layer located on the sidewall of the upper superconducting layer, on the upper and lower surfaces of the barrier layer, and on a portion of the barrier layer that extends laterally beyond the upper superconducting layer.

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