Chip-to-wafer bonding structure thinning method and chip-to-wafer bonding structure

Abstract

The invention provides a chip-to-wafer bonding structure thinning method and a chip-to-wafer bonding structure. After bonding and before thinning, the edge of the side wall of the chip is optimized into an arc profile such as a chamfer or a fillet, so that the transverse shear force generated when a thinning tool such as a polishing pad for chemical mechanical polishing is in contact with the side wall of the chip is effectively reduced, and the chip can stably bear the stress in the thinning process only by virtue of the bonding strength of the chip and the substrate; and supporting materials do not need to be filled. According to the method, the technological process is simplified, the problems of cost control, technological difficulty and the like caused by material filling are solved, and the problem of splitting defects caused by transverse shearing force of the isolated chip in the chemical mechanical polishing process is effectively solved.

Description

Technical Field

[0001] This invention belongs to the field of advanced semiconductor packaging technology, and particularly relates to a chip-to-wafer bonding structure thinning method and chip-to-wafer bonding structure. Background Technology

[0002] As semiconductor process nodes continue to advance, the critical dimensions of integrated circuits (ICs) continue to shrink, and Moore's Law, which traditionally relies on transistor size reduction to improve performance and reduce costs, is gradually facing bottlenecks. On the one hand, the technical difficulty and manufacturing cost of front-end processes such as photolithography, etching, and deposition have increased dramatically after entering the nanometer or even sub-nanometer scale; on the other hand, physical limitations such as power consumption, heat dissipation, and interconnect delays also hinder the improvement of single-chip integration density. Against this backdrop, the industry has begun to seek new technological paths to continue the trend of performance growth and functional integration. Among them, advanced packaging technology, due to its ability to achieve multi-chip integration at the packaging level, effectively improves system performance and functional density, and has become an important means to break through the limitations of Moore's Law.

[0003] Compared to 2.5D packaging, 3D packaging is a more advanced packaging solution. It achieves higher integration and superior performance by vertically stacking chips, representing the future direction of advanced packaging technology. Its core idea is to increase the transistor density per unit volume by vertically stacking chips. However, simply stacking chips vertically, while reducing the area occupied in a two-dimensional plane, does not reduce the overall volume. Therefore, chip thinning is necessary to reduce the vertical height after stacking, thereby truly achieving an increase in transistor density per unit volume. Summary of the Invention

[0004] Therefore, the purpose of this invention is to simplify the process flow, avoid the problems of cost control and process difficulty caused by filling materials, and effectively solve the problem of splitting defects caused by lateral shear force on isolated chips during chemical mechanical polishing.

[0005] This invention provides a chip-to-wafer bonding structure thinning method, comprising the following steps: providing a substrate, bonding a chip with at least one sidewall having an arcuate profile after edge morphology optimization on the substrate to form a bonding structure; and reducing the lateral shear force acting on the chip sidewall by utilizing the interaction between a thinning tool and the arcuate sidewall of the chip without filling the gaps between the chips, thereby completing the thinning process of the bonding structure.

[0006] Preferably, in the chip-to-wafer bonding structure thinning method according to the present invention, the arcuate sidewalls of the chip are formed by one or more of the following methods: controlling the anisotropic dry etching process to naturally form arcuate sidewalls by utilizing the characteristic that the etching rate of the chip's sharp corner region is higher than that of the plane; exposing the chip edge through photolithography and edge washing processes, and then etching the edge with isotropic wet etching to form arcuate sidewalls; or using a focused ion beam to precisely trim the chip edge to form arcuate sidewalls.

[0007] Preferably, in the chip-to-wafer bonding structure thinning method according to the present invention, after forming the arc-shaped sidewalls and before performing the thinning process, the method further includes the following step: depositing a dielectric material on the arc-shaped sidewalls of the chip to further enhance the surface hardness of the arc-shaped profile.

[0008] Preferably, in the chip-to-wafer bonding structure thinning method according to the present invention, the dielectric material is silicon oxide, and the deposition thickness is 0.5 micrometers to 2 micrometers.

[0009] Preferably, in the chip-to-wafer bonding structure thinning method according to the present invention, the thinning process is chemical mechanical polishing, and the polishing pad used meets the following conditions: Shore A hardness between 20 and 40; compressibility between 10% and 20%; elastic modulus between 1 MPa and 5 MPa; surface roughness Ra between 0.5 μm and 1.5 μm; and porosity between 30% and 50%.

[0010] Preferably, in the chip-to-wafer bonding structure thinning method according to the present invention, the thinning process is mechanical polishing.

[0011] Preferably, in the chip-to-wafer bonding structure thinning method according to the present invention, the chip is bonded to the substrate by hybrid bonding or melt bonding, and undergoes an annealing process before the thinning process to enhance the bonding strength.

[0012] Furthermore, the present invention also provides a chip-to-wafer bonding structure, comprising: a substrate; and at least one chip bonded to the substrate. The chip has sidewalls with optimized edge morphology, the sidewalls having an arcuate profile, and the gaps between the chips are not completely filled with a filler material.

[0013] Furthermore, preferably, in the chip-to-wafer bonding structure of the present invention, a silicon oxide layer with a thickness of 0.5 micrometers to 2 micrometers is deposited on the arc-shaped sidewall of the chip.

[0014] This invention optimizes the sidewall edges of the chip into an arc-shaped profile, such as chamfers or rounded corners, after bonding and before thinning. This effectively reduces the lateral shear force generated when thinning tools, such as polishing pads used in chemical mechanical polishing (CMP), come into contact with the chip sidewalls. This allows the chip to stably withstand the stress of the thinning process solely based on its bonding strength with the substrate, eliminating the need for filler support materials. This method simplifies the process flow, avoids cost control and process difficulty issues caused by filler materials, and effectively solves the problem of splitting defects caused by lateral shear force on isolated chips during CMP. Attached Figure Description

[0015] Figure 1 This is a schematic diagram illustrating the flow of a prior art chip-to-wafer hybrid bonding process.

[0016] Figure 2 This is a schematic diagram illustrating the die splitting mechanism and the supporting role of the filling material during the CMP process in one embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram illustrating the interaction between a wafer, a pre-modification chip, and a post-modification chip with a polishing pad (CMP Pad) in one embodiment of the present invention.

[0018] Figure 4 This is a schematic diagram illustrating the formation of an arc-shaped morphology at the edge of plasma maskless etching in one embodiment of the present invention.

[0019] Figure 5 This is a schematic diagram illustrating the formation of an arc-shaped morphology at the edge of wet etching in one embodiment of the present invention.

[0020] Figure 6 This is a schematic diagram showing the rounding arc-shaped region at the edge of the CMP Pad grinding core in one embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0022] In chip stacking manufacturing processes, wafer-to-wafer and die-to-wafer are two main stacking methods. Wafer-to-wafer stacking requires that the chips involved in the stacking be of consistent size and that the wafers be of uniform size, while also meeting stringent alignment and process compatibility requirements. However, when the chips to be stacked cannot meet these conditions, die-to-wafer stacking becomes a more suitable option. Die-to-wafer stacking offers greater flexibility, with no strict limitations on chip size, wafer size, or materials. Furthermore, die-to-wafer processes allow for pre-screening of chips before bonding, using only chips that pass yield tests for stacking, thus significantly improving the overall yield of the final stacked chips. However, in the field of hybrid bonding, die-to-wafer processes are still less mature than wafer-to-wafer processes, presenting numerous technical challenges and room for optimization. In conclusion, wafer-to-wafer and die-to-wafer stacking each have their advantages and limitations, and their selection must be based on a trade-off between specific application scenarios and process requirements. This invention is mainly aimed at the chip-to-wafer stacking process route, specifically the die thinning and planarization process, with the goal of optimizing the technical implementation of chip-to-wafer stacking and improving process maturity.

[0023] In current mainstream die-to-wafer hybrid bonding processes, the die and wafer achieve both structural and electrical connections after bonding. To further extract electrical signals from the stacked chips, through-silicon via (TSV) formation is typically performed on the die side, or backside via reveal (BVR) technology is used to expose the TSV structure pre-embedded within the chip from the back side, thus enabling electrical extraction. Based on this, backside metal interconnects can be further constructed to form hybrid bonding blind vias or pad structures to support subsequent multi-layer die-to-wafer hybrid bonding stacking. For example, multi-layer stacking structures in the form of 1+1, 1+2, and 1+3 can be progressively built to achieve a highly integrated three-dimensional packaging architecture, meeting the multiple requirements of heterogeneous integrated systems for performance, bandwidth, and size. A schematic diagram of the existing die-to-wafer hybrid bonding process flow is shown below. Figure 1 As shown.

[0024] from Figure 1As shown in the process flow diagram, during the die thinning process, we don't directly thin the die. Instead, we fill the bonding gaps with an ultra-thick silicon oxide film, then thin the surface silicon oxide, and finally thin the silicon die itself before proceeding with subsequent processes. The purpose of filling the gaps is that, during the thinning process, we typically use CMP (Chip Motion Processing). However, because the CMP polishing pad is soft, it deforms during contact with the die, generating strong shear forces on the chip's sidewalls. This can cause the chip to break off during CMP polishing, rendering it unusable. This situation is equivalent to a fragment, requiring the replacement of many components in the CMP process, such as the pad, disk, and head components, with serious consequences.

[0025] Therefore, the common practice is to fill the gaps between the chips with a certain thickness of material after the chip-to-wafer hybrid bonding. This way, during the subsequent CMP milling and thinning process, the chips are supported by the material, preventing lateral shear forces. This is equivalent to thinning an entire wafer, not isolated chips, thus avoiding the chip splitting phenomenon mentioned above.

[0026] A schematic diagram illustrating the principle of chip splitting caused by CMP polishing and the prevention of splitting by filler material is shown below. Figure 2 As shown.

[0027] As described above, filling the gaps between chips with support material is a critical operation in semiconductor manufacturing. The filling film must be compatible with subsequent standard fab processes. For example, while depositing films to fill the gaps between chips, some films inevitably deposit on top of the chips, which then need to be removed via chemical mechanical polishing (CMP). Therefore, silicon oxide is commonly used as the deposition material. However, depositing such thick films also presents a series of challenges, as detailed below: Stress and Warpage: To ensure complete filling of the gaps between chips and coverage of the chip surface, the thickness of the deposited film must exceed the thickness of the chip. Typically, the minimum chip thickness is tens of micrometers (e.g., 10 μm). When a dielectric film tens of micrometers thick is deposited, the significant difference in the coefficient of thermal expansion (CTE) between the dielectric film and the silicon substrate leads to a sharp deterioration in wafer warpage. Abnormally warped wafers may cause processing anomalies in subsequent processes, affecting manufacturing stability.

[0028] Deposition efficiency and cost issues: In conventional fab processes, the thickness of the dielectric film is typically only a few micrometers (less than 5 μm). However, the time required to deposit a dielectric film layer tens of micrometers thick is significantly increased, resulting in a substantial reduction in wafer throughput per hour (WPH) and a significant increase in production costs.

[0029] The challenges of film removal: After filling the gaps between chips, a dielectric film of equal thickness is also applied to the top of the chip. This top film needs to be removed after gap filling is complete, while ensuring that the dielectric film within the gap is not damaged. Therefore, wet etching cannot be used; only grinding or CMP processes can be employed. As mentioned earlier, the grinding process needs to remove a dielectric film layer tens of micrometers thick (equivalent to the thickness of the die). This process is difficult, has a low wet etching potential (WPH), and significantly increases production costs.

[0030] The above analysis shows that although depositing thick dielectric films can meet the requirements for filling gaps between chips, it also brings problems such as wafer warpage, low process efficiency, increased costs, and difficulty in film removal. There is an urgent need to optimize the solution to improve the feasibility and economy of the manufacturing process.

[0031] In summary, there is currently a dilemma in the process of realizing the process: if the gaps between the chips are not filled and supported, the isolated chips will split off under shear stress during the subsequent CMP process due to the lack of structural support; on the other hand, if support materials such as SiO2 are filled, it may cause the aforementioned problems such as increased warpage and process compatibility, affecting the overall stability and yield of the process.

[0032] To address the above issues, the main current solutions include: Optimize the filling material and deposition process for chip gaps: By selecting dielectric materials with low internal stress, high fluidity and good compatibility with CMP processes (such as low-temperature CVD oxides), the integrity and rate of gap filling can be improved, and the warpage of the overall structure can be effectively controlled. Further thinning of the chip: Further thinning of the chip before gap filling can significantly reduce the volume of the required deposited material, reduce warping problems caused by thick films, and reduce the burden of film removal in subsequent CMP processes, thereby improving processing efficiency and reducing costs.

[0033] While existing process optimizations have alleviated the stability issues of isolated chips during CMP to some extent, they still rely on filling the gaps between chips with support material to prevent them from splitting due to lateral shear forces, making it difficult to fundamentally solve this technical bottleneck. Therefore, this study deeply analyzes the microscopic contact morphology between the pad and the chip during CMP and optimizes the chip's structural morphology accordingly to significantly reduce the lateral shear stress it experiences. Even without filling the gaps with support material, the optimized chip can still effectively resist the lateral stress during CMP due to its bonding force with the substrate, achieving stable thinning and planarization of isolated chips.

[0034] Figure 1 This is a schematic diagram illustrating the existing chip-to-wafer hybrid bonding process.

[0035] Figure 2 This is a schematic diagram illustrating the chip splitting mechanism and the supporting role of the filling material during the CMP process in one embodiment of the present invention.

[0036] When directly thinning and planarizing isolated chips, the flexibility of the CMPpad leads to localized energy deformation upon contact with surfaces of uneven height, introducing lateral shear forces during polishing. For isolated chips not supported by surrounding materials, their sidewalls are exposed and lack structural constraints, making them susceptible to concentrated lateral shear forces acting on the chip's sides. During continuous CMP, this stress can cause the chip to split or detach entirely from the substrate, severely impacting process yield and structural integrity.

[0037] After filling the gaps between chips, although the surface has some unevenness, the flexible deformation of the pads during CWP (Chip-on-Pack) generates some lateral shear force. However, at this stage, since the surface of the filling layer is still higher than the top surface of the chip, the lateral shear force has not yet directly acted on the chip body, and therefore has no significant impact on the chip structure. As the CMP (Chip-on-Pack) process continues, the overlay thickness gradually becomes more uniform, and the overall surface morphology tends to be flat. At this point, the force is mainly vertical downward pressure, and the lateral shear component is significantly weakened. Therefore, when the entire process tends to a steady state, the chip will not experience significant lateral shear stress, thus effectively avoiding the risk of chip splitting or breakage.

[0038] As mentioned above, existing optimization schemes still rely on filling the gaps between chips with support material to prevent chip splitting due to lateral shear forces during subsequent CMP thinning and planarization. Current improvements are largely based on this underlying logic. Besides optimizing the gap-filling material and its deposition process, and further thinning the chip, another strategy is to use harder CMP pads to reduce deformation upon contact with isolated chips, thereby lowering lateral shear forces. However, in practice, even high-hardness pads inevitably experience localized deformation upon contact with the chip, generating lateral shear stress that can still lead to chip splitting. Therefore, this strategy is currently insufficient to effectively address the CMP stability problem of isolated chips under unsupported conditions.

[0039] The core idea of ​​this invention is to introduce chamfered or rounded edges at the chip edge, similar to the Bevel structure at the wafer edge, to alleviate local deformation at the contact point between the pad and the chip during CMP (Chemical Motion Processing) and reduce the resulting lateral shear force. Through this morphology optimization, the chip can stably withstand the mechanical stress during CMP thinning and planarization processes solely based on its bonding strength with the substrate, effectively avoiding chipping. This method eliminates the need for inter-chip support materials, thus avoiding a series of problems that may arise from filler materials, such as warping, low deposition efficiency, and increased difficulty in removing thick films from the top of the chip. It successfully resolves the dilemma between reliance on bonding strength leading to chipping and the process problems caused by filler support materials.

[0040] Currently, there is limited analysis of the specific mechanisms underlying die splitting during chemical mechanical polishing (CMP). This study, through experimental observation and theoretical analysis, delves into the causes of die splitting during CMP and compares it with the edge-free splitting phenomenon observed in wafer-level CMP.

[0041] Experiments show that when thinning isolated chips using mechanical grinding, the chips do not detach or split. The thinning principle of mechanical grinding is purely mechanical, utilizing a virtually deformation-free grinding wheel to polish the chip. The wheel advances vertically (from top to bottom), avoiding significant lateral forces on the chip sidewalls. Therefore, during the grinding process, no large shear forces are generated between the chip and the substrate, thus preventing peeling or splitting.

[0042] In contrast, the CMP process uses soft polishing pads, which exert shear forces on the chip's sidewalls upon contact. Because these shear forces act directly on the chip's vertical sidewalls, they are relatively large, leading to chip splitting or peeling. This difference indicates that the mechanical properties of the polishing pad have a crucial influence on the splitting phenomenon during CMP.

[0043] A key question is: why doesn't wafer-level CMP exhibit edge chipping, while isolated chips are prone to splitting? To address this, we analyzed the differences in size and edge morphology between wafers and chips. Taking a 12-inch CMP device as an example, the diameter of the polishing pad is typically 24 to 36 inches (30 inches is common), much larger than the size of the wafer and chip. Therefore, the absence of edge chipping on wafers is not due to the wafer being larger than the chip, as shown in Table 1.

[0044] Table 1. Correspondence between common wafer dimensions and CMP pad dimensions Further analysis revealed that the suppression of wafer edge chipping stems from its edge morphology. Wafer edges typically have a bevel or rounded shape. During CMP (Chip Motion Processing), the polishing pad adheres closely to the rounded edge region of the wafer, rather than being stuck on its vertical sidewalls, thus significantly reducing shear force and preventing edge chipping. In contrast, the edges of isolated chips typically exhibit near-right angles, with the polishing pad directly stuck to the chip sidewalls, resulting in greater shear force. This excessive shear force is a primary cause of chip splitting during CMP.

[0045] In summary, the main mechanism of isolated chip splitting during CMP is the significant shear force generated by the contact between the polishing pad and the chip's vertical sidewalls. In contrast, the rounded edge morphology of the wafer effectively reduces the shear force, thereby preventing edge chipping. Therefore, this invention emphasizes the importance of edge morphology in optimizing the CMP process, and it is based on the above analysis that this invention is proposed.

[0046] Figure 3 This is a schematic diagram illustrating the interaction between a wafer, a pre-modification chip, and a post-modification chip with a polishing pad (CMP Pad) in one embodiment of the present invention.

[0047] Figure 3 This diagram illustrates the bevel morphology of a wafer during chemical mechanical polishing (CMP). Based on this, we designed and plotted a similar edge morphology for an isolated die after modification, referencing the wafer's bevel morphology. Figure 3 The image presents a schematic diagram of the chip's edge before the improvement, to illustrate the differences between the two.

[0048] A schematic diagram of the Bevel region during wafer CMP polishing shows that the shear force exerted by the CMP pad on the sidewalls is effectively dispersed by the arc-shaped morphology of the wafer's Bevel region, preventing it from acting directly on the wafer's sidewalls. Therefore, the shear force is significantly reduced, thus preventing damage to the wafer.

[0049] A schematic diagram of the chip edge area before the improvement shows that its side has a right-angle shape, and the CMP Pad acts directly on the chip sidewall, resulting in a large shear force.

[0050] The schematic diagram of the improved chip edge region shows that the arc-shaped topography effectively disperses the shear force exerted by the CMP Pad on the chip sidewall, so that it has almost no significant impact on the sidewall, thereby significantly reducing the shear force.

[0051] Figure 4 This is a schematic diagram illustrating the formation of an arc-shaped morphology at the edge of plasma maskless etching in one embodiment of the present invention.

[0052] Figure 5 This is a schematic diagram illustrating the formation of an arc-shaped morphology at the edge of wet etching in one embodiment of the present invention.

[0053] Figure 6 This is a schematic diagram showing the rounding arc-shaped region at the edge of the CMP Pad grinding core in one embodiment of the present invention.

[0054] During the grinding process, the CMP Pad remains in contact with the rounding arc area at the edge. Therefore, the CMP grinding process does not cause the initial arc shape to gradually change into a vertical shape, and thus it does not cause the phenomenon of increased lateral shear force on the core particles that leads to splitting.

[0055] This shows that the rounding morphology of the chip edge can effectively reduce the shearing force of the CMP Pad on the chip during the thinning process.

[0056] Below, we describe the process for creating a rounding shape at the edge of a chip: We can leverage the preferential etching characteristic of plasma etching for sharp corner regions. After the die and substrate are bonded, a Blank Etch is applied to the die surface. While planar silicon is also etched, the silicon in the sharp corner regions exhibits a higher etching rate than planar regions in dry etching due to the electric field concentration effect (the electric field strength is significantly enhanced in sharp corners due to the sharp geometry, resulting in higher ion bombardment density and energy, thus accelerating material removal) and the micro-loading effect (the diffusion and removal of etching byproducts (such as volatile gases) are relatively fast in sharp corner regions, whereas byproducts may remain in planar or recessed regions, leading to a reduced local etching rate. The open geometry of sharp corner regions facilitates rapid diffusion of byproducts, thus promoting faster etching). Therefore, a curved morphology gradually forms during the etching process. Figure 4 As shown; We can also first coat the chip surface with photoresist, then wash the chip edges, leaving the edges uncovered. Next, we use an isotropic etching solution (such as an HF-based solution) to lightly etch the edges, creating smooth rounded corners. A schematic diagram of the process flow is shown below. Figure 5 As shown; For more precise edge rounding of the chip, a SEM+FIB approach can be used. The SEM lens provides real-time observation of the chip edge, while the FIB precisely chamfers or rounds the edges, controlling the corner radius (e.g., 0.5-2μm) to ensure a smooth edge. In summary, by simultaneously using FIB for edge rounding and observing the effect in real-time with SEM, the best possible edge rounding morphology can be achieved. The advantages of this method are high precision, in-situ analysis (which can be performed within a single instrument integrating SEM and FIB), and flexibility. The disadvantages are high cost and low wharf rate (WPH), making it suitable for small-scale research and development in a laboratory but not for large-scale mass production.

[0057] In chemical mechanical polishing (CMP) thinning, the CMP pad, due to its flexible properties, can continuously adhere to the chip surface, including the chip edge areas, during the polishing process. This dynamic adhesion ensures close contact between the edge areas and the polishing pad. Therefore, the rounded shape of the chip edge is preserved during CMP, does not disappear, and maintains a stable rounded feature. Thus, the chip edge shape will not gradually transform from an initial rounded shape to a vertical shape, nor will it cause chip splitting due to increased lateral shear force exerted by the polishing pad on the chip sides. In other words, the CMP process will not exhibit a situation where there is no splitting problem in the initial stage, but splitting occurs later due to a significant increase in shear force caused by the edge shape becoming vertical. A specific schematic diagram is shown below. Figure 6 As shown.

[0058] This solution is designed for chemical mechanical polishing (CMP) and grinding thinning processes, aiming to optimize the edge morphology of core particles to improve the stability of the thinning process. After cutting, especially laser and mechanical cutting, the edges of core particles have complex morphologies, high surface roughness, and often protruding areas. Without edge optimization, even with a high-rigidity grinding process, stress concentration can lead to increased shear force, potentially causing core particle damage or splitting. Therefore, this solution optimizes the core particle edges with a rounding arc shape, effectively reducing edge roughness caused by cutting and improving the uniformity and smoothness of the edge morphology. This optimization is not only applicable to CMP thinning but also significantly improves the performance of grinding thinning, providing a more stable process foundation for subsequent processing. In summary, if grinding is used to thin core particles, this solution can also reduce shear force, thereby significantly reducing the impact of the thinning process on the bonding interface and providing a more stable process foundation for subsequent processing.

[0059] After the core particles are bonded to the substrate, we thin the core particles using a CMP process for precise thinning. We create a bevel morphology for the core particle edges, similar to the edge of a wafer, and a rounding arc morphology for the core particle edges. This significantly reduces the lateral shear force applied to the vertical sidewalls of the core particles due to the deformation of the CMP pads, thus ensuring that the core particles do not split off without the support of gap filler.

[0060] The bevel morphology at the edge can be fabricated using the aforementioned maskless etching (Blank ETCH), isotropic wet etching of the edge by photolithography, and SEM+FIB.

[0061] After the arc-shaped morphology of the core particle edge is formed, a thin layer of SiO2 material (0.5um-2um) can be deposited by PECVD to further enhance the arc-shaped degree of the core particle edge, so that the lateral shear force can be further reduced in the subsequent CMP process.

[0062] To maintain the rounded shape of the chip edge and reduce the risk of splitting during CMP thinning, the following are the quantitative indicators and recommended ranges of the preferred CMP polishing pads in this solution, in order to optimize the fit of the rounded edge area and reduce lateral shear forces.

[0063] Recommended hardness range: Shore A 20-40 Note: This range ensures that the polishing pad is soft enough to fit closely to the chip edge, maintaining a rounded shape, while avoiding excessively soft pads that would result in low polishing efficiency.

[0064] Recommended range for compressibility: 10%-20% (at 10-100 kPa pressure) Note: The high compression ratio allows the polishing pad to adapt to minor irregularities on the chip surface (including edges), reducing local stress concentration and protecting chip edges.

[0065] Recommended range for Young's Modulus: 1-5 MPa Note: A lower modulus of elasticity provides sufficient elastic deformation, enhancing the polishing pad's ability to buffer edge areas and reducing the risk of splitting.

[0066] Recommended surface roughness range: Ra 0.5-1.5 μm Note: Moderate surface roughness ensures good contact between the polishing pad and the chip edge, while maintaining uniform paste distribution, balancing edge adhesion and polishing effect.

[0067] Recommended porosity range: 30%-50% Note: Higher porosity enhances the polishing pad's softness and slurry retention, which helps with uniform polishing and reduces edge stress.

[0068] Recommended range for storage modulus and loss modulus: Storage modulus: 1-5 MPa Loss modulus: 0.5-2 MPa Explanation: The lower storage modulus and moderate loss modulus give the polishing pad good viscoelasticity, which can absorb the shear force during the polishing process and protect the edge morphology of the chip.

[0069] The above-mentioned performance parameters are optimized for flexible polishing pads to ensure dynamic adhesion between the polishing pad and the chip edge during CMP, maintain the rounding of the chip edge, and effectively reduce the risk of die splitting due to lateral shear forces. Suitable for low-shear CMP die thinning processes.

[0070] This solution eliminates the need for supporting materials such as dielectric films between cores; the bonding strength between the cores and the substrate is sufficient. Hybrid Bonding / Fusion Bonding processes require annealing after bonding to enhance bond strength, thereby meeting the bonding strength requirements of subsequent thinning. As described above, this solution is not only applicable to the subsequent CMP thinning process, but also effectively reduces the lateral shear force of the core particles in the grinding process, thereby significantly reducing the impact of the thinning process on the bonding interface. After optimizing the edge morphology of the core particles using this solution, the subsequent grinding process also yields beneficial results.

[0071] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0072] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0073] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0074] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for thinning a chip-to-wafer bonding structure, characterized in that, Includes the following steps: A substrate is provided on which a chip with at least one sidewall having an arcuate profile optimized by edge morphology is bonded to form a bonding structure; Without filling the gaps between chips, the interaction between the thinning tool and the arc-shaped sidewall of the chip reduces the lateral shear force acting on the chip sidewall, thus completing the thinning process of the bonding structure.

2. The chip-to-wafer bonding structure thinning method according to claim 1, characterized in that, The arcuate sidewalls of the chip are formed by one or more of the following methods: By controlling the anisotropic dry etching process, the etching rate of the chip's sharp corners is higher than that of the flat surface, thus naturally forming arc-shaped sidewalls. The chip edges are exposed through photolithography and edge washing processes, and then isotropic wet etching is used to etch the edges to form arc-shaped sidewalls. A focused ion beam is used to precisely trim the chip edges, forming arc-shaped sidewalls.

3. The chip-to-wafer bonding structure thinning method according to claim 1, characterized in that, After the arcuate sidewalls are formed and before the thinning process is performed, the following step is also included: depositing a dielectric material on the arcuate sidewalls of the chip to further enhance the surface hardness of the arcuate profile.

4. The chip-to-wafer bonding structure thinning method according to claim 3, characterized in that, The dielectric material is silicon oxide, and the deposition thickness is 0.5 micrometers to 2 micrometers.

5. The chip-to-wafer bonding structure thinning method according to claim 1, characterized in that, The thinning process is chemical mechanical polishing, and the polishing pad used meets the following conditions: Shore A hardness is between 20 and 40; Compression rate is between 10% and 20%; The elastic modulus is between 1 MPa and 5 MPa; The surface roughness Ra is between 0.5 micrometers and 1.5 micrometers; The porosity is between 30% and 50%.

6. The chip-to-wafer bonding structure thinning method according to claim 1, characterized in that, The thinning process is mechanical grinding.

7. The chip-to-wafer bonding structure thinning method according to claim 1, characterized in that, The chip is bonded to the substrate by hybrid bonding or melt bonding, and undergoes an annealing process before thinning to enhance the bonding strength.

8. A chip-to-wafer bonding structure, characterized in that, include: Base; At least one chip bonded to the substrate; The chip has sidewalls with optimized edge morphology, the sidewalls have an arcuate profile, and the gaps between the chips are not completely filled with filling material.

9. The chip-to-wafer bonding structure according to claim 8, characterized in that, A silicon oxide layer with a thickness of 0.5 micrometers to 2 micrometers is deposited on the arc-shaped sidewalls of the chip.

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