TSV solid-phase hole filling interconnection method and TSV solid-phase hole filling interconnection structure
By inserting copper pillars into through-silicon vias and subjecting them to plastic deformation, combined with insulating and barrier layers, the problem of poor flowability of electroplating solutions in deep holes was solved. This enabled high aspect ratio, defect-free filling, and reliable vertical interconnection, simplifying the process flow and improving the reliability and fatigue resistance of silicon wafers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINGHONG SEMICONDUCTOR (GUANGDONG HENGQIN) CO LTD
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-01
AI Technical Summary
In existing TSV technology, the electroplating solution has poor fluidity in deep holes, resulting in voids and defects at the bottom of the holes, making it difficult to achieve high aspect ratio and defect-free filling. Furthermore, stress is easily generated at the interface during the electroplating process and subsequent thermal cycling, leading to silicon wafer cracking or decreased reliability.
By employing a solid-phase via-filling method, copper pillars are inserted into silicon through-holes and subjected to plastic deformation. Combined with an insulating layer and a barrier layer, a tight mechanical bond is achieved, avoiding the problems of holes and seams during the electroplating process, simplifying the process flow, and improving the fatigue resistance of the interconnect structure.
It achieves high aspect ratio and defect-free filling, avoids the complex processes of electroplating and chemical mechanical polishing, improves the reliability and thermal cycling stability of the interconnect structure, and reduces production costs.
Smart Images
Figure CN121969136A_ABST
Abstract
Description
A method and structure for TSV solid-phase via filling interconnect. Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, specifically to a TSV solid-state via filling interconnect method and structure. Background Technology
[0002] Current mainstream TSV technology relies on electroplated copper to fill silicon vias.
[0003] This method has the following inherent limitations: Limited aspect ratio: The electroplating solution has poor fluidity in deep holes, and it is difficult to control the deposition rate at the hole opening and bottom uniformly during copper electroplating. This can easily lead to voids and defects at the bottom of the hole, making it difficult to achieve defect-free filling with a high aspect ratio. This exacerbates the problems of increased resistance and localized heating, and stress concentration occurs due to the mismatch between the thermal expansion coefficients of copper and silicon during subsequent thermal cycles, leading to reliability failure.
[0004] The process is complex and time-consuming: it requires multiple steps such as etching, deposition of insulating layer, barrier layer, seed layer, electroplating and polishing. After electroplating, chemical mechanical polishing is often required to remove the overplated layer on the surface, which increases the process time and cost.
[0005] Thermomechanical stress problem: The thermal expansion coefficients of copper and silicon are mismatched, and stress is easily generated at the interface during the electroplating process and subsequent thermal cycling, which may lead to cracking of silicon wafers or a decrease in reliability.
[0006] Existing processing methods improve filling by optimizing etching or using segmented electroplating, but they do not fundamentally solve the limitations of the electroplating principle. The problem of poor fluidity of the electroplating solution in deep holes still exists. In addition, copper pillar interconnects are also used in existing technologies, but they are mostly used for chip side connections or board-level interconnects, and are not used to replace the filling of silicon vias in silicon substrates. Summary of the Invention
[0007] To address the shortcomings of existing technologies, this invention provides a TSV solid-phase via-filling interconnect method and structure, which solves the problems of poor flowability of electroplating solution in deep holes leading to voids and defects at the bottom of the holes, making it difficult to achieve high aspect ratio and defect-free filling, as well as the problems of chemical mechanical polishing to remove the over-plating layer after electroplating, and the stress generated at the interface during the electroplating process and subsequent thermal cycling, which can lead to silicon wafer cracking or decreased reliability.
[0008] To achieve the above objectives, the present invention provides the following technical solution: a TSV solid-phase via-filling interconnect method and structure, comprising the following steps: Step S1: Silicon via etching and deposition: Through-holes are etched on a silicon substrate, and an insulating layer and a barrier layer are sequentially deposited within the through-holes on the silicon substrate. The dimensions and quality of the deposited through-holes are then inspected and assessed to determine the subsequent copper-filling process. Step S2: Copper pillar insertion and fixing: Based on the quality assessment results of Step S1, an integral or segmented copper pillar insertion process is selected to insert at least one solid copper pillar into the through-hole. The pillar is then plastically deformed by stamping to form a tight mechanical bond with the inner wall of the through-hole. Step S3: Surface treatment and interconnect construction: Excess copper material on the surface is removed and planarized. The ends of the copper pillars are exposed by back-side thinning. Wiring layers and bumps are constructed on the silicon substrate to complete the interconnect structure. Step S4: Electrical testing and process feedback: Electrical testing is performed on the completed interconnect structure. The batch quality is evaluated based on the test results, and processing parameters are adjusted accordingly.
[0009] Preferably, based on step S1, the vias after deposition are subjected to size inspection and quality judgment, specifically including: random sampling test of the vias after deposition on the silicon substrate, measuring the diameter and depth of the vias, and judging whether they meet the preset qualified threshold; the qualified threshold is set according to the size and length of the prefabricated solid copper pillar, and the qualified threshold is specifically set to the size of the solid copper pillar being slightly larger than the diameter of the via; the aspect ratio of the via is calculated and compared with the preset aspect ratio threshold.
[0010] Preferably, when judging the quality of through-holes based on step S1, the following steps are performed: When the diameter of the through-hole is lower than the lower threshold, it is judged as unqualified and needs to be reworked, and it is judged as a deposition process problem, and the deposition process is adjusted; When there are foreign objects in the through-hole diameter, it is judged as unqualified and needs to be reworked, and it is judged as not a process problem, and the processing environment and raw materials are controlled; When the diameter of the through-hole exceeds the upper threshold, it is judged as needing secondary process processing or adjustment of subsequent stamping parameters, and it is judged as a deposition process problem, and the deposition process is adjusted; When the diameter of the through-hole is within the qualified threshold range, the depth-to-width ratio of the through-hole is calculated to obtain the depth-to-width ratio, and when the depth-to-width ratio does not exceed the depth-to-width ratio threshold, the one-piece copper pillar insertion process is selected; When the diameter of the through-hole is within the qualified threshold range, the depth-to-width ratio of the through-hole is calculated to obtain the depth-to-width ratio, and when the depth-to-width ratio exceeds the depth-to-width ratio threshold, the segmented copper pillar insertion process is selected.
[0011] Preferably, when using the integrated copper pillar insertion process in step S2, the process includes the following steps: inserting the copper pillar into the corresponding through hole by pressing the copper pillar into the through hole; when using the segmented copper pillar insertion process, the process includes the following steps: aligning and inserting multiple copper pillar segments sequentially with the through holes on the silicon substrate, and plastically deforming the copper pillars that are not the last segment by pressing them and inserting them all into the through hole; the subsequent insertion of copper pillars pushes the previously inserted copper pillars further towards the bottom of the through hole until the last copper pillar is inserted, thus achieving spliced filling of the through hole.
[0012] Preferably, based on the segmented copper pillar insertion process in step S2, after the stamping process of connecting two copper pillars, the debris on the surface of the silicon substrate is cleaned; the length of the last copper pillar is designed such that after it is inserted, its upper part extends out of the surface of the silicon substrate.
[0013] Preferably, based on step S2, the insertion and fixing process of the copper column includes three stages of pressure control performed sequentially: Stage 1: Constant speed pressing stage, the copper column is pressed into the through hole at a constant speed, and the ratio of pressing pressure to pressing displacement is monitored in real time. When the ratio is abnormal, pressing is stopped and the deviation is checked; when the ratio of pressing displacement to pressure is normal and the pressing pressure reaches the preset pressing threshold, the next stage is entered; Stage 2: Uniform speed pressurization stage, after the copper column is fully inserted, the pressure is increased uniformly to cause plastic deformation of the copper column, and pressure fluctuations are monitored in real time. When abnormal pressure fluctuations occur, pressurization is stopped; when the pressure reaches the preset pressurization threshold, the next stage is entered; Stage 3: Pressure holding stage, the pressure is maintained at the pressurization threshold until the preset pressure holding time is reached to complete the fixing.
[0014] Preferably, during the three-stage pressure control process, pressure data is acquired through the current signal of the stamping shaft servo motor or a high-precision load unit, and displacement data is measured through a high-precision linear encoder.
[0015] Preferably, in step S4, the electrical testing includes sampling the test structure using a probe station and / or performing a full wafer scan using micro-area infrared thermal imaging technology to locate high-resistance defect areas; and based on the test results, the process parameters of the size threshold in step S1 and / or the pressure thresholds at each stage in step S2 are adjusted to optimize the process.
[0016] A TSV solid-state via-filled interconnect structure includes: a silicon substrate having through-holes; at least one copper pillar body inserted and fixed within the through-holes of the silicon substrate; wherein an insulating layer and a barrier layer are sequentially deposited on the inner wall of the through-holes of the silicon substrate; and the copper pillar body forms a tight mechanical bond with the inner wall of the through-holes of the silicon substrate through plastic deformation.
[0017] Preferably, the copper pillar body has tapered ports at both the upper and lower ends.
[0018] This invention discloses a TSV solid-phase via filling interconnect method and structure, which has the following beneficial effects: it eliminates the complex electroplating production line, significantly simplifies the process flow, saves time-consuming electroplating and subsequent polishing steps, avoids the use of expensive electroplating chemicals and seed layer deposition equipment, and effectively avoids the problem of mismatch in thermal expansion coefficients between copper and silicon, stress generated at the interface during the electroplating process and subsequent thermal cycling, which leads to silicon wafer cracking or reliability degradation.
[0019] This method uses solid copper pillars to plastically deform and fill through holes, avoiding the inherent hole and seam problems of electroplating. The high-purity solid copper pillars have high mechanical strength and are tightly mechanically interlocked with the inner wall of the through hole through plastic deformation. Combined with the insulating layer and the barrier layer, this improves the fatigue resistance of the interconnect structure under thermal cycling load, thereby obtaining reliable vertical interconnects.
[0020] The precise diameter and depth of the through-silicon via (TSV) are obtained through high-precision sampling and the aspect ratio is calculated. The appropriate filling process is then selected. When the aspect ratio exceeds a preset threshold, a segmented insertion scheme is automatically activated. This scheme divides the long copper pillar into multiple segments, which are then stamped and spliced together segment by segment. This solves the buckling instability problem of the long copper pillar during the stamping process, allowing the filling method to meet the requirements of TSVs with high aspect ratios. For TSVs, a single one-piece stamping is used. When encountering TSVs with ultra-high aspect ratios, the copper pillar with an excessively large aspect ratio is prone to elastic instability under axial pressure, leading to filling failure and potentially damaging the silicon wafer.
[0021] By setting up a three-stage pressure control system, which includes constant-speed pressing, uniform-speed pressing, and pressure holding, the rough stamping process is transformed into a controllable plastic forming process. During the constant-speed pressing stage, the curves of the pressing force and displacement are monitored in real time, which can quickly identify abnormalities in the copper column during the pressing process. During the uniform-speed pressing stage, the copper column is ensured to undergo sufficient plastic deformation, so that the copper column completely fills the through hole and forms a tight mechanical bond.
[0022] The final electrical performance test results are correlated with the through-hole size threshold and the pressure threshold parameters at each stage. When the test finds that the batch resistance is too high or there are hot spots, the relevant process parameters can be traced back and compensated in subsequent production to achieve closed-loop optimization of the process and adjust to a suitable processing method. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 is a flowchart of the TSV solid-phase via-filling interconnect method of the present invention; Figure 2 is a flowchart of the silicon through-hole etching and deposition process of the present invention; Figure 3 is a flowchart of the copper pillar insertion process of the present invention; Figure 4 is a flowchart of the segmented copper pillar stamping process of the present invention; Figure 5 is a flowchart of the three-stage pressure control process of the present invention; Figure 6 is a flowchart of the surface treatment and interconnect construction process of the present invention; Figure 7 is a schematic diagram of the integrated copper pillar TSV solid-phase via-filling interconnect structure of the present invention; Figure 8 is a cross-sectional view of the integrated copper pillar TSV solid-phase via-filling interconnect structure of the present invention; Figure 9 is a schematic diagram of the segmented copper pillar TSV solid-phase via-filling interconnect structure of the present invention; Figure 10 is a cross-sectional view of the segmented copper pillar TSV solid-phase via-filling interconnect structure of the present invention.
[0025] In the figure: 1. Silicon substrate; 2. Copper pillar body; 21. Tapered port; 3. Insulating layer; 4. Barrier layer. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0027] This application provides a TSV solid-phase via-filling interconnect method and structure, which solves the problems of poor flowability of electroplating solution in deep holes leading to voids and defects at the bottom of the holes, making it difficult to achieve high aspect ratio defect-free filling, as well as the problems of chemical mechanical polishing to remove the surface over-plating layer after electroplating, and the stress generated at the interface during the electroplating process and subsequent thermal cycling, which can lead to silicon wafer cracking or decreased reliability. It achieves the use of solid copper pillars to plastically deform and fill through holes, avoiding the inherent hole and seam problems of electroplating. The high-purity solid copper pillars have high mechanical strength and form a tight mechanical interlock with the inner wall of the through hole through plastic deformation. Combined with the insulating layer and the barrier layer, it improves the fatigue resistance of the interconnect structure under thermal cycling load, thereby obtaining reliable vertical interconnects.
[0028] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.
[0029] This invention discloses a TSV solid-phase via-filling interconnect method and structure.
[0030] As shown in Figures 1-10, the process includes the following steps: Step 1: Silicon via etching and deposition: Through-holes are etched on the silicon substrate 1. In a pulse etching process, high aspect ratio anisotropic etching is achieved through rapid, cyclic alternating etching and passivation steps. After etching the through-holes, an insulating layer 3 and a barrier layer 4 are deposited sequentially inside the through-holes in the silicon substrate 1. The insulating layer 3 is SiO2. The silicon dioxide thin film ensures that the current can only be conducted vertically along the copper pillar path and will not leak laterally into the silicon substrate. The barrier layer 4 prevents copper atoms from diffusing into SiO2 and the silicon substrate 1, causing device contamination and failure. The barrier layer 4 usually adopts a TaN / Ta double-layer structure. Tantalum nitride is used as the diffusion barrier layer 4, and the upper pure Ta is a good adhesion layer, providing bonding force for the subsequent direct insertion of copper pillars.
[0031] The etching of vias and the deposition of insulating layer 3 and barrier layer 4 are both existing mature technologies and will not be described in detail here. After etching the silicon vias and depositing insulating layer 3 and barrier layer 4, the vias deposited on the silicon substrate 1 need to be inspected and their quality judged online or by sampling. This is a prerequisite for ensuring reliable filling of the subsequent copper pillars. By randomly sampling and testing the vias deposited on the silicon substrate 1, it is necessary to measure the diameter and depth of the vias. The threshold values need to be set according to the size and length of the prefabricated solid copper pillars. The size of the solid copper pillar needs to be slightly larger than the diameter of the via. This is to ensure that the solid copper pillar fits tightly with the via. When the solid copper pillar is pressed into the via, it is already tightly fitted. By applying pressure, the copper pillar will undergo plastic deformation and form a tight mechanical bond with the via. In addition, the length of the solid copper pillar needs to be longer than the depth of the via. When the copper pillar is tightly mechanically bonded to the silicon via, the upper end of the copper pillar needs to be under pressure at all times. In order to ensure that the upper end of the copper pillar is under pressure, when the copper pillar fills the via, the upper end of the copper pillar also needs to be partially outside the via on the silicon substrate 1.
[0032] The specific dimensional and depth differences can be fine-tuned based on actual production results.
[0033] Based on step S1, when judging the quality of through-holes, the following steps are performed: When the through-hole diameter is below the lower threshold, it is judged as unqualified and needs to be reworked, and it is judged as a deposition process problem, and the deposition process is adjusted; When there are foreign objects in the through-hole diameter, it is judged as unqualified and needs to be reworked, and it is judged as not a process problem, and the processing environment and raw materials are controlled; When the through-hole diameter exceeds the upper threshold, it is judged as needing secondary process processing or adjustment of subsequent stamping parameters, and it is judged as a deposition process problem, and the deposition process is adjusted; When the through-hole diameter is within the qualified threshold range, the depth-to-width ratio of the through-hole is calculated to obtain the depth-to-width ratio. When the depth-to-width ratio does not exceed the depth-to-width ratio threshold, the one-piece copper pillar insertion process is selected; When the through-hole diameter is within the qualified threshold range, the depth-to-width ratio of the through-hole is calculated to obtain the depth-to-width ratio. When the depth-to-width ratio exceeds the depth-to-width ratio threshold, the segmented copper pillar insertion process is selected.
[0034] Specifically, the following steps are performed when judging the quality of through-holes: First, determine whether the diameter of the through-hole is within the acceptable threshold range. When the hole diameter is lower than the lower threshold, the force required to push the copper pillar into the smaller diameter through-hole will obviously need to be increased. When the pushing force is increased, there are problems such as excessive pushing force on the copper pillar and excessive friction between the copper pillar and the through-hole during insertion. If the copper pillar is subjected to excessive pushing force, it may bend, which will prevent the copper pillar from being inserted into the through-hole, thus causing processing failure. If the friction between the copper pillar and the through-hole is too great during insertion, will the excessive force damage the insulating layer 3 and the barrier layer 4 deposited in the through-hole? All of the above problems can directly lead to the scrapping of the processed product. The silicon substrate 1 needs to be reworked, and the deposition process needs to be adjusted.
[0035] When the aperture size exceeds the upper limit threshold but does not reach the appropriate threshold, a certain gap will appear between the copper pillar and the through hole. This problem can be solved by performing secondary deposition to enlarge the aperture size. Alternatively, the problem of a certain gap between the copper pillar and the through hole, which leads to incomplete filling under normal pressure, can be solved by increasing the pressure and time during the subsequent copper pillar pressurization process. In addition, the deposition process of the previous batch should be adjusted.
[0036] When it is determined that there is a foreign object in the aperture, the device cannot be used and it is not a process problem. It is necessary to control the processing environment and raw materials.
[0037] When the diameter of the through-hole is within the acceptable threshold range, the depth and width of the through-hole are compared to obtain the depth-to-width ratio. The depth-to-width ratio is calculated because if the ratio is too large, inserting a single copper pillar will result in the pillar being too long and not large enough, causing it to bend during stamping and preventing insertion. When the ratio exceeds the acceptable threshold, the copper pillar is inserted in segments based on its length. The depth-to-width ratio is then calculated again, and a threshold comparison is performed to determine whether to use segmented or single-piece copper pillar insertion. The threshold can be set to a depth-to-diameter ratio of 10:1, but this can be adjusted during processing as it is affected by material hardness. The diameter and depth of the through-hole can be detected and judged online using a high-precision optical profilometer or scanning electron microscope.
[0038] It is particularly important to emphasize that when inserting multiple copper pillars, the copper pillar needs to be processed during the insertion of the last copper pillar to ensure that the length of the copper pillar exceeding the silicon substrate 1 is within a specified range. This setting is to ensure that the length design of the last copper pillar during the subsequent pressurization process requires additional consideration of the stability of its protruding portion, ensuring that it can withstand axial pressure without bending during the final stamping stage. In step S2, copper pillar insertion and fixing, based on the quality judgment result of step S1, a one-piece or segmented copper pillar insertion process is selected to insert at least one solid copper pillar into the through hole, and to plastically deform it through stamping to form a tight mechanical bond with the inner wall of the through hole. Based on step S2, a one-piece copper pillar insertion process is selected. The insertion process includes the following steps: inserting copper pillars into the corresponding through holes by pressing the copper pillars into the through holes; when using a segmented copper pillar insertion process, the process includes the following steps: aligning and inserting multiple copper pillars sequentially with the through holes on the silicon substrate 1; plastically deforming copper pillars other than the last segment by pressing and inserting them all into the through holes; subsequent insertion operations push the previously inserted copper pillars further towards the bottom of the through holes until the last copper pillar is inserted, achieving splicing filling of the through holes; after the stamping process of every two copper pillar segments, cleaning the debris on the surface of the silicon substrate 1; the length of the last copper pillar is designed such that its upper part extends beyond the surface of the silicon substrate 1 after insertion.
[0039] Specifically, when performing the copper pillar insertion and fixing process, the corresponding copper pillar processing procedure is selected, and the specific steps are as follows: When using an integrated copper pillar inserter, the copper pillar is aligned once and inserted into the through hole. During the insertion process, the copper pillar is pressed into the through hole by stamping, and then pressure is applied to make the copper pillar plastically deform and form a tight mechanical combination with the through hole. Finally, pressure is maintained to complete the insertion and fixing of the copper pillar.
[0040] When segmented copper pillars are used, the copper pillars are arranged in sequence, aligned with the through holes, and inserted. A stamping process is applied to cause the copper pillar to plastically deform and insert into the through hole. Then, the next segment is aligned with the through hole and inserted, pushing the previous segment further into the through hole until the entire copper pillar is inserted. If the current segment is not the last to be inserted, the next segment is inserted, and this cycle continues until the current segment is the last to be inserted. At this point, the copper pillars are spliced and filled completely into the through hole. Pressure is then applied, causing the copper pillar to plastically deform and form a tight mechanical bond with the through hole. Finally, pressure is maintained to complete the insertion and fixation of the copper pillar.
[0041] Specifically disclosed is that during the segmented stamping of copper pillars, each time the two ends of the copper pillars are joined and stamped, the stamping debris on the silicon substrate 1 needs to be processed to prevent metal or dielectric debris from entering the via or the inter-segment interface, affecting the filling effect and interface reliability. Specifically disclosed is that the insertion and alignment of the copper pillars is achieved by using the nozzle of a high-precision pick-and-place machine to pick up the copper pillar and align it with the via. During the insertion process, the nozzle dynamically and finely adjusts its own posture to guide the copper pillar back to the correct axis. When the visual endoscope detects an eccentricity between the copper pillar axis and the TSV hole axis, it immediately calculates the small translational and rotational movements required for compensation to achieve alignment.
[0042] Based on step S2, the insertion and fixing process of the copper column includes three stages of pressure control performed sequentially: Stage 1: Constant speed pressing stage, the copper column is pressed into the through hole at a constant speed, and the ratio of pressing pressure to pressing displacement is monitored in real time. If the ratio is abnormal, pressing is stopped and the deviation is checked; when the ratio of pressing displacement to pressure is normal and the pressing pressure reaches the preset pressing threshold, the next stage is entered; Stage 2: Uniform speed pressurization stage, after the copper column is fully inserted, the pressure is increased uniformly to cause plastic deformation of the copper column, and pressure fluctuations are monitored in real time. When abnormal pressure fluctuations occur, pressurization is stopped; when the pressure reaches the preset pressurization threshold, the next stage is entered; Stage 3: Pressure holding stage, the pressure is maintained at the pressurization threshold until the preset pressure holding time is reached to complete the fixing.
[0043] Specifically, the three-stage pressure control process during the insertion of the copper pillar is as follows: Stage 1: The copper pillar is pressed down into the silicon substrate 1. By moving it downward at a constant speed, the pressure-to-pressure-height ratio is checked. During pressing, the pressure increases as the contact area between the copper pillar and the via increases, and the pressure is proportional to the contact area between the copper pillar and the via. The contact area of the via and the pressing height of the copper pillar can be converted into the contact area of the via. When the pressure-to-pressure-height ratio is abnormal, pressing is stopped. At this point, it is determined whether the pillar is skewed. When the copper pillar is skewed, it will exert oblique pressure on the edge of the via, i.e., sidewall pressure on the via. The pressure will cause the copper pillar to exert lateral pressure on the silicon substrate 1, resulting in damage to the silicon substrate 1. During the pressing of the copper column, the pressure-to-press ratio remains within the normal range. The pressure is monitored in real-time to determine if it has reached the pressing threshold. If it hasn't reached the threshold, pressing continues at a constant speed until the pressure reaches the threshold and the pressing height is in the normal ratio. At this point, it can be determined that the copper column is completely pressed into the through-hole, and the constant-speed pressing process stops, proceeding to stage two. In stage two, pressure is applied at a uniform speed. The copper column is now fully inserted into the through-hole and will not move relative to it. The pressure on the copper column is then increased at a uniform speed, causing it to gradually undergo plastic deformation. Since the copper column cannot move, it is plastically deformed, and its deformation compresses against the inner wall of the through-hole, completely filling the through-hole and forming a tight mechanical bond.
[0044] During uniform pressurization, the pressure needs to be monitored in real time. Under normal circumstances, there will be no large pressure fluctuations during uniform pressurization. If large fluctuations occur, pressurization should be stopped immediately, which is considered an abnormal pressurization. This abnormality needs to be judged manually and can be divided into several situations, such as the pressure threshold being set too high, causing excessive pressure from the copper pillar to the through hole, resulting in damage to the silicon substrate 1; or the copper pillar having internal voids, which are densified by pressurization.
[0045] When the pressure is increased at a constant rate to the specified pressure threshold, the constant rate of pressure increase is stopped, and stage three begins. In stage three, the current pressure is maintained until the set threshold time is reached, thus completing the insertion and fixation of the copper pillar.
[0046] Specifically disclosed, during the copper column stamping process, the pressure data during the stamping process can be acquired through the current signal of the stamping shaft servo motor or the integrated dedicated high-precision load unit, and the displacement data is measured by a high-precision linear encoder.
[0047] Specifically, it is disclosed that in the trailer for inserting copper pillars into through holes, an ultrasonic-assisted method can be used to utilize the cavitation effect to break the oxide film on the surface of the copper pillar and promote the bonding between the copper pillar and the inner wall of the through hole.
[0048] Step S3 involves surface treatment and interconnect construction. Excess copper material on the surface is removed and planarized. The copper pillar ends are exposed by thinning on the back side. Wiring layers and bumps are constructed on the silicon substrate 1 to complete the interconnect structure.
[0049] Step S4 Electrical Testing and Process Feedback: Perform electrical testing on the interconnected structure, evaluate batch quality based on test results, and provide feedback to adjust processing parameters.
[0050] Based on step S4, the electrical testing includes sampling the test structure using a probe station and / or performing a full wafer scan using micro-area infrared thermal imaging technology to locate high-resistance defect areas; and based on the test results, the process parameters are adjusted for the size threshold in step S1 and / or the pressure thresholds at each stage in step S2 to optimize the process.
[0051] The specific steps are as follows: After chemical mechanical polishing and planarization, a probe station is used to perform sampling electrical tests on the test structure in the dicing groove to determine the overall quality of the batch.
[0052] Using micro-area infrared thermal imaging or terahertz imaging, when current flows through the copper pillar, defective copper pillars will exhibit high resistance, causing localized heating, which is captured by the thermal imager. The entire wafer is then quickly scanned to locate suspicious areas.
[0053] If the test is deemed satisfactory, the current processing method is maintained. If the electrical test is deemed unsatisfactory, a failure analysis is required. Based on the failure results, the pressure thresholds for the three stages and the through-hole size thresholds are adjusted, and the processing test is repeated until the processed product is satisfactory. The processing method is then saved.
[0054] A TSV solid-state via-filled interconnect structure includes: a silicon substrate 1 with through-holes; at least one copper pillar 2, which is inserted into the through-hole of the silicon substrate 1. The upper and lower ends of the copper pillar 2 are provided with tapered ports 21, which facilitate insertion into the through-hole of the silicon substrate 1. During the insertion of the copper pillar 2 into the through-hole of the silicon substrate 1, the copper pillar 2 is picked up and aligned with the through-hole by a high-precision pick-and-place machine nozzle through the tapered ports 21. The nozzle dynamically adjusts its posture during insertion using endoscopic vision to guide the copper pillar 1 to align with the through-hole. However, the size of the copper pillar 2 is slightly larger than the through-hole size to ensure a mechanical connection between the copper pillar 2 and the through-hole. During stamping, the tapered ports 21 are inserted along the through-hole, leading to… The copper pillar body 2 is inserted into the through hole. Under the extrusion and plastic deformation of the copper pillar body 2, it fits tightly with the through hole during insertion, avoiding gaps. Further pressurization time is required to ensure mechanical connection between the copper pillar body 2 and the inner wall of the through hole. When the copper pillar body 2 is fully pushed into the through hole, the tapered port 21 at the bottom of the copper pillar body 2 contacts the silicon substrate 1. The tapered port 21 undergoes plastic deformation during pressurization, fitting tightly against the inner wall of the through hole. In the segmented copper pillar insertion process, the two segments of the copper pillar body 2 contact each other via the tapered port 21. During contact and extrusion, plastic deformation occurs, connecting them. Furthermore, by creating grooves at the tapered ports 21, the tapered ports 21 deform and connect through the grooves under the extrusion of the two segments of the copper pillar body 2, effectively improving the connection strength.
[0055] An insulating layer 3 and a barrier layer 4 are sequentially deposited in the vias of the silicon substrate 1.
[0056] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.
Claims
1. A TSV solid-phase via-filling interconnect method, characterized in that, Includes the following steps: Step S1: Silicon via etching and deposition: Through holes are etched on the silicon substrate (1), and an insulating layer (3) and a barrier layer (4) are deposited sequentially in the through holes of the silicon substrate (1). The dimensions and quality of the deposited through holes are inspected and judged to determine the subsequent copper filling process scheme. Step S2: Copper pillar insertion and fixing: According to the quality judgment result of step S1, an integral or segmented copper pillar insertion process is selected to insert at least one solid copper pillar into the through hole, and it is plastically deformed by stamping to form a tight mechanical bond with the inner wall of the through hole. Step S3: Surface treatment and interconnect construction: Excess copper material on the surface is removed and planarized. The copper pillar ends are exposed by thinning on the back side, and wiring layers and bumps are constructed on the silicon substrate (1) to complete the interconnect structure. Step S4: Electrical testing and process feedback: Electrical testing is performed on the completed interconnect structure. The batch quality is evaluated according to the test results, and the processing parameters are adjusted accordingly.
2. The TSV solid-phase via-filling interconnection method according to claim 1, characterized in that, Based on step S1, the size detection and quality judgment of the deposited vias are carried out, specifically including: random sampling test of the deposited vias on the silicon substrate (1), measuring the diameter and depth of the vias, and judging whether they meet the preset qualified threshold; the qualified threshold is set according to the size and length of the prefabricated solid copper pillar, and the qualified threshold is specifically set to the size of the solid copper pillar being slightly larger than the diameter of the via; the aspect ratio of the vias is calculated and compared with the preset aspect ratio threshold.
3. The TSV solid-phase via-filling interconnection method according to claim 1, characterized in that, Based on step S1, when judging the quality of through-holes, the following steps are performed: When the through-hole diameter is below the lower threshold, it is judged as unqualified and needs to be reworked, and it is judged as a deposition process problem, and the deposition process is adjusted; When there are foreign objects in the through-hole diameter, it is judged as unqualified and needs to be reworked, and it is judged as not a process problem, and the processing environment and raw materials are controlled; When the through-hole diameter exceeds the upper threshold, it is judged as needing secondary process processing or adjustment of subsequent stamping parameters, and it is judged as a deposition process problem, and the deposition process is adjusted; When the through-hole diameter is within the qualified threshold range, the depth-to-width ratio of the through-hole is calculated to obtain the depth-to-width ratio. When the depth-to-width ratio does not exceed the depth-to-width ratio threshold, the one-piece copper pillar insertion process is selected; When the through-hole diameter is within the qualified threshold range, the depth-to-width ratio of the through-hole is calculated to obtain the depth-to-width ratio. When the depth-to-width ratio exceeds the depth-to-width ratio threshold, the segmented copper pillar insertion process is selected.
4. The TSV solid-phase via-filling interconnection method according to claim 1, characterized in that, When using the integrated copper pillar insertion process in step S2, the following steps are included: inserting the copper pillar into the corresponding through hole and pressing the copper pillar into the through hole by stamping; when using the segmented copper pillar insertion process, the following steps are included: aligning and inserting multiple copper pillars with the through holes on the silicon substrate (1) in sequence, and plastically deforming the copper pillars that are not the last segment by stamping and inserting them all into the through hole; the subsequent insertion operation of the copper pillars pushes the copper pillars that have been inserted in the previous sequence to move further to the bottom of the through hole until the last segment of the copper pillar is inserted, so as to realize the splicing filling of the through hole.
5. The TSV solid-phase via-filling interconnection method according to claim 4, characterized in that, Based on the segmented copper pillar insertion process in step S2, after the stamping process of connecting two copper pillars, the debris on the surface of the silicon substrate (1) is cleaned; the length of the last copper pillar is designed such that after it is inserted, its upper part extends out of the surface of the silicon substrate (1).
6. The TSV solid-phase via-filling interconnection method according to claim 1, characterized in that, Based on step S2, the insertion and fixing process of the copper column includes three stages of pressure control performed sequentially: Stage 1: Constant speed pressing stage, the copper column is pressed into the through hole at a constant speed, and the ratio of pressing pressure to pressing displacement is monitored in real time. If the ratio is abnormal, pressing is stopped and the deviation is checked; when the ratio of pressing displacement to pressure is normal and the pressing pressure reaches the preset pressing threshold, the next stage is entered; Stage 2: Uniform speed pressurization stage, after the copper column is fully inserted, the pressure is increased uniformly to cause plastic deformation of the copper column, and pressure fluctuations are monitored in real time. When abnormal pressure fluctuations occur, pressurization is stopped; when the pressure reaches the preset pressurization threshold, the next stage is entered; Stage 3: Pressure holding stage, the pressure is maintained at the pressurization threshold until the preset pressure holding time is reached to complete the fixing.
7. The TSV solid-phase via-filling interconnection method according to claim 1, characterized in that, During the three-stage pressure control process, pressure data is acquired through the current signal of the stamping shaft servo motor or a high-precision load unit, and displacement data is measured through a high-precision linear encoder.
8. The TSV solid-phase via-filling interconnection method according to claim 1, characterized in that, Based on step S4, the electrical testing includes sampling the test structure using a probe station and / or performing a full wafer scan using micro-area infrared thermal imaging technology to locate high-resistivity defect areas. Based on the test results, process parameters are adjusted for the size threshold in step S1 and / or the pressure thresholds at each stage in step S2 to optimize the process.
9. A TSV solid-phase via-filling interconnect structure, comprising a TSV solid-phase via-filling interconnect method according to any one of claims 1-8, characterized in that, include: A silicon substrate (1) has through holes; at least one copper pillar body (2) is inserted and fixed in the through holes of the silicon substrate (1); wherein an insulating layer (3) and a barrier layer (4) are sequentially deposited on the inner wall of the through holes of the silicon substrate (1); the copper pillar body (2) forms a tight mechanical bond with the inner wall of the through holes of the silicon substrate (1) through plastic deformation.
10. A TSV solid-phase via-filling interconnect structure according to claim 9, characterized in that, The copper column body (2) is provided with tapered ports (21) at both the upper and lower ends.