Structure including mechanical and photonic features

Abstract

Examples of the present disclosure provide a structure comprising: a photonic integrated circuit (PIC) layer wherein at least one first gap is formed in the PIC layer to define at least one first portion, and the PIC layer comprises one or more optical structures, each having a corresponding optical field, the first electrode is arranged on one side of at least one first gap and is opposite to one first part of at least one first part of the PIC layer; a microelectromechanical system (MEMS) structural layer comprising a MEMS structure suspended proximate to at least one first portion of the PIC layer and defined by at least one second gap in the MEMS structural layer, the MEMS structure being deflectable under the effect of a force or disturbance; and a sacrificial layer arranged to separate the at least one first portion of the PIC layer from the at least one first portion of the MEMS structural layer, where lack of the first portion of the sacrificial layer causes the at least one first gap to communicate with the at least one second gap; wherein at least one first portion of the PIC layer is mechanically coupled to the MEMS structure to move in accordance with a deflection of the MEMS structure; and wherein a change in spacing between the at least one first portion and one of the one or more optical structures causes a change in light field characteristics of the optical structure. The structure also includes at least one coupling element that provides a mechanical coupling between the at least one first portion of the PIC layer and the MEMS structure. The at least one coupling element includes at least one first coupling element formed in a through-hole through a portion of the at least one first portion to a portion of the MEMS structure. Examples of the present disclosure also provide a method of manufacturing a structure.

Description

[0001] This disclosure generally relates to a structure comprising a mechanical layer and / or an electromechanical layer and a photonic layer, and also includes methods for manufacturing the same. Various examples disclosed herein relate to chips or structures including microelectromechanical (MEMS) structures and photonic integrated circuit (PIC) structures (e.g., via MEMS and PIC layers), which are directly and / or indirectly attached or bonded to each other. According to various examples, a MEMS-photonic circuit or chip includes one or more optical structures in a PIC layer and one or more MEMS structures in a MEMS layer, wherein displacement of the MEMS structures results in a change in the optical field characteristics associated with the one or more optical structures. According to various examples, such a circuit or chip is included in a wafer comprising additional circuitry / chips. Background Technology

[0002] Microelectromechanical systems (MEMS) are miniature devices that include both electronic and moving parts. MEMS structures can have thicknesses ranging from a few micrometers to tens of micrometers, for example, greater than 1 μm.

[0003] Photonic integrated circuits (PICs) are also miniature devices and can include multiple photonic components that form functional circuits. PIC structures can have a thickness on the order of hundreds of nanometers, such as 70-1000 nm.

[0004] Compared to PIC structures, MEMS structures can be significantly thicker. Furthermore, structures utilizing a combination of MEMS and PIC features may require small distances (e.g., less than 1 μm) between the MEMS and PIC features. If a combination of a PIC structure and one or more MEMS structures is implemented, such distances may be required in multiple dimensions. For example, the MEMS structure may need to be within 1 μm of the PIC structure in a first direction, and the MEMS structure may need to be within 1 μm of another PIC structure in a second direction (e.g., perpendicular to the first direction). Additional PIC structures may be located on opposite sides of the already described PIC structure, further requiring distances of less than 1 μm between the corresponding PIC and MEMS structures, thus increasing complexity.

[0005] Due to size mismatches, it is extremely difficult to fabricate structures combining MEMS and PIC features using conventional processes for manufacturing MEMS and PIC separately. Furthermore, existing wafer bonding methods for joining separately fabricated MEMS and PIC wafers have numerous drawbacks, such as low alignment accuracy between features on the MEMS and PIC wafers. In addition, the techniques used to create MEMS structures themselves introduce dimensional variations, so even if wafer bonding is precise, features on the two bonded wafers may differ in location and / or size. Summary of the Invention

[0006] Some examples of this disclosure are intended to at least partially solve, address, and / or mitigate at least one problem and / or defect associated with related technologies, such as at least one problem and / or defect described herein. Some examples of this disclosure are intended to provide at least one advantage relative to related technologies, such as at least one advantage described herein.

[0007] In various examples of this disclosure (e.g., the first example), a structure is provided comprising: a photonic integrated circuit (PIC) layer, wherein at least one first gap is formed in the PIC layer to define at least one first portion, and the PIC layer includes one or more optical structures, each optical structure having a corresponding optical field and located on one side of one of the first gaps and opposite to one of the first portions of the PIC layer; a microelectromechanical system (MEMS) structure layer including a MEMS structure suspended near at least one first portion of the PIC layer and defined by at least one second gap in the MEMS structure layer, the MEMS structure being deflectable under the action of a force or disturbance; and a sacrificial layer arranged to separate at least one first portion of the PIC layer from at least one first portion of the MEMS structure layer, wherein the absence of the first portion of the sacrificial layer causes at least one first gap to communicate with at least one second gap; wherein at least one first portion of the PIC layer is mechanically coupled to the MEMS structure to move according to the deflection of the MEMS structure; and wherein a change in the spacing between at least one first portion and one of the optical structures causes a change in the optical field characteristics of the optical structure. Advantageously, such a structure allows for the sensing of changes in the optical field characteristics in-plane or substantially in-plane within the PIC layer (or more specifically, the optical structure), thereby allowing the derivation of one or more related factors (e.g., displacement, velocity, or acceleration of the MEMS structure or at least one of the first parts).

[0008] In another example of this disclosure, a structure is provided comprising: a photonic integrated circuit (PIC) layer, wherein at least one first gap is formed in the PIC layer to define at least one first portion, and the PIC layer includes one or more optical structures, each optical structure having a corresponding optical field and located on one side of one of the first gaps and opposite to one of the first portions of the PIC layer; a microelectromechanical system (MEMS) structure layer including a MEMS structure suspended near at least one first portion of the PIC layer, the MEMS structure being deflectable under force or disturbance; and a sacrificial layer arranged to separate at least one first portion of the PIC layer from at least one first portion of the MEMS structure layer, wherein a first portion of the sacrificial layer is absent between the MEMS structure and at least one first portion of the PIC layer; wherein at least one first portion of the PIC layer is mechanically coupled to the MEMS structure to move according to the deflection of the MEMS structure; and wherein a change in the spacing between at least one first portion and one of the optical structures causes a change in the optical field characteristics of the optical structure. This can provide similar advantages to the first example.

[0009] In various examples (e.g., the second example), a structure according to any of the above examples (e.g., the first example) is provided, wherein at least one first portion is electrically coupled to the MEMS structure.

[0010] In various examples (e.g., the third example), a structure according to any of the above examples (e.g., the first or second example) is provided, wherein the structure includes at least one coupling element, and the mechanical coupling between at least one first portion of the PIC layer and the MEMS structure is provided by the at least one coupling element.

[0011] In various examples (e.g., the fourth example), a structure according to any of the above examples (e.g., the third example) is provided, wherein at least one coupling element is configured to electrically couple at least one first portion to the MEMS structure; or wherein the integrated circuit further includes at least one coupler configured to electrically couple the PIC layer to the MEMS structure. Advantageously, providing both mechanical and electrical coupling via at least one coupling element can improve functionality.

[0012] In various examples (such as the fifth example), a structure according to any of the above examples (such as the third example or the fourth example) is provided, wherein at least one coupling element comprises polysilicon, doped polysilicon, crystalline silicon, doped crystalline silicon, conductive material or semiconductor material.

[0013] In various examples (e.g., the sixth example), a structure according to any of the above examples (e.g., any of the third to fifth examples) is provided, wherein each of the at least one coupling element is formed in a through-hole passing through a portion of one of the first portions to a portion of the MEMS structure, wherein the MEMS structure is not adjacent to at least one first portion.

[0014] In various examples (e.g., the seventh example), a structure according to any of the above examples (e.g., the sixth example) is provided, further comprising a cavity provided below at least one first portion and located on one side of at least one first portion and opposite to the side on which the MEMS structure is located on at least one first portion. Advantageously, this allows at least one first portion to move more freely, for example, in a direction perpendicular to the plane in which the PIC layer extends.

[0015] In various examples (e.g., the eighth example), a structure according to any of the above examples (e.g., any of the third to fifth examples) is provided, wherein at least one coupling element is provided by a second portion of a sacrificial layer between the MEMS structure and at least one first portion, wherein the MEMS structure is not adjacent to at least one first portion. Advantageously, this can provide an alternative to forming at least one coupling element using vias, which can reduce the complexity of providing at least one coupling element.

[0016] In various examples (e.g., the ninth example), a structure according to any of the above examples (e.g., the eighth example) is provided, further comprising a cavity provided below the MEMS structure and located on one side of the MEMS structure and opposite to the side on which at least one first portion of the MEMS structure is located.

[0017] In various examples (e.g., the tenth example), a structure according to any of the above examples (e.g., any of the sixth to ninth examples) is provided, wherein the MEMS structure is defined by at least one second gap opened around the MEMS structure in the MEMS structure layer to separate the MEMS structure from the remainder of the MEMS structure layer.

[0018] In various examples (e.g., example eleven), a structure according to any of the foregoing examples (e.g., any of examples three through five) is provided, wherein at least one coupling element or MEMS structure is formed by depositing material on at least one first portion to provide a MEMS structure adjacent to and mechanically coupled to at least one first portion. Advantageously, this can provide an alternative to forming at least one coupling element using vias, which can reduce the complexity of providing at least one coupling element; or it can provide a method for simultaneously forming the MEMS structure and the coupling element.

[0019] In various examples (e.g., the twelfth example), a structure according to any of the above examples (e.g., the eleventh example) is provided, wherein at least one coupling element is formed by epitaxial deposition on at least one first portion and on at least a portion of a sacrificial layer to grow a first bulk of a first material on at least one first portion and a second bulk of a second material on the sacrificial layer; wherein the first bulk and the second bulk correspond to a MEMS structure layer, and the first layer contains a MEMS structure; and wherein at least one coupling element corresponds to a bonding region between at least one first portion and the first bulk.

[0020] In various examples (e.g., example thirteen), a structure according to any of the above examples (e.g., example twelfth) is provided, wherein the PIC layer is formed of silicon; the sacrificial layer is formed of oxide; the first material is crystalline silicon formed by epitaxial deposition of silicon onto the PIC layer; and the second material is polycrystalline silicon formed by epitaxial deposition of silicon onto the sacrificial layer.

[0021] In various examples (e.g., the fourteenth example), a structure according to any of the above examples (e.g., any of the eleventh to thirteenth examples) is provided, wherein at least one second gap is formed in a second block surrounding the first block, and the at least one second gap is arranged to be connected to or aligned with at least one first gap.

[0022] In various examples (e.g., the fifteenth example), a structure according to any of the above examples (e.g., the tenth example or the fourteenth example) is provided, wherein each of the at least one first gap is a gap between 100 nm and 500 nm; and / or wherein each of the at least one second gap surrounding the MEMS structure is larger than each of the at least one first gap.

[0023] In various examples (e.g., the sixteenth example), a structure according to any of the above examples (e.g., any of the first to fifteenth examples) is provided, wherein the PIC layer further includes: one or more input waveguides, each input waveguide being configured to provide input light to one of the one or more optical structures; and one or more output waveguides, each output waveguide being configured to receive output light from one of the one or more optical structures.

[0024] In various examples (e.g., the seventeenth example), a structure according to any of the above examples (e.g., any of the first to sixteenth examples) is provided, wherein one or more optical structures are optical resonators and the optical field characteristics are optical resonant characteristics.

[0025] In various examples (e.g., example eighteen), a structure according to any of the above examples (e.g., example seventeen) is provided, wherein the change in the optical field characteristics is a shift in the optical resonance and / or a broadening or deepening of the optical resonance curve.

[0026] In various examples (e.g., the nineteenth example), a structure according to any of the above examples (e.g., any of the first to eighteenth examples) is provided, wherein the structure includes two optical structures; and wherein a change in a first spacing between a first portion of at least one first portion and a first optical structure in the optical structure, and a change in a second spacing between a second portion of at least one first portion and a second optical structure in the optical structure, results in a differential change in the optical field characteristics of the first optical structure and the second optical structure in the at least two optical structures.

[0027] In various examples (e.g., the twentieth example), a structure according to any of the above examples (e.g., any of the first to nineteenth examples) is provided, wherein at least one active optical structure is formed on the PIC layer.

[0028] In various examples of this disclosure (e.g., example twenty-one), a method of fabricating a structure is provided, the method comprising: preparing a stacked structure including a photonic integrated circuit (PIC) layer by the steps of: forming at least one first gap in the PIC layer to define at least one first portion; and forming one or more optical structures in the PIC layer, each optical structure having a corresponding optical field, wherein each of the one or more optical structures is located on one side of one of the first gaps and opposite to one of the first portions, wherein the stacked structure further includes a sacrificial layer near the PIC layer; and providing a MEMS structure in a microelectromechanical system (MEMS) structure layer. The MEMS structure is mechanically coupled to at least one first portion and suspended near the at least one first portion, such that the MEMS structure is deflectable under the action of force or disturbance, and the deflection of the MEMS structure causes the at least one first portion to move; wherein the MEMS structure is defined in the MEMS structure layer by at least one second gap; wherein a sacrificial layer is arranged to separate at least one first portion of the PIC layer from at least one first portion of the MEMS structure layer, wherein the absence of the sacrificial layer in the first portion causes the at least one first gap to communicate with the second gap; and wherein a change in the spacing between the at least one first portion and one of the optical structures causes a change in the optical field characteristics of the optical structure.

[0029] In various examples (such as example twenty-two), a method according to any of the above examples (such as example twenty-one) is provided, further comprising: electrically coupling at least one first portion to a MEMS structure.

[0030] In various examples (e.g., example twenty-three), a method according to any of the above examples (e.g., example twenty-one or example twenty-two) is provided, further comprising: providing at least one coupling element in the structure to mechanically couple at least one first portion of the PIC layer to the MEMS structure.

[0031] In various examples (e.g., example twenty-four), a method according to any of the above examples (e.g., example twenty-three) is provided, wherein at least one coupling element is configured to electrically couple at least one first portion to a MEMS structure; or wherein the method further includes providing at least one coupler in the structure, the at least one coupler being configured to electrically couple a PIC layer to the MEMS structure.

[0032] In various examples (e.g., example twenty-fifth), a method according to any of the above examples (e.g., example twenty-third or example twenty-fourth) is provided, wherein at least one coupling element comprises polysilicon, doped polysilicon, crystalline silicon, doped crystalline silicon, conductive material or semiconductor material.

[0033] In various examples (e.g., example twenty-six), a method according to any of the above examples (e.g., any of examples twenty-three to twenty-five) is provided, wherein the step of providing at least one coupling element comprises: defining a through-hole through a portion of one of the at least one first portion to a portion of a MEMS structure for each of the at least one coupling element, and forming each of the at least one coupling element in a corresponding through-hole in the at least one through-hole; and wherein the MEMS structure is mechanically coupled to at least one first portion and is not adjacent to at least one first portion.

[0034] In various examples (e.g., example twenty-seven), a method according to any of the above examples (e.g., example twenty-six) is provided, further comprising: providing a cavity below at least one first portion and located on one side of at least one first portion and opposite to the side on which the MEMS structure is located on at least one first portion.

[0035] In various examples (e.g., example twenty-eight), a method according to any of the above examples (e.g., any of examples twenty-three to twenty-five) is provided, wherein at least one coupling element is provided by a second portion of a sacrificial layer between a MEMS structure and at least one first portion, and wherein the MEMS structure is mechanically coupled to at least one first portion and is not adjacent to at least one first portion.

[0036] In various examples (such as example twenty-nine), a method according to any of the above examples (such as example twenty-eight) is provided, further comprising: providing a cavity below the MEMS structure and located on one side of the MEMS structure and opposite to the side on which at least one first portion of the MEMS structure is located.

[0037] In various examples (e.g., the thirtieth example), a method according to any of the above examples (e.g., any of the twenty-sixth to twenty-ninth examples) is provided, further comprising: defining the MEMS structure by opening at least one second gap around the MEMS structure in the MEMS structure layer to separate the MEMS structure from the remainder of the MEMS structure layer.

[0038] In various examples (e.g., example thirty-first), a method according to any of the above examples (e.g., any of examples twenty-six to thirtieth) is provided, further comprising: providing a sacrificial layer on the PIC layer after forming at least one first gap and one or more optical structures.

[0039] In various examples (such as example thirty-two), a method according to any of the above examples (such as example thirty-one) is provided, further comprising: after providing the sacrificial layer, bonding the MEMS structure layer to one side of the sacrificial layer and opposite to the side on which the PIC layer is located on the sacrificial layer.

[0040] In various examples (e.g., example thirty-three), a method according to any of the above examples (e.g., example thirty-two) is provided, further comprising: after bonding the MEMS structure layer and providing the MEMS structure, removing a first portion of the sacrificial layer between the MEMS structure and at least a first portion of the PIC layer.

[0041] In various examples (e.g., example thirty-four), a method according to any of the above examples (e.g., any of examples twenty-one to thirty-three) is provided, wherein: the PIC layer is formed of silicon; the sacrificial layer is formed of oxide; and the MEMS structure layer is formed of silicon.

[0042] In various examples (e.g., example thirty-fifth), a method according to any of the above examples (e.g., any of examples twenty-first to twenty-fifth) is provided, wherein the step of providing a MEMS structure and / or providing at least one coupling element includes: depositing material on at least one first portion to provide a MEMS structure adjacent to and mechanically coupled to at least one first portion.

[0043] In various examples (e.g., example thirty-six), a method according to any of the foregoing examples (e.g., example thirty-five) is provided, wherein the steps of providing a MEMS structure and / or providing at least one coupling element include: growing a first bulk of a first material on at least one first portion and on at least a portion of a sacrificial layer by epitaxial deposition, and growing a second bulk of a second material on the sacrificial layer; wherein the first bulk and the second bulk correspond to a MEMS structure layer, and the first layer contains a MEMS structure; and wherein at least one coupling element corresponds to a bonding region between at least one first portion and the first bulk.

[0044] In various examples (such as example thirty-seven), a method according to any of the above examples (such as example thirty-six) is provided, wherein: the PIC layer is formed of silicon; the sacrificial layer is formed of oxide; the first material is crystalline silicon formed by epitaxial deposition of silicon onto the PIC layer; and the second material is polycrystalline silicon formed by epitaxial deposition of silicon onto the sacrificial layer.

[0045] In various examples (e.g., example thirty-eight), a method according to any of the above examples (e.g., example thirty-six or example thirty-seven) is provided, wherein at least one second gap is formed in a second block surrounding a first block, the at least one second gap being connected to at least one first gap.

[0046] In various examples (such as example thirty-nine), a method according to any of the above examples (such as any of examples thirty-five to thirty-eight) is provided, further comprising: removing a first portion of the sacrificial layer from near at least one first portion of the PIC layer before providing the MEMS structure.

[0047] In various examples (e.g., the fortieth example), a method according to any of the above examples (e.g., the thirtieth or the thirty-eighth example) is provided, wherein each of the at least one first gap is a gap between 100 nm and 500 nm; and / or wherein each of the at least one second gap surrounding the MEMS structure is larger than each of the at least one first gap.

[0048] In various examples (e.g., example forty-first), a method according to any of the above examples (e.g., any of examples twenty-first to forty) is provided, further comprising: forming one or more input waveguides in a PIC layer, each input waveguide being configured to provide input light to one of one or more optical structures; and forming one or more output waveguides in the PIC layer, each output waveguide being configured to receive output light from one of one or more optical structures.

[0049] In various examples (e.g., example forty-two), a method according to any of the foregoing examples (e.g., any of examples one through twenty) is provided, wherein light is coupled into and out of each of one or more optical structures; one or more detectors are configured to detect light received from the one or more optical structures; and one or more processors are configured to receive the outputs of the one or more detectors and determine a change in the spacing between at least one first portion and one of the one or more optical structures by detecting changes in the light field characteristics of the optical structures.

[0050] In various examples (such as example forty-three), an apparatus according to any of the foregoing examples (such as example forty-two) is provided, wherein the apparatus is or is included in an inertial sensor, microphone, timing oscillator, pressure sensor, ultrasonic transceiver, ultrasonic receiver, micromirror, or microstructure whose spacing changes due to an applied force or disturbance.

[0051] In various examples (such as example forty-four), a wafer is provided that includes a plurality of structures as described in any of the examples from the first to the twentieth.

[0052] Other aspects, advantages, and distinctive features of the invention will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0053] The embodiments, examples, and aspects of this disclosure are further described below with reference to the accompanying drawings, in which:

[0054] Figures 1A to 1D The illustrations illustrate first methods for providing structures according to various examples of this disclosure.

[0055] Figures 2A to 2C The illustrations illustrate first methods for providing hierarchical structures according to various examples of this disclosure.

[0056] Figures 3A to 3D The illustrations illustrate a second method for providing a hierarchical structure according to various examples of this disclosure.

[0057] Figures 4A to 4F The illustrations illustrate various examples of second methods for providing structures according to this disclosure.

[0058] Figures 5A to 5H The illustrations illustratively depict various examples of third methods for providing structures according to this disclosure.

[0059] Figures 6A to 6F The illustrations illustrate a fourth method for providing a structure according to several examples of this disclosure.

[0060] Figure 7 The hierarchical structure is illustrated schematically according to various examples of this disclosure. Detailed Implementation

[0061] Throughout the description and claims of this specification, the words “comprising” and “including” and their variations mean “including, but not limited to”, and are not intended to (and do not) exclude other additional components, elements, integers, or steps. Throughout the description and claims of this specification, unless the context otherwise requires, the singular form includes the plural meaning. In particular, where the indefinite article is used, the specification should be understood to consider both the plural and singular forms, unless the context otherwise requires.

[0062] When used with a list of items, the phrases or expressions “at least one,” “one or more,” and “and / or” mean that different combinations of one or more of the listed items may be used, and only one item from the list may be required. For example, “at least one of the following: A, B, and C” (and “one or more of A, B, and C”, and “A, B, and / or C”) includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C.

[0063] This disclosure provides various methods or processes for fabricating structures including MEMS features and photonic integrated circuit (PIC) features (e.g., chips or circuits including mechanical layers and photonic chip layers (e.g., not limited to integrated circuits (ICs)), wherein the photonic chip layer itself may include one or more layers defining active photonic structures, such as lasers, detectors, heaters, etc.). This disclosure also provides a structure including MEMS features and PIC features, for example, a chip or circuit including MEMS layers and photonic chip layers. In some examples, this structure can be fabricated using one of the processes disclosed herein.

[0064] The use of “first step,” “second step,” “third step” (or similar expressions such as “operation” or “subprocess” may be used instead of “step”) in the following text is not intended to indicate the chronological order of the steps, but rather to distinguish the individual steps by using the terms “first,” “second,” and “third.”

[0065] Figure 1A , Figure 1B , Figure 1C and Figure 1D This schematically illustrates a first method for providing a structure comprising PIC and MEMS layers (sometimes referred to as a chip or circuit in the given example without limitation). This method can be viewed as a chip-to-chip flip-chip bonding process.

[0066] Figure 1AThe MEMS die 100 is shown in cross-sectional view, comprising a first layer 101 (e.g., a first silicon layer), a second layer 103 (e.g., a buried oxide (BOX) layer, such as a silicon dioxide layer), and a third layer 105 (e.g., a second silicon layer). The MEMS die 100 also includes a metallic (e.g., gold, indium, aluminum, germanium, or an alloy (e.g., tin)) conductive element 107. In various examples, element 107 may be additionally or alternatively provided for use with the MEMS die 100. Figure 1B The bonding between the PIC dies 120 shown, or facilitating the bonding between them. The portion of the MEMS die 100 on which the components 107 are arranged can be regarded as part of the bonding frame.

[0067] The third layer 105 includes a MEMS structure 109, which in one example may be a test block (inspection block). The third layer 105 or the MEMS structure 109 may also be considered a MEMS device layer. The MEMS die 100 can be fabricated using conventional methods. The first layer 101 may be considered a MEMS support layer 101. It can be seen that the second layer 103 is not present between the MEMS structure 109 and the first layer 101. In some examples, the MEMS structure 109 is attached or coupled to the third layer 105 (e.g., the remainder of the third layer 105 excluding the MEMS structure 109) via one or more springs, wherein one or more springs are coupled or attached to one or more anchor points attached to the third layer 105. The springs may allow movement of the MEMS structure 109 (e.g., movement in response to an external force acting on the MEMS die 100), for example, once the external force is no longer acting on the MEMS die 100, the MEMS structure 109 may then return to a resting position via the springs.

[0068] Figure 1B The PIC die 120 is shown in cross-sectional view and includes a first layer 121 (e.g., a first silicon layer), a second layer 123 (e.g., a first silicon dioxide layer), a third layer 125 (e.g., a second silicon layer), and a fourth layer 127 (e.g., a second silicon dioxide layer). The PIC die 120 also includes a metallic (e.g., gold, indium, aluminum, germanium, or an alloy (e.g., tin)) conductive element 129. In various examples, element 129 may be additionally or alternatively provided for bonding between the MEMS die 100 and the PIC die 120, or to facilitate bonding therebetween.

[0069] The third layer 125 includes a PIC structure 131 or an optical structure 131. The third layer 125 or the optical structure 131 itself can also be regarded as a PIC device layer. For illustrative purposes, the first layer 121 can be regarded as a PIC support layer 121. Figure 1BThe diagram also shows a hard stop 133, which may be selectively formed on the PIC die 120. In some examples, the hard stop 133 may comprise an oxide layer, silicon, or polysilicon. One or more active layers (e.g., including on-chip photodetectors or lasers) may also be included in or on the PIC die 120, for example, by forming on a third layer 125.

[0070] Figure 1C The cross-sectional view illustrates a structure 140 (e.g., chip 140) obtained by bonding a MEMS die 100 and a PIC die 120. For example, a MEMS wafer including one or more MEMS dies 100 can be bonded to a PIC wafer including one or more corresponding PIC dies 120, thereby obtaining a wafer including a corresponding number of chips 140. For clarity, Figure 1C The middle part is omitted Figure 1A and Figure 1B The reference numerals shown in the figures; however, Figure 1A and Figure 1B The same components represented in the text exist in Figure 1C Therefore, the corresponding figure labels can be referred to.

[0071] exist Figure 1C As can be seen in the figures, element 107 of MEMS die 100 is in contact with element 129 of PIC die 120. For example, the corresponding elements are permanently bonded or glued together (e.g., using metal connections (e.g., eutectic or thermoforming bonding) or conductive epoxy), thereby attaching MEMS die 100 to the individual PIC die 120. In the figures, bonding is reflected by variations in the shape of elements 107, 129, for example, indicating that bonding may result in compression and / or protrusion of these elements 107, 129. If a hard stop 133 is included, the first layer 101 of MEMS die 100 may contact the hard stop 133 when element 107 is bonded to element 129.

[0072] Based on this attachment, the MEMS structure 109 is suspended near the optical structure 131 (e.g., suspended near but not adjacent to the optical structure 131). For example, the MEMS structure 109 may be located at a distance d from the optical structure 131, where d < 1 μm (e.g., d = 0.5 μm). The edge of the MEMS structure 109 facing the optical structure 131 may be aligned with the edge facing the optical structure 131.

[0073] Furthermore, the MEMS structure 109 is suspended at a distance z above the PIC support layer 121. This distance can be determined based on one or more hard stops 133 included within / on the PIC die 120 (and / or hard stops within / on the MEMS die 100). That is, when the first layer 101 of the MEMS die 100 contacts the hard stop 133, the hard stop 133 can prevent or at least partially restrict the first layer 101 of the MEMS die 100 along the y-direction (e.g., Figure 1C The '-y' direction shown further moves toward the first layer 121 of the PIC die. A non-limiting dimensional example is given, z = 1.3 μm.

[0074] Positioning the MEMS structure 109 close to the optical structure 131 (i.e., within a specified distance) may be critical, if not necessary, for providing certain functions in / by means of the chip 140.

[0075] For example, optical structure 131 may be an optical microresonator having or exhibiting an optical field. For instance, when light propagates along the microresonator (i.e., through optical structure 131), the optical field of the microresonator may correspond to or include an evanescent field outside the microresonator that extends from the boundary of the microresonator (e.g., a silicon-air or silicon-vacuum boundary). It can be understood that the evanescent field (i.e., the optical field) extends in different directions, such as the horizontal direction (e.g., within the plane of the microresonator, towards MEMS structure 109; along...). Figure 1C The x-direction shown), the vertical direction (e.g., towards the second layer 123 and into the air surface / layer; along Figure 1C The y-direction shown), diagonal direction, etc.

[0076] The presence of the MEMS structure 109 (as previously described, which may be a test or inspection block) in the optical field alters the properties of the microresonator (e.g., at least one characteristic of the microresonator's optical field). For example, due to the interaction of the MEMS structure 109 with the evanescent field, the effective refractive index of the microresonator will change, leading to a change in the optical resonance of the microresonator's modes (e.g., whispering-gallery modes). This change in optical resonance could, for example, be a shift in the resonant wavelength and / or a broadening or deepening of the optical resonance curve. Therefore, it can be understood that the distance d between the MEMS structure 109 and the microresonator will affect the change in optical resonance (effective refractive index) caused by the MEMS structure 109. In another example, the microresonator may be affected by increased losses due to scattering or absorption effects caused by the presence of the MEMS structure 109.

[0077] MEMS structure 109 is suspended on MEMS layer 105, for example, via a spring and anchor system as described above, allowing it to be displaced or deflected (e.g., moved from an initial or equilibrium position). For example, when chip 140 moves or is subjected to a force (e.g., an inertial force), MEMS structure 109 can be displaced accordingly. For example, due to the unbalanced force causing chip 140 to move and the suspension of MEMS structure 109, chip 140 moves to the right (i.e., Figure 1C (From the center to the right or in the '+x' direction) will cause the MEMS structure 109 to shift to the left (i.e., Figure 1C (From left or '-x' direction). If chip 140 stops moving, MEMS structure 109 will return to its initial position (assuming chip 140 is in the same orientation as before moving - for example, no rotation occurred).

[0078] Figure 1D An example of a spring and anchor system is shown for attaching (i.e., suspending, movably attaching, coupling, etc.) the MEMS structure 109 to another part of the MEMS die 100 (e.g., a third layer 105).

[0079] The plan view shown in the image on the right (which may reflect a portion of chip 140 or MEMS die 100, where features of PIC die 120 are omitted, for example, relative to...) Figure 1C The diagram (viewed along the '+y' direction) illustrates how a portion of the second layer 103 (e.g., a buried oxide / silicon dioxide layer) is separated from the MEMS structure 109 (e.g., considering...) Figure 1C The arrangement shown is characterized by the removal of portions of the third layer 105 above or along the '+y' direction (or, in other words, around the portion of the third layer 105 including the location where the MEMS structure 109 is formed, e.g., along the '+y' direction). Springs 111a, 111b attach the MEMS structure 109 to anchor points 113 (which may be formed of silicon), and anchor points 113a, 113b attach to or connect to the remainder of the third layer 105. In some examples, anchor points 113a, 113b and / or springs 111a, 111b are formed by the third layer 105.

[0080] In an illustrative example, the MEMS structure 109 can be released from the second layer 103, which serves as a BOX layer, using etching (e.g., hydrogen fluoride (HF) vapor phase etching). Openings around the MEMS structure 109 allow the vapor phase HF to attack or process the exposed BOX layer around the MEMS structure 109. However, in areas without openings (e.g., where most anchors 113a, 113b are found), the BOX is preserved (i.e., not removed by the HF vapor phase), allowing most anchors 113a, 113b to remain attached to the BOX layer.

[0081] Figure 1D The diagram also shows three cross-sectional views: A – A', B – B', and C – C'. In the cross-sectional view corresponding to the dashed line A – A', anchor point 113a (i.e., a portion thereof) can be seen attached to the second layer 103 and the third layer 105. In the cross-sectional view corresponding to line B – B', spring 111a (i.e., a portion thereof) is shown suspended, meaning it is not directly attached to the second layer 103 or the third layer 105, but rather attached between anchor point 113a and MEMS structure 109. In the cross-sectional view corresponding to line C – C', the suspension of MEMS structure 109 is shown; MEMS structure 109 is not directly attached to the second layer 103 or the third layer 105, but is attached to anchor point 113a via spring 111a (and also to anchor point 113b via spring 111b).

[0082] It should be understood that although the spring and anchor system was described to illustrate how a MEMS structure can be suspended on a MEMS die (or within a PIC-MEMS structure), other methods can be used to achieve the same result, and therefore the given example should not be considered a limitation. In other examples in this paper, for example, […]. Figure 1D The spring and anchor system shown is used to suspend the MEMS structure.

[0083] It should be understood that changes in the position of the MEMS structure 109 relative to the microresonator (e.g., caused by displacement of the MEMS structure 109) will alter the effect of the presence of the MEMS structure 109 (or its potentially opaque surface) on the optical field of the microresonator. For example, the resonant wavelength may shift (e.g., increase or decrease). Changes in the optical field characteristics (e.g., changes in the optical resonant linewidth or shape, or changes in the value of the optical resonant itself) can be measured to determine (or calculate, infer, etc.) the displacement of the MEMS structure 109.

[0084] The PIC die 120 may include an input waveguide arranged to provide (e.g., couple) light to the optical structure 131. For example, the input waveguide may be located in a third layer 125, such that light propagating in the input waveguide (e.g., light input from a laser to the input waveguide) is coupled into the microresonator. It should be understood that other methods exist for inputting light to the optical structure 131; the method described above is merely one example.

[0085] The PIC die 120 may also include an output waveguide arranged to receive or acquire light from the optical structure 131. The output waveguide may be formed as part of the same element / assembly (e.g., waveguide) as the input waveguide within the PIC die 120 (e.g., in the third layer 125), or it may be provided separately within the PIC die 120. For example, the output waveguide may be located in the third layer 125 adjacent to a microresonator, such that light propagating in the microresonator is coupled into the output waveguide. In some cases, the optical coupler included in the PIC die 120 may include both an input waveguide and an output waveguide; for example, in an all-through arrangement, a single waveguide provides both an input port and a through port; or in a plug-in arrangement, two separate waveguides are used to provide four ports (plug-in port, input through port).

[0086] The output waveguide can provide light to a detector (e.g., a measuring device, or any device that converts an optical signal into an electrical signal; an example of a detector is a photodetector). The detector can be included in chip 140 and arranged to receive light from the output waveguide, or it can be provided separately and arranged relative to chip 140 to receive light from the output waveguide. The detector, alone or in combination with another component (which may also be included within or separate from chip 140), can detect changes in the optical field characteristics. Based on the detected changes (e.g., a shift in the resonant wavelength or a broadening / narrowing of the resonant linewidth), the displacement of the MEMS structure 109 can be determined.

[0087] It should be understood that detecting or calculating the displacement of MEMS structure 109 has many practical applications. For example, knowing the displacement and / or, further, the rate at which the displacement occurs (i.e., the velocity of the displacement, which can be determined by measuring multiple changes in the characteristics of the optical field) can be used to determine the acceleration, rotation, or velocity of chip 140 or a device including chip 140. For example, if chip 140 is an inertial sensor (which itself may be included in a mobile phone or other device) or is included in an inertial sensor, the inertial sensor can determine the acting inertial forces. Therefore, chip 140 can facilitate the realization of accelerometers, gyroscopes, and other inertial sensors.

[0088] Chips or circuits such as structure / chip 140 have other uses. For example, if MEMS structure 109 is driven by its mechanical resonance (e.g., by an actuator driven by an electrostatic comb also present in the third layer 105 (or in a suitable location), then structure 140 can be used as an oscillator element or clock. In another example, if MEMS structure 109 is formed as a plate or membrane structure that can be struck by sound waves, then structure 140 can be used as a pressure sensor, microphone, or ultrasonic transceiver. In yet another example, if MEMS structure 109 is formed as a plate or membrane structure that can be struck by infrared light, then structure 140 can be used as a calorimeter or temperature sensor.

[0089] Combination Figures 1A to 1D The advantage of the publicly disclosed die-to-die flip-chip bonding process is that separate dedicated foundries or manufacturing facilities for PIC and MEMS can produce PIC dies 120 and MEMS dies 100, respectively. Therefore, each facility manufactures with optimized equipment types for its tools, potentially resulting in lower wafer manufacturing operating costs and higher yields. Furthermore, by selecting the best-performing dies from each PIC and MEMS wafer and then bonding them together, this process can create high-performance chips / circuits.

[0090] However, this method also has drawbacks. First, while this method may be applicable to die-to-die bonding, it is not suitable for wafer-to-wafer bonding because the optical structure 131 is preferably (if not necessarily) located close to the edge of the MEMS structure 109, for example, less than 1 micrometer apart (i.e., d < 1µm). This is because the evanescent field does not extend far away from the optical structure 131, so the MEMS structure 109 can only have a perceptible or measurable effect on the optical field characteristics of the optical structure 131 within a very short distance. For example, if the test block is too far from the microresonator, the test block or its displacement may not have a suitable measurable effect on the optical resonance of the microresonator, or may not have a sustained suitable measurable effect on the optical resonance, thus making it impossible to continuously and accurately detect the displacement. Using a die-to-die approach, MEMS structures cannot be etched as precisely or accurately as PIC structures. This means that the blocks on the MEMS wafer will not be uniformly aligned with their corresponding blocks on the PIC wafer across the entire wafer formed by bonding the MEMS wafer to the PIC wafer, resulting in misalignment between components on the individual MEMS and PIC dies. For mass production, the die-to-die approach may also have scalability issues, considering its potentially slow throughput and expensive processes.

[0091] Another drawback is that wafer warping can occur after processing PIC and MEMS wafers, causing the wafer edges to bend upwards, forming a bowl shape. If wafer-to-wafer bonding is used, misalignment may occur at the edges and / or peripheries of the individual dies when compared to the center. This could result in the inability to achieve the critical gap (i.e., the space between the MEMS structure (e.g., MEMS structure 109) and the corresponding optical structure (e.g., optical structure 131)) via the bonding process, or even cause mechanical interference or potential damage to features if misalignment causes misalignment. After bonding, the chips are unlikely to provide high yields, and there will be differences between different chips. Therefore, performing differential sensing using chips manufactured in this way may be very difficult or even infeasible.

[0092] Furthermore, the robustness of the bonding scheme may have weaknesses because it may rely on the bonding layer (e.g., metal, epoxy, polymer) whose properties differ significantly from those of the materials used to define / form the PIC structure (e.g., optical structure 131) and MEMS structure (e.g., MEMS structure 109). For example, a mismatch in the coefficients of thermal expansion can stress the bonding layer over time and compromise bond integrity. Changes in the bonding layer and the resulting changes in the bonding interface can alter and affect the vertical position ( Figure 1C Changes in the "z" in the equation can lead to changes in the evanescent field.

[0093] Therefore, the various examples of this disclosure provide alternative methods for fabricating structures (e.g., including chips or circuits) that include PIC features and MEMS features, and some examples are designed to avoid one or more of the aforementioned disadvantages of die-to-die flip chip bonding methods and / or provide their own advantages.

[0094] According to various examples of this disclosure, higher yield and more robust methods are provided in which photonic and mechanical structures are created from a single wafer. In such a structure, the alignment between MEMS features and PIC features is defined by design (e.g., mask, etching, etc.) rather than achieved by integrating or bonding two separate wafers.

[0095] Figures 2A to 2C A method for providing a structure including a PIC layer and a MEMS layer is schematically illustrated, wherein the structure is formed from a single wafer (e.g., including a PIC layer and a MEMS layer).

[0096] Figures 3A to 3D An alternative method for providing a structure including a PIC layer and a MEMS layer is schematically illustrated, wherein the structure is formed by bonding two separate wafers (i.e., substructures, for example, corresponding to a MEMS wafer including a MEMS layer and a PIC wafer including a PIC layer).

[0097] As can be seen below, in the second method, any structure can be used (i.e., by...). Figures 2A to 2C The resulting structure 240 or by Figures 3A to 3D The resulting structure (360°) provides a structure including a PIC layer and a MEMS layer, such as Figures 4A to 4F As shown schematically in the diagram.

[0098] Figure 2A The structure 200 is shown in cross-sectional view, comprising a first layer 201, a second layer 203, a third layer 205, a fourth layer 207, and a fifth layer 209. The first layer 201 is the PIC layer 201, and this designation will be used throughout the hereinafter. The third layer 205 is the MEMS layer 205, and this designation will be used throughout the hereinafter.

[0099] PIC layer 201 may include or be formed of photonic functional materials. In some examples, PIC layer 201 may include or be formed of a stack of photonic materials, such as indium phosphide or germanium, wherein one or more materials included in the stack can be used to define a laser and / or a photodetector (i.e., an active layer). MEMS layer 205 may include or be formed of crystalline or polycrystalline materials (e.g., silicon or glass). If silicon is used, dopants may be added to achieve semiconductor or conductive properties. In various examples, both MEMS layer 205 and PIC layer 201 may be silicon layers. Alternatively, MEMS layer 205 and PIC layer 201 (or each layer / material in the stack of photonic materials included in PIC layer 201) may be formed of the same or different of the following materials: silicon, silicon nitride, polycrystalline silicon, silicon-germanium, germanium, indium phosphide, gallium nitride, and silicon carbide.

[0100] The second layer 203 and the fourth layer 207 can be insulating layers and / or sacrificial layers. In various examples, one or both of the second layer 203 and the fourth layer 207 can be silicon oxide layers (i.e., oxide layers or buried oxides).

[0101] The fifth layer 209 can be a support layer 209 (e.g., a support wafer). In one example, the support layer 209 is formed of crystalline silicon.

[0102] In the exemplary case where the PIC layer 201 and MEMS layer 205 are silicon layers and the second layer 203 and the fourth layer 207 are buried oxide layers, the structure 200 can be provided by a double silicon-on-insulator (SOI) wafer (DSOI wafer).

[0103] In the first step (PIC process manufacturing step), multiple features are defined by processing the PIC layer 201 to obtain... Figure 2B The structure 220 is shown. In various non-limiting examples, this process can be performed using electron beam lithography or deep ultraviolet lithography, or next-generation lithography methods (such as X-ray lithography, focused ion beam lithography, quantum lithography, extreme ultraviolet lithography, and nanoimprint lithography), followed by etching. In this disclosure, when describing the defined features in the PIC layer, it should be assumed that various examples consider performing the above-described defined / processed features using one of the foregoing methods (but not excluding other methods).

[0104] In particular, such as Figure 2B As shown, the PIC layer 201 can be fabricated to form: one or more optical structures 221 (wherein) Figure 2BOne cross-sectional example is shown, but more can be formed in structure 220), at least one gap 223 (e.g., a first gap 223; these can alternatively be referred to as a first space, a first opening, a first groove, etc.), and at least one portion 225 (e.g., a first portion 225—wherein) Figure 2B Two cross-sectional examples are shown, but more or fewer can be formed in structure 220; these may alternatively be referred to as first regions, first portions, first segments, etc., as well as other gaps (e.g., the gap between two first portions 225). Other features that can be formed in PIC layer 201 (optionally) include gratings and / or waveguides (e.g., input waveguides and / or output waveguides). According to various examples, these features can be formed by etching PIC layer 201.

[0105] The first gap 223 can have the characteristics of targeting Figure 1C The defined distance d is a similar dimension. For example, the width of the first gap (i.e., the wall-to-wall distance) can be less than 1 μm, and in some examples, this gap is less than 500 nm. The width of the first gap may depend on the limits of the photolithography performed before etching the first gap. The example accuracy of this process is ±50 nm, but it should be understood that this may vary depending on the photolithography (or other) method used.

[0106] The first gap 223 may at least partially define the first portion 225. For example, in Figure 2B In the diagram, the first portion 225 is defined by the first gap 223 and the gap etched between the two first portions 225. In the example, besides... Figure 2B In addition to the other gaps defined between the two first portions 225, a single first gap 223 may also be defined around the two first portions 225 in the form of a closed loop; here, Figure 2B The two first gaps 223 indicated / numbered in the middle are actually cross-sections of the same first gap 223. In other examples, multiple separate first gaps 223 are provided to define the first portion 225.

[0107] Optical structure 221 can have a corresponding light field, similar to that for... Figures 1A to 1C Description of optical structure 131. For example, optical structure 211 may be a microresonator (e.g., a whispering-gallery mode resonator), and the optical field may correspond to the evanescent field of light originating from the microresonator propagating in the microresonator. Although not shown, PIC layer 201 may also include an input waveguide arranged to provide light to optical structure 221 (e.g., via coupling), and an output waveguide arranged to receive light from optical structure 221 (e.g., via coupling). Alternatively, such waveguides may be provided at other locations on structure 220, or on the wafer including structure 220.

[0108] like Figure 2C As shown, the second step is to perform oxidation to protect the features formed in the PIC layer 201. As a result, structure 240 includes an oxide layer 227, or sacrificial layer 227 as hereinafter, which at least partially surrounds the PIC layer 201 (specifically covering the optical structure 221, the first gap 223, and at least one first portion 225 to protect these features). In addition to oxidation, or as an alternative to oxidation, in some examples, silicon oxide material may be deposited and / or planarization may be performed to smooth the surface of the sacrificial layer 227. In various examples, the second process step may include depositing silicon oxide material, such as plasma-enhanced chemical vapor deposition (PECVD) oxide or tetraethyl orthosilicate (TEOS), on the PIC layer 201.

[0109] In various examples, one or more active layers (not shown in the figures) are formed in structure 240, such as prior to an oxidation or deposition step. For example, an active layer (e.g., a germanium or indium phosphide layer) may be formed on at least a portion of PIC layer 201 to define one or more lasers and / or one or more photodetectors in the resulting structure / chip / wafer, and oxidation causes a sacrificial layer 227 to at least partially surround the active layer. Further discussion of these structures, examples, etc., follows. Figure 7 Related content.

[0110] In some examples, the sacrificial layer 227 and the second layer 203 may be considered to substantially form a single layer or portion of the structure 240 (e.g., the sacrificial layer 227 includes the second layer 203 and a protective layer above and around the features in the PIC layer 201). In the following text, reference to the sacrificial layer 227 may also be understood to mean at least a portion of the second layer 203 and / or at least a portion of the material produced by the oxidation step (or other deposition step).

[0111] Now go to Figure 3A The figure shows structure 300 in cross-section, which includes a first layer 301, a second layer 303 and a sixth layer 311.

[0112] The first layer 301 is the PIC layer 301, and this designation will be used throughout the hereinafter. Similar to PIC layer 201, the PIC layer 301 of structure 300 can be formed of or include a photonic functional material. In some examples, the PIC layer 301 can include or be formed of a stack of photonic materials, such as indium phosphide or germanium, wherein one or more materials included in the stack can be used to define a laser and / or a photodetector (i.e., one or more active layers). For example, the PIC layer 301 can be formed of silicon, silicon nitride, polycrystalline silicon, silicon germanium, germanium, indium phosphide, gallium nitride, or silicon carbide (or each layer / material in the stack of photonic materials included in the PIC layer 301 can be formed of the same or different of these materials).

[0113] The second layer 303 can be an insulating layer or a sacrificial layer. In various examples, the second layer 303 can be formed of silicon oxide (i.e., it can be an oxide layer or a buried oxide). The sixth layer 311 can be a support layer 311 (e.g., a support wafer), and in various examples, this layer can be formed of crystalline silicon.

[0114] In the exemplary case where the PIC layer 301 is a silicon layer and the second layer 303 is an oxide layer, the structure 300 can be provided by a silicon-on-insulator (SOI) wafer, particularly a PIC-quality SOI wafer.

[0115] In the first step (PIC processing step), multiple features are defined by processing the PIC layer 301 to obtain... Figure 3B The structure 320 is shown. In various non-limiting examples, electron beam lithography or deep ultraviolet lithography, or next-generation lithography methods (such as X-ray lithography, focused ion beam lithography, quantum lithography, extreme ultraviolet lithography, and nanoimprint lithography), followed by etching, can be used to perform this process.

[0116] like Figure 3B As shown, the PIC layer 301 can be fabricated to form one or more optical structures 321 (wherein) Figure 3B One cross-sectional example is shown, but more can be formed in structure 320), at least one gap 323 (e.g., a first gap 323; these can alternatively be referred to as a first space, a first opening, a first groove, etc.), and at least one portion 325 (e.g., a first portion 325—wherein) Figure 3BTwo cross-sectional examples are shown, but more or fewer may be formed in structure 320; these may alternatively be referred to as first regions, first portions, first segments, etc., as well as other gaps (e.g., the gap between two first portions 325). Other features that may be formed in PIC layer 301 include gratings and / or waveguides (e.g., input waveguides and / or output waveguides). According to various examples, these features may be formed by etching PIC layer 301.

[0117] The limitation of the first gap 323 can be used in conjunction with the target Figure 2B The first gap 223 of the described structure 220 is similar. The definition of the optical structure 321 can be similar to that for... Figure 2B The optical structure 221 described is similar. Therefore, for the sake of brevity, the corresponding description is omitted here. Furthermore, as in conjunction with... Figure 2B As described in structure 220, although not in Figure 3B As shown, but the PIC layer 301 may also include an input waveguide arranged to provide light to the optical structure 321 (e.g., via coupling), and an output waveguide arranged to receive light from the optical structure 321 (e.g., via coupling). Alternatively, such waveguides may be provided at other locations on the structure. Other photonic features may also be formed in the PIC layer 301 if desired.

[0118] The first gap 323 may at least partially define the first portion 325. For example, in Figure 3B In the diagram, the first portion 325 is defined by the first gap 323 and the gap etched between the two first portions 325. In one example, besides as shown... Figure 3B In addition to the other gaps defined between the two first portions 325, a single first gap 323 may also be defined around the two first portions 325 in the form of a closed loop; here, Figure 3B The two first gaps 323 numbered in the middle are actually cross-sections of the same first gap 323. In other examples, multiple separate first gaps 323 are provided to define the first portion 325.

[0119] like Figure 3C As shown, the second step is to perform oxidation to protect the features formed in the PIC layer 301. As a result, structure 340 includes an oxide layer 327, or sacrificial layer 327 hereinafter, which at least partially surrounds the PIC layer 301 (specifically covering the optical structure 321, the first gap 323, and at least one first portion 325 to protect these features). In addition to oxidation, or as an alternative to oxidation, in some examples, silicon oxide material may be deposited and / or planarization may be performed to smooth the surface of the sacrificial layer 327. In various examples, further processing steps may include depositing silicon oxide material, such as PECVD oxide or TEOS.

[0120] In some examples, the sacrificial layer 327 and the second layer 303 may be considered to substantially form a single layer or portion of the structure 340 (e.g., the sacrificial layer 327 includes the second layer 303 and a protective layer above and around the features in the PIC layer 301). In the following text, reference to the sacrificial layer 327 may also be understood to mean at least a portion of the second layer 303 and / or at least a portion of the material produced by the oxidation step (or other deposition step).

[0121] In the third step, such as Figure 3D As shown, structure 340 is bonded to a MEMS structure (or a PIC wafer containing structure 340 repeated once or multiple times is bonded to a MEMS wafer) to obtain structure 360. This can be achieved by bonding sacrificial layer 327 to another structure including third layer 305, fourth layer 307, and fifth layer 309 (e.g., a MEMS chip / die or MEMS wafer). For example, the surface of sacrificial layer 327 (i.e., the surface of sacrificial layer 327 opposite to the surface of contact support layer 311) can be bonded or attached to third layer 305. Once sacrificial layer 327 is bonded to third layer 305, support layer 311 can be removed.

[0122] The third layer 305 is the MEMS layer 305, and this designation will be used throughout the following text. In various examples, the MEMS layer 305 may be formed of one or more of silicon, silicon nitride, polycrystalline silicon, silicon oxide, silicon germanium, germanium, silicon carbide, or gallium nitride, or may include these materials.

[0123] The fourth layer 307 can be an insulating layer or a sacrificial layer. In various examples, the fourth layer 307 can be formed of silicon oxide (i.e., it can be an oxide layer or a buried oxide).

[0124] The fifth layer 309 can be a support layer 309 (e.g., a support wafer), which in various examples can be formed of silicon, crystalline silicon, or glass.

[0125] In the exemplary case where MEMS layer 305 is a silicon layer and the fourth layer 307 is an oxide layer, another structure (e.g., a MEMS wafer) can be provided by a silicon-on-insulator (SOI) wafer, particularly a MEMS-quality SOI wafer.

[0126] Figure 3D The positions of the optical features in the structure 360 ​​shown appear to be related to Figure 2C The different positions of the optical features in structure 240 shown are accidental and unrelated. Figure 3D The locations shown are merely illustrative of the attachment of the MEMS wafer to structure 240. It should be understood that structure 240 is highly similar to structure 360 ​​and can be considered identical for the purposes of this disclosure.

[0127] In various examples, one or more active layers (not shown in the figures) are formed in structure 360, such as prior to the oxidation step and / or oxide material deposition step. For example, an active layer (e.g., a germanium or indium phosphide layer) may be formed on at least a portion of PIC layer 301 to define one or more lasers and / or one or more photodetectors in the final structure / chip / wafer, and oxidation causes a sacrificial layer 327 to at least partially surround the active layer. Further discussion of these features, examples, etc., follows. Figure 7 Related content.

[0128] therefore, Figures 2A to 2C A method for providing structure 240 using a DSOI wafer is described, while Figures 3A to 3D A method for providing structure 360 ​​using two SOI wafers is described. The resulting structure 360 ​​can be considered as a DSOI wafer. It should be understood that other methods providing structures similar to structure 240 or structure 360 ​​are included within the scope of this disclosure.

[0129] In both cases, it should be understood that, in various examples, the cross-sectional view may only show a portion of a larger wafer, where the structure (or similar structure) shown is repeated. For example, structure 240 or structure 360 ​​can be repeated on / on the entire wafer by fabricating individual portions of the wafer to define optical structures, first gaps, and first portions (and, for example, other gaps). Note that the optical structures may differ between different portions of the wafer (i.e., the individual structures on the wafer do not need to be exactly the same). Therefore, a wafer according to this disclosure may include multiple regions provided with fabricated structures, each of which includes one or more optical structures, gaps, and one or more portions.

[0130] Figure 7 This schematically illustrates the formation of one or more active layers or one or more active optical structures in structure 700.

[0131] Structure 700 can correspond to structure 240 or structure 360, such that structure 700 can be used as follows: Figures 2A to 2C The process shown is for providing structure 240 or as... Figures 3A to 3D The process shown is used to obtain structure 360.

[0132] Therefore, the following correspondences exist: the first layer 701 corresponds to the first layers 201 and 301; the second layer 703 corresponds to the second layers 203 and 303; the third layer 305 corresponds to the third layers 205 and 305; the fourth layer 707 corresponds to the fourth layers 207 and 307; the fifth layer 709 corresponds to the fifth layers 209 and 309; the optical structure 721 corresponds to the optical structures 221 and 321; the first gap 723 corresponds to the first gaps 223 and 323; the first part 725 corresponds to the first parts 225 and 325; and the sacrificial layer 727 (which may include the third layer 705) corresponds to the sacrificial layers 227 and 327 (which may respectively include the third layers 205 and 305). In other words, Figure 7 These features can each have the same properties, details, etc. as the corresponding features in Figure 2 or Figure 3. For example, the first layer 701 can be the PIC layer 701, while the third layer 705 can be the MEMS layer.

[0133] In structure 700, active structures 783 and 787 (which may also be referred to as active layers 783 and 787, or metal layers 783 and 787) have been formed. For example, active structure 783 is formed on optical structure 721, wherein an example of active structure 783 may be an on-chip photodetector, or used to form / provide an on-chip photodetector (e.g., for detecting light propagating in optical structure 721 and / or its properties), and may be formed of germanium. In another example, active structure 787 formed on another portion of PIC layer 701 may be a laser, or used to form / provide a laser, and may be formed of indium phosphide. Active materials used to form active structures 783 and 787, such as germanium and indium phosphide, may be provided in the form of layers on the first layer 701 or a portion thereof. For example, in the case where the active structure is a laser, active material layers may be provided to form a laser with multiple quantum wells.

[0134] Figure 7 The diagram also shows that structure 700 includes one or more metal components 781a, 781b, 781c, 785b, 785b for each active structure 783, 787, which are provided for driving the respective active structure (e.g., this may include supplying power to the respective active structure). For example, metal components 781a, 781b, 781c are provided for driving active structure 783, and metal components 785a, 785b are provided for driving active structure 787. It should be understood that, in various examples, each metal component may be connected to an electrical contact (…). Figure 7 (not shown in the diagram), such as N-doped or P-doped regions in structure 700. For example, N-doped or P-doped regions can be formed on a portion of PIC layer 701.

[0135] As mentioned above, Figures 4A to 4FA second method for providing a structure including a PIC layer and a MEMS layer is schematically shown via a cross-section of a portion of a wafer, wherein the structure may sometimes be referred to as a chip (or circuit) in this given example without limitation.

[0136] exist Figure 4A In the structure 400, the PIC layer 401 (corresponding to PIC layer 201, PIC layer 301 and / or PIC layer 701), the sacrificial layer 427 (corresponding to sacrificial layer 227, sacrificial layer 327 and / or sacrificial layer 727), the MEMS layer 405 (corresponding to MEMS layer 205, MEMS layer 305 and / or MEMS layer 705), another buried oxide or insulating layer 407 (corresponding to fourth layer 207, fourth layer 307 and / or fourth layer 707), and the support wafer 409 (corresponding to support wafer 209, support wafer 309 and / or support wafer 709). Furthermore, structure 400 may include (e.g., in PIC layer 401): optical structure 421 (corresponding to optical structure 221, optical structure 321 and / or optical structure 721), first gap 423 (corresponding to first gap 223, first gap 323 and / or first gap 723; these may also be considered evanescent gaps), and at least one portion 425 (e.g., first portion 425; corresponding to first portion 225, first portion 325 and / or first portion 725). Although not shown, one or more active optical structures may be included in structure 400 (e.g., such as...). Figure 7 (The structure shown).

[0137] Figure 4A The illustrated structure 400 may correspond to structure 240, structure 360, or structure 700, wherein optical structures have been exposed (e.g., a portion of PIC layers 201, 301, 701, such as optical structures 221, 321, 721); that is, a portion of the sacrificial layer 427 may be removed to expose the optical structures, resulting in the absence of a sacrificial layer at the corresponding location. In one example, this portion of the sacrificial layer 427 may be removed using liquid, vapor phase, or plasma etching methods. Furthermore, another portion 431 of the sacrificial layer 427 (e.g., the portion located between the first portions 425) may be removed to open or expose a portion of the MEMS layer 405, such as a portion of the surface of the MEMS layer 405.

[0138] In other words, it can be considered a combination Figures 4A to 4F The described approach begins with a structure (e.g., a hierarchical structure), such as Figure 2C Structure 240 Figure 3D 360 or structure Figure 7 The structure is 700. Advantageously, with the combination Figures 1A to 1DIn contrast to the first method described, the PIC layer and MEMS layer of this structure are bonded or attached together before the MEMS structure is formed in the MEMS layer.

[0139] Furthermore, as shown in structure 400, at least one coupling element 429 has been formed to mechanically couple the PIC layer 401 to the MEMS layer 405. It should be understood that, although in Figure 4A The cross-sectional example shows two coupling elements 429, but one or more coupling elements may be formed for this purpose in structure 400.

[0140] Regarding coupling elements 429, each coupling element 429 mechanically couples a first portion of the first portion 425 to the MEMS layer 405 (e.g., a portion of the MEMS layer below the respective first portion 405). In one example, the coupling element 429 is formed by opening a via down through the PIC layer 401 (i.e., in the first portion 425) to (and optionally into) the MEMS layer 405 (through the sacrificial layer 427) and filling the via with a material suitable for coupling.

[0141] The coupling element 429 enables attachment between the PIC layer 401 and the MEMS layer 405 by firmly filling the via with a material that adheres well to its via walls (such as CVD metal, electroplated metal, or LPCVD polycrystalline material). The coupling element 429 may also be referred to as a through-silicon via, pin, coupler, retainer, attachor, or bonder. The coupling element 429 can prevent or reduce misalignment between the MEMS layer 405 (e.g., the MEMS structure of the MEMS layer 405 fabricated in subsequent processes, described later below) and the PIC layer 401 (e.g., features such as optical structures 421 defined in the PIC layer 401).

[0142] The coupling element 429 may be formed, for example, from a low-resistivity material, a conductive material, a semiconductor material, or polysilicon. For example, the coupling element 429 may be formed using a mechanism for conformal deposition (e.g., in an open via) of a low-resistivity thin film.

[0143] In some examples of this disclosure, coupling element 429 also provides electrical coupling between PIC layer 401 and MEMS layer 405. This can provide several advantages in the resulting structure. For example, PIC layer 401 (or a portion thereof, such as a specific optical structure) and MEMS layer 305 (or a portion thereof, such as a structure to be described later) Figure 4EThe electrical connection between the MEMS structures in MEMS layer 405 described herein can prevent unwanted surface charge accumulation, which could otherwise damage the chip or negatively affect its function, and can ensure that the first part 425 and MEMS layer 405 maintain the same (or substantially the same) potential (voltage) that may be required for the correct MEMS function.

[0144] In various examples, as an alternative to providing electrical coupling between MEMS layer 405 and PIC layer 401 via coupling element 429, or in addition to coupling element 429 providing electrical coupling, separate electrical coupling elements or couplers (not shown) may be provided. For example, PIC layer 401 may include one or more capacitor plates arranged to capacitively couple with one or more capacitor plates included in MEMS layer 405; or PIC layer 401 may include one or more electrical contacts arranged to contact one or more electrical contacts included in MEMS layer 405 (e.g., through another via through sacrificial layer 427 or through some other connection). In another example, one or more portions of PIC layer 401 may be doped to provide electrical wiring to MEMS layer 405 or portions thereof.

[0145] In one example, coupling element 429 is formed of polysilicon or doped polysilicon (e.g., boron doping to form a p-type conductor). Here, the open vias can be filled with (doped) polysilicon to provide a mechanical anchor point between the first portion 425 of PIC layer 401 and a portion of MEMS layer 405, and to provide an electrical connection between PIC layer 401 and MEMS layer 405. Polysilicon can be an advantageous material for coupling element 429 when PIC layer 401 and / or MEMS layer 405 are silicon layers, as polysilicon has similar material properties to silicon and is therefore a good choice for connecting two silicon layers (or connecting two layers, at least one of which is silicon). Matching the coefficients of thermal expansion is particularly important to limit mechanical stresses that could slightly affect the first gap 423 or even cause the first portion 425 to warp.

[0146] Figure 4B It shows the relationship with Figure 4A The cross-section of the auxiliary structure 420 separated from the structure 400. The auxiliary structure 420 includes or is formed in a bulk wafer 431 (e.g., silicon).

[0147] Reference Figure 4C The bulk wafer 431 is processed to etch at least one cavity 435 (although) Figure 4CThe cross-sectional example shows a cavity 435, but it should be understood that multiple cavities can be etched in the bulk wafer 431. As seen below, at least one cavity 435 may be located at a position corresponding to a portion of the PIC layer 401 (e.g., the first portion 425) and / or a portion of the MEMS layer 405 (e.g., the portion exposed by removing portion 431 of the sacrificial layer 427), thereby providing a cavity 435 below the corresponding portion of the PIC and / or MEMS layer. Thus, the cavity 435 may allow displacement of the corresponding portion of the MEMS layer 405 (such as the portion used as a test block or otherwise attached to the first portion 425 of the PIC layer 401), and / or allow displacement of the first portion 425.

[0148] Once at least one cavity 435 is formed in the bulk wafer 431, oxidation is performed to obtain an oxide layer 433. Thus, the auxiliary structure 440 includes the bulk wafer 431 (i.e., the remaining portion of the bulk wafer 431), the oxide layer 433, and the cavity 435.

[0149] Now refer to Figure 4D It shows an example of a cross-section of structure 460 obtained by bonding structure 400 with auxiliary structure 440. Figure 4D The diagram shows structure 400 flipped and placed on auxiliary structure 440, but it should be understood that other orientations are also possible.

[0150] In various examples, structure 400 is fused-bonded to auxiliary structure 440. In other examples, structure 400 is eutectic-bonded (e.g., using gold-tin or gold-indium) to auxiliary structure 440. Furthermore, support layer 409, or at least a portion thereof (e.g., the portion above which will form a structure in MEMS layer 405 (see below),) is removed, as is another layer 407 (i.e., an insulator or other buried oxide layer 407), or at least a portion thereof (e.g., these layers / portions may be removed together).

[0151] As can be seen, the attachment aligns the cavity 435 with the exposed portion of the MEMS layer 405, and / or aligns the cavity 435 with the first portion 425 of the PIC layer 401. It should be understood that when structure 460 appears repeatedly on a wafer / the entire wafer (or a pair of bonded wafers: one structure 400 is repeated and the other structure 440 is repeated), the respective cavities 435 may be aligned with the corresponding portions of the MEMS layer (e.g., the portions corresponding to the MEMS structures, which will be described later) and / or the corresponding portions of the PIC layer 401 (e.g., the first portion 425).

[0152] Furthermore, structure 460 can be fabricated to form one or more elements 441, 443, and 445. In one example, this yields an electrical connector (or connecting pad) 445, and bonding ring elements 441, 443 (or bonding frame elements 441, 443, such as those that may be included in a bonding frame). In various examples, bonding ring elements 441, 443 correspond to a single bonding ring surrounding a portion of the surface of the MEMS layer 405. In other words, when viewed from above, structure 460 includes a bonding ring that surrounds a portion of the top of structure 460, for example, by surrounding a second gap 453. Thus, in this example, bonding ring elements 441, 443 may show different portions of the bonding ring's cross-section.

[0153] Figure 4E The following steps are illustrated for fabricating MEMS layer 405 to provide, define, or form at least one MEMS structure 451, resulting in structure 480. For example, deep reactive ion etching (DRIE) can be used to form the MEMS structure 451. The MEMS structure 451 may be a test / verification block (e.g., for inertial sensing as described above), a sheet or diaphragm (e.g., for a microphone, pressure sensor, or ultrasonic transceiver), or a resonant structure (e.g., for an oscillator or clock).

[0154] As can be seen, one or more second gaps 453 are opened in MEMS layer 405 (down to sacrificial layer 427) to define MEMS structure 451. In various examples, a single second gap 453 may be etched around MEMS structure 451 (e.g., in the form of a loop or other type of closed gap), while in other examples, multiple second gaps 453 are opened to define MEMS structure 451 (e.g., individual second gaps are opened and then these gaps are connected to form a gap around MEMS structure 451).

[0155] In various examples, the width of the second gap 453 can be greater than the width of the first gap 423. The second gap 453, defined in the MEMS layer 405, can be formed using processes such as deep ultraviolet lithography, which are less precise than the processes used to form the first gap 423 (e.g., extreme ultraviolet lithography, electron beam lithography, or other lithography methods). Advantageously, the formation of structure 480 allows for the use of such processes to form the second gap 453, while using more precise processes to form the optical structure 421 and the gaps in the PIC layer 401.

[0156] MEMS structure 451 is defined (e.g., formed in a location within MEMS layer 405) such that it includes a portion of MEMS layer 405 mechanically coupled to a first portion 425 of PIC layer 401 via coupling element 429. Therefore, MEMS structure 451 is decoupled from, or coupled to, the remaining portion of MEMS layer 405 only via an attachment system such as the anchor and spring system described herein. Furthermore, MEMS structure 451 is mechanically coupled to PIC layer 401.

[0157] MEMS structure 451 is movable (i.e., deflectable); for example, in response to a force acting on MEMS structure 451 or the entire structure 480, MEMS structure 451 will displace (e.g., deflect) from its initial position (e.g., at rest or in equilibrium). Furthermore, mechanical coupling to the first portion 425 means that displacement of MEMS structure 451 may result in displacement of the first portion 425 of the PIC layer. For example, the resulting displacement of the first portion 425 may be the same as, proportional to, or at least based on the displacement of MEMS structure 451.

[0158] It should be understood that the optical field characteristics of the optical structure 421 may be affected or influenced by the displacement of the MEMS structure 451, the first portion 425, the MEMS structure 451, and / or the first portion 425. For example, an optical field (e.g., an evanescent field) may extend from the boundary of the optical structure 421, such that the first portion 425 and / or the MEMS structure 451 are located within this optical field. As stated above regarding... Figures 1A to 1D The description states that this affects one or more optical field characteristics of the optical structure 421 (wherein, the proximity of the first part 425 may be related to...). Figure 1C The effect caused by proximity of MEMS structure 109 is similar. For example, in the case where optical structure 421 is an optical microresonator, the presence or movement of the bulk (i.e., the first part 425, MEMS structure 451) in the evanescent field of the microresonator may cause a shift in the resonant wavelength and / or a broadening or deepening of the optical resonance curve.

[0159] In some examples, optical microresonators can be provided in the PIC layer 401, on both sides (e.g., opposite sides) of the MEMS structure 451, with two or more optical microresonators interacting with each other. In various examples, two or more optical structures (e.g., optical microresonators) can be positioned relative to the MEMS structure 451 such that movement of the MEMS structure 451 toward one of the optical structures causes a corresponding movement of the MEMS structure 451 away from the other optical structure (thus allowing differential sensing). For example, a first optical microresonator can be defined in a first region of the PIC layer 401, located on the opposite side of a first gap 423, opposite to the side providing a first portion 425 with a corresponding coupling element 429; and a second optical microresonator can be defined in a second region of the PIC layer 401, located on the opposite side of another first gap 423 (or the same first gap 423 if the first gap 423 surrounds the first portion 425), opposite to the side providing another first portion 425 with another corresponding coupling element. The first and second optical microresonators are located on opposite sides of the MEMS structure 451. For example, when viewing structure 480 from above (such as from a direction perpendicular to the surface of PIC layer 401 or MEMS layer 405), the first optical microresonator can be seen located on one side of MEMS structure 451, while the second optical microresonator can be seen located on the opposite side of MEMS structure 451. Therefore, movement of MEMS structure 451 or the first portion 425 toward one of the first or second optical microresonators will result in its corresponding movement away from the other optical microresonator, or away from both the first and second optical microresonators, and vice versa. It should be understood that other examples may provide four optical microresonators in PIC layer 401, such as surrounding MEMS structure 451 at equal intervals.

[0160] Although not in Figure 4E As shown, but in some examples, MEMS structure 451 may also be coupled to another part of structure 480 (such as, coupled to another part of MEMS layer 405, or coupled to the bonding layer) via one or more elastically deformable coupling elements, such as (but not limited to) the springs mentioned above. Figure 4DThe described removal operation leaves a portion of the support layer 409 or other layer / insulating layer 407 above the MEMS layer 405 (or coupled to an external structure) to assist in suspending the MEMS structure 451 and the first portion 425 while allowing displacement of the MEMS structure 451, and also controls the displacement of the MEMS structure 451 (e.g., depending on the tension of the elastically deformable coupling element). Furthermore, other components (not shown) may be provided for controlling the displacement of the MEMS structure 451; for example, providing forces (e.g., driving forces, reaction forces, etc. provided via one or more electrodes) to restore the displaced MEMS structure 451 to its equilibrium position, or otherwise limiting the extent to which the MEMS structure 451 can be displaced without losing information about the forces acting on the MEMS structure 451. For example, the driving force of the aforementioned electrodes can be used to actively restore the MEMS structure 451 to equilibrium, thereby extending linearity and sensing range, and reducing or offsetting drift that may occur over time due to temperature fluctuations, bias, or nonlinearity under large displacements.

[0161] It should be understood that in some examples, when multiple optical structures are provided around the MEMS structure 451 in the PIC layer 401, the MEMS structure 451 can be attached using a spring and anchoring system to a portion of a layer retained around the MEMS layer 405 (e.g., another portion of the MEMS layer 405, support layer 409, or insulating layer 407) (i.e., the portion not removed from the area of ​​the MEMS layer 405 around which the MEMS structure 451 is to be formed), such that the MEMS structure is suspended between the optical structures and can be elastically displaced from its rest or initial position. Furthermore, other components / elements described above (e.g., electrodes, actuators, etc.) can also be provided in conjunction with springs to assist in restoring the MEMS structure 451 to equilibrium, limiting the extent to which the MEMS structure 451 can move between the optical structures, and / or achieving any other purpose / effect mentioned above for such elements / components. See also... Figure 1D It shows an example of a spring and anchor system for coupling MEMS structures to portions surrounding the MEMS layer.

[0162] exist Figure 4E In the cross-sectional example, structure 480 shows a single MEMS structure 451, but it should be understood that more than one (i.e., other) MEMS structures may be provided in MEMS layer 405. For example, where structure 480 is repeated on / on the entire wafer (or a pair of bonded wafers), multiple MEMS structures 451 may be defined, each MEMS structure located at a position corresponding to a respective feature (e.g., first portion 425), coupling element 429, and / or cavity 435 of PIC layer 401.

[0163] Figure 4FStructure 490, obtained by processing structure 480, is shown. This processing may include: removing at least a portion of the sacrificial layer 427 between the first portion 425 and the MEMS structure 451, and between the first portion 425 and the first gap 423; and / or removing a portion of the sacrificial layer 427 to allow communication between the first gap 423 and the second gap 453 (i.e., such that no material, such as the material forming the sacrificial layer 427, exists between one or more first gaps 423 and one or more second gaps 453). This has the effect of releasing the MEMS structure 451 from the sacrificial layer; for example, the MEMS structure 451 can therefore move freely (or move based on constraints imposed by a spring and anchor system or similar structure attaching the MEMS structure 451 to another portion of the MEMS layer 405), and the first portion 425 can also move freely via the coupling element 429.

[0164] In some examples, a portion of the sacrificial layer 427 can remain between the first portion 425 and the MEMS structure 451, provided that the MEMS structure 451 and the first portion 425 are released from the surrounding portion of the sacrificial layer 427; for example, this surrounding portion may be a portion of the sacrificial layer 427 between the first portion 425 and other portions of the PIC layer 401 (such as the optical structure 421 and / or the portion located on the side of the first gap 423 opposite to the first portion 425). In this case, the sacrificial layer 427 remaining between the first portion 425 and the MEMS structure 451 mechanically couples the first portion 425 and the MEMS structure 451 together, thereby helping to strengthen the mechanical coupling between the first portion 425 of the PIC layer 405 and the MEMS structure 451 in addition to the coupling element 429.

[0165] As discussed elsewhere in this document, the displacement of MEMS structure 451 and / or the first portion 425 can affect the optical field characteristics of optical structure 421, thereby enabling various functions. For example, structure 490 can be used in accelerometers, gyroscopes, or other inertial sensors. Other applications exist for chips such as or containing structure 490; for example, as optoelectronic or optomechanical pickups for reading out MEMS devices such as MEMS structure 451 or its displacement, replacing solutions that use capacitive readout in devices such as microphones and timing oscillators. Optical pickups offer significant advantages over conventional capacitive readouts because they are (at least substantially) unaffected by stray electrical noise or interference, while maintaining at least comparable sensitivity in detection.

[0166] In one example, this process can be performed using an etching process, such as vapor phase etching. For example, hydrogen fluoride (HF) vapor phase etching can be used to etch the sacrificial layer 427 around the MEMS structure 451. In this case, the vapor phase HF isotropic etching (similar etching rates in the vertical and horizontal directions) may result in portions of the sacrificial layer 427 above and below the portion of the PIC layer 401 (e.g., as shown in the image). Figure 4F As shown, the portion surrounding the end of the optical structure 421 is removed. In other words, HF vapor etching can be controlled to only partially release a portion of the optical structure 421. Holes may be present in the MEMS structure 451 to influence the removal rate of the sacrificial layer beneath and around it. Furthermore, HF vapor etching can remove portions of the oxide layer 433, such as the portion around the cavity 435. Additionally, the sacrificial layer 427 surrounding the first portion 425 may also be removed.

[0167] In some examples, it can be considered Figure 4F The fabrication process shown is to expose the first gap 423 in the PIC layer 401. This allows the MEMS structure 451 and the first portion 425 to be released accordingly.

[0168] The resulting structure 490 can be considered as a chip, circuit, or IC including a PIC layer 401 (including optical structures / features) and a MEMS layer 405 (including MEMS structures / features). Therefore, through... Figures 4A to 4F The steps shown are as follows, and refer to Figures 2A to 2C , Figures 3A to 3D and / or Figure 7 This paper presents a second method for providing / producing / manufacturing such structures (i.e., chips, circuits, ICs, etc.).

[0169] In an optional further step, a cap wafer (not shown) may be bonded over structure 490. For example, bonding rings included in the cap wafer (e.g., formed on its surface) may be bonded to bonding rings corresponding to bonding ring elements 441, 443. This may seal (e.g., vacuum seal, hermetic seal) the space beneath the cap wafer, which may include cavity 432, first gap 423, and second gap 453.

[0170] The second method described above offers several advantages. According to various examples of the second method, it allows for a small gap (e.g., the first gap 423) between the MEMS features and the PIC device features, for example, due to the smaller lithography nodes that can be used in the process fabricating the PIC layer 401 or in the PIC foundry providing the wafer with the PIC layer 401. Furthermore, according to various examples of the second method, by utilizing a DSOI wafer, all crystalline silicon can be used, thus providing better layer dimensional accuracy and mechanical robustness. Moreover, according to various examples of the second method, since the MEMS features and the laser cavity are created within the second bulk wafer, it allows for increased flexibility (relatively speaking) in the variation of the depth of the MEMS features and the laser cavity.

[0171] Now combine Figures 5A to 5H A third method is given for providing a structure comprising a PIC layer (including optical structures / features) and a MEMS layer (including MEMS structures / features), illustrated schematically via a cross-section of a portion of a wafer to show the progress of the method. In the following description of the given examples, the structure may sometimes be referred to non-limitingly as a chip or circuit. It should be understood that... Figures 5A to 5H The various features shown can optionally be shared with Figures 2A to 2C , Figures 3A to 3D , Figures 4A to 4F and / or Figure 7 The corresponding features shown in any of the attached figures have the same or similar properties.

[0172] Figure 5A Structure 500 is shown, which includes a first layer 501, a second layer 503, a third layer 505, a fourth layer 507, and a fifth layer 509. The first layer 501 is the PIC layer 501, and this designation will be used throughout the following text. The third layer 505 is the MEMS layer 505, and this designation will be used throughout the following text.

[0173] The PIC layer 501 may include or be formed of a photonic functional material. In some examples, the PIC layer 501 may include or be formed of a stack of photonic materials, such as indium phosphide or germanium, wherein one or more materials included in the stack can be used to define a laser and / or a photodetector. The MEMS layer 505 may include or be formed of a crystalline or polycrystalline material (such as silicon or glass). If it is silicon, dopants may be added to achieve semiconductor or conductive properties. In various examples, both the MEMS layer 505 and the PIC layer 501 may be layers of silicon, silicon-germanium, germanium, indium phosphide, gallium nitride, or silicon carbide. Alternatively, the MEMS layer 505 and the PIC layer 501 may each be formed of the same or different of the following materials: silicon, silicon nitride, polycrystalline silicon, silicon-germanium, germanium, indium phosphide, gallium nitride, or silicon carbide.

[0174] The second layer 503 and the fourth layer 507 can be insulating layers and / or sacrificial layers. In various examples, one or both of the second layer 503 and the fourth layer 507 can be silicon oxide layers (i.e., oxide layers or buried oxides).

[0175] The fifth layer 509 can be a support layer 509 (e.g., a support wafer). In one example, the support layer 509 is formed of crystalline silicon.

[0176] In the exemplary case where the PIC layer 501 and MEMS layer 505 are silicon layers and the second layer 503 and the fourth layer 507 are buried oxide layers, the structure 500 can be provided by a double silicon-on-insulator (SOI) wafer (DSOI wafer) with a buried cavity.

[0177] As shown in the figure, cavity 511 is formed in support layer 509 of structure 500. This cavity can be formed in support layer 509 by conventional methods (e.g., within the body region), and its purpose is similar to that of other cavities described herein.

[0178] It should be understood that Figure 5A The illustrated structure 500 can be repeated multiple times on / through the entire wafer (e.g., a predetermined number based on manufacturing capabilities and / or design). Therefore, a wafer provided via the third method of this disclosure can include multiple cavities in the body layer 509, and the structure 500 can be arranged accordingly. A similar description also applies. Figures 5B to 5H The structures shown are because these structures (showing their cross-sections from which the complete structure (e.g., a three-dimensional structure) can be repeated on a larger wafer.

[0179] The first step involves machining (PIC machining) the structure 500 to obtain... Figure 5B The structure 510 is shown. In various non-limiting examples, this process can be performed using electron beam lithography or deep ultraviolet lithography, or next-generation lithography methods (such as X-ray lithography, focused ion beam lithography, quantum lithography, extreme ultraviolet lithography, and nanoimprint lithography), followed by etching.

[0180] In particular, such as Figure 5B As shown, the PIC layer 501 can be processed to form: at least one optical structure 521 (wherein, Figure 5B One cross-sectional example is shown, but more can be formed in structure 510), at least one gap 523 (e.g., a first gap 523; these may alternatively be referred to as a first space, a first opening, a first groove, etc.), and at least one portion 525 (e.g., a first portion 525—wherein) Figure 5BOne cross-sectional example is shown, but more can be formed in structure 510; these may be alternatively referred to as first regions, first portions, first segments, etc., as well as other gaps (e.g., gaps on the side of optical structure 521 not defined by the first gap 523). Other features that can be formed in PIC layer 501 (optionally) include other portions 529, gratings, and / or waveguides (e.g., input waveguides and / or output waveguides). According to various examples, these features can be formed by etching PIC layer 501. Of course, in addition to the features described above, additional photonic features may also be included in PIC layer 501 (e.g., formed therein).

[0181] The first gap 523 can have the characteristics of targeting Figure 1C The defined distance d is a similar dimension. For example, the width of the first gap (i.e., the wall-to-wall distance) can be less than 1 μm, and in some examples, this gap is less than 500 nm. The width of the first gap can depend on the limits of the photolithography performed before etching the first gap. The example accuracy of this process is ±50 nm, but it should be understood that this may vary depending on the photolithography (or other) method used.

[0182] The first gap 523 may at least partially define the first portion 525. It should be understood that a single first gap 523 may be defined in the PIC layer 501, wherein the first gap 523 is a closed loop surrounding at least one first portion 525. In this case, Figure 5C The two first gaps 523 shown illustrate different portions of the same first gap 523, providing a cross-section of the first gap 523. In other examples, multiple first gaps 523 may be formed to define at least one first portion 525 in the PIC layer 501. For example, multiple first gaps 523 may be defined separately and then joined together to define at least one first portion 525. Alternatively, individual first gaps 523 may be defined to the edge of the wafer or structure 520 to define at least one first portion 525.

[0183] Optical structure 521 can have a corresponding light field, similar to that for... Figures 1A to 1D The optical field defined by optical structure 521. For example, optical structure 521 may be a microresonator (e.g., a whispering-gallery mode resonator), and the optical field may correspond to the evanescent field of light originating from the microresonator. Although not shown, PIC layer 501 may also include an input waveguide arranged to provide light to optical structure 521 (e.g., via coupling), and an output waveguide arranged to receive light from optical structure 521 (e.g., via coupling). Alternatively, if such waveguides are included, they may be provided at other locations on the structure.

[0184] like Figure 5CAs shown in structure 520, the second step is to perform oxidation to protect the features formed in the PIC layer 501. Thus, structure 520 includes an oxide layer 527 (hereinafter referred to as sacrificial layer 527) that at least partially surrounds the PIC layer 501 (specifically covering the optical structure 521, the first gap 523, and at least one first portion 525 to protect these features). In addition to oxidation, or as an alternative to oxidation, in some examples, silicon oxide material may be deposited and / or planarization may be performed to smooth the surface of the sacrificial layer 527. In various examples, the second process step may include depositing silicon oxide material, such as PECVD oxide or tetraethyl orthosilicate (TEOS), on the PIC layer 501.

[0185] In various examples, one or more active layers (not shown in the figures) are formed in structure 520, such as prior to an oxidation or deposition step. For example, an active layer (e.g., a germanium or indium phosphide layer) may be formed on at least a portion of PIC layer 501 to define one or more lasers and / or one or more photodetectors in the resulting structure / chip / wafer, and oxidation causes a sacrificial layer 527 to at least partially surround the active layer. Examples of this feature formation can be found in [reference]. Figure 7 .

[0186] In some examples, the sacrificial layer 527 and the second layer 503 may be considered to substantially form a single layer or portion of the structure 520 (e.g., the sacrificial layer 527 includes the second layer 503, and a protective layer above and around the feature). In the following text, reference to the sacrificial layer 527 may also be understood to refer to at least a portion of the second layer 503 and / or at least a portion of the material produced by the oxidation step.

[0187] like Figure 5D As shown, the third step is to remove a portion of the sacrificial layer 527 to expose the MEMS layer 505 (e.g., a portion of the surface of the MEMS layer 505) through the first gap 523. Alternatively, as shown, a portion of the sacrificial layer 527 at either end of the structure 530 can also be removed to expose a larger portion of the surface of the MEMS layer 505. For example, as shown later below, a laser or laser die can be provided in the space or recess formed on the right side of the optical structure 521 where a portion of the sacrificial layer 527 has been removed, while an electrode 531 can be provided on the left side of the other portion 529. The removal of the sacrificial layer can be performed using conventional etching processes, such as etching processes capable of providing the resolution required to etch narrow features, such as within the first gap 523 (in some examples, its width is shown as 100 nm to 500 nm, with a tolerance of ±50 nm).

[0188] At this stage, one or more electrodes 531 and bonding ring elements 533, 535 may be formed, for example, by metallization, thereby providing these features to structure 530. In various examples, bonding ring elements 533, 535 correspond to a single bonding ring surrounding a portion of the surface of the sacrificial layer 527. In other words, when viewed from above, structure 530 includes a bonding ring that surrounds a portion of the top of structure 530, such as by surrounding a first gap 523 (i.e., a gap in the sacrificial layer 527 defined to expose a portion of the surface of the MEMS layer 505 through the first gap 525). Thus, in this example, bonding ring elements 533, 535 show different portions of the cross-section of the bonding ring.

[0189] Optionally, a recess can be formed in the MEMS layer 505 on the side of the optical structure 521, for example, at a location where a portion of the sacrificial layer 527 has been removed to expose the MEMS layer 505. This recess is located in... Figure 5E The structure 540 is shown, in which pads 541 (or supports 541) (e.g., formed of AuSn) are formed, and optionally with alignment targets. The purpose of this recess may be to accommodate a laser die (e.g., attached to pad 541). Of course, in some examples, such a recess is not necessary, as etching away a portion of the sacrificial layer can provide sufficient space for mounting the laser die, depending on the properties of the laser (e.g., size). Alternatively, removing this portion of the sacrificial layer (i.e., the portion of the optical structure 521 not defined by the first gap 523) is itself optional, particularly when not using a laser die to provide light to the optical structure 521. It should be understood that other methods of coupling light into the optical structure 521 are conceivable, methods that do not involve mounting the laser die near the sidewalls of the optical structure 521. If an alignment target is included, it can be used to align the laser die with the optical structure 521.

[0190] Reference Figure 5FIn structure 550, the MEMS structure 551 is defined within the MEMS layer 505 by removing a portion of the MEMS layer 505 on either side of the MEMS structure 551 to define at least one second gap 553. For example, a single second gap 553 may be formed around the MEMS structure 551 to release it from the remainder of the MEMS layer 505, or multiple second gaps 553 may be formed around the MEMS structure 551 and then interconnected to define the MEMS structure 551. In one example, DRIE (Device Detailed Interchange) may be used to fabricate the MEMS layer 505 to form the MEMS structure 551. The second gap 553 may be formed through a first gap 523, thereby constraining the width of the second gap 553. The second gap 553 may communicate with the first gap 523, and there is no partial sacrificial layer 527 between the first gap 523 and the second gap 553. Furthermore, it should be understood that an HF vapor phase process can be performed to release (at least partially) the MEMS structure 551 (e.g., to release the MEMS structure 551 from the fourth layer 507, which could also release the MEMS structure 551 from the support layer 509). Although Figure 5F As not shown, but it should be understood that a portion of the fourth layer 507 may remain beneath (e.g., near) the MEMS structure 551 – this is because the HF gas phase may cut laterally and longitudinally, thus, for example, a portion of the fourth layer 507 may be removed between the MEMS structure 551 and the support layer 509, but other portions of the fourth layer 507 may remain between the MEMS structure 551 and the support layer 509. However, even if these portions of the fourth layer 507 remain, the MEMS structure 551 will still be released.

[0191] As can be seen, the MEMS structure 551 is effectively coupled (e.g., mechanically coupled) to the first portion 525 of the PIC layer 501 via the insertion portion of the sacrificial layer 527. The MEMS structure 551 is suspended above the cavity 511 and can move freely (e.g., referring to the description of the MEMS structure 451 related to the movement of the MEMS structure), and the coupled first portion 525 moves freely accordingly with the MEMS structure 551. As can be understood from the foregoing disclosure, this will affect the optical field characteristics of the optical structure 521, thereby enabling various functions.

[0192] It should be understood that, in various examples, a portion of the sacrificial layer 527 between the first portion 525 and the MEMS structure 551 can be considered as at least one coupling element mechanically coupling the first portion 525 to the MEMS structure 551. In other words, this portion of the sacrificial layer 527 acts as a coupling element between the first portion 525 and the MEMS structure 551. Figure 4A ,and Figures 4D to 4F It functions similarly to the coupling element 429 in the diagram, and therefore can be considered as a coupling element.

[0193] For example, when structure 550 (or structures 560, 570 described later) is used in an inertial sensor, or when structure 550 (or structures 560, 570 described later) is used for inertial sensing and wherein optical structure 521 is an optical resonator, changes in the optical field characteristics (e.g., optical resonance) of the optical microresonator can be measured to identify corresponding or associated displacements of MEMS structure 551 (which may be a test block) and / or the first portion 525 (which may be considered part of the test block), thereby allowing the measurement or determination of the corresponding inertial force acting on structure 550 or the inertial sensor. Therefore, structure 550 can be used in accelerometers, gyroscopes, or other inertial sensors.

[0194] In various examples, additional optical microresonators (not shown) may be provided on the opposite side of the MEMS structure 551 (i.e., on the opposite side of the first portion 525 of the PIC layer 501 coupled to the MEMS structure 551). This may be similar to the above description regarding... Figure 4E The described example has two optical microresonators, where movement of the MEMS structure 551 (or the first portion 525) toward one optical structure causes it to move away from the other optical structure accordingly. Furthermore, in various examples, four optical microresonators may be provided at equidistant locations around the MEMS structure 551 or the first portion 525 within the PIC layer 501. Details of this arrangement of multiple optical structures around the MEMS structure 551 within the PIC layer 501 can be found in the above description of... Figures 4A to 4F The details given regarding the multiple optical structures surrounding MEMS structure 451 within PIC layer 401 are identical. Therefore, the above description of... Figures 4A to 4F The features of these arrangements described are also relevant here and incorporated. Figures 5A to 5H In the description.

[0195] Other uses exist for chips or circuits such as or containing structure 550; for example, as optoelectronic or optomechanical pickups to read out MEMS devices (such as MEMS structure 551 or its displacement), for example, replacing solutions that use capacitive readout in devices such as microphones and timing oscillators.

[0196] In some examples, MEMS structure 551 is consistent with any other MEMS structure defined herein—for example, it can be an inertial test block (e.g., for inertial sensing as described above), a thin plate or diaphragm (e.g., for a microphone, pressure sensor, or ultrasonic transceiver) or a resonant structure (e.g., for an oscillator or clock).

[0197] Although not shown, structure 550 may also include one or more electrical couplers for electrically coupling MEMS structure 551 to a portion of PIC layer 501 (such as first portion 525). For example, one or more portions of PIC layer 501 may be doped to provide electrical wiring to MEMS layer 505 or portions thereof (e.g., MEMS structure 551).

[0198] In a further operation, a portion of the sacrificial layer 527 is removed from around the sidewalls of one or more features in the PIC layer 501. This process may include using vapor-phase HF etching to remove a portion of the sacrificial layer 527. For example, as... Figure 5F As shown, by removing at least a portion of the sacrificial layer 527, one or more sidewalls of the optical structure 521 (including sidewall 521a, shown herein to provide an example of a sidewall as referred to herein), the first portion 525, and other portions 529 are exposed. In this case, a sidewall (such as sidewall 521a of the optical structure 521) refers to a PIC feature perpendicular to the longitudinal direction of the PIC layer 501 (i.e., the longitudinal direction is the direction along the wafer including structure 550, as indicated by...). Figure 5F The 'x' in the figure represents the surface, or the surface parallel to. Figure 5F The surface in the direction indicated by 'y'. For example, the sidewall 521a of the optical structure 521 can be exposed to allow light to couple into the optical structure 521 (e.g., via an input waveguide (not shown) or mounted on the optical structure 521). Figure 5H (as shown in the diagram) near the laser die. For example, a portion of the sacrificial layer 527 can be removed to expose the sidewalls of the optical structure 521 (the side opposite to sidewall 521a) and the opposing sidewalls of the first portion 525, thereby enhancing or otherwise enabling the interaction between these components. That is, the different effects that displacement of the first portion 525 can have on the optical field characteristics of the optical structure 521 depend on whether any sacrificial layer is present between the corresponding sidewalls of these features in the PIC layer 501.

[0199] Now refer to Figure 5GThis illustrates the result of further optional steps in attaching or bonding a cap wafer 561 to structure 550, as shown in structure 560. The cap wafer 561 may include contacts 563 and 565 for bonding to corresponding contacts on the sacrificial layer 527, such as bonding ring elements 533, 535. In one example, contacts 563 and 565 correspond to portions of the same bonding ring on the cap wafer 561, for example, when bonding ring elements 533, 535 represent portions of the same bonding ring. For example, a single bonding ring (e.g., along the periphery of the cap wafer 561) may be provided on the cap wafer 561, its size and shape corresponding to the bonding ring provided on the sacrificial layer 527. Thus, the cap wafer 561 is bonded to structure 550 by securing or bonding the bonding ring on the cap wafer 561 to the bonding ring on the sacrificial layer 527. This can be done via metallic bonding (e.g., eutectic bonding, thermoforming bonding, etc.).

[0200] The cap wafer 561 is used to seal (e.g., in the case of an inertial sensor or resonator, to form a vacuum seal) the space comprising cavity 511, a first gap 523, and a second gap 553; that is, the space beneath the cap wafer 561. In some examples, the vacuum will be formed during the bonding step (or at the required operating pressure of the device).

[0201] Optionally, such as Figure 5H As shown, a laser die 571 can be provided in a recess at the end of structure 570; for example, in a recess formed by removing a portion of sacrificial layer 527 and / or a portion of MEMS layer 505. However, including a laser die in structure 570 is not mandatory. Furthermore, in some examples, the laser (e.g., laser die 571) can be placed / located on PIC layer 501, such as on the top layer of PIC layer 501, and this can be an alternative to forming a recess and providing the laser die in the recess. For example, the laser can be provided on a portion of the surface of PIC layer 501 opposite the surface facing MEMS layer 505, where sacrificial layer 527 has been removed from around this portion of the surface of PIC layer 501. In various examples, a photodetector can be placed in the recess instead of or separately from the laser die 571, wherein the photodetector is optically coupled to optical structure 521 via a surface of optical structure 521 facing the recess.

[0202] Although Figures 5A to 5H Not shown, but one or more coupling elements may be provided between the first portion 525 and the MEMS structure 551 to mechanically couple the first portion 525 of the PIC layer 501 to the MEMS structure 551, and optionally electrically couple it. The aforementioned coupling elements may be formed at any stage of the above method, such as... Figure 5GAs shown, this may be except after the cap wafer 561 is attached. For example, before the features in PIC layer 501 are defined ( Figure 5B A coupling element can be formed by opening a via in the PIC layer 501 (i.e., in the first portion 525) down to (and optionally into) the MEMS layer 505 (through the sacrificial layer 503) and filling the via with a suitable coupling material. This via can be aligned with the region in the MEMS layer 505 that defines the MEMS structure 551. In another example, the coupling element can be formed after oxidation ( Figure 5C ) or after removing part of the sacrificial layer 527 ( Figure 5D A via is formed, opening in the sacrificial layer 527 (upper part), passing through the PIC layer 501 and down through the sacrificial layer 527 (lower part) to the MEMS layer 505. In another example, coupling elements can be defined in the MEMS structure 551 ( Figure 5F Formed before or after. If provided, the coupling element can be used with respect to... Figures 4A to 4F Any coupling element 429 described is provided in a similar manner (e.g., having a design for...). Figures 4A to 4F (Any one or more features / details of the described coupling element 429). For example, the coupling element may provide mechanical and / or electrical coupling between the PIC layer 501 (or a portion thereof) and the MEMS layer 505 (or a portion thereof).

[0203] MEMS structure 551 can be coupled to another part of structure 570, such as a portion of MEMS layer 505, fourth layer 507, or fifth layer 509, enabling movement of MEMS structure 551 and its coupled first portion 525. For example, a spring and anchor system, such as those described elsewhere herein (e.g., reference...), can be provided. Figure 1D ( ), to suspend the MEMS structure 551 while allowing the MEMS structure 551 to be displaced.

[0204] The third method described above offers several advantages. According to various examples of the third method, by utilizing DSOI wafers, all crystalline silicon can be used, thus providing better layer dimensional accuracy and mechanical robustness.

[0205] Now combine Figures 6A to 6F A fourth method for providing structures (i.e., chips, circuits, ICs, etc.) including a PIC layer (including optical structures / features) and a MEMS layer (including MEMS structures / features) is presented. The accompanying figures schematically illustrate the process of this method via a cross-section of a portion of a wafer. It should be understood that... Figures 6A to 6F The various features shown can optionally be shared with Figures 2A to 2C , Figures 3A to 3D , Figures 4A to 4F , Figures 5A to 5H and / or Figure 7 The corresponding features shown are the same or similar attributes.

[0206] Figure 6A A cross-section of structure 600 is shown, which includes a first layer 601, a second layer 603, and a third layer 609.

[0207] The first layer 601 is the PIC layer 601, and this designation will be used throughout the hereinafter. Similar to PIC layers 201 and 501, the PIC layer 601 of structure 600 can be formed of or include a photonic functional material. In some examples, the PIC layer 601 can include or be formed of a stack of photonic materials, such as indium phosphide or germanium, wherein one or more materials included in the stack can be used to define a laser and / or a photodetector. For example, the PIC layer 601 can be formed of silicon, silicon nitride, polycrystalline silicon, silicon germanium, germanium, indium phosphide, gallium nitride, or silicon carbide.

[0208] The second layer 603 may be an insulating layer and / or a sacrificial layer. In various examples, the second layer 603 may be formed of silicon oxide (i.e., it may be a buried oxide layer). The third layer 609 may be a support layer 609 (e.g., a support wafer), and in various examples, this layer may be formed of crystalline silicon.

[0209] In the exemplary case where the PIC layer 601 is a silicon layer and the second layer 603 is a buried oxide layer, the structure 600 can be provided by a silicon-on-insulator (SOI) wafer, particularly a PIC-quality SOI wafer.

[0210] The first step involves machining structure 600 (PIC machining) to obtain... Figure 6B The structure 610 is shown. In various non-limiting examples, this process can be performed using electron beam lithography or deep ultraviolet lithography, or next-generation lithography methods (such as X-ray lithography, focused ion beam lithography, quantum lithography, extreme ultraviolet lithography, and nanoimprint lithography), followed by etching.

[0211] In particular, such as Figure 6B As shown, the PIC layer 601 can be processed to form: at least one optical structure 621 (wherein, Figure 6B One cross-sectional example is shown, but more can be formed in structure 610), at least one gap 623 (e.g., a first gap 623; these can alternatively be referred to as a first space, a first opening, a first groove, etc.), and at least one portion 625 (e.g., a first portion 625—wherein) Figure 6BOne cross-sectional example is shown, but more can be formed in structure 610; these can be alternatively referred to as a first region, first portion, first segment, etc., other gaps (e.g., a gap on the side of optical structure 621 not defined by the first gap 623), and optionally at least one other portion 611, 613 (which may be used to provide other components, as described below). Other features that can be formed in PIC layer 601 (optionally) include gratings and / or waveguides (e.g., input waveguides and / or output waveguides). According to various examples, these structures can be formed by etching PIC layer 601.

[0212] The first gap 623 can have the characteristics of targeting Figure 1C The defined distance d is a similar dimension. For example, the width of the first gap (i.e., the wall-to-wall distance) can be less than 1 μm, and in some examples, this gap is less than 500 nm. The width of the first gap may depend on the limits of the photolithography performed before etching the first gap. The example accuracy of this process is ±50 nm, but it should be understood that this may vary depending on the photolithography (or other) method used. In some examples, the width of the first gap is between 100 nm and 200 nm.

[0213] The first gap 623 may at least partially define the first portion 625. It should be understood that a single first gap 623 may be defined within the PIC layer 601, and this first gap 623 may be a closed loop or similar structure surrounding at least one first portion 625. In this case, Figure 6C The two first gaps 623 shown illustrate different portions of the same first gap 623, providing a cross-section of the first gap 623. In other examples, multiple first gaps 623 may be formed to define at least one first portion 625 in the PIC layer 601. For example, multiple first gaps 623 may be defined separately and then connected together to define at least one first portion 625. Alternatively, individual first gaps 623 may be defined to the edge of the wafer or structure 620 to define at least one first portion 625.

[0214] Optical structure 621 can have a corresponding light field, similar to that for... Figures 1A to 1D Definition of optical structure 131. For example, optical structure 621 may be a microresonator (e.g., a whispering-gallery mode resonator), and the optical field may correspond to the evanescent field of light originating from the microresonator. Although not shown, PIC layer 601 may also include an input waveguide arranged to provide light to optical structure 621 (e.g., via coupling), and an output waveguide arranged to receive light from optical structure 621 (e.g., via coupling). If such a waveguide is included, it may be provided at other locations on the structure.

[0215] like Figure 6C As shown, the second step is to perform oxidation to protect the features formed in the PIC layer 601. Thus, structure 620 includes an oxide layer 627, or sacrificial layer 627 as described below. After oxidation, the sacrificial layer 627 may at least partially surround the PIC layer 601 (specifically, cover the optical structure 621, the first gap 623, and at least one first portion 625 to protect these features). In addition to oxidation, or as an alternative to oxidation, in some examples, silicon oxide material may be deposited and / or planarization may be performed to smooth the surface of the sacrificial layer 627. In various examples, the second process step may include depositing silicon oxide material, such as PECVD oxide or tetraethyl orthosilicate (TEOS), on the PIC layer 601.

[0216] In some examples, the sacrificial layer 627 and the second layer 603 may be considered to substantially form a single layer or portion of the structure 620 (e.g., the sacrificial layer 627 includes the second layer 603, and a protective layer above and around the feature). In the following text, reference to the sacrificial layer 627 may also be understood to refer to at least a portion of the second layer 603 and / or at least a portion of the material produced by the oxidation step.

[0217] After oxidation, a step is performed to remove a portion of the sacrificial layer 627 from above at least a portion of the PIC layer 605, as follows: Figure 6C The structure 620 is shown in the diagram. Figure 6C The diagram shows that the sacrificial layer 627 is removed from above the portion of the first portion 625 and from above the other portions 611, i.e., missing. It should be understood that the sacrificial layer 627 may be removed from above the additional portion of the PIC layer 601, or not from above the other portions 611; but advantageously, it is removed from above the first portion 625.

[0218] Figure 6D The diagram illustrates a structure 630 obtained by performing a step of growing or depositing material over the exposed portions / enclosed portions of the sacrificial layer and PIC layer 601. As shown, a first bulk or material layer (a combination thereof is identified as 651, discussed further below) is formed on the first portion 625, and a second bulk 637 or material layer is formed on the sacrificial layer 627. A third bulk or material layer may also be formed on other portions 611.

[0219] In various examples, it should be understood that the material grown over a portion of PIC layer 601 (e.g., on the first portion 625) can be considered as providing or forming at least one coupling element between the first portion 625 and the bulk formed by the grown / deposited material. That is, an attachment or coupling (e.g., molecular bond) may exist between the first portion 625 of PIC layer 601 and the deposited material—this can be considered as at least one coupling element (similar to...). Figure 4A , Figures 4D to 4F (Coupled element 429 in the middle).

[0220] For example, in the case where the PIC layer 601 is silicon and the sacrificial layer 627 is an oxide (e.g., silicon oxide), epitaxial silicon can be grown or deposited (e.g., via a silicon epitaxial process) over the structure 620.

[0221] When epitaxial silicon is provided above silicon (such as on an exposed portion of PIC layer 601), crystalline silicon (c-Si) is formed / grown. As a result, as... Figure 6D As shown, silicon is formed on / above the first portion 625, which is thereafter considered as a MEMS structure 651 (in various examples, it can be consistent with any MEMS structure described herein). In other words, the combination of the first portion 625 and the grown / formed material is considered as a MEMS structure 651 (its size is on the order of MEMS features, not PIC features).

[0222] Alternatively, the MEMS structure 651 can be considered effectively mechanically coupled to the first portion 625 of the PIC layer 601, regardless of whether the two are considered as a single MEMS structure. In other words, although the grown bulk and the first portion 625 are... Figure 6D Represented by a single digit 651 and referred to as MEMS structure 651, these can still be considered as separate mechanically coupled elements. For example, the coupling elements can be thought of as being formed by a deposited silicon epitaxial layer; that is, epitaxial silicon is provided above the exposed portions of the PIC layer 601, and coupling elements are formed between these exposed portions and the portions that will become MEMS structure 651.

[0223] Alternatively, if other portions 611 of the PIC layer 601 are also exposed, then crystalline silicon can also be formed there, such as... Figure 6D As shown, this actually causes other parts 611 to increase in size.

[0224] When epitaxial silicon is provided over an oxide layer (such as on a sacrificial layer 627), polycrystalline silicon is formed / grown. As previously mentioned, polycrystalline silicon has material properties similar to silicon, which can provide advantages in structure 630.

[0225] After the material (e.g., epitaxial silicon) is grown or deposited, the structure 630 can be planarized to make the top surface of the structure 630 smooth (e.g., to make the top of the silicon (c-Si) and polycrystalline silicon regions smooth).

[0226] In various examples, other epitaxial materials can be deposited instead of silicon epitaxial deposition to grow MEMS features, such as MEMS structures 651. For example, SiGe (silicon germanium) or GaN (gallium nitride) can be deposited—these are other examples of epitaxial materials. Therefore, although Figures 6A to 6F The example described uses silicon epitaxial deposition, but it should be understood that other epitaxial materials (such as SiGe or GaN) can be deposited instead to achieve similar results.

[0227] Furthermore, one or more electrodes 631 and bonding ring elements 633, 635 can be formed (e.g., metallized) to provide these features to structure 630. In various examples, bonding ring elements 633, 635 correspond to a single bonding ring surrounding a portion of the surface of structure 640, such as the surface surrounding MEMS structure 651. In other words, when viewed from above, structure 630 includes a bonding ring, such as a portion of the top of structure 630 surrounded by the MEMS structure 651 and the first gap 623 (i.e., the material grown / formed on top of the portion of the sacrificial layer 627 filling the first gap 623). Thus, in this example, bonding ring elements 633, 635 show different portions of the cross-section of the bonding ring.

[0228] After that, as Figure 6E As shown, structure 630 is processed to further expose MEMS structure 651. For example, a second gap 643 can be formed, for example by etching from... Figure 6E The formed material (e.g., polysilicon) and a portion of the sacrificial layer 627 are removed at the indicated locations. For example, the polysilicon can be removed using DRIE, while a portion of the sacrificial layer 627 can be removed using reactive ion etching (RIE).

[0229] In some examples, the MEMS structure 651 can be provided or formed by processing the material to define at least one second gap 643 (e.g., above the first gap 623). For example, a single second gap 643 can be formed around the MEMS structure 651 to release it from the surrounding material (e.g., polysilicon), or multiple second gaps 643 can be formed around the MEMS structure 651 and then interconnected to release the MEMS structure 651. The second gap 643 can lead to the first gap 623, which can at least partially release the MEMS structure 651 from surrounding features such as the second bulk 637, other portions 611 of the PIC layer, and / or optical structures 621.

[0230] Optionally, a recess may be formed on the side of the optical structure 621 in structure 630. This recess... Figure 6EAs shown in structure 640, a pad 641 (or support 621) is formed (e.g., formed of AuSn). Forming the recess may involve etching polysilicon over the area provided by the pad 641, and similarly etching a sacrificial layer 627 over that area. The pad 641 may be formed on the support layer 609. The purpose of this recess may be to accommodate a laser die (e.g., to be attached to the pad 641). Of course, in some examples, such a recess is not necessary, as etching away a portion of the sacrificial layer may provide sufficient space for mounting the laser die. If the laser is not used to provide light (directly) to the optical structure 621, then the recess is not necessary. It should be understood that other methods of coupling light into the optical structure 621 are conceivable, methods that do not involve mounting the laser near the sidewalls of the optical structure 621. Alternatively, if exposed by etching overlaid polysilicon and sacrificial layer 627, alignment targets for the laser can be formed on other portions 613 for aligning the laser die with the optical structure 621.

[0231] Electrical coupling between MEMS structure 651 and PIC layer 601 (i.e., a portion of PIC layer 601, such as first portion 625) is achieved by growing c-Si directly on PIC layer 601.

[0232] Further processing can be performed on structure 640 to remove portions of the sacrificial layer 627 around the sidewalls of one or more features in the PIC layer 601 and release the MEMS structure 651. This process may include vapor phase HF etching.

[0233] For example, such as Figure 6F As shown, by removing at least a portion of the sacrificial layer 527, the sidewalls of the optical structure 621 are exposed (including sidewall 621a, which is indicated herein for reference to a sidewall). In this context, a sidewall (such as sidewall 621a of the optical structure 621) refers to a PIC structure perpendicular to the longitudinal direction of the PIC layer 601 (i.e., the longitudinal direction is the direction along the wafer containing structure 650, formed by...). Figure 6F The 'x' in the figure represents the surface, or the surface parallel to. Figure 6F The surface in the direction indicated by 'y'. For example, the sidewall 621a of the optical structure 621 can be exposed to allow light to couple into the optical structure 621 (e.g., via an input waveguide (not shown) or mounted on the optical structure 621). Figure 6F(The laser is shown in the image). For example, a portion of the sacrificial layer 627 can be removed to expose the sidewalls of the optical structure 621 (the side of the optical structure 621 opposite to sidewall 621a) and the opposite sidewalls of the MEMS structure 651, thereby enhancing or otherwise enabling the interaction between these components (e.g., the different effects of displacement of the MEMS structure 651 on the optical field properties of the optical structure 621 depending on the presence of any sacrificial layer between the corresponding sidewalls of these features in the PIC layer 601).

[0234] Furthermore, as described above, the MEMS structure 651 is released by removing the sacrificial layer 627 around it (e.g., by HF vapor etching). The MEMS structure 651 is thus suspended in space and can move freely (e.g., similar to the cases of MEMS structures 451 and 551). As understood from the foregoing disclosure, this will affect the optical field characteristics of the optical structure 621, thereby enabling various functions. For example, in the case where structure 640 (or structure 650 described later) is used for an inertial sensor or inertial sensing (where the optical structure 621 is a microresonator), changes in the optical field characteristics (such as optical resonance) of the microresonator can be measured to identify the corresponding or associated displacement of the MEMS structure 651 (which may be a test block), thereby allowing the measurement or determination of the corresponding inertial force acting on structure 640 or the inertial sensor. Therefore, structure 640 can be used for accelerometers, gyroscopes, or other inertial sensors. Other applications exist for chips such as structure 640 or chips containing structure 640; for example, as optoelectronic or optomechanical pickups for reading out MEMS devices such as MEMS structure 651 or its displacement, for example, replacing solutions that use capacitive readout in devices such as microphones and timing oscillators.

[0235] MEMS structure 651 can be coupled to another part of structure 650, such as a portion of sacrificial layer 627, a portion of first layer 601 (such as other portions 611), or a portion of third layer 609, enabling MEMS structure 651 to move. For example, a spring and anchor system as described elsewhere herein can be provided to suspend MEMS structure 651 while allowing MEMS structure 651 to be displaced.

[0236] In some examples, MEMS structure 651 is consistent with any other MEMS structure defined herein—for example, it can be an inertial test block as described above (e.g., for inertial sensing as described above), a thin plate or diaphragm (e.g., for a microphone, pressure sensor, or ultrasonic transceiver), or a resonant structure (e.g., for an oscillator or clock).

[0237] For example, an anchor point and spring system can be provided to suspend the MEMS structure 651 within the structure. Here, the spring and anchor point (e.g., formed of crystalline silicon) can also be grown (e.g., as part of the growth of the MEMS structure 651, or in a separate growth / deposition process); the anchor point can be grown together with a larger surrounding bulk (e.g., extending in-plane and / or above and / or below the MEMS structure 651, forming a frame around the MEMS structure 651), while the spring can be grown according to a spring shape already defined by the underlying PIC portion (e.g., a portion of the PIC layer 601). Alternatively, the spring can be grown within the bulk (e.g., on the PIC layer 601), and then the shape of the spring can be etched / defined using DRIE (e.g., DRIE etches through the grown silicon and the underlying PIC silicon to form the shape of the spring). It should be understood that any / all portions of the grown MEMS feature can be formed based on a portion of the PIC layer 601 from which the MEMS feature is grown. Growing MEMS features from a pre-existing portion of the PIC layer 601 (e.g., which may be formed from silicon) allows for the formation of thick MEMS structures / features (e.g., which may be formed from silicon). Etching can then be used after epitaxial growth to define more complex shapes, such as spring shapes, within the grown MEMS structure / feature. Etching can also be used to define vents within the structure (e.g., within the created MEMS feature), which can facilitate HF gas phase release from the MEMS structure 651 by allowing the HF gas phase to pass through the grown MEMS feature. Thus, the MEMS structure 651 can be coupled with springs and anchor points, suspending the MEMS structure 651 and allowing it to be displaced as discussed elsewhere herein.

[0238] Figure 6F The results of further optional steps of attaching or bonding the cap wafer 661 to structure 640 are also shown, as illustrated in structure 650. The cap wafer 661 may include contacts 663 and 665 for bonding to corresponding contacts on structure 640, such as bonding ring elements 633, 635. In one example, contacts 663 and 665 correspond to portions of the same bonding ring on the cap wafer 661, such as when bonding ring elements 633, 635 represent portions of the same bonding ring. For example, a single bonding ring (e.g., along the periphery of the cap wafer 661) is provided on the cap wafer 661, its size and shape corresponding to the bonding ring provided on the sacrificial layer 627. The cap wafer 661 is then bonded to structure 640 by securing or bonding the bonding ring on the cap wafer 661 to the bonding ring on the sacrificial layer 627. This can be achieved through metal bonding (such as eutectic bonding, thermo-press bonding, etc.).

[0239] The cap wafer 661 is used for sealing (e.g., in the case of an inertial sensor or resonator, to form a vacuum seal or hermetic seal) including the space below the MEMS structure 651, the space between the first gap 623 and the second gap 653; that is, the space below the cap wafer 661. In some examples, a vacuum will be formed during the bonding step (or set to the operating pressure required by the device).

[0240] Alternatively, as in Figure 6F As shown, a laser die 667 may be provided in a recess at the end of structure 650; for example, in a recess formed as described above. However, including a laser in structure 650 is not necessary. In various examples, a photodetector that is optically coupled to optical structure 621 via surface 621a may be placed in the recess instead of or separately from the laser die 667.

[0241] Although not shown, it corresponds to the above text regarding... Figures 4A to 4F The coupling element, formed as a through-hole, described in via 429, can also be incorporated into structure 650. In such an example, the coupling element can be formed by opening a through-hole extending through the first portion 625 of the PIC layer 601 into the growth block that co-forms the MEMS structure 651, and filling the through-hole with a suitable coupling material to form one or more pins. It should be understood that when incorporated into structure 650, for... Figures 4A to 4F The description of the intermediate coupling element 429 is therefore equally applicable.

[0242] The fourth method described above offers several advantages. According to various examples of the fourth method, the gap between MEMS device features and PIC device features (e.g., the first gap 623) can be very small, for example, due to the smaller lithographic dimensions of the PIC layer 601 that can be fabricated using the process or the ability of a PIC foundry to provide a wafer with the PIC layer 601. Furthermore, various examples of the second method may have lower costs than other methods disclosed herein. Relatedly, epitaxial silicon addition processes are well-established and, for example, may be applicable (as described above) in the high-volume production of inertial sensors (such as structure 650) according to various examples.

[0243] Therefore, this document discloses four methods for manufacturing (producing, providing, etc.) structures, chips, circuits, etc., including PIC layers containing PIC features and MEMS layers containing MEMS features capable of interacting with PIC features. As previously stated, the scope of this disclosure covers these methods (including equivalents of the features or operations disclosed therein), and the various structures described throughout the methods (e.g., Figures 1A to 1D , Figures 2A to 2C , Figures 3A to 3D , Figures 4A to 4F , Figures 5A to 5H , Figures 6A to 6Fand Figure 7 The various structures shown in the figure, as well as the various structures obtained by these methods.

[0244] Many variations of the methods described herein will be apparent to those skilled in the art.

[0245] and Figures 4A to 4F Configuration-related examples are as follows Figure 8 As shown.

[0246] Figure 8 The structure 800 is schematically shown, which includes a PIC layer, a MEMS layer, and coupling elements.

[0247] More specifically, a sacrificial layer 803 (e.g., corresponding to the second layers 203, 303) is disposed on a PIC support layer 811 (e.g., corresponding to support layers 211, 311). As shown, a portion of the sacrificial layer 803 has been removed. The PIC layer is located on the sacrificial layer and includes optical structures 821a, 821b and first portions 825a, 825b.

[0248] As can be seen, the first portion 825b is located above the other listed components in the PIC layer, for example, it is not in the same plane as the first portion 825a. However, this does not mean that the first portion 825b is not part of the PIC layer; rather, for example, the PIC layer is formed with a large thickness, and then a portion of the PIC layer is removed to expose it. Figure 8 The structure is illustrated. For example, a PIC layer can be formed to have a greater thickness by stacking multiple suitable photonic functional materials, including but not limited to, stacked silicon layers, silicon dioxide layers, and another silicon layer. Alternatively, the PIC layer may be formed by stacking two PIC layers one on top of the other, where one layer includes optical structures 821a, 821b and a first portion 825a, and the other layer includes the first portion 825b; this situation is generally still considered to have a single PIC layer. It should be understood that the two PIC layers can be formed from different or the same photonic functional materials. This will be understood in particular when considering that structure 800 includes first gaps 823a, 823b. For example, optical structure 821a can be used to detect the movement or displacement of the first portion 825a (caused by the coupling of the first portion 825a to the MEMS structure 851a, discussed below), and optical structure 821b can be used to detect the displacement movement of the first portion 825b (caused by the coupling of the first portion 825b to the MEMS structure 851b, discussed below). Therefore, the interaction between the first part 825b and the optical structure 821b is similar to that between the two parts. Figures 4A-4F The optical structure 421 is described in the manner in which it interacts with the first region 425.

[0249] Although Figure 8The diagram shows a PIC layer comprising two PIC layers stacked vertically, but it should be understood that in some examples, more than two PIC layers may be stacked vertically. For example, in addition to optical structures 821a, 821b and first portions 825a, 825b, the PIC layer may also include one or more second portions (not shown) disposed between the optical structures 821a, 821b and the first portions 825a, 825b. In doing so, the second portions of the PIC layer will be located in gaps 823a, 823b, respectively. In such examples, additional gaps are defined between the respective first portions and second portions, and between the respective second portions and the optical structures, such that the second portions are not adjacent to either the first portions or the optical structures.

[0250] Structure 800 also includes a MEMS layer 805, which includes MEMS structures 851a and 851b.

[0251] MEMS structure 851a is mechanically coupled to first portion 825a via coupling element 829a. The dashed line, also indicated by the number 829a, indicates that coupling element 829a can extend completely through MEMS structure 851a—this is optional—and coupling element 829a can instead extend partially into MEMS structure 851a or be attached to the surface of MEMS structure 851a. Although no similar indication is made for coupling element 829a associated with first portion 825a, it should be understood that coupling element 829a can also extend partially or completely through first portion 825a, or be attached to the surface of first portion 825a.

[0252] The MEMS structure 851a is attached to the first part 825a by coupling element 829a. The first part 825a can move within the plane of the optical structure 821a (i.e., beside it, along it, parallel to the x-direction, etc.). In other words, the first part 825a is essentially suspended on the MEMS structure 851a, similar to... Figures 4A-4F The description of the first portion 825a and the MEMS structure 451 in the figure can be applied accordingly. This arrangement allows for in-plane sensing when the displacement of the first portion 825a is determined using the optical structure 821a. For example, the optical structure 821a can be used to detect the movement of the first portion 825a and the MEMS structure 851a (and even the entire device 800) in the x-direction (as shown in the figure).

[0253] MEMS structure 851b is mechanically coupled to first portion 825b via coupling element 829b. The dashed line, also indicated by the number 829b, shows that coupling element 829b can extend completely through MEMS structure 851b—this is optional—and coupling element 829b can instead extend partially into MEMS structure 851b or be attached to the surface of MEMS structure 851b. Although no similar indication is made for coupling element 829b associated with first portion 825b, it should be understood that coupling element 829b can also extend partially or completely through first portion 825b, or be attached to the surface of first portion 825b.

[0254] The MEMS structure 851b is attached to the first part 825b via coupling element 829b. The first part 825b is movable outside the plane of the optical structure 821b (i.e., above it, perpendicular to the y-direction, etc.). In other words, the first part 825b is essentially suspended on the MEMS structure 851b, similar to... Figures 4A-4F The description of the first portion 825 and the MEMS structure 451 in the figure can be applied accordingly. Furthermore, the first portion 825b is suspended above the optical structure 821b, i.e., offset vertically from the optical structure 821b, while the first portion 825a is offset horizontally from the optical structure 821a. This arrangement allows for out-of-plane sensing when the displacement of the first portion 825b is determined using the optical structure 821b. For example, the optical structure 821b can be used to detect the movement of the first portion 825b and the MEMS structure 851b (and the entire device 800) in the x-direction (as shown).

[0255] Therefore, by providing MEMS structure 851a, first part 825a and optical structure 821a in combination with MEMS structure 851b, first part 825b and optical structure 821b, two-dimensional motion sensing (e.g., along mutually perpendicular x-axis and y-axis) can be performed.

[0256] Structure 800 also includes a sacrificial layer 807, part of which has been removed.

[0257] Couplers 829a and 829b correspond to those for Figures 4A to 4F Those publicly disclosed coupling elements (e.g., see above) Figure 4A The description is as described above, and therefore similar descriptions can be applied. For example, coupling elements 829a and 829b can also be considered as nails or through holes, and can be formed of polysilicon.

[0258] Therefore, in response to Figure 8In one example of this disclosure, a structure includes: a PIC layer, wherein two first gaps are formed in the PIC layer, each first gap defining a first portion (the structure includes two first portions), and the PIC layer includes two optical structures, each optical structure having an optical field and located on one side of one of the first gaps and opposite to one of the first portions; and a MEMS structure layer, including a first MEMS structure suspended in a first direction near one of the first portions, and a second MEMS structure suspended in a second direction near the other of the first portions, and each MEMS structure is defined by at least one second gap in the MEMS structure layer, the first MEMS structure and the second MEMS structure being deflectable in the first direction and the second direction respectively under the action of force or disturbance; wherein each first portion of the PIC layer is mechanically coupled to one of the adjacent MEMS structures so as to move according to the deflection of the MEMS structure; and wherein a change in the spacing between each first portion and the optical structure located on the other side of the corresponding first gap causes a change in the optical field characteristics of the optical structure. The first direction and the second direction may be perpendicular to each other. Optionally, the first direction lies in the plane containing the two optical structures. Optionally, the first direction is horizontal and the second direction is vertical.

[0259] Unless otherwise expressly stated, each feature disclosed in this specification (including any accompanying claims, abstract, and drawings) may be replaced by an alternative feature for the same, equivalent, or similar purpose. Therefore, unless otherwise expressly stated, each disclosed feature is merely one example of a series of equivalent or similar features.

[0260] Features, integers, properties, compounds, or compositions described in connection with a particular aspect, embodiment, or example of this disclosure should be understood to be applicable to any other aspect, embodiment, or example described herein, unless incompatible with it. All features disclosed in this specification (including any appended claims, abstract, and drawings), and / or all steps of any method or process so disclosed, may be combined in any combination, except for combinations in which at least some features and / or steps are mutually exclusive. This disclosure is not limited to the details of any of the foregoing embodiments. This disclosure extends to any novel feature or combination of novel features disclosed in this specification (including any appended claims, abstract, and drawings), or to any novel step or combination of novel steps of any disclosed method or process.

[0261] The various functions described herein (e.g., in conjunction with any embodiment or example of this disclosure) can be implemented or supported by one or more computer programs, each computer program being formed by computer-readable program code and embodied in a computer-readable medium. The terms "application program" and "program" refer to one or more computer programs, software components, instruction sets, procedures, functions, objects, classes, instances, associated data, or portions thereof, adapted to be implemented in suitable computer-readable program code. To provide an example relevant to this disclosure, the operation of detecting or measuring changes in the light field characteristics of an optical structure can be performed by, or in conjunction with, a computer (e.g., a processor in a computer) executing appropriate instructions stored in a computer-readable medium (e.g., the computer's memory, such as read-only memory (ROM), random access memory (RAM), hard disk drive, or optical disc (CD), digital video disc (DVD), flash memory, or any other type of memory).

[0262] Readers should note all papers and documents related to this application that were submitted concurrently with or prior to this specification and are publicly available together with this specification. The contents of all such papers and documents are incorporated herein by reference.

Claims

1. A structure comprising: A photonic integrated circuit (PIC) layer, wherein at least one first gap is formed in the PIC layer to define at least one first portion, and the PIC layer includes one or more optical structures, each optical structure having a corresponding light field and located on one side of one of the at least one first gap and opposite to one of the at least one first portion of the PIC layer; A microelectromechanical system (MEMS) structure layer, comprising a MEMS structure suspended near at least one first portion of the PIC layer and defined by at least one second gap in the MEMS structure layer, the MEMS structure being deflectable under force or disturbance; and A sacrificial layer is arranged to separate at least one first portion of the PIC layer from at least one first portion of the MEMS structure layer, wherein the absence of the first portion of the sacrificial layer causes the at least one first gap to communicate with the at least one second gap; In this embodiment, at least one first portion of the PIC layer is mechanically coupled to the MEMS structure to move according to the deflection of the MEMS structure; Wherein, the change in the spacing between the at least one first portion and one of the one or more optical structures causes a change in the optical field characteristics of the optical structure; The structure includes at least one coupling element, and the mechanical coupling between at least one first portion of the PIC layer and the MEMS structure is provided by the at least one coupling element; and The at least one coupling element includes at least one first coupling element, wherein each of the at least one first coupling element is formed in a through-hole passing through a portion of one of the at least one first portion to a portion of the MEMS structure.

2. The structure according to claim 1, wherein, At least one first portion is electrically coupled to the MEMS structure.

3. The structure according to claim 1 or 2, wherein, The at least one first coupling element is configured to electrically couple the at least one first portion to the MEMS structure; or The structure further includes at least one coupler configured to electrically couple the PIC layer to the MEMS structure.

4. The structure according to any of the preceding claims, wherein, The at least one first coupling element includes polycrystalline silicon, doped polycrystalline silicon, crystalline silicon, doped crystalline silicon, conductive material, or semiconductor material.

5. The structure according to any of the preceding claims, wherein, The MEMS structure is not adjacent to the at least one first portion.

6. The structure according to any of the preceding claims further includes a cavity provided below the at least one first portion and located on one side of the at least one first portion and opposite to the side on which the MEMS structure is located on the at least one first portion.

7. The structure according to any of the preceding claims, wherein, The at least one coupling element further includes at least one second coupling element provided by a second portion of a sacrificial layer between the MEMS structure and the at least one first portion, wherein the MEMS structure is not adjacent to the at least one first portion.

8. The structure according to any of the preceding claims, wherein, The MEMS structure is defined by at least one second gap formed around the MEMS structure in the MEMS structure layer to separate the MEMS structure from the remainder of the MEMS structure layer.

9. The structure according to any one of claims 1-4, wherein, The at least one coupling element further includes at least one third coupling element, which is formed by depositing material on the at least one first portion to provide a MEMS structure that is adjacent to and mechanically coupled to the at least one first portion.

10. The structure according to claim 9, wherein, The at least one third coupling element is formed by epitaxial deposition on the at least one first portion and on at least a portion of the sacrificial layer to grow a first bulk of a first material on the at least one first portion and a second bulk of a second material on the sacrificial layer; Wherein, the first block and the second block correspond to the MEMS structure layer, and the first layer contains the MEMS structure; and Wherein, the at least one third coupling element corresponds to the bonding region between the at least one first portion and the first block.

11. The structure according to claim 10, wherein: The PIC layer is formed of silicon; The sacrificial layer is formed of oxide; The first material is crystalline silicon formed by silicon epitaxial deposition onto the PIC layer; as well as The second material is polycrystalline silicon formed by silicon epitaxial deposition onto the sacrificial layer.

12. The structure according to any one of claims 9-11, wherein, The at least one second gap is formed in a second block surrounding the first block, and the at least one second gap is arranged to connect with or align with the at least one first gap.

13. The structure according to claim 8 or 12, wherein, Each of the at least one first gap is a gap between 100 nm and 500 nm; and / or Wherein, each of the at least one second gap surrounding the MEMS structure is larger than each of the at least one first gap.

14. The structure according to any of the preceding claims, wherein, The PIC layer also includes: One or more input waveguides, each configured to provide input light to one of the one or more optical structures; and One or more output waveguides, each output waveguide being configured to receive output light from one of the one or more optical structures.

15. The structure according to any one of the preceding claims, wherein, The one or more optical structures are optical resonators, and the optical field characteristics are optical resonant characteristics.

16. The structure according to claim 15, wherein, The change in the optical field characteristics is the shift in optical resonance and / or the broadening or deepening of the optical resonance curve.

17. The structure according to any one of the preceding claims, wherein, The structure includes two optical structures; and The change in the first distance between the first portion of the at least one first part and the first optical structure in the optical structure, and the change in the second distance between the second portion of the at least one first part and the second optical structure in the optical structure, result in a differential change in the optical field characteristics of the first optical structure and the second optical structure in the at least two optical structures.

18. The structure according to any one of the preceding claims, wherein, At least one active optical structure is formed on the PIC layer.

19. A method for manufacturing a structure, the method comprising: The following steps are used to fabricate a stacked structure including a photonic integrated circuit (PIC) layer: At least one first gap is formed in the PIC layer to define at least one first portion; as well as One or more optical structures are formed in the PIC layer, each optical structure having a corresponding light field, wherein each of the one or more optical structures is located on one side of one of the at least one first gap and opposite to one of the at least one first portion. The stacked structure further includes a sacrificial layer near the PIC layer; and A MEMS structure and at least one coupling element are provided in a microelectromechanical system (MEMS) structure layer, wherein the MEMS structure is mechanically coupled to and suspended near the at least one first part, such that the MEMS structure is deflectable under the action of force or disturbance, and the deflection of the MEMS structure causes the at least one first part to move. The MEMS structure is defined by at least one second gap within the MEMS structure layer; The sacrificial layer is arranged to separate at least one first portion of the PIC layer from at least one first portion of the MEMS structure layer, wherein the absence of the first portion of the sacrificial layer causes the at least one first gap to communicate with the second gap; and Wherein, a change in the spacing between the at least one first portion and one of the one or more optical structures causes a change in the optical field characteristics of the optical structure; The MEMS structure is mechanically coupled to the at least one first part by the at least one coupling element; and The at least one coupling element includes at least one first coupling element, wherein each of the at least one first coupling element is formed in a through-hole passing through a portion of one of the at least one first portion to a portion of the MEMS structure.

20. An apparatus comprising: The structure according to any one of claims 1-18, wherein light is coupled to and coupled out of each of the one or more optical structures; One or more detectors are configured to detect light received from the one or more optical structures; and One or more processors are configured to: receive the output of the one or more detectors and determine the spacing change between the at least one first portion and one of the one or more optical structures by detecting changes in the light field characteristics of the optical structure.

21. The apparatus according to claim 20, wherein, The device is or includes an inertial sensor, microphone, timing oscillator, pressure sensor, ultrasonic transceiver, micromirror, or microstructure, the microstructure being configured to change its spacing in response to an applied force or disturbance.

22. A wafer comprising a plurality of structures according to any one of claims 1 to 18.

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