Electronic device and electronic equipment

Abstract

The invention provides an electronic device and electronic equipment, relates to the field of single-ended signal transmission, and aims to reduce the crosstalk problem between single-ended signals. The electronic device comprises a first transmission line, a second transmission line, a first coil and a second coil. Wherein the first coil is coupled with the first transmission line, and the second coil is coupled with the second transmission line. The first coil comprises at least two turns of winding wires distributed on different layers, and the second coil comprises at least one turn of winding wire. At least two turns of winding wires in the first coil and at least one turn of winding wires in the second coil are alternately arranged in the thickness direction (namely the Z direction) of the electronic device and are inductively coupled with each other.

Description

Electronic devices and electronic equipment Technical Field

[0001] The present application relates to the field of single-ended signal transmission, and in particular to an electronic device and an electronic device. Background Art

[0002] In the field of high-speed parallel interfaces, such as DDR (double data rate) and LPDDR (low power double data rate), crosstalk between single-ended signals has become a key factor limiting further improvements in system performance. To reduce crosstalk between single-ended signals in parallel interfaces, existing solutions involve adding more solder balls to the chip package (PKG) and correspondingly increasing the number of plated through holes (PTHs) on the printed circuit board (PCB) for isolation. This increases the chip package size and PCB layout space, further reducing the competitiveness of the chip and related systems.

[0003] Summary of the Invention

[0004] The present application provides an electronic device and an electronic device, which can reduce the crosstalk problem between single-ended signals while meeting the miniaturization requirements of the electronic device.

[0005] The present application provides an electronic device, which includes: a first transmission line, a second transmission line, a first coil, and a second coil. The first coil is coupled to the first transmission line, and the second coil is coupled to the second transmission line. The first coil includes multiple turns of winding wires distributed in different layers, and the second coil includes at least one turn of winding wires. The multiple turns of winding wires in the first coil and the multiple turns of winding wires in the second coil are alternately arranged along the thickness direction of the electronic device and are inductively coupled to each other (inductive couple), that is, mutual inductance is generated. In this case, by setting the currents on the first coil and the second coil to flow in opposite directions, reverse inductive coupling can be formed between the first coil and the second coil, thereby reducing or eliminating the mutual inductance between the first transmission line and the second transmission line, thereby reducing the crosstalk between the signals on the first transmission line and the second transmission line.

[0006] In addition, based on the multi-layer coupled inductor design in this application, crosstalk between single-ended signals is reduced through mutual inductance, which is more conducive to high-speed and high-bandwidth scenarios.

[0007] In some possible implementations, the projections of the multiple turns of the first coil and the projection of at least one turn of the second coil at least partially overlap, so as to ensure that significant mutual inductance and mutual capacitance can be generated between the two adjacent windings.

[0008] In some possible implementations, the electronic device includes: multiple wiring layers and a dielectric layer arranged between two adjacent wiring layers; in this case, multiple turns of winding in the first coil and at least one turn of winding in the second coil can be distributed in multiple wiring layers.

[0009] In some possible implementations, the projections of the multiple turns of the first coil and the projection of at least one turn of the second coil at least partially overlap, so as to ensure that significant mutual inductance and mutual capacitance can be generated between the two adjacent windings.

[0010] In some possible implementations, the first coil includes two turns of wire distributed in different layers, and the second coil includes one turn of wire.

[0011] In some possible implementations, the first coil includes two turns of wire distributed in different layers, and the second coil includes two turns of wire distributed in different layers.

[0012] In some possible implementations, the first coil further includes a plurality of first metal vias; and two adjacent turns of windings in the first coil are connected via at least one first metal via.

[0013] In some possible implementations, the first coil also includes multiple first connecting portions; a first connecting portion is provided between two adjacent turns of winding in the first coil, and two adjacent turns of winding in the first coil are respectively connected to the two ends of the first connecting portion through different first metal vias.

[0014] In some possible implementations, the first connecting portion and a winding turn in the second coil are distributed in the same layer, thereby simplifying the process, reducing the manufacturing cost, and reducing the thickness of the packaging substrate.

[0015] In some possible implementations, the second coil further includes a plurality of second metal vias; and two adjacent turns of windings in the second coil are connected via at least one second metal via.

[0016] In some possible implementations, the second coil also includes multiple second connecting portions; a second connecting portion is provided between two adjacent turns of winding in the second coil, and two adjacent turns of winding in the second coil are respectively connected to the two ends of the second connecting portion through different second metal vias.

[0017] In some possible implementations, the second connecting portion and a winding turn in the first coil are distributed in the same layer, thereby simplifying the process, reducing the manufacturing cost, and reducing the thickness of the packaging substrate.

[0018] In some possible implementations, the transmission signals on the first transmission line and the second transmission line are single-ended signals.

[0019] In some possible implementations, the multi-turn windings in the first coil use defective strip lines or microstrip lines (i.e., defected micro strip structure, DMS). By setting defects (or gaps) on the sides of the windings, a slow wave structure is introduced, which can reduce the layer deviation between the multi-turn windings and reduce the space occupied by the coil.

[0020] In some possible implementations, at least one turn of the winding in the second coil uses a defective stripline or microstrip line (DMS). By setting defects (or gaps) on the side of the winding, a slow wave structure is introduced, which can reduce the layer deviation between multiple turns of winding and reduce the space occupied by the coil.

[0021] In some possible implementations, the electronic device may further include: a third transmission line, a third coil; the third coil is coupled to the third transmission line; the third coil includes multiple turns of winding wire distributed in different layers; the multiple turns of winding wire in the third coil and at least one turn of winding wire in the second coil are alternately arranged along the thickness direction of the electronic device and are inductively coupled to each other.

[0022] In some possible implementations, projections of the multiple turns of wire in the third coil at least partially overlap with a projection of at least one turn of wire in the second coil.

[0023] In some possible implementations, the active surface of the above-mentioned electronic device is provided with multiple connection structures, the multiple connection structures include a first connection structure, a second connection structure, and a third connection structure; the second connection structure is arranged adjacent to the first connection structure and the third connection structure; the first transmission line is connected to the first connection structure through the first coil, the second transmission line is connected to the second connection structure through the second coil, and the third transmission line is connected to the third connection structure through the third coil.

[0024] In some possible implementations, the first connection structure, the second connection structure, and the third connection structure are arranged in a straight line.

[0025] In some possible implementations, the first connection structure, the second connection structure, and the third connection structure are arranged in a Z shape.

[0026] In some possible implementations, the first connection structure, the second connection structure, and the third connection structure are arranged in a zigzag pattern.

[0027] The present application also provides an electronic device, which includes: a first transmission line, a second transmission line, a first coil, and a second coil. The first coil is coupled to the first transmission line, and the second coil is coupled to the second output line. The first coil includes at least one turn of a horizontal coil distributed on different layers; the second coil includes at least one turn of a vertical coil, and the vertical coil is wound around the horizontal coil. In this way, the horizontal inductance formed in the first coil can generate inductive coupling (inductive couple) with the vertical inductance formed in the second coil, that is, mutual inductance. In this case, by setting the current flow direction of the first coil and the second coil, the induced current on the second coil by the horizontal inductance on the first coil can be opposite to the current flow direction of the second coil; similarly, the induced current on the first coil by the vertical inductance on the second coil can be opposite to the current flow direction of the first coil, thereby forming reverse inductive coupling between the first coil and the second coil, thereby reducing or eliminating the mutual inductance between the first transmission line and the second transmission line, thereby reducing signal crosstalk on the transmission line.

[0028] In some possible implementations, the first coil includes multiple turns of transverse coils distributed in different layers, and the second coil includes multiple turns of vertical coils.

[0029] In some possible implementations, the second coil includes: a plurality of upper-layer wires, a plurality of lower-layer wires, and a plurality of first metal vias. The plurality of upper-layer wires are disposed above the first coil, and the plurality of lower-layer wires are disposed below the first coil. The plurality of upper-layer wires and the plurality of lower-layer wires are sequentially connected at their ends via the plurality of first metal vias to form a multi-turn vertical coil.

[0030] In some possible implementations, the electronic device includes: multiple wiring layers and a dielectric layer disposed between two adjacent wiring layers; multiple upper-layer wires, multiple lower-layer wires, and multiple turns of transverse coils are distributed in the multiple wiring layers.

[0031] In some possible implementations, multiple upper-layer lines are located on the same layer, and multiple lower-layer lines are located on the same layer; that is, multiple upper-layer lines are produced through the same process, and multiple lower-layer lines are produced through the same process, thereby reducing and simplifying the process, lowering production costs, and reducing the thickness of the packaging substrate.

[0032] In some possible implementations, the plurality of upper-layer wires are arranged in parallel with the plurality of lower-layer wires, thereby reducing the space occupied by the second coil.

[0033] In some possible implementations, the first coil further includes: a plurality of second metal vias; and two adjacent turns of windings in the first coil are connected via at least one second metal via.

[0034] In some possible implementations, the first coil further includes: a plurality of connecting portions; a connecting portion is provided between two adjacent turns of winding in the first coil, and the two adjacent turns of winding are respectively connected to two ends of the connecting portion through different first metal vias.

[0035] The present application also provides a circuit board, which includes an electronic device provided in any of the possible implementation methods described above.

[0036] The present application also provides a chip, which includes an electronic device provided in any of the possible implementation methods described above.

[0037] The present application also provides an electronic device, which includes a first electronic device and a second electronic device that are interconnected; wherein the first electronic device is provided by any of the aforementioned possible implementation methods; and the second electronic device is electrically connected to the first transmission line and the second transmission line in the first electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a differential equivalent circuit diagram of two lossless coupled transmission lines;

[0039] FIG2 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0040] FIG3 is a perspective schematic diagram of a multilayer coupled inductor in a packaging substrate provided by an embodiment of the present application;

[0041] FIG4 is a side view of FIG3;

[0042] FIG5 is a top view of FIG3;

[0043] FIG6 is a schematic structural diagram of a group of multi-layer mutual inductance coils provided in an embodiment of the present application;

[0044] FIG7 is a schematic diagram of the distribution of multiple coils provided in an embodiment of the present application;

[0045] FIG8 is a schematic diagram of an arrangement of multiple solder balls provided in an embodiment of the present application;

[0046] FIG9 is a schematic diagram of an arrangement of multiple solder balls provided in an embodiment of the present application;

[0047] FIG10 is a schematic diagram of the distribution of multiple coils provided in an embodiment of the present application;

[0048] FIG11 is a schematic diagram of an arrangement of multiple solder balls provided in an embodiment of the present application;

[0049] FIG12 is a schematic diagram of the distribution of multiple coils provided in an embodiment of the present application;

[0050] FIG13 is a schematic diagram of an arrangement of multiple solder balls provided in an embodiment of the present application;

[0051] FIG14 is a schematic diagram of an arrangement of multiple solder balls provided in an embodiment of the present application;

[0052] FIG15 is a schematic diagram of the structure of a winding provided in an embodiment of the present application;

[0053] FIG16 is a schematic diagram of the structure of a winding provided in an embodiment of the present application;

[0054] FIG17 is a schematic diagram of the structure of a winding provided in an embodiment of the present application;

[0055] FIG18 is a schematic diagram of the structure of a winding provided in an embodiment of the present application;

[0056] FIG19 is a crosstalk curve of the electronic device of the prior art and the present application;

[0057] FIG20 is a step response crosstalk curve of the electronic device of the prior art and the present application;

[0058] FIG21 is an eye diagram of the prior art and the present application;

[0059] FIG22 is a schematic structural diagram of a set of multi-layer mutual inductance coils provided in an embodiment of the present application;

[0060] FIG23 is a schematic cross-sectional view of FIG22 taken along position OO'. DETAILED DESCRIPTION

[0061] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0062] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0063] Single-ended signals use ground as a reference and require only one wire to transmit the signal, plus a reference wire, which is the ground wire. Single-ended signals have the advantage of low cost, but also have the problem of poor anti-interference ability.

[0064] In electronic devices, between two single-ended signal transmission lines (or channels), the signal on one transmission line (the aggressor line) can produce an undesirable effect on the other transmission line (the victim line), causing crosstalk. This crosstalk may be caused by the coupling of electromagnetic fields between the two transmission lines, and can usually be characterized by mutual capacitance and mutual inductance.

[0065] The ratio of the voltage noise measured at the near-end of the victim line to the incident stimulus voltage on the aggressor line is called near-end crosstalk (NEXT). The ratio of the voltage noise measured at the far-end of the victim line to the incident stimulus voltage on the aggressor line is called far-end crosstalk (FEXT). Near-end crosstalk (NEXT) and far-end crosstalk (FEXT) are two important components of total channel crosstalk. Of these, far-end crosstalk (FEXT) is the more serious problem and has become a key factor limiting device performance.

[0066] The following is a brief explanation of far-end crosstalk (FEXT) between single-ended signals.

[0067] Figure 1 shows the differential equivalent circuit of two lossless coupled transmission lines. Referring to Figure 1, if line 1 is the aggressor line and line 2 is the victim line, the far-end crosstalk (FEXT) on line 2 is:

[0068] Where k is a constant, Ls represents the self-inductance per unit length of a single transmission line, and L M Represents the mutual inductance of two transmission lines per unit length, C M Represents the mutual capacitance per unit length between two transmission lines, C g Represents the capacitance per unit length of a single transmission line to ground.

[0069] For vertical (Z-direction) interconnect structures (such as TSV, PTH, solder balls, connectors, etc.), the following relationship exists:

[0070] Therefore, in order to reduce the problem of far-end crosstalk (FEXT), there are two methods: (1) increase the mutual capacitance between the two interconnect structures; (2) reduce the mutual inductance between the two interconnect structures. The mechanism of reducing mutual inductance is to add an additional reverse mutual inductance L M’ , so that the equivalent mutual inductance becomes (L M -L M’ ), thereby achieving mutual inductance elimination (or crosstalk elimination).

[0071] It is understood that, in an electronic device, a signal transmission channel may include a transmission line and a vertical interconnection structure connected to the transmission line, etc. The vertical interconnection structure may include TSV, PTH, solder balls, connection pads (or connectors), etc. The vertical interconnection structure is also called a vertical transition section, a Z-direction interconnection structure, etc. In addition, the "adjacent" in "adjacent single-ended signals", "adjacent transmission lines", and "adjacent transmission channels" involved in this application refers to the adjacent arrangement of the vertical interconnection structures in the corresponding signal transmission channels.

[0072] The embodiments of the present application provide a novel technical solution, which forms a multi-layer coupled inductor by adding coils in the vertical interconnection structure of adjacent transmission channels, that is, forming an inductive couple, thereby reducing crosstalk between single-ended signals.

[0073] The novel technical solution provided in this application can be applied to parallel port interconnection scenarios with single-ended signals, such as DDR (double data rate), LPDDR (low power double data rate), and HBM (high bandwidth memory), but this application is not limited to this.

[0074] Schematically, an embodiment of the present application provides an electronic device, which can be an electronic product such as a mobile phone, a tablet computer, a personal computer (PC), a car computer, a smart watch, a smart bracelet, a server, etc. The present application does not limit the setting form of the electronic device. The electronic device is provided with a first electronic device and a second electronic device that are interconnected, wherein the first electronic device has a plurality of single-ended signal transmission channels (or conductive paths), and the first electronic device is electrically connected to the second electronic device through the plurality of transmission channels, and realizes the input and output (I / O) of single-ended signals. A coil is provided in the vertical interconnection structure of the adjacent signal transmission channels in the first electronic device to form a multi-layer coupled inductor, thereby reducing the mutual inductance between the two adjacent vertical interconnection structures, and further reducing the crosstalk between adjacent single-ended signals.

[0075] Of course, according to actual needs, additional coils may be provided in the second electronic device to form a multi-layer coupled inductor to reduce crosstalk between adjacent single-ended signals in the second device.

[0076] The above-mentioned first electronic device can be any device that uses a single-ended signal. This application does not impose any limitation on this, and it can be set as needed in practice.

[0077] For example, in some possible implementations, the first electronic device may be a chip or a partial device in a chip.

[0078] For another example, in some possible implementations, the first electronic component may be a circuit board, or a component of a circuit board. For example, the circuit board may be a printed circuit board (PCB), a package substrate, an interposer, a carrier board with a functional module, or the like.

[0079] Schematically, referring to FIG. 2 , in some possible implementations, the first electronic device may be a package substrate, and the second electronic device may be a PCB, with the package substrate connected to the PCB via solder balls. The multilayer coupled inductor added to the first electronic device may be disposed within the vertical interconnect structure illustrated by the dashed box in FIG. 2 .

[0080] The following takes a packaging substrate as an example to illustrate the specific arrangement of the multi-layer coupled inductor in the packaging substrate through specific embodiments.

[0081] Example 1

[0082] FIG3 is a three-dimensional schematic diagram of a multi-layer coupled inductor in a packaging substrate provided in the first embodiment of the present invention, FIG4 is a side view of FIG3 , and FIG5 is a top view of FIG3 .

[0083] 2 , 3 , 4 , and 5 , this embodiment provides a package substrate including a first transmission line L1, a second transmission line L2, a first coil 10, and a second coil 20. The first coil 10 is coupled to the first transmission line L1, and the second coil 20 is coupled to the second transmission line L2.

[0084] Schematically, referring to Figures 2 and 3 , a first coil 10 and a second coil 20 are arranged in a vertical interconnect structure on a package substrate. One end of the first coil 10 can be connected to a solder ball, and the other end can be connected to a first transmission line L1 via a plated through hole (PTH). Similarly, one end of the second coil 20 can be connected to a solder ball, and the other end can be connected to a second transmission line L2 via a plated through hole (PTH).

[0085] On this basis, referring to Figure 3 , the first coil 10 includes multiple turns ( a1 , a2 ) distributed across different layers, and the second coil 20 includes multiple turns ( b1 , b2 ) distributed across different layers. Figure 3 illustrates an example where both the first coil 10 and the second coil 20 include two turns, but the present invention is not limited thereto. In other possible implementations, the first coil 10 may include two turns, while the second coil 20 may include only one turn.

[0086] It is understood that multiple wiring layers can be provided in the package substrate, and a dielectric layer can be provided between adjacent wiring layers to achieve electrical insulation between the two adjacent wiring layers through the dielectric layer. In the application, the multiple turns of winding (a1, a2) in the first coil 10 can be distributed in multiple wiring layers, and the single turn winding can be provided as a non-enclosed structure with an opening, and the two ends of the single turn winding at the opening can be connected to the adjacent winding through a connection structure such as a metal via.

[0087] Similarly, the multiple turns of winding wires (b1, b2) in the second coil 20 can also be distributed in multiple wiring layers, and two adjacent turns of winding wires (b1 and b2) can be connected to the adjacent winding wires by a connection structure such as a metal via.

[0088] On this basis, referring to FIG. 3 , the multiple turns of winding wire ( a1 , a2 ) in the first coil 10 and the multiple turns of winding wire ( b1 , b2 ) in the second coil 20 are alternately arranged in sequence along the thickness direction of the package substrate, so that an inductive couple is generated between the first coil 10 and the second coil 20 .

[0089] Schematically, as shown in Figure 3, the windings a1 and a2 in the first coil 10 and the windings b1 and b2 in the second coil 20 can be arranged from top to bottom in the distribution manner of a1, b1, a2, b2, so that inductive coupling can be formed between two adjacent windings (a1 and b1, b1 and a2, a2 ​​and b2), that is, mutual inductance is generated, forming a multi-layer coupled inductor.

[0090] By setting the currents in the first coil 10 and the second coil 20 to flow in opposite directions, a reverse inductive coupling is formed between the first coil 10 and the second coil 20. This reduces or eliminates the mutual inductance between the first transmission line L1 and the second transmission line L2, thereby reducing crosstalk between the signals on the first and second transmission lines. Furthermore, the multi-layer coupled inductor design of this application reduces crosstalk between signals through mutual inductance, making it more suitable for high-speed and high-bandwidth scenarios.

[0091] Of course, to ensure significant mutual inductance between two adjacent windings (a1 and b1, b1 and a2, a2 ​​and b2), the projection of the multiple turns (a1, a2) in the first coil 10 and the projection of the multiple turns (b1, b2) in the second coil 20 can be set to have at least a partial overlap. For example, in some embodiments, as shown in Figure 3, the projection of the multiple turns (a1, a2) in the first coil 10 can overlap with the projection of the multiple turns (b1, b2) in the second coil 20, thereby generating a greater degree of mutual inductance and mutual capacitance between the two adjacent windings.

[0092] In addition, based on the multi-layer coupled inductor design in the present application, when the projection of the multiple turns of winding (a1, a2) in the first coil 10 and the projection of the multiple turns of winding (b1, b2) in the second coil 20 have at least a partially overlapping area, in addition to being able to generate inductive coupling (inductive couple) between the two adjacent windings (a1 and b1, b1 and a2, a2 ​​and b2), capacitive coupling (capacitive couple) can also be generated, that is, mutual capacitance is generated between the two adjacent coils, thereby increasing the mutual capacitance between the first transmission line L1 and the second transmission line L2, and further reducing the crosstalk between the signals on the first transmission line and the second transmission line.

[0093] FIG6 is a schematic structural diagram of a group of multi-layer mutual inductance coils ( 10 , 20 ) provided in the first embodiment of the present invention. The arrows in FIG6 represent the direction of current flow.

[0094] Referring to Figure 6, in order to generate reverse inductance between the first coil 10 and the second coil 20, in some possible implementation methods, the current flow direction on the multiple turns of winding (a1, a2) in the first coil 10 can be set to be counterclockwise, and the current flow direction on the multiple turns of winding (b1, b2) in the second coil 20 can be set to be clockwise, thereby ensuring that the current flow directions of the two adjacent windings (a1 and b1, b1 and a2, a2 ​​and b2) are opposite, thereby ensuring that reverse inductive coupling is generated between any two adjacent windings.

[0095] Of course, in some possible implementations, the current flow direction on the multiple turns of winding (a1, a2) in the first coil 10 can be set to be clockwise, and the current flow direction on the multiple turns of winding (b1, b2) in the second coil 20 can be set to be counterclockwise.

[0096] Continuing with FIG6 , a turn of wire b1 from the second coil 20 is interposed between two adjacent turns of wire ( a1, a2 ) in the first coil 10 . In other words, an intermediate wiring layer (at least including the layer containing wire b1 ) is provided between the wiring layer containing wire a1 and the wiring layer containing wire a2 . In this case, to ensure the connection between the two adjacent turns of wire and to ensure that the current flows in the two turns in the same direction, a first connector 101 can be provided in the intermediate wiring layer. This first connector 101, in conjunction with a metal via V1 (also referred to as a first metal through-hole), connects wire a1 and wire a2, ensuring that the current flows in both wires in a counterclockwise (or clockwise) direction. Similarly, a second connecting portion 201 is provided in the middle wiring layer between two adjacent turns of winding (b1, b2) in the second coil 20, and the winding b1 and the winding b2 are connected through the first connecting portion 101 in combination with the metal via V2 (also referred to as the second metal through-hole) to ensure that the current flow direction on the winding b1 and the winding b2 is clockwise (or counterclockwise).

[0097] Of course, according to needs, the first coil 10 may be provided with a plurality of first connecting portions 101 and a plurality of metal vias V1 , and the second coil 20 may be provided with a plurality of second connecting portions 201 and a plurality of metal vias V2 .

[0098] Schematically, regarding the configuration of the above-mentioned first connection portion 101, taking the first connection portion 101 connecting the winding a1 and the winding a2 as an example, with reference to FIG6 , in some possible implementations, the first end e1 of the winding a1, the first end e1 of the winding a2, and the first end e1 of the first connection portion 101 can be aligned (or their projections overlap), and the second end e2 of the winding a1, the second end e2 of the winding a2, and the second end e2 of the first connection portion 101 can be aligned. In this case, the first end e1 of the winding a1 can be connected to the first end e1 of the first connection portion 101 through a metal via V1, and the second end e2 of the first connection portion 101 can be connected to the second end e2 of the winding a2 through a metal via V1, thereby ensuring that the current on the winding a1 and the winding a2 flows in the same direction, either counterclockwise or clockwise.

[0099] The second end e2 of the winding a1 and the first end e1 of the winding a2 can be connected to other coils or other connection structures in the packaging substrate through connection structures such as the metal via V1 and the first connection portion 101 as needed.

[0100] Regarding the configuration of the second connection portion 201, taking the second connection portion 201 connecting the winding b1 and the winding b2 as an example, as shown in FIG6 , in some possible implementations, the first end e1 of the winding b1, the first end e1 of the winding b2, and the first end e1 of the second connection portion 201 can be aligned vertically, and the second end e2 of the winding b1, the second end e2 of the winding b2, and the second end e2 of the second connection portion 201 can be aligned vertically. In this case, the first end e1 of the winding b1 can be connected to the first end e1 of the second connection portion 201 via a metal via V2, and the second end e2 of the second connection portion 201 can be connected to the second end e2 of the winding b2 via a metal via V2, thereby ensuring that the current flowing in the windings b1 and b2 is consistent, both clockwise or both counterclockwise.

[0101] The second end e2 of the winding b1 and the second end e2 of the winding b2 can be connected to other coils or other connection structures in the packaging substrate through connection structures such as the metal via V2 and the second connection portion 201 as needed.

[0102] Of course, according to actual needs, the windings (a1, a2, b1, b2) can be connected to the corresponding metal vias (V1, V2) through the connection pads, and similarly, the connecting parts (101, 201) can also be connected to the corresponding metal vias (V1, V2) through the connection pads. However, this is not limited to this.

[0103] Furthermore, to simplify the process, reduce manufacturing costs, and reduce the thickness of the package substrate, as shown in Figures 4 and 6 , multiple first connecting portions 101 in the first coil 10 can be arranged to be located in the same wiring layer as the multiple turns (b1, b2) of the second coil 20. That is, the first connecting portion 101 and a single winding of the second coil 20 are located in the same wiring layer. Similarly, multiple connecting portions 201 in the second coil 20 can be arranged to be located in the same wiring layer as the multiple turns (a1, a2) of the first coil 10. That is, the second connecting portion 102 and a single winding of the first coil 10 are located in the same wiring layer.

[0104] For example, referring to Figures 3 and 6, the first connection portion 101 connected between the winding a1 and the winding a2 can be located in the same wiring layer as the winding b2 arranged between the winding a1 and the winding a2, that is, the first connection portion 101 and the winding b2 can be manufactured through the same manufacturing process.

[0105] For another example, referring to Figures 3 and 6, the second connection portion 201 connected between the winding b1 and the winding b2 can be located in the same wiring layer as the winding a2 arranged between the winding b1 and the winding b2, that is, the second connection portion 201 and the winding a2 can be manufactured through the same manufacturing process.

[0106] It is understandable that compared to planar coupled inductors, which occupy a larger space, this can lead to the problem of an excessively large deployment area on the package substrate. In the present application, the coils (10, 20) are arranged on multiple wiring layers to form a multilayer coupled inductor. This multilayer coupled inductor has the advantage of occupying a small space and is more conducive to the miniaturization of the device. In addition, the present application uses a multilayer coupled inductor that occupies a small space, which can achieve mutual inductance coupling between any two adjacent single-ended signals.

[0107] It can also be understood that there are usually multiple single-ended signal transmission channels in the packaging substrate, and multiple single-ended signal transmission channels may be arranged around a single-ended signal transmission channel, that is, a single-ended signal may generate crosstalk with multiple (that is, more than two) single-ended signals. For example, a single-ended signal may generate crosstalk with two or three adjacent single-ended signals. In this case, the present application adopts a small-volume multi-layer coupled inductor design, which can be flexibly deployed and can achieve mutual inductance coupling between a single-ended signal and multiple adjacent single-ended signals, thereby solving the crosstalk problem between multiple single-ended signals.

[0108] Taking the aforementioned example of first coil 10 being located in the first transmission channel and second coil 20 being located in the second transmission channel, in addition to the first and second transmission channels being adjacent to each other, a third transmission channel may also be provided. This third transmission channel is adjacent to the second transmission channel and includes a third transmission line and a vertical connection structure connected to the third transmission line. In other words, the second transmission channel is adjacent to both the first and third transmission channels.

[0109] To solve the crosstalk between the single-ended signals in the second transmission channel and the third transmission channel, as shown in FIG7 , a third coil 30 may be provided in the vertical connection structure of the third transmission channel, and the third coil 30 is coupled to the third transmission line.

[0110] Similar to the arrangement of the first coil 10 and the second coil 20 , the third coil 30 can adopt a multi-layer coupled inductor design. The third coil 30 includes multiple turns of winding wires distributed in different wiring layers, and along the thickness direction of the packaging substrate, the multiple turns of winding wires in the third coil 30 and the multiple turns of winding wires in the second coil 20 are alternately arranged in sequence, so that the third coil 30 can form an inductive couple and a capacitive couple with the second coil 20 .

[0111] To ensure greater mutual inductance and mutual capacitance between the third coil 30 and the second coil 20 , the projection of the multiple turns ( a1 , a2 ) in the third coil 30 and the projection of the multiple turns in the second coil 20 may have at least a partial overlap.

[0112] As shown in Figure 7 , since the second coil 20 needs to generate mutual inductance and mutual capacitance with both the first coil 10 and the third coil 30, the single-turn winding in the second coil 20 can have two wraparound portions: a first wraparound portion T1 and a second wraparound portion T2. ​​The first wraparound portion T1 is aligned vertically with the winding in the first coil 10 to generate mutual inductance and mutual capacitance, while the second wraparound portion T2 is aligned vertically with the winding in the third coil 30 to generate mutual inductance and mutual capacitance.

[0113] Of course, the first coil 10 and the third coil 30 may be provided with one surrounding portion or multiple surrounding portions. This application does not impose any restrictions on this, and the surrounding portions may be provided according to actual needs.

[0114] The arrangement and connection of the multiple turns of winding in the third coil 30 can refer to the relevant descriptions of the first coil 10 and the second coil 20, and will not be repeated here.

[0115] In addition, depending on actual needs, the transmission channel is provided with a connection structure (such as, but not limited to, solder balls) on the active surface of the device, which can be deployed in different arrangements, such as linear, Z-shaped, broken line, regular hexagonal, etc. The multi-layer coupled inductor design of the present application can meet different arrangements of the connection structure (single-ended signal transmission channel) and is more suitable for mutual inductance coupling between multiple adjacent single-ended signals arranged in a high density.

[0116] FIG8 , FIG9 , FIG11 , and FIG13 respectively illustrate four different solder ball arrangements, where G represents a solder ball in a ground signal transmission channel, and S represents a solder ball in a single-ended signal line transmission channel.

[0117] Schematically, in some possible implementations, as shown in the dotted box in Figure 8, three adjacent solder balls (S) are arranged in a straight line. In this case, referring to Figure 7, the coils (10, 20, 30) in the corresponding three transmission channels can also be deployed in a straight line direction.

[0118] Schematically, in some possible implementations, as shown in the dotted box in Figure 9, three adjacent solder balls (S) are arranged in a "Z" shape. In this case, as shown in Figure 10, the coils (10, 20, 30) in the corresponding three transmission channels can also be deployed in a "Z" shape.

[0119] Schematically, in some possible implementations, as shown in FIG. 11 and FIG. 12 , when a plurality of solder balls (S) are arranged in a regular hexagon, the coils in the corresponding six transmission channels can also be deployed in a regular hexagonal manner.

[0120] Schematically, in some possible implementations, as shown in FIG. 13 and FIG. 14 , when a plurality of solder balls (S) are arranged in a zigzag pattern, the coils in the corresponding plurality of transmission channels may also be deployed in a zigzag pattern.

[0121] In addition, for the multi-layer coupled coils (10, 20, 30) used in this application, this application does not limit the winding shape of the coils, and in practice it can be set as needed.

[0122] For example, as shown in FIG. 15 , in some possible implementations, the windings in the coil may be a circular structure with an opening.

[0123] For another example, as shown in FIG16 , in some possible implementations, the windings in the coil may be a rectangular structure with an opening.

[0124] For another example, as shown in FIG17 , in some possible implementations, the windings in the coil may be an octagonal structure with an opening.

[0125] Considering that circular winding has less layer deviation during production, that is, circular winding has better resistance to layer deviation, in some possible implementation methods, the multiple turns of winding in the coil (10, 20, 30) can all adopt a circular winding structure.

[0126] Of course, in the case where one coil needs to be coupled with multiple coils, a single-turn winding in the coil may have multiple circular winding structures (see FIG. 7 ).

[0127] On this basis, referring to FIG18 , in some possible implementations, the multi-turn windings in the coils (10, 20, 30) may be formed using a stripline or microstrip line with defects (i.e., a defective microstrip structure (DMS)). This application does not impose any restrictions on this, and in practice, this may be configured according to the needs of the device. By providing defects (or gaps) on the sides of the windings, thereby introducing a slow wave structure into the coils, the layer deviation between the multi-turn windings can be reduced, and the space occupied by the coils (10, 20, 30) can be reduced.

[0128] The present application does not impose any restrictions on the shape of the defects set in the coil, which may be sawtooth, comb, etc.

[0129] Schematically, as shown in FIG18 , in some possible implementations, the multi-turn windings in the coils ( 10 , 20 , 30 ) may be strip lines or microstrip lines having a comb-like shape.

[0130] It should be noted that in some possible implementations, the multiple turns of the windings in the first coil 10, the second coil 20, and the third coil 30 may all be defective stripline or defective microstrip line; however, this is not limiting. In other possible implementations, only some of the coils may be configured to use defective stripline or defective microstrip line. For example, one or two of the first coil 10, the second coil 20, and the third coil 30 may be configured to use defective stripline or defective microstrip line.

[0131] For a single coil, all windings in the coil can be set to use defective strip lines or defective microstrip lines, or part of the windings in the coil can be set to use defective strip lines or defective microstrip lines; this application does not impose any restrictions on this.

[0132] In addition, the following compares the prior art that does not use a multi-layer coupled inductor design with the present application that uses the multi-layer coupled inductor design, in combination with relevant detection parameters.

[0133] Figure 19 shows the crosstalk and insertion loss curves of electronic devices using the present application and prior art. Curve S1 shows the crosstalk curve for the multilayer coupled inductor design using the present application; curve S2 shows the curve for the prior art design without a multilayer coupled inductor design; curve S3 shows the insertion loss curve for the multilayer coupled inductor design using the present application; and curve S4 shows the insertion loss curve for the prior art design without a multilayer coupled inductor design.

[0134] Comparing curves S1 and S2 in Figure 19, it can be seen from the frequency domain that the crosstalk of curve S1 at 6.4 GHz and 12.8 GHz is reduced by about 14 dB and 8 dB respectively compared with curve S2; that is, the multilayer coupled inductor design (S1) of the present application has a crosstalk benefit of about 14 dB at 6.4 GHz and a crosstalk benefit of about 8 dB at 12.8 GHz.

[0135] Comparing curves S3 and S4 in FIG19 , it can be seen from the frequency domain that, with the multilayer coupled inductor design (S3) of the present application, the insertion loss is basically not deteriorated below 15 GHz, making it more suitable for high-bandwidth scenarios.

[0136] Figure 20 shows the step response crosstalk curves of the electronic devices of the present application and the prior art. Curve S5 is the step response crosstalk curve of the multilayer coupled inductor design of the present application; curve S6 is the step response crosstalk curve of the prior art that does not use the multilayer coupled inductor design.

[0137] As shown in Figure 20, curve S6 shows that the prior art design without a multilayer coupled inductor has a time-domain crosstalk of approximately 50.5mV. In contrast, curve S5 shows that the time-domain crosstalk of the multilayer coupled inductor design of the present application is reduced to 20.8mV, a gain of 58.81%. In other words, the multilayer coupled inductor design of the present application can significantly reduce time-domain crosstalk.

[0138] Figure 21(a) shows an eye diagram using the multilayer coupled inductor design of this application. The jitter in this eye diagram is approximately 11.8 ps, and the eye height is approximately 283 mV. Figure 21(b) shows an eye diagram using the prior art design without a multilayer coupled inductor design. The jitter in this eye diagram is approximately 16.4 ps, and the eye height is approximately 220 mV.

[0139] Comparing (a) and (b) in Figure 21, it can be seen that compared to the prior art design without a multilayer coupled inductor, the multilayer coupled inductor design of this application can increase the eye height from 220mV to 283mV and reduce the jitter from 16.4ps to 11.8ps, a gain of 22.26%. In other words, the multilayer coupled inductor design of this application can increase the eye height and reduce the jitter. It should be understood here that the lower the jitter, the better, and the higher the eye height, the better.

[0140] Example 2

[0141] This second embodiment provides a packaging substrate. The main difference between this packaging substrate and the packaging substrate in the first embodiment is the arrangement of the windings in the coils. In the first embodiment, both coupled coils use horizontal windings, meaning that each turn is wound within the wiring layer. In this second embodiment, one of the two coupled coils (the first coil) has at least one horizontal winding within the wiring layer, and the other coil (the second coil) has at least one vertical winding perpendicular to the wiring layer.

[0142] The following describes the coil arrangement in the second embodiment.

[0143] FIG22 is a top view of a coil in a packaging substrate provided in the second embodiment; FIG23 is a cross-sectional view taken along position OO' of FIG22 .

[0144] As shown in Figure 12, this second embodiment provides a packaging substrate, which includes a first transmission line, a second transmission line, a first coil 100, and a second coil 200. The first coil 101 is coupled to the first transmission line, and the second coil 200 is coupled to the second transmission line. The first coil 100 may include one or more turns of horizontal winding wire, and the second coil 200 may include one or more turns of vertical winding wire. The following embodiments are described using the example of the first coil 100 including multiple turns of horizontal winding wire and the second coil 200 including multiple turns of vertical winding wire.

[0145] The first transmission line and the second transmission line in the second embodiment are basically configured the same as the first transmission line L1 and the second transmission line L2 in the first embodiment. For details, please refer to the corresponding description in the first embodiment, which will not be repeated here.

[0146] Similar to the arrangement of the coils (10, 20) in the aforementioned embodiment 1, the first coil 100 and the second coil 200 can be distributed in multiple wiring layers in the packaging substrate. For details, please refer to the corresponding description in the aforementioned embodiment 1.

[0147] As shown in Figures 12 and 13, the first coil 100 may include multiple turns of winding wire (also known as multiple turns of lateral winding wire) distributed in different layers. The configuration of the first coil 100 is substantially consistent with that of the coils (10, 20) in the first embodiment. For example, the distribution and connection method of the multiple turns of the coils can be referred to the corresponding description in the first embodiment, and will not be repeated here.

[0148] The main difference from the first embodiment is that in this second embodiment, the multiple turns of winding wire in the second coil 200 are vertically wound, and these multiple turns of vertical winding wire are wound around the multiple turns of horizontal winding wire in the first coil 100. In this case, the horizontal inductance formed in the first coil 100 and the vertical inductance formed in the second coil 200 can generate inductive coupling, that is, mutual inductance.

[0149] In this case, by setting the current flow directions in the first coil 100 and the second coil 200, the lateral inductance of the first coil 100 can induce a current in the second coil 200 in the opposite direction of the current flow. Similarly, the vertical inductance of the second coil 200 can induce a current in the first coil 100 in the opposite direction of the current flow. This creates a reverse inductive coupling between the first coil 100 and the second coil 200, thereby reducing or eliminating the mutual inductance between the first and second transmission lines and, consequently, lowering signal crosstalk on the transmission lines.

[0150] The present application does not impose any restrictions on the configuration of the multiple turns of vertical winding in the second coil 200 , and in practice it can be manufactured as needed.

[0151] Schematically, as shown in Figures 22 and 23 , in some possible implementations, the second coil 200 may include multiple upper-layer wires c1, multiple lower-layer wires c2, and multiple metal vias V3. The multiple upper-layer wires c1 may be arranged in a wiring layer above the multiple-turn horizontal windings in the first coil 100, and the multiple lower-layer wires c2 may be arranged in a wiring layer below the multiple-turn horizontal windings in the first coil 100. On this basis, the multiple upper-layer wires c1 and the multiple lower-layer wires c2 are sequentially connected through metal vias V3 to form a multi-turn vertical coil.

[0152] Schematically, referring to Figures 22 and 23, the plurality of upper-layer lines c1 are, from right to left, the first upper-layer line, the second upper-layer line, and the third upper-layer line, and the plurality of lower-layer lines c2 are, from right to left, the first lower-layer line, the second lower-layer line, and the third lower-layer line. In this case, the lower end of the first upper-layer line can be connected to the lower end of the first lower-layer line via a metal via V3, the upper end of the first lower-layer line can be connected to the upper end of the second upper-layer line via a metal via V3, the lower end of the second upper-layer line can be connected to the lower end of the second lower-layer line via a metal via V3, the upper end of the second lower-layer line can be connected to the upper end of the third upper-layer line via a metal via V3, and the lower end of the third upper-layer line can be connected to the lower end of the third lower-layer line via a metal via V3.

[0153] Of course, the upper layer line c1 and the lower layer line c2 can be directly connected through the metal via V3, or can be connected through the metal via V3 combined with other connection structures. This application does not limit this, and it can be set as needed in practice.

[0154] In order to simplify the process, reduce the production cost, and reduce the thickness of the packaging substrate, referring to Figures 22 and 23, in some possible implementation methods, the multiple upper-layer wires c1 in the second coil 200 can be located in the same wiring layer, and the multiple lower-layer wires c2 can be located in the same wiring layer; that is, the multiple upper-layer wires c1 are produced by the same process, and the multiple lower-layer wires c2 are produced by the same process.

[0155] In order to reduce the space occupied by the second coil 200 , referring to FIG. 22 and FIG. 23 , in some possible implementations, a plurality of upper layer wires c1 may be arranged in parallel, and a plurality of lower layer wires c2 may be arranged in parallel.

[0156] Of course, the packaging substrate may also include a third coil, which is similar to the configuration of the second coil 200 . The third coil may include one or more turns of vertical winding wire, and the multiple turns of vertical winding wire may be wound around the first coil 100 .

[0157] In addition, in the second embodiment, the windings in the first coil 100 and the second coil 200 may be strip lines with defects or microstrip lines with defects. For details, please refer to the corresponding description in the above-mentioned first embodiment.

[0158] Regarding other settings and related explanations of the second embodiment, please refer to the aforementioned first embodiment, and will not be described in detail here.

[0159] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An electronic device, characterized in that: include: A first transmission line, a second transmission line, a first coil, and a second coil; The first coil is coupled to the first transmission line, and the second coil is coupled to the second transmission line; The first coil includes a plurality of windings distributed in different layers, and the second coil includes at least one winding; The multiple turns of winding wire in the first coil and at least one turn of winding wire in the second coil are alternately arranged along the thickness direction of the electronic device and are inductively coupled to each other.

2. The electronic device according to claim 1, characterized in that The first coil and the second coil are inversely inductively coupled.

3. The electronic device according to claim 1 or 2, characterized in that: The projection of the plurality of winding turns in the first coil at least partially overlaps with the projection of at least one winding turn in the second coil.

4. The electronic device according to any one of claims 1 to 3, characterized in that: The electronic device comprises: a plurality of wiring layers and a dielectric layer arranged between two adjacent wiring layers; The plurality of winding turns in the first coil and at least one winding turn in the second coil are distributed in the plurality of wiring layers.

5. The electronic device according to any one of claims 1 to 4, characterized in that: The first coil includes two turns of winding wire distributed in different layers, and the second coil includes one turn of winding wire.

6. The electronic device according to any one of claims 1 to 4, characterized in that: The first coil includes two turns of winding wire distributed in different layers, and the second coil includes two turns of winding wire distributed in different layers.

7. The electronic device according to any one of claims 1 to 6, characterized in that: The first coil also includes: a plurality of first metal vias; Two adjacent turns of winding wire in the first coil are connected through at least one of the first metal vias.

8. The electronic device according to claim 7, characterized in that: The first coil further includes: a plurality of first connecting parts; A first connecting portion is provided between two adjacent turns of winding wire in the first coil, and two adjacent turns of winding wire in the first coil are connected to two ends of the first connecting portion through different first metal vias, respectively.

9. The electronic device according to claim 8, characterized in that: The first connecting portion and a winding turn in the second coil are distributed in the same layer.

10. The electronic device according to any one of claims 1 to 4 and 6 to 9, characterized in that: The second coil also includes: a plurality of second metal vias; Two adjacent turns of winding wire in the second coil are connected by at least one of the second metal vias.

11. The electronic device according to claim 10, characterized in that: The second coil further includes: a plurality of second connecting parts; A second connecting portion is provided between two adjacent turns of winding wire in the second coil, and two adjacent turns of winding wire in the second coil are connected to two ends of the second connecting portion through different second metal vias, respectively.

12. The electronic device according to claim 11, characterized in that: The second connecting portion and a winding turn in the first coil are distributed in the same layer.

13. The electronic device according to any one of claims 1 to 12, characterized in that: The transmission signals on the first transmission line and the second transmission line are single-ended signals.

14. The electronic device according to any one of claims 1 to 13, characterized in that: The multiple turns of winding wire in the first coil are strip lines with defects or microstrip lines with defects; And / or, at least one winding turn in the second coil is a strip line with defects or a microstrip line with defects.

15. The electronic device according to any one of claims 1 to 14, characterized in that: The electronic device further comprises: a third transmission line and a third coil; the third coil is coupled to the third transmission line; The third coil includes multiple turns of winding wire distributed in different layers; The multiple turns of winding wire in the third coil and at least one turn of winding wire in the second coil are alternately arranged along the thickness direction of the electronic device and inductively coupled to each other.

16. The electronic device according to claim 15, characterized in that: The projection of the plurality of winding turns in the third coil at least partially overlaps with the projection of at least one winding turn in the second coil.

17. The electronic device according to claim 15 or 16, characterized in that: The active surface of the electronic device is provided with a plurality of connection structures, wherein the plurality of connection structures include a first connection structure, a second connection structure, and a third connection structure; The second connection structure is arranged adjacent to the first connection structure and the third connection structure; The first transmission line is connected to the first connection structure through the first coil, the second transmission line is connected to the second connection structure through the second coil, and the third transmission line is connected to the third connection structure through the third coil.

18. The electronic device according to claim 17, characterized in that: The first connection structure, the second connection structure, and the third connection structure are arranged in a straight line; Alternatively, the first connection structure, the second connection structure, and the third connection structure are arranged in a Z shape; Alternatively, the first connection structure, the second connection structure, and the third connection structure are arranged in a zigzag shape.

19. An electronic device, characterized in that: include: A first transmission line, a second transmission line, a first coil, and a second coil; The first coil is coupled to the first transmission line, and the second coil is coupled to the second output line; The first coil includes at least one turn of a transverse coil; The second coil includes at least one turn of a vertical coil, and the at least one turn of the vertical coil is wound around the at least one turn of the horizontal coil.

20. The electronic device according to claim 19, characterized in that The first coil and the second coil are inversely inductively coupled.

21. The electronic device according to claim 19 or 20, characterized in that: The first coil includes a plurality of turns of transverse coils distributed in different layers, and the second coil includes a plurality of turns of vertical coils.

22. The electronic device according to any one of claims 19 to 21, characterized in that: The second coil includes: a plurality of upper layer wires, a plurality of lower layer wires, and a plurality of first metal vias; The plurality of upper wires are arranged above the first coil, and the plurality of lower wires are arranged below the first coil; The ends of the multiple upper-layer wires and the multiple lower-layer wires are sequentially connected through the multiple first metal vias to form multiple turns of the vertical coil.

23. The electronic device according to claim 22, characterized in that The electronic device comprises: a plurality of wiring layers and a dielectric layer arranged between two adjacent wiring layers; The plurality of upper layer wires, the plurality of lower layer wires, and the lateral coil are distributed in the plurality of wiring layers.

24. The electronic device according to any one of claims 22 to 23, characterized in that: The plurality of upper-layer lines are located in the same layer, and the plurality of lower-layer lines are located in the same layer.

25. The electronic device according to any one of claims 22 to 24, characterized in that: The plurality of upper layer lines are arranged in parallel, and are arranged in parallel with the plurality of lower layer lines.

26. The electronic device according to any one of claims 21 to 25, characterized in that: The first coil also includes: a plurality of second metal vias; Two adjacent turns of winding wire in the first coil are connected through at least one of the second metal vias.

27. The electronic device according to claim 26, characterized in that The first coil further includes: a plurality of connecting parts; A connecting portion is provided between two adjacent turns of winding wire in the first coil, and the two adjacent turns of winding wire are connected to two ends of the connecting portion through different first metal vias, respectively.

28. A circuit board, characterized in that: Comprising the electronic device according to any one of claims 1 to 27.

29. A chip, characterized in that: Comprising the electronic device according to any one of claims 1 to 27.

30. An electronic device, characterized in that: It comprises a first electronic device and a second electronic device that are interconnected; wherein the first electronic device is an electronic device as claimed in any one of claims 1 to 27; The second electronic device is electrically connected to the first transmission line and the second transmission line in the first electronic device.

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