Photoelectric co-packaging structure and forming method thereof

Abstract

The invention discloses a photoelectric co-packaging structure and a forming method thereof, and the forming method comprises the steps: providing a photon chip which comprises a first surface and a second surface which are opposite, and the first surface is provided with a bonding pad and an optical coupling port located at one side of the bonding pad; forming a protective layer covering the optical coupling port, wherein the protective layer exposes the bonding pad; after the protection layer is formed, forming a first welding bump on the bonding pad; an initial packaging panel is provided, the initial packaging panel comprises a third surface and a fourth surface which are opposite to each other, an electronic chip is arranged in the initial packaging panel, the third surface of the initial packaging panel is provided with a first wiring layer, and the electronic chip is electrically connected with the first wiring layer; inversely mounting the photon chip on the first wiring layer, and welding the first welding bump with the first wiring layer; an optical interface device is installed on one side of the photon chip, and the optical interface device is right opposite to the optical coupling port; and after the optical interface device is installed, the protection layer is removed, and the optical coupling port is exposed. And the optical coupling port is prevented from being damaged and polluted in the whole packaging process.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more particularly to an optoelectronic co-packaging structure and a method for forming the same. Background Technology

[0002] Co-Packaged Optics (CPO) is an advanced optoelectronic integration technology that directly integrates a light engine or photonic integrated circuit (PIC) with an electronic integrated circuit (EIC) within the same package.

[0003] In the optoelectronic co-packaging process, the optical coupling port (or optical port) of photonic chips, especially the optical coupling port of indium phosphide-based photonic chips, faces two major issues: Vulnerability: Indium phosphide material has low hardness (Krüger hardness is only 537) and high brittleness. During the packaging process, grinding, cleaning, welding and other processes are very prone to microcracks or cleavage fractures due to mechanical stress, which can lead to the scrapping of photonic chips.

[0004] Contamination risk: When the optical coupling port is exposed, dust particles, metal debris or chemical solvents in the environment can easily penetrate the waveguide structure, causing an increase in light scattering loss (typical value >1dB), which is especially significant in non-hermetic environments. Summary of the Invention

[0005] The purpose of this application is to provide an optoelectronic co-packaging structure and a method for forming the same, so as to prevent damage and contamination of the optical coupling port during the entire packaging process. To achieve the above objectives, embodiments of this application provide a method for forming an optoelectronic co-packaging structure, including: A photonic chip is provided, the photonic chip including opposing first and second surfaces, the first surface having pads and an optical coupling port located on one side of the pads; A protective layer is formed covering the optical coupling port, the protective layer exposing the pads; After the protective layer is formed, a first solder bump is formed on the solder pad; An initial package panel is provided, the initial package panel including opposing third and fourth surfaces, an electronic chip is provided in the initial package panel, the third surface of the initial package panel has a first wiring layer, and the electronic chip is electrically connected to the first wiring layer; The photonic chip is flip-chipped onto the first wiring layer, and the first welding bump is welded to the first wiring layer. An optical interface device is installed on one side of the photonic chip, and the optical interface device is directly opposite the optical coupling port. After installing the optical interface device, remove the protective layer to expose the optical coupling port.

[0006] In some embodiments of this application, the material of the protective layer includes thermosetting polyimide resin or photocurable epoxy resin.

[0007] In some embodiments of this application, the viscosity range of the thermosetting polyimide resin or the photocurable epoxy resin is 50 cP - 200 cP, and the thickness range is 20 μm - 50 μm.

[0008] In some embodiments of this application, the process for forming the protective layer includes inkjet printing or micro-dispensing.

[0009] In some embodiments of this application, after the protective layer is formed, the protective layer is further cured.

[0010] In some embodiments of this application, when the material of the protective layer includes thermosetting polyimide resin, the curing temperature is 170℃-190℃ and the curing time is 25min-35min.

[0011] In some embodiments of this application, when the material of the protective layer includes a thermosetting polyimide resin, the curing is performed by exposure to 365nm UV light.

[0012] In some embodiments of this application, the protective layer is removed using a plasma desmearing process. The plasma desmearing process uses a gas mixture of O2 and CF4, with the volume ratio of O2 to CF4 ranging from 5:1 to 3:1, and the plasma energy is ≤100eV.

[0013] In some embodiments of this application, during the plasma stripping process, an endpoint detection system is used to monitor the remaining thickness of the protective layer to ensure that the stripping stops at the surface of the optical coupling port.

[0014] In some embodiments of this application, the protective layer includes a central region and an edge region surrounding the central region, the edge region having an annular groove.

[0015] In some embodiments of this application, the width of the annular groove is 4μm-6μm.

[0016] In some embodiments of this application, silica nanoparticles are added to the thermosetting polyimide resin or the photocurable epoxy resin, and the particle size of the silica nanoparticles is less than 100 nm.

[0017] In some embodiments of this application, the material of the protective layer further includes photoresist; The protective layer can be removed using adhesive remover or laser removal.

[0018] In some embodiments of this application, the first welding bump includes a metal bump located on the pad and a solder ball located on the top surface of the metal bump.

[0019] In some embodiments of this application, the process of forming a first solder bump on the solder pad after forming the protective layer includes: A conductive layer is formed on the surface of the protective layer, the surface of the pads, and the first surface between the pads; A photoresist layer is formed on the conductive layer; An opening is formed in the photoresist layer, and the opening exposes a portion of the conductive layer on the pad. The opening is filled with metal to form the metal bump; Remove the photoresist layer and etch away the conductive layers on both sides of the metal bump; The solder ball is formed on the top surface of the metal bump.

[0020] In some embodiments of this application, the initial encapsulation panel includes a first molding layer, the first molding layer including the opposing third and fourth surfaces; The electronic chip is located in the first molding layer; A first wiring layer is formed on the third surface of the first molding layer.

[0021] In some embodiments of this application, a second wiring layer is formed on the fourth surface of the first molding compound, and the electronic chip is also electrically connected to the second wiring layer; A second solder bump electrically connected to the second wiring layer is formed on the second wiring layer.

[0022] In some embodiments of this application, a first metal pillar is further provided in the first molding compound layer on one side or around the electronic chip, and the two ends of the first metal pillar are electrically connected to the first wiring layer and the second wiring layer, respectively. The number of electronic chips is one or more.

[0023] In some embodiments of this application, the optical coupling port is located at the edge of the photonic chip; It also includes: attaching a heat sink to the second surface of the photonic chip, a portion of the heat sink extending beyond the edge of the photonic chip having an optical coupling port, and mounting the optical interface device on the bottom surface of the extended portion of the heat sink.

[0024] In some embodiments of this application, the optical coupling port includes a grating coupling port or an end-face coupling port; The optical interface device includes a fiber optic interface connector or a laser connector.

[0025] This application also provides an optoelectronic co-packaging structure, including: A photonic chip, comprising a first surface and a second surface opposite to each other, the first surface having pads and an optical coupling port located on one side of the pads; a first solder bump located on the pads; and a protective layer covering the optical coupling port; An initial package panel, the initial package panel including opposing third and fourth surfaces, the initial package panel having an electronic chip, the third surface of the initial package panel having a first wiring layer, the electronic chip being electrically connected to the first wiring layer; The photonic chip is flip-chip mounted on the first wiring layer, and the first welding bump is welded to the first wiring layer. An optical interface device is located on one side of the photonic chip, and the optical interface device is directly opposite the optical coupling port.

[0026] This application also provides a method for forming an optoelectronic co-packaging structure, including: A photonic chip is provided, the photonic chip including opposing first and second surfaces, the first surface having pads and an optical coupling port located on one side of the pads, and a groove located on one side of the optical coupling port; A protective layer is formed covering the optical coupling port, the protective layer exposing the pads and the groove; A second molding compound is formed to cover the photonic chip. The second molding compound includes a fifth surface and a sixth surface opposite to each other. The fifth surface exposes the protective layer, the pads, and the grooves. A third wiring layer is formed on the fifth surface of the second molding layer, the third wiring layer being electrically connected to the pads of the photonic chip, and the third wiring layer exposing the protective layer and the groove; An electronic chip is provided, and the electronic chip is flip-chip mounted on the third wiring layer, and the electronic chip is electrically connected to the third wiring layer; An optical interface device is installed in the groove, and the optical interface device is directly opposite the optical coupling port. After installing the optical interface device, remove the protective layer to expose the optical coupling port.

[0027] In some embodiments of this application, the material of the protective layer includes thermosetting polyimide resin or photocurable epoxy resin; The viscosity range of the thermosetting polyimide resin or the photocurable epoxy resin is 50 cP - 200 cP, and the thickness range is 20 μm - 50 μm.

[0028] In some embodiments of this application, the process for forming the protective layer includes inkjet printing or micro-dispensing.

[0029] In some embodiments of this application, the protective layer is removed using a plasma desmearing process. The plasma desmearing process uses a gas mixture of O2 and CF4, with the volume ratio of O2 to CF4 ranging from 5:1 to 3:1, and the plasma energy is ≤100eV.

[0030] In some embodiments of this application, it also includes: When forming the second molding layer covering the photonic chip, the second molding layer also covers a second metal pillar located on one side of the photonic chip; The second metal pillar is electrically connected to the first wiring layer; It also includes: forming a fourth wiring layer on the fifth surface of the second molding layer, the fourth wiring layer being electrically connected to the second metal pillar; A third solder bump electrically connected to the fourth wiring layer is formed on the fourth wiring layer.

[0031] This application also provides an optoelectronic co-packaging structure, including: A photonic chip includes a first surface and a second surface opposite to each other, the first surface having a pad and an optical coupling port located on one side of the pad, and a groove located on one side of the optical coupling port; a protective layer covering the optical coupling port, the protective layer exposing the pad and the groove; A second molding compound covering the photonic chip, the second molding compound including a fifth surface and a sixth surface opposite each other, the fifth surface exposing the protective layer, the pads and the groove; A third wiring layer is located on the fifth surface of the second molding layer, the third wiring layer is electrically connected to the pads of the photonic chip, and the third wiring layer exposes the protective layer and the groove; An electronic chip, wherein the electronic chip is flip-chip mounted on the third wiring layer and is electrically connected to the third wiring layer; An optical interface device is located in the groove, and the optical interface device is directly opposite the optical coupling port.

[0032] The beneficial effects of this application are: The method for forming an optoelectronic co-package structure of this application includes: providing a photonic chip, the photonic chip including opposing first and second surfaces, the first surface having pads and an optical coupling port located on one side of the pads; forming a protective layer covering the optical coupling port, the protective layer exposing the pads; after forming the protective layer, forming a first solder bump on the pads; providing an initial package panel, the initial package panel including opposing third and fourth surfaces, the initial package panel having an electronic chip, the third surface of the initial package panel having a first wiring layer, the electronic chip being electrically connected to the first wiring layer; flip-chip bonding the photonic chip onto the first wiring layer, the first solder bump being soldered to the first wiring layer; mounting an optical interface device on one side of the photonic chip, the optical interface device being directly opposite the optical coupling port; after mounting the optical interface device, removing the protective layer to expose the optical coupling port. In this application, a protective layer covering the optical coupling port is used, and this protective layer is only removed after the optical interface device is installed. Therefore, the protective layer can prevent dust particles, metal debris, or chemical solvents from entering the optical coupling port throughout the packaging process, avoiding contamination of the optical coupling port, ensuring the integrity of the optical coupling port, and thus reducing the light scattering loss of the optical coupling port. Furthermore, the protective layer can also absorb the mechanical stress (such as the pressure and / or thermal stress generated during grinding, cleaning, and soldering) in the subsequent packaging process, thereby preventing microcracks or fractures in the optical coupling port and avoiding damage to the coupling port. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0034] Figure 1 This is a schematic diagram of the process for forming an optoelectronic co-packaging structure provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure after a photonic chip is provided in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 3 This is a schematic diagram of the structure after forming a protective layer covering the optical coupling port in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 4This is a schematic diagram of the structure after forming an annular groove in the edge region of the protective layer in the method of forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure after the photoresist layer is formed in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 6 This is a schematic diagram of the structure after an opening is formed in the photoresist layer in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 7 This is a schematic diagram of the structure after forming metal bumps in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 8 This is a schematic diagram of the structure after solder balls are formed in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 9 This is a schematic diagram of the structure after the initial encapsulation panel is provided in the method for forming the optoelectronic co-encapsulation structure provided in some embodiments of this application; Figure 10 This is a schematic diagram of the structure after flip-chip is flip-chip mounted on the first wiring layer in the method of forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 11 This is a schematic diagram of the structure after installing the optical interface device in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 12 This is a schematic diagram of the structure after removing the protective layer in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 13 This is a schematic diagram of the structure for forming a protective layer and groove in a method for forming an optoelectronic co-packaging structure provided in other embodiments of this application; Figure 14 This is a schematic diagram of the structure after the second molding layer is formed in the method for forming the optoelectronic co-packaging structure provided in some other embodiments of this application; Figure 15 This is a schematic diagram of the structure after the third wiring layer is formed in the method for forming the optoelectronic co-packaging structure provided in some other embodiments of this application; Figure 16 This is a schematic diagram of the structure after the electronic chip is flip-chip mounted on the third wiring layer in the method of forming the optoelectronic co-packaging structure provided in some other embodiments of this application; Figure 17 This is a schematic diagram of the structure after installing the optical interface device in the method for forming the optoelectronic co-packaging structure provided in some other embodiments of this application; Figure 18This is a schematic diagram of the structure after removing the protective layer in the method for forming the optoelectronic co-packaging structure provided in some other embodiments of this application. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0038] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.

[0040] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0041] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0042] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0043] It is understood that in some of the accompanying drawings of this application, adjacent films with the same processing material are drawn as connected to make them resemble the actual structure.

[0044] This application provides a method for forming an optoelectronic co-packaging structure. Figure 1 This is a flowchart illustrating the method for forming an optoelectronic co-packaging structure provided in some embodiments of this application. (Refer to...) Figure 1 The method for forming the optoelectronic co-packaging structure includes the following steps: Step S101: Provide a photonic chip, the photonic chip including a first surface and a second surface opposite each other, the first surface having a pad and an optical coupling port located on one side of the pad; Step S102: Form a protective layer covering the optical coupling port, the protective layer exposing the pad; Step S103: After forming the protective layer, a first welding bump is formed on the solder pad; Step S104: Provide an initial package panel, the initial package panel including opposing third and fourth surfaces, the initial package panel having an electronic chip, the third surface of the initial package panel having a first wiring layer, and the electronic chip being electrically connected to the first wiring layer; Step S105: The photonic chip is flip-chip mounted on the first wiring layer, and the first solder bump is soldered to the first wiring layer; Step S106: Install an optical interface device on one side of the photonic chip, with the optical interface device facing the optical coupling port. Step S107: After installing the optical interface device, remove the protective layer to expose the optical coupling port.

[0045] The method for forming the optoelectronic co-packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0046] First, refer to Figure 1 In conjunction with references Figure 2 In step S101, a photonic chip 100 is provided, the photonic chip 100 including a first surface 11 and a second surface 12 opposite to each other, the first surface 11 having a pad 101 and an optical coupling port 102 located on one side of the pad 101.

[0047] In optoelectronic co-packaged structures, the Photonic Chip (PIC) 100 is the "integrated processing core" of optical signals and a key hub connecting electronic chips (EICs) and optical interface devices (such as fiber optic connectors or laser connectors (LDs)). Essentially, it is a miniaturized chip that integrates traditional discrete optical devices (such as lenses, optical fibers, filters, modulators, etc.) onto a single substrate through micro-nano fabrication processes to achieve functions such as optical signal transmission, wave splitting and combining, modulation / demodulation, switching, amplification, and detection.

[0048] The optical coupling port 102 of the photonic chip 100 is used for efficient optical coupling between the photonic chip 100 and optical interface devices (such as fiber optic connectors or laser connectors (LDs)), solving the mode matching problem between the "in-chip waveguide" and the "external optical interface" and reducing coupling loss. The pads 101 of the photonic chip 100 are used to receive electrical signals (such as control signals) transmitted from the subsequently mounted electronic chip 203 to the photonic chip 100.

[0049] In some embodiments, the number of optical coupling ports 102 can be one or more, and the number of pads 101 can be multiple. The optical coupling ports 102 are located at the edge of the photonic chip 100.

[0050] In some embodiments, the photonic chip 100 may include a substrate 103 and a passivation layer 104 located on the substrate, the pads 101 are isolated from each other by the passivation layer 104, the optical coupling port 102 is formed in the passivation layer and / or on the surface of the substrate 103, and the passivation layer 104 exposes the side and top surfaces of the optical coupling port 102, as well as the top surface of the pads 101.

[0051] In a specific example, the optical coupling port 102 includes a grating coupler (GC) or an edge coupler (EG).

[0052] In a specific example, the substrate 103 is made of silicon (Si), indium phosphide (InP), or silicon nitride (SiN); the pad 101 is made of metal, specifically one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN; and the passivation layer 104 is made of silicon oxide.

[0053] Next, continue to refer to Figure 1 In conjunction with references Figure 3 In step S102, a protective layer 105 is formed covering the optical coupling port 102, and the protective layer 105 exposes the pad 101.

[0054] The protective layer 105 is in direct contact with the optical coupling port 102 and covers the top and sides of the optical coupling port 102. The protective layer 105 is subsequently used when the optical interface device 302 is installed (see reference). Figure 11 The protective layer 105 is removed only after the dust particles, metal debris, or chemical solvents have been removed. Therefore, the protective layer 105 can prevent dust particles, metal debris, or chemical solvents from entering the optical coupling port 102 during the entire subsequent packaging process, thus avoiding contamination of the optical coupling port 102, ensuring the integrity of the optical coupling port 102, and reducing the light scattering loss of the optical coupling port 102. In addition, the protective layer 105 can also absorb the mechanical stress (such as the pressure and / or thermal stress generated during grinding, cleaning, and welding) during the entire subsequent packaging process, thereby preventing the optical coupling port 102 from developing microcracks or breaking, and avoiding damage to the coupling port 102.

[0055] In some embodiments, the protective layer 105 is made of thermosetting polyimide resin or photocurable epoxy resin, thus allowing for simple and accurate formation of the protective layer 105 using inkjet printing or micro-dispensing processes, improving the formation efficiency and positional accuracy of the protective layer 105. Furthermore, the protective layer 105 can be easily and accurately removed using a plasma removal process, avoiding damage to the optical coupling port 102 during removal. Moreover, the thermosetting polyimide resin or photocurable epoxy resin protective layer 105 can better absorb mechanical stress (such as pressure and / or thermal stress generated during grinding, cleaning, and welding) throughout the subsequent encapsulation process, thereby preventing microcracks or fractures in the optical coupling port 102 and avoiding damage to the coupling port 102.

[0056] If the viscosity of the protective layer 105 is too low, the thickness of the formed protective layer 105 will be relatively thin. If the viscosity of the protective layer 105 is too high, bubbles are easily generated in the protective layer 105. Therefore, in some embodiments, the viscosity range of the thermosetting polyimide resin or the photocurable epoxy resin is 50 cP-200 cP, specifically 50 cP, 60 cP, 70 cP, 80 cP, 90 cP, 100 cP, 120 cP, 150 cP, 180 cP, 200 cP, to ensure that no bubble defects are generated in the protective layer 105 when forming the protective layer 105 covering the optical coupling port 102.

[0057] If the thickness of the protective layer 105 is too small, it cannot effectively prevent dust particles, metal debris, or chemical solvents from entering the optical coupling port 102, nor can it effectively absorb the mechanical stress during the subsequent packaging process. If the thickness of the protective layer 105 is too large, it increases the difficulty of forming the protective layer 105 and the difficulty of removing the protective layer 105. Therefore, in some embodiments, the thickness of the formed protective layer 105 is in the range of 20μm-50μm, so that it can more effectively prevent dust particles, metal debris, or chemical solvents from entering the optical coupling port 102 during the subsequent packaging process, and can effectively absorb the mechanical stress (such as the pressure and / or thermal stress generated during grinding, cleaning, and soldering) during the subsequent packaging process, and can facilitate the subsequent removal of the protective layer.

[0058] In some embodiments, after the protective layer 105 is formed, it needs to be cured. In one example, when the material of the protective layer 105 includes a thermosetting polyimide resin, the curing temperature is 170°C-190°C, specifically 170°C, 180°C, or 190°C. The curing time is 25 min-35 min, specifically 25 min, 30 min, or 25 min. In another example, when the material of the protective layer 105 includes a thermosetting polyimide resin, the curing is performed using 365 nm UV light exposure.

[0059] In some embodiments, silica nanoparticles are added to the thermosetting polyimide resin or the photocurable epoxy resin. The silica nanoparticles have a particle size of less than 100 nm to improve the mechanical strength (compressive strength > 50 MPa) of the thermosetting polyimide resin or the photocurable epoxy resin, while reducing the curing shrinkage rate (< 0.1%), so that the formed protective layer 105 has a stronger protective effect and a stronger ability to absorb mechanical stress.

[0060] In other embodiments, the material of the protective layer 105 may also include photoresist; the protective layer 105 may be removed subsequently by photoresist remover or by laser removal.

[0061] In some embodiments, reference Figure 4 The protective layer 105 includes a central region and an edge region surrounding the central region. The edge region has an annular groove 106. When the protective layer 105 is subsequently removed using a plasma stripping process, the annular groove 106 guides the plasma to preferentially etch the central region of the protective layer 105, preventing lateral over-etching. This cleanly removes the protective layer 105 while preventing etching damage to the optical coupling port 102. In a specific example, the width of the annular groove 106 is 4μm-6μm.

[0062] Next, continue to refer to Figure 1 In conjunction with reference 8, after step S103 to form the protective layer 105, a first welding bump (109 and 110) is formed on the pad 101.

[0063] In some embodiments, the first solder bump includes a metal bump 109 located on the pad 101 and solder balls 110 located on the top surface of the metal bump 109. The metal bump 109 is made of metal, specifically one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. The process of forming the metal bump 109 includes electroplating. The solder balls 110 are made of solder, specifically one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony. The process of forming the solder balls 110 includes stencil printing and reflow processes.

[0064] In some embodiments, the process of forming the first welding bump includes: refer to Figure 5 A conductive layer (not shown in the figure) is formed on the surface of the protective layer 105, the surface of the pad 101, and the first surface 11 between the pads 101. The conductive layer can be used as a seed layer and a conductive layer during the electroplating process. A photoresist layer 107 is formed on the conductive layer. In one example, the photoresist layer 107 is formed by a coating process. refer to Figure 6 An opening 108 is formed in the photoresist 107, the opening 108 exposing a portion of the conductive layer on the pad 101. In one example, the opening 108 is formed in the photoresist 107 using an exposure process and a development process. refer to Figure 7 The opening is filled with metal to form the metal bump 109. In one example, the metal is filled in the opening using an electroplating process. refer to Figure 8 The photoresist layer is removed, and the conductive layers on both sides of the metal bump 109 are etched away. The solder balls 110 are formed on the top surface of the metal bump 109. In one example, the solder balls 110 are formed by stencil printing and reflow process. When the photoresist layer is removed, the protective layer 105 is not removed.

[0065] It should be noted that the aforementioned processes are all performed on the wafer. After the solder balls 110 are formed, the wafer can be divided to form multiple discrete photonic chips 100 with first solder bumps.

[0066] Next, continue to refer to Figure 1 In conjunction with references Figure 9In step S104, an initial packaging panel 20 is provided. The initial packaging panel 20 includes a third surface 13 and a fourth surface 14 opposite to each other. An electronic chip 203 is provided in the initial packaging panel 20. The third surface 13 of the initial packaging panel 20 has a first wiring layer 201. The electronic chip 203 is electrically connected to the first wiring layer 201.

[0067] The initial packaged panel 20 is a panel encapsulating an electronic chip 203, and the initial packaged panel 20 can be formed using a fan-out process.

[0068] In some embodiments, continue to refer to Figure 9 The initial encapsulation panel 20 includes a first molding layer 200, which includes the opposing third surface 13 and fourth surface 14. The electronic chip 203 is located in the first molding layer 200; A first wiring layer 201 is formed on the third surface 13 of the first molding layer 200.

[0069] In some embodiments, the method further includes: forming a second wiring layer 202 on the fourth surface 14 of the first molding layer 200, wherein the electronic chip 203 is also electrically connected to the second wiring layer 202; A second solder bump 205 is formed on the second wiring layer 202 and is electrically connected to the second wiring layer 202.

[0070] In some embodiments, the first molding compound 200 on one side or around the electronic chip 203 further includes a first metal pillar 204, the two ends of which are electrically connected to the first wiring layer 201 and the second wiring layer 202, respectively. The number of electronic chips 203 is one or more.

[0071] In some embodiments, the first wiring layer 201 may include a first dielectric layer and a first metal wiring 201a located in the first dielectric layer. The number of layers of the first dielectric layer and the first metal wiring 201a may be single or multiple. In a specific embodiment, the material of the first dielectric layer may be an inorganic material (such as one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, or low dielectric constant materials) or an organic material (resin material, such as ABF resin or resin of other materials). The material of the first metal wiring 201a may be one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. It should be noted that, in this application, the electrical connection between the electronic chip 203 and the metal pillar 204 and the first wiring layer 201 means that the electronic chip 203 and the metal pillar 204 are respectively electrically connected to the corresponding first metal wiring 201a in the first wiring layer 201.

[0072] In some embodiments, the second wiring layer 202 may include a second dielectric layer and a second metal wiring 202a located in the second dielectric layer. The number of layers of the second dielectric layer and the second metal wiring 202a may be single or multiple. In a specific embodiment, the material of the second dielectric layer may be an inorganic material (such as one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, or low dielectric constant materials) or an organic material (resin material, such as ABF resin or resin of other materials). The material of the second metal wiring 202a may be one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. It should be noted that, in this application, the electrical connection between the electronic chip 203 and the metal pillar 204 and the second wiring layer 202 means that the electronic chip 203 and the metal pillar 204 are respectively electrically connected to the corresponding second metal wiring 202a in the second wiring layer 202.

[0073] In some embodiments, the material of the first molding layer 200 may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin with or without fillers; or it may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol with fillers.

[0074] Next, continue to refer to Figure 1 In conjunction with references Figure 10 In step S105, the photonic chip 100 is flip-chip mounted on the first wiring layer 201, and the first welding bumps (109 and 110) are welded to the first wiring layer 201.

[0075] When the photonic chip 100 is flip-chip mounted, the first surface 11 of the photonic chip 100 faces the first wiring layer 201. The bonding of the first solder bumps (109 and 110) to the first wiring layer 201 includes bonding the solder balls 110 in the first solder bumps to the corresponding second metal wirings 202a in the first wiring layer 201.

[0076] Next, continue to refer to Figure 1 In conjunction with references Figure 11 In step S106, an optical interface device 302 is installed on one side of the photonic chip 100, and the optical interface device 302 is directly opposite the optical coupling port 102.

[0077] In some embodiments, the optical interface device 302 includes an optical fiber interface connector or a laser connector.

[0078] In some embodiments, the optical interface device 302 is located at the edge of the photonic chip 100.

[0079] The method also includes: attaching a heat sink 301 to the second surface 12 of the photonic chip 100, a portion of which extends beyond the edge of the photonic chip 100 having the optical coupling port 102; the optical interface device 302 is mounted on the bottom surface of the extended portion of the heat sink 301; and the heat sink, in addition to mounting the optical interface device 302, also serves to dissipate heat from the photonic chip 100. In a specific example, the heat sink 301 is attached to the second surface 12 of the photonic chip 100 using thermally conductive adhesive, and the optical interface device 302 is attached to the bottom surface of the extended portion of the heat sink 301 using thermally conductive adhesive.

[0080] In some embodiments, the method further includes forming an underfill layer between the photonic chip 100 and the first wiring layer 201.

[0081] Finally, refer to Figure 1 In conjunction with references Figure 12 After performing step S107 and installing the optical interface device 302, remove the protective layer 105 (see reference). Figure 11 ), exposing the optical coupling port 102.

[0082] In some embodiments, the protective layer 105 is removed using a plasma stripping process. The plasma stripping process uses a gas mixture of O2 and CF4, with the volume ratio of O2 to CF4 ranging from 5:1 to 3:1. The plasma energy is ≤100eV. These specific parameters help prevent etching damage to the optical coupling port 102.

[0083] In some embodiments, during the plasma resist removal process, an endpoint detection system is used to monitor the remaining thickness of the protective layer 105 to ensure that the resist removal stops on the surface of the optical coupling port 102, which further helps to prevent etching damage to the optical coupling port 102.

[0084] In some embodiments, when the protective layer 105 includes a central region and an edge region surrounding the central region, the edge region has an annular groove 106 (see reference). Figure 4 When the protective layer 105 is removed using a plasma stripping process, the annular groove 106 can guide the plasma to preferentially etch the middle area of ​​the protective layer 105, preventing lateral over-etching. This not only cleanly removes the protective layer 105 but also helps prevent etching damage to the optical coupling port 102.

[0085] In some embodiments, before removing the protective layer 105, the method further includes: forming a second solder bump 205 electrically connected to the second wiring layer 202 on the second wiring layer 202. In a specific example, the second solder bump 205 includes solder balls, or includes a metal bump and solder balls located on top of the metal bump. The electrical connection between the second solder bump 205 and the second wiring layer 202 includes: the second solder bump 205 being electrically connected to a corresponding second metal wiring 202a in the second wiring layer 202.

[0086] This application also provides an optoelectronic co-packaging structure, see reference. Figure 11 ,include: A photonic chip 100 includes a first surface 11 and a second surface 12 opposite to each other. The first surface 11 has a pad 101 and an optical coupling port 102 located on one side of the pad 101; first solder bumps (109 and 110) located on the pad 101; and a protective layer 105 covering the optical coupling port 102. An initial package panel 20 includes opposing third surface 13 and fourth surface 14. An electronic chip 203 is provided in the initial package panel 20. The third surface 13 of the initial package panel 20 has a first wiring layer 201. The electronic chip 203 is electrically connected to the first wiring layer 301. The photonic chip 100 is flip-chip mounted on the first wiring layer 201, and the first welding bumps (109 and 110) are welded to the first wiring layer 201. An optical interface device 302 is located on one side of the photonic chip 100, and the optical interface device 302 is directly opposite the optical coupling port 102.

[0087] It should be noted that the same or similar limitations or descriptions in this embodiment (optoelectronic co-packaging structure) as those in the foregoing embodiment (method for forming optoelectronic co-packaging structure) will not be repeated in this embodiment. Please refer to the corresponding limitations or descriptions in the foregoing embodiments for details.

[0088] Another embodiment of this application provides a method for forming an optoelectronic co-package structure. The main difference between this embodiment and the previous embodiment is that the photonic chip 100 is packaged below the electronic chip 203. The following embodiments, in conjunction with the appendix... Figure 13 - Appendix Figure 18 The formation process of the optoelectronic co-packaging structure is described in detail.

[0089] refer to Figure 13 A photonic chip 100 is provided, the photonic chip 100 includes a first surface 11 and a second surface 12 opposite to each other, the first surface 11 having a pad 101 and an optical coupling port 102 located on one side of the pad 101, and a groove 112 located on one side of the optical coupling port 102.

[0090] In some embodiments, the photonic chip 100 may include a substrate 103 and a passivation layer 104 located on the substrate. The pads 101 are isolated from each other by the passivation layer 104. The optical coupling port 102 is formed in the passivation layer and / or on the surface of the substrate 103. The passivation layer 104 exposes the side and top surfaces of the optical coupling port 102, as well as the top surface of the pads 101. The groove 112 is subsequently used to mount the optical interface device 302. The side of the groove 112 exposes the side of the optical coupling port 102. The groove 112 is located in the passivation layer 104 on one side of the optical coupling port 102, or the groove 112 is located in the passivation layer 104 and part of the substrate 103 on one side of the optical coupling port 102.

[0091] In a specific example, the optical coupling port 102 includes a grating coupler (GC) or an edge coupler (EG).

[0092] In a specific example, the substrate 103 is made of silicon (Si), indium phosphide (InP), or silicon nitride (SiN); the pad 101 is made of metal, specifically one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN; and the passivation layer 104 is made of silicon oxide.

[0093] Continue to refer to Figure 13 A protective layer 105 is formed covering the optical coupling port 102, the protective layer 105 exposing the pad 101 and the groove 112.

[0094] The protective layer 105 is in direct contact with the optical coupling port 102 and covers the top and sides of the optical coupling port 102. The protective layer 105 is subsequently used when the optical interface device 302 is installed (see reference). Figure 17 The protective layer 105 is removed only after the dust particles, metal debris, or chemical solvents have been removed. Therefore, the protective layer 105 can prevent dust particles, metal debris, or chemical solvents from entering the optical coupling port 102 during the entire subsequent packaging process, thus avoiding contamination of the optical coupling port 102, ensuring the integrity of the optical coupling port 102, and reducing the light scattering loss of the optical coupling port 102. In addition, the protective layer 105 can also absorb the mechanical stress (such as the pressure and / or thermal stress generated during grinding, cleaning, and welding) during the entire subsequent packaging process, thereby preventing the optical coupling port 102 from developing microcracks or breaking, and avoiding damage to the coupling port 102.

[0095] In some embodiments, the material of the protective layer 105 includes thermosetting polyimide resin or photocurable epoxy resin, thus the protective layer 105 can be formed easily and accurately using inkjet printing or micro-dispensing head dispensing processes, improving the formation efficiency and positional accuracy of the protective layer 105. Furthermore, the protective layer can be removed easily and accurately using a plasma removal process, avoiding damage to the optical coupling port 102 when removing the protective layer 105.

[0096] In some embodiments, after the protective layer 105 is formed, it needs to be cured. In one example, when the material of the protective layer 105 includes a thermosetting polyimide resin, the curing temperature is 170°C-190°C, specifically 170°C, 180°C, or 190°C. The curing time is 25 min-35 min, specifically 25 min, 30 min, or 25 min. In another example, when the material of the protective layer 105 includes a thermosetting polyimide resin, the curing is performed using 365 nm UV light exposure.

[0097] In some embodiments, silica nanoparticles are added to the thermosetting polyimide resin or the photocurable epoxy resin. The silica nanoparticles have a particle size of less than 100 nm to improve the mechanical strength (compressive strength > 50 MPa) of the thermosetting polyimide resin or the photocurable epoxy resin, while reducing the curing shrinkage rate (< 0.1%), so that the formed protective layer 105 has a stronger protective effect and a stronger ability to absorb mechanical stress.

[0098] In other embodiments, the material of the protective layer 105 may also include photoresist; the protective layer 105 may be removed subsequently by photoresist remover or by laser removal.

[0099] refer to Figure 14 A second molding compound 113 is formed to cover the photonic chip 100. The second molding compound 113 includes a fifth surface and a sixth surface opposite to each other. The fifth surface exposes the protective layer 105, the pads 101 and the grooves 112.

[0100] In some embodiments, the material of the second molding layer 113 may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin with or without fillers; or it may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyimide, ethylene-vinyl acetate copolymer or polyvinyl alcohol with fillers.

[0101] In some embodiments, the method further includes: when forming a second molding layer 113 covering the photonic chip 100, the second molding layer 113 also covers a second metal pillar 117 located on one side of the photonic chip 100.

[0102] refer to Figure 15 A third wiring layer 114 is formed on the fifth surface of the second molding layer 113. The third wiring layer 114 is electrically connected to the pads 101 of the photonic chip 100. The third wiring layer 114 exposes the protective layer 105 and the groove 112.

[0103] In some embodiments, the third wiring layer 114 may include a third dielectric layer and a third metal wiring 114a located in the third dielectric layer. The number of layers of the third dielectric layer and the third metal wiring 114a may be single or multiple. In a specific embodiment, the material of the third dielectric layer may be an inorganic material (such as one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, or low dielectric constant materials) or an organic material (resin material, such as ABF resin or resin of other materials). The material of the third metal wiring 114a may be one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. It should be noted that, in this application, the electrical connection between the photonic chip 100 and the third wiring layer 114 means that the pads 101 on the photonic chip 100 are electrically connected to the corresponding third metal wiring 114a in the third wiring layer 114.

[0104] In some embodiments, when the second molding layer 113 further includes a second metal pillar 117, the second metal pillar 117 is electrically connected to the first wiring layer 114. It also includes: forming a fourth wiring layer 115 on the fifth surface of the second molding layer 113, the fourth wiring layer 115 being electrically connected to the second metal pillar 117.

[0105] In some embodiments, the fourth wiring layer 115 may include a fourth dielectric layer and a fourth metal wiring 115a located in the fourth dielectric layer. The fourth dielectric layer and the fourth metal wiring 115a may be a single layer or multiple layers. In a specific embodiment, the material of the fourth dielectric layer may be an inorganic material (such as one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, or low dielectric constant materials) or an organic material (resin material, such as ABF resin or resin of other materials). The material of the fourth metal wiring 115a may be one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. It should be noted that, in this application, the electrical connection between the photonic chip 100 and the second metal pillar 117 and the fourth wiring layer 115 means that the photonic chip 100 may also have a through-hole connection structure, one end of the through-hole connection structure exposed on the second surface 12 is electrically connected to the corresponding fourth metal wiring 115a in the fourth wiring layer 115, and the second metal pillar 117 is electrically connected to the corresponding fourth metal wiring 115a in the fourth wiring layer 115. It should also be noted that, before forming the fourth wiring layer 115, a masking process can be performed on the sixth surface of the second molding layer 113 to expose one end surface of the second metal pillar 117 and the second surface 12 of the photonic chip 103.

[0106] refer to Figure 16 An electronic chip 203 is provided, and the electronic chip 203 is flip-chip mounted on the third wiring layer 114, and the electronic chip 203 is electrically connected to the third wiring layer 114.

[0107] The electrical connection between the electronic chip 203 and the third wiring layer 114 includes: the port on the electronic chip 203 is soldered to the corresponding third metal wiring 114a in the third wiring layer 114 using solder.

[0108] refer to Figure 17 An optical interface device 302 is installed in the groove 112, and the optical interface device 302 is directly opposite the optical coupling port 102.

[0109] The bottom end of the optical interface device 302 is installed in the groove 112 with adhesive.

[0110] refer to Figure 18 After installing the optical interface device 302, remove the protective layer 105 to expose the optical coupling port 102.

[0111] In some embodiments, the protective layer 105 is removed using a plasma desmearing process. The plasma desmearing process uses a gas mixture of O2 and CF4, with the volume ratio of O2 to CF4 ranging from 5:1 to 3:1, and the plasma energy is ≤100eV.

[0112] In some embodiments, before removing the protective layer 105, the method further includes forming a third solder bump 116 electrically connected to the fourth wiring layer 115. In a specific example, the third solder bump 116 includes solder balls, or includes a metal bump and solder balls located on top of the metal bump. The electrical connection between the third solder bump 116 and the fourth wiring layer 115 includes the third solder bump 116 being electrically connected to a corresponding third metal wiring 115a in the fourth wiring layer 115.

[0113] Other embodiments of this application also provide an optoelectronic co-packaging structure, see reference. Figure 17 ,include: A photonic chip 100 includes a first surface 11 and a second surface 12 opposite to each other. The first surface 11 has a pad 101 and an optical coupling port 102 located on one side of the pad 101, and a groove 112 located on one side of the optical coupling port 102. A protective layer 105 covers the optical coupling port 102, and the protective layer 105 exposes the pad 101 and the groove 112. A second molding compound 113 covers the photonic chip 100. The second molding compound 113 includes a fifth surface and a sixth surface opposite to each other. The fifth surface exposes the protective layer 105, the pads 101 and the grooves 112. A third wiring layer 114 is located on the fifth surface of the second molding layer 113. The third wiring layer 114 is electrically connected to the pad 101 of the photonic chip 100. The third wiring layer 114 exposes the protective layer 105 and the groove 112. Electronic chip 203, which is flip-chip mounted on the third wiring layer 114 and electrically connected to the third wiring layer 114; The optical interface device 302 is located in the groove 112 and is directly opposite the optical coupling port 102.

[0114] It should be noted that the same or similar limitations or descriptions in this embodiment (optoelectronic co-packaging structure) as those in the foregoing embodiment (method for forming optoelectronic co-packaging structure) will not be repeated in this embodiment. Please refer to the corresponding limitations or descriptions in the foregoing embodiments for details.

[0115] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0116] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0117] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming an optoelectronic co-packaging structure, characterized in that, include: A photonic chip is provided, the photonic chip including opposing first and second surfaces, the first surface having pads and an optical coupling port located on one side of the pads; A protective layer is formed covering the optical coupling port, the protective layer exposing the pads; After the protective layer is formed, a first solder bump is formed on the solder pad; An initial package panel is provided, the initial package panel including opposing third and fourth surfaces, an electronic chip is provided in the initial package panel, the third surface of the initial package panel has a first wiring layer, and the electronic chip is electrically connected to the first wiring layer; The photonic chip is flip-chipped onto the first wiring layer, and the first welding bump is welded to the first wiring layer. An optical interface device is installed on one side of the photonic chip, and the optical interface device is directly opposite the optical coupling port. After installing the optical interface device, remove the protective layer to expose the optical coupling port.

2. The method for forming the optoelectronic co-packaging structure according to claim 1, characterized in that, The material of the protective layer includes thermosetting polyimide resin or photocurable epoxy resin.

3. The method for forming the optoelectronic co-packaging structure according to claim 2, characterized in that, The viscosity range of the thermosetting polyimide resin or the photocurable epoxy resin is 50 cP - 200 cP, and the thickness range is 20 μm - 50 μm.

4. The method for forming the optoelectronic co-packaging structure according to claim 3, characterized in that, The process for forming the protective layer includes inkjet printing or micro-dispensing.

5. The method for forming the optoelectronic co-packaging structure according to claim 4, characterized in that, After the protective layer is formed, the process also includes curing the protective layer.

6. The method for forming an optoelectronic co-packaging structure according to claim 5, characterized in that, When the material of the protective layer includes thermosetting polyimide resin, the curing temperature is 170℃-190℃ and the curing time is 25min-35min.

7. The method for forming an optoelectronic co-packaging structure according to claim 5, characterized in that, When the material of the protective layer includes a thermosetting polyimide resin, the curing is performed by exposure to 365nm UV light.

8. The method for forming an optoelectronic co-packaging structure according to claim 2, characterized in that, The protective layer is removed using a plasma desmearing process. The plasma desmearing process uses a mixture of O2 and CF4 gases, with the volume ratio of O2 to CF4 ranging from 5:1 to 3:1, and the plasma energy is ≤100eV.

9. The method for forming an optoelectronic co-packaging structure according to claim 8, characterized in that, During the plasma debonding process, an endpoint detection system is used to monitor the remaining thickness of the protective layer to ensure that the debonding stops at the surface of the optical coupling port.

10. The method for forming an optoelectronic co-packaging structure according to claim 8, characterized in that, The protective layer includes a central region and an edge region surrounding the central region, the edge region having an annular groove.

11. The method for forming an optoelectronic co-packaging structure according to claim 10, characterized in that, The width of the annular groove is 4μm-6μm.

12. The method for forming an optoelectronic co-packaging structure according to claim 2, characterized in that, The thermosetting polyimide resin or the photocurable epoxy resin contains silica nanoparticles, the particle size of which is less than 100 nm.

13. The method for forming an optoelectronic co-packaging structure according to claim 1, characterized in that, The protective layer also includes photoresist; The protective layer can be removed using adhesive remover or laser removal.

14. The method for forming an optoelectronic co-packaging structure according to claim 1, characterized in that, The first welding bump includes a metal bump located on the pad and a solder ball located on the top surface of the metal bump.

15. The method for forming an optoelectronic co-packaging structure according to claim 1, characterized in that, The initial encapsulation panel includes a first molding layer, the first molding layer including the opposing third and fourth surfaces; The electronic chip is located in the first molding layer; A first wiring layer is formed on the third surface of the first molding layer.

16. The method for forming an optoelectronic co-packaging structure according to claim 15, characterized in that, A second wiring layer is formed on the fourth surface of the first molding layer, and the electronic chip is also electrically connected to the second wiring layer; A second solder bump electrically connected to the second wiring layer is formed on the second wiring layer.

17. The method for forming an optoelectronic co-packaging structure according to claim 16, characterized in that, The first molding compound on one side or around the electronic chip also has a first metal pillar, the two ends of which are electrically connected to the first wiring layer and the second wiring layer, respectively. The number of electronic chips is one or more.

18. The method for forming an optoelectronic co-packaging structure according to claim 1, characterized in that, The optical coupling port is located at the edge of the photonic chip; It also includes: attaching a heat sink to the second surface of the photonic chip, a portion of the heat sink extending beyond the edge of the photonic chip having an optical coupling port, and mounting the optical interface device on the bottom surface of the extended portion of the heat sink.

19. The method for forming an optoelectronic co-packaging structure according to claim 1 or 18, characterized in that, The optical coupling port includes a grating coupling port or an end face coupling port; The optical interface device includes a fiber optic interface connector or a laser connector.

20. A photoelectric co-packaging structure, characterized in that, include: A photonic chip, comprising a first surface and a second surface opposite to each other, the first surface having pads and an optical coupling port located on one side of the pads; a first solder bump located on the pads; and a protective layer covering the optical coupling port; An initial package panel, the initial package panel including opposing third and fourth surfaces, the initial package panel having an electronic chip, the third surface of the initial package panel having a first wiring layer, the electronic chip being electrically connected to the first wiring layer; The photonic chip is flip-chip mounted on the first wiring layer, and the first welding bump is welded to the first wiring layer. An optical interface device is located on one side of the photonic chip, and the optical interface device is directly opposite the optical coupling port.

21. A method for forming an optoelectronic co-packaging structure, characterized in that, include: A photonic chip is provided, the photonic chip including opposing first and second surfaces, the first surface having pads and an optical coupling port located on one side of the pads, and a groove located on one side of the optical coupling port; A protective layer is formed covering the optical coupling port, the protective layer exposing the pads and the groove; A second molding compound is formed to cover the photonic chip. The second molding compound includes a fifth surface and a sixth surface opposite to each other. The fifth surface exposes the protective layer, the pads, and the grooves. A third wiring layer is formed on the fifth surface of the second molding layer, the third wiring layer being electrically connected to the pads of the photonic chip, and the third wiring layer exposing the protective layer and the groove; An electronic chip is provided, and the electronic chip is flip-chip mounted on the third wiring layer, and the electronic chip is electrically connected to the third wiring layer; An optical interface device is installed in the groove, and the optical interface device is directly opposite the optical coupling port. After installing the optical interface device, remove the protective layer to expose the optical coupling port.

22. The method for forming an optoelectronic co-packaging structure according to claim 21, characterized in that, The material of the protective layer includes thermosetting polyimide resin or photocurable epoxy resin; The viscosity range of the thermosetting polyimide resin or the photocurable epoxy resin is 50 cP - 200 cP, and the thickness range is 20 μm - 50 μm.

23. The method for forming an optoelectronic co-packaging structure according to claim 21, characterized in that, Also includes: When forming the second molding layer covering the photonic chip, the second molding layer also covers a second metal pillar located on one side of the photonic chip; The second metal pillar is electrically connected to the first wiring layer; It also includes: forming a fourth wiring layer on the fifth surface of the second molding layer, the fourth wiring layer being electrically connected to the second metal pillar; A third solder bump electrically connected to the fourth wiring layer is formed on the fourth wiring layer.

24. A photoelectric co-packaging structure, characterized in that, include: A photonic chip includes a first surface and a second surface opposite to each other, the first surface having a pad and an optical coupling port located on one side of the pad, and a groove located on one side of the optical coupling port; a protective layer covering the optical coupling port, the protective layer exposing the pad and the groove; A second molding compound covering the photonic chip, the second molding compound including a fifth surface and a sixth surface opposite each other, the fifth surface exposing the protective layer, the pads and the groove; A third wiring layer is located on the fifth surface of the second molding layer, the third wiring layer is electrically connected to the pads of the photonic chip, and the third wiring layer exposes the protective layer and the groove; An electronic chip, wherein the electronic chip is flip-chip mounted on the third wiring layer and is electrically connected to the third wiring layer; An optical interface device is located in the groove, and the optical interface device is directly opposite the optical coupling port.

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