Synchronous rectification simulation backflow solving method
By predicting backflow risk, modulating pre-shutdown impedance, and using dynamic time window shielding, combined with system-level timing interlocking, the problem of current backflow in synchronous rectification is solved, achieving efficient and reliable synchronous rectification and improving system stability and safety.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MIX DESIGN SEMICON TECH LTD
- Filing Date
- 2025-12-11
- Publication Date
- 2026-05-05
AI Technical Summary
In synchronous rectification technology, the phenomenon of current backflow leads to energy recovery, increased losses, voltage ringing, and device overstress damage. Traditional solutions are difficult to adapt to a wide range of load variations and may affect efficiency.
By predicting backflow risk, modulating pre-shutdown impedance, using dynamic time window shielding, and implementing system-level timing interlocking, the synchronous rectifier switch achieves adaptive shutdown and interlocking, preventing current backflow and accidental start-up.
It effectively prevents backflow of current, reduces losses, improves system stability and safety, adapts to a wide load range and variable operating conditions, and avoids accidental activation and common circuit phenomena.
Smart Images
Figure CN121984331A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of synchronous rectification technology, and in particular to a solution for synchronous rectification simulation backflow. Background Technology
[0002] In modern switching power supplies, especially high-frequency and high-efficiency AC-DC or DC-DC converters, synchronous rectification technology has become a key means to improve efficiency. It uses power MOSFETs with extremely low on-resistance to replace traditional Schottky diodes as rectifier devices, thereby significantly reducing secondary-side conduction losses and improving overall efficiency. However, while synchronous rectification brings efficiency advantages, it also introduces technical challenges that traditional diode rectification does not have. One of the most prominent problems is current backflow.
[0003] Current backflow typically refers to the phenomenon where, under specific operating conditions, current flows in the opposite direction into the synchronous rectifier switch, causing energy to abnormally flow back from the output to the secondary winding of the transformer. This phenomenon not only causes additional losses and reduces system efficiency, but may also lead to severe voltage ringing, electromagnetic interference, and even overstress damage to components, seriously threatening the reliability and stability of the power supply.
[0004] The risk of backflow is particularly prominent in the following two typical scenarios: First, in continuous conduction mode (CCM) or under heavy load conditions, when the control logic decides to turn off the synchronous rectifier switch, if it is in the "deep linear region" where it is conducting with a large current and the voltage drop is extremely low, the rapid turn-off will cause the channel providing the freewheeling path for the inductor current to suddenly disappear. The rapidly changing current will induce high-frequency oscillations on the circuit parasitic parameters and create huge current and voltage stresses on the body diode or parasitic capacitance of the switch, which manifests as severe voltage spikes and ringing. Second, during the turn-off process and the subsequent ringing stage, the violent fluctuations in the drain-source voltage of the switch can easily exceed the turn-on threshold of the synchronous rectifier controller, causing the switch to be turned on erroneously, forming an unexpected turn-on pulse. This will not only exacerbate backflow, but may also cause the "common" phenomenon where the primary-side main switch and the secondary-side synchronous rectifier switch are turned on simultaneously, resulting in a direct energy short circuit and burning out the device.
[0005] Traditional solutions often have limitations. For example, simply optimizing the turn-off timing or setting a fixed dead time is difficult to adapt to a wide range of load variations. While reducing the turn-off speed can slow down the rate of current change, it will increase turn-off losses and offset the efficiency advantages of synchronous rectification. In addition, using a fixed ringing shielding window may result in insufficient or excessive shielding because it cannot match the actual ringing duration. The former cannot effectively prevent false turn-on, while the latter will sacrifice effective conduction time and affect efficiency. Summary of the Invention
[0006] To address the aforementioned problems, this application provides a synchronous rectification simulation backflow solution.
[0007] This application provides a synchronous rectification simulation backflow solution, which adopts the following technical solution: A synchronous rectification simulation backflow solution includes the following steps: Step 1: Backflow risk prediction. At the turn-off decision moment of the synchronous rectifier switch, the instantaneous values of its drain-source voltage Vds and current Ids are detected simultaneously. If the conditions are met that Vds is lower than a preset low-voltage threshold and Ids is higher than a preset current threshold, it is determined that there is a high backflow risk scenario. Then, pre-turn-off impedance modulation is started and its modulation depth is adaptively enhanced. Otherwise, the normal turn-off logic is executed.
[0008] As a preferred technical solution of this application, when the backflow risk prediction step determines that a high backflow risk scenario exists, the following steps are executed sequentially: Step 2, pre-turn-off impedance modulation: after determining that the synchronous rectifier switch needs to be turned off and before it is completely turned off, the gate drive voltage is controlled to drop from the first level to the preset second level. The second level makes the switch work in the critical conduction region, and the conduction resistance increases, thereby naturally suppressing the amplitude and rate of change of potential backflow current during the turn-off delay time. Step 3: Dynamic time window shielding. After the synchronous rectifier switch is completely turned off, a dynamic shielding signal of a preset duration is immediately generated and activated. During the validity period of this signal, any possible synchronous rectifier turn-on signal is unconditionally shielded to prevent false turn-on caused by turn-off ringing. Step four: System-level timing interlock. Based on the duration of the dynamic shielding signal, the minimum turn-off time of the primary-side main switch drive signal is set to ensure that the time interval between any two consecutive turn-on times is not less than the duration of the dynamic shielding signal, thereby achieving mandatory timing interlock between the primary and secondary switches and eliminating common phenomena.
[0009] As a preferred technical solution of this application, the second level is set between 2V and 3V, and the determination is based on the reverse voltage detection of the secondary winding voltage.
[0010] As a preferred technical solution of this application, the duration of the dynamic shielding signal is 3μs to 4μs, and its value is set according to the statistical duration of ringing after shutdown.
[0011] As a preferred technical solution of this application, the system-level timing interlock is indirectly achieved by the primary-side controller through detecting the voltage waveform of the transformer auxiliary winding.
[0012] As a preferred technical solution of this application, the modulation depth is reflected in the rate at which the gate drive voltage drops from the first level to the second level and the specific voltage value of the second level. When the determined reverse current risk level is high, the control voltage drops to a lower second level value at a faster rate, so that the synchronous rectifier switch can enter the high impedance state more quickly.
[0013] As a preferred technical solution of this application, the voltage value of the second level in the pre-turn-off impedance modulation in step two is not a fixed value, but is adaptively adjusted according to the real-time current value flowing through the switch before it is turned off. Specifically, a negative correlation mapping relationship is established between the real-time current value and the target second level voltage value. When the real-time current value before turn-off is larger, the selected second level voltage value is lower, so that the switch can exit the deep linear region more quickly when it is turned off under large current, and the on-resistance is increased more significantly.
[0014] As a preferred technical solution of this application, the preset duration of the dynamic time window shielding in step three is not a fixed value, but is adaptively set according to the ringing characteristic frequency caused by the current change rate di / dt collected in the pre-off impedance modulation stage of step two. Specifically, the oscillation period of the ringing waveform is detected and analyzed, and the duration of the dynamic shielding signal is set to cover multiple cycles of the ringing, and the duration is inversely proportional to the main frequency of the ringing.
[0015] In summary, this application includes at least one of the following beneficial technical effects of the synchronous rectification simulation backflow solution: First, this method achieves proactive prevention and smooth suppression of backflow risk. Through the linkage of "risk prediction" and "pre-shutdown impedance modulation," the switching transistor is placed in the critical conduction region at the initial stage of shutdown, causing its on-resistance to increase naturally. This gently limits the rate of current change, avoiding severe voltage backlash and ringing caused by sudden current changes at the source, effectively protecting the switching transistor. Second, this method has a high degree of adaptive intelligence. Its core parameters (such as the depth of impedance modulation and the duration of the shielding window) are not fixed values, but are dynamically adjusted according to the real-time current before shutdown and the actual ringing frequency after shutdown. This ensures that the solution can maintain high efficiency and reliability under a wide load range and variable operating conditions. Finally, through "dynamic time window shielding" and "system-level timing interlocking," the risks of false start-up and common risks are eliminated. This method not only immunizes against false triggering caused by shutdown ringing, but also forcibly guarantees the interlocking of the primary and secondary switching transistor drives from the system timing perspective, greatly improving the stability and safety of the system. Attached Figure Description
[0016] Figure 1 This is a flowchart of the synchronous rectification simulation backflow solution for this application. Detailed Implementation
[0017] The following is in conjunction with the appendix Figure 1 Further detailed description of this application is provided below.
[0018] Refer to Figure 1 , a method for solving synchronous rectification reverse current, including the following steps: Step 1, reverse current risk prediction: At the turn-off decision moment of the synchronous rectifier switch, synchronously detect the instantaneous values of its drain-source voltage Vds and the flowing current Ids. If the conditions that Vds is lower than a preset low voltage threshold and Ids is higher than a preset current threshold are met, it is determined that there is a high reverse current risk scenario, and then pre-turn-off impedance modulation is started and its modulation depth is adaptively enhanced. Otherwise, the conventional turn-off logic is executed.
[0019] At the turn-off decision moment of the synchronous rectifier switch (hereinafter referred to as the SR switch, usually determined by the turn-on signal of the primary side main switch or the turn-off logic based on the output voltage), synchronously sample its drain-source voltage Vds and the flowing current Ids. This sampling can be achieved through a high-bandwidth differential amplifier and a precision sampling resistor or a current sensor; Preset low voltage threshold (Vds_th): Set as a positive value close to zero, such as 0.5V, to determine whether the SR switch is in a low voltage drop state close to full conduction.
[0020] Preset current threshold (Ids_th): Set as a positive value determined according to the ratio of the rated current of the circuit, such as 10% of the rated output current, to determine whether there is a non-negligible conduction current.
[0021] At the turn-off decision moment, if the sampled Vds < Vds_th and Ids > Ids_th are both established, it is determined that there is a high reverse current risk scenario. The logic of this criterion is that a large current with a low voltage drop means that the SR switch is in the deep linear region. If it is forced to turn off quickly at this moment, the inductor current has nowhere to freewheel, which is extremely likely to cause a violent backrush to the body diode or parasitic capacitance of the SR switch, resulting in serious reverse current and ringing; Once it is determined to be a high risk, the pre-turn-off impedance modulation process is immediately triggered, and an adaptive mechanism is started. The adaptation is reflected in that the greater the amplitude by which Ids exceeds Ids_th, the higher the determined risk level, and the faster the falling rate of the gate voltage and the lower the target second-level voltage value should be set in the subsequent Step 2.
[0022] When the reverse current risk prediction step determines that there is a high reverse current risk scenario, the following steps are executed in sequence: Step 2, pre-turn-off impedance modulation: after determining that the synchronous rectifier switch needs to be turned off and before it is completely turned off, the gate drive voltage is controlled to drop from the first level to the preset second level. The second level makes the switch work in the critical conduction region, and the conduction resistance increases, thereby naturally suppressing the amplitude and rate of change of potential backflow current during the turn-off delay time. After determining that a shutdown is necessary and there is a high risk of backflow, instead of immediately and rapidly pulling the gate drive voltage (Vgs) of the SR switch down from the first level (e.g., 10V to ensure full conduction) to 0V, a two-stage or slope-controlled shutdown process is adopted.
[0023] Fast pull-down phase: Vgs is reduced from the first level at a relatively fast rate (e.g., 1V / ns).
[0024] Impedance modulation stage: When Vgs drops to the preset second level range (between 2V and 3V), the pull-down is paused or the drop becomes extremely slow. This second level needs to be precisely controlled so that the SR switch operates in the critical conduction region (the transition zone between the linear region and the saturation region), and its on-resistance (Rds(on)) will increase significantly.
[0025] The second level value (Vgs_mod) is not a fixed value, but a function of the instantaneous current (Ids_pre) before the SR switch turns off. The following negative correlation mapping relationship is established: Vgs_mod = V_max - k * Ids_pre.
[0026] Where V_max is the upper limit of the second level (e.g., 3V), k is a slope coefficient (unit V / A) determined based on the transconductance characteristics of the switching transistor; and Ids_pre is the real-time current value sampled in step one. This algorithm ensures that when turning off a large current, a lower Vgs_mod (e.g., 2V) is used, allowing the switching transistor to exit the low-resistance state more quickly and more effectively limiting the rate of change of current (di / dt). This stage lasts for a preset turn-off delay time (e.g., 100ns). During this period, due to the increased resistance of the SR switch, the freewheeling path impedance of the inductor current increases, which naturally suppresses the current amplitude and its rate of change, thus ensuring a smooth transition and avoiding sudden current changes.
[0027] Step 3: Dynamic time window shielding. After the synchronous rectifier switch is completely turned off, a dynamic shielding signal of a preset duration is immediately generated and activated. During the validity period of this signal, any possible synchronous rectifier turn-on signal is unconditionally shielded to prevent false turn-on caused by turn-off ringing. After the pre-turn-off impedance modulation phase ends, the gate voltage of the SR switch is completely turned off to 0V; then, a programmable delay is immediately started to generate a shield signal (active high) with a validity period of T_blank. T_blank is not a fixed value. In the impedance modulation stage of step two, the ringing waveform is analyzed by using a frequency detection circuit or a digital processor (such as the input capture function of an MCU) to detect the initial stage of the ringing at the drain voltage of the SR switch.
[0028] Ringing characteristic frequency (f_ring) extraction: Measure the time interval between multiple consecutive zero crossings of the ringing waveform and calculate its average period T_ring=1 / f_ring.
[0029] Duration setting algorithm: T_blank = N * T_ring. Where N is an empirical coefficient, typically between 3 and 5, to ensure coverage of the main cycle where ringing energy decays. Therefore, the higher the ringing frequency (the shorter the cycle), the shorter the shielding window T_blank (e.g., 3μs), and vice versa (e.g., 4μs). This algorithm ensures that the shielding time precisely matches the actual ringing duration.
[0030] During the validity period of this T_blank signal, all turn-on logic conditions of the synchronous rectifier controller are blocked. Regardless of whether the detected winding voltage meets the turn-on conditions, the SR switch is prohibited from turning on, thereby preventing false triggering caused by the shutdown ringing.
[0031] Step four: System-level timing interlock. Based on the duration of the dynamic shielding signal, the minimum turn-off time of the primary-side main switch drive signal is set to ensure that the time interval between any two consecutive turn-on times is not less than the duration of the dynamic shielding signal, thereby achieving mandatory timing interlock between the primary and secondary switches and eliminating common phenomena.
[0032] To ensure that the primary-side main switch does not turn on within the shielding window of the SR switch, system-level timing interlocking needs to be implemented.
[0033] Implementation mechanism: The primary-side controller (PWMIC) indirectly senses the secondary-side state by detecting the voltage waveform of the transformer auxiliary winding. When the SR switch is completely turned off, the secondary-side energy is reflected back to the primary side, generating a characteristic voltage waveform on the auxiliary winding. The primary-side controller monitors this waveform and, in conjunction with its own drive logic, implements interlocking.
[0034] The primary-side controller internally sets a minimum turn-off timer (T_off_min); this timer starts when the main switch is turned off; before T_off_min ends, the turn-on command of the main switch is blocked by hardware logic; the set value of T_off_min must be greater than or equal to the duration of the dynamic shielding signal T_blank generated in step three; that is: T_off_min>=T_blank; in this way, the timing ensures that the dynamic shielding window of the secondary-side SR switch falls completely within the turn-off time of the primary-side main switch, and there is absolutely no possibility of the two being turned on simultaneously (common), thus realizing mandatory timing interlocking.
[0035] The second voltage level is set between 2V and 3V, and the determination is based on the reverse voltage detection of the secondary winding.
[0036] The duration of the dynamic shielding signal is 3μs to 4μs, and its value is set according to the statistical duration of ringing after shutdown.
[0037] System-level timing interlocking is indirectly achieved by the primary-side controller through detecting the voltage waveform of the transformer auxiliary winding.
[0038] The modulation depth is reflected in the rate at which the gate drive voltage drops from the first level to the second level and the specific voltage value of the second level. When the determined backflow risk level is high, the control voltage drops to a lower second level value at a faster rate, so that the synchronous rectifier switch can enter the high impedance state more quickly.
[0039] In step two, the pre-turn-off impedance modulation has a second-level voltage value that is not fixed. Instead, it is adaptively adjusted based on the real-time current value flowing through the switch before it is turned off. Specifically, a negative correlation mapping relationship is established between the real-time current value and the target second-level voltage value. The larger the real-time current value before turn-off, the lower the selected second-level voltage value, so that the switch can exit the deep linear region more quickly when subjected to a large current turn-off, and the on-resistance is increased more significantly.
[0040] The preset duration of the dynamic time window shielding in step three is not a fixed value, but is adaptively set according to the ringing characteristic frequency caused by the current change rate di / dt collected in the pre-off impedance modulation stage of step two. Specifically, the oscillation period of the ringing waveform is detected and analyzed, and the duration of the dynamic shielding signal is set to cover multiple cycles of the ringing, and the duration is inversely proportional to the main frequency of the ringing.
[0041] This application begins with step one: backflow risk prediction. At the critical moment of deciding to turn off the synchronous rectifier, the system simultaneously samples its drain-source voltage and current. If it is determined to be a high-risk scenario of "low voltage drop and high current", it means that the switching transistor is in the deep linear region. Forced rapid turn-off will cause a violent backflow of inductor current. This criterion triggers the subsequent fine turn-off procedure, and the higher the risk level, the stronger the subsequent suppression. Next, step two is executed: pre-shutdown impedance modulation; this step is the key to smooth shutdown; the system does not directly turn off the gate voltage to zero, but first pulls it down quickly to a carefully set second level, so that the switch works in the critical conduction region and the on-resistance increases significantly; this level is not a fixed value, but is adaptively adjusted according to the real-time current value before shutdown, so as to more effectively limit the rate of current change when a large current is turned off, thereby achieving gentle energy dissipation and smooth transition; After impedance modulation is completed and the circuit is completely shut down, the process proceeds to step three: dynamic time window shielding. To prevent false turn-on caused by ringing during shutdown, the system generates a shielding signal. Its duration is not a preset fixed value, but is dynamically calculated and set to cover several ringing cycles by detecting the actual voltage ringing frequency generated after shutdown, thereby achieving precise shielding and avoiding efficiency loss or insufficient shielding caused by "one-size-fits-all". Finally, the global closed loop is completed through step four: system-level timing interlocking; the primary-side controller senses the secondary-side status by monitoring the voltage of the transformer auxiliary winding and forcibly sets the minimum turn-off time of its main switch to ensure that the time covers the entire dynamic shielding window of the secondary side; this establishes a mandatory interlocking in terms of system timing, eliminating the fundamental risk of "common" primary and secondary switches.
[0042] First, this method achieves proactive prevention and smooth suppression of backflow risk. Through the linkage of "risk prediction" and "pre-shutdown impedance modulation," the switching transistor is placed in the critical conduction region at the initial stage of shutdown, causing its on-resistance to increase naturally. This gently limits the rate of current change, avoiding severe voltage backlash and ringing caused by sudden current changes at the source, effectively protecting the switching transistor. Second, this method has a high degree of adaptive intelligence. Its core parameters (such as the depth of impedance modulation and the duration of the shielding window) are not fixed values, but are dynamically adjusted according to the real-time current before shutdown and the actual ringing frequency after shutdown. This ensures that the solution can maintain high efficiency and reliability under a wide load range and variable operating conditions. Finally, through "dynamic time window shielding" and "system-level timing interlocking," the risks of false start-up and common risks are eliminated. This method not only immunizes against false triggering caused by shutdown ringing, but also forcibly guarantees the interlocking of the primary and secondary switching transistor drives from the system timing perspective, greatly improving the stability and safety of the system.
[0043] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A synchronous rectification simulation backflow solution, characterized in that, Includes the following steps: Step 1: Backflow risk prediction. At the turn-off decision moment of the synchronous rectifier switch, the instantaneous values of its drain-source voltage Vds and current Ids are detected simultaneously. If the conditions are met that Vds is lower than a preset low-voltage threshold and Ids is higher than a preset current threshold, it is determined that there is a high backflow risk scenario. Then, pre-turn-off impedance modulation is started and its modulation depth is adaptively enhanced. Otherwise, the normal turn-off logic is executed.
2. The synchronous rectification simulation backflow solution according to claim 1, characterized in that, When the backflow risk prediction step determines that a high backflow risk scenario exists, the following steps are executed sequentially: Step 2, pre-turn-off impedance modulation: after determining that the synchronous rectifier switch needs to be turned off and before it is completely turned off, the gate drive voltage is controlled to drop from the first level to the preset second level. The second level makes the switch work in the critical conduction region, and the conduction resistance increases, thereby naturally suppressing the amplitude and rate of change of potential backflow current during the turn-off delay time. Step 3: Dynamic time window shielding. After the synchronous rectifier switch is completely turned off, a dynamic shielding signal of a preset duration is immediately generated and activated. During the validity period of this signal, any possible synchronous rectifier turn-on signal is unconditionally shielded to prevent false turn-on caused by turn-off ringing. Step four: System-level timing interlock. Based on the duration of the dynamic shielding signal, the minimum turn-off time of the primary-side main switch drive signal is set to ensure that the time interval between any two consecutive turn-on times is not less than the duration of the dynamic shielding signal, thereby achieving mandatory timing interlock between the primary and secondary switches and eliminating common phenomena.
3. The synchronous rectification simulation backflow solution according to claim 2, characterized in that, The second voltage level is set between 2V and 3V, and the determination is based on the reverse voltage detection of the secondary winding.
4. The synchronous rectification simulation backflow solution according to claim 2, characterized in that, The duration of the dynamic shielding signal is 3μs to 4μs, and its value is set according to the statistical duration of ringing after shutdown.
5. The synchronous rectification simulation backflow solution according to claim 2, characterized in that, System-level timing interlocking is indirectly achieved by the primary-side controller through detecting the voltage waveform of the transformer auxiliary winding.
6. The synchronous rectification simulation backflow solution according to claim 1, characterized in that, The modulation depth is reflected in the rate at which the gate drive voltage drops from the first level to the second level and the specific voltage value of the second level. When the determined backflow risk level is high, the control voltage drops to a lower second level value at a faster rate, so that the synchronous rectifier switch can enter the high impedance state more quickly.
7. The synchronous rectification simulation backflow solution according to claim 2, characterized in that, In step two, the pre-turn-off impedance modulation has a second-level voltage value that is not fixed. Instead, it is adaptively adjusted based on the real-time current value flowing through the switch before it is turned off. Specifically, a negative correlation mapping relationship is established between the real-time current value and the target second-level voltage value. The larger the real-time current value before turn-off, the lower the selected second-level voltage value, so that the switch can exit the deep linear region more quickly when subjected to a large current turn-off, and the on-resistance is increased more significantly.
8. The synchronous rectification simulation backflow solution according to claim 2, characterized in that, The preset duration of the dynamic time window shielding in step three is not a fixed value, but is adaptively set according to the ringing characteristic frequency caused by the current change rate di / dt collected in the pre-off impedance modulation stage of step two. Specifically, the oscillation period of the ringing waveform is detected and analyzed, and the duration of the dynamic shielding signal is set to cover multiple cycles of the ringing, and the duration is inversely proportional to the main frequency of the ringing.