Internal heating test method, system and equipment of memory chip and storage medium

Abstract

The invention provides an internal heating test method, system and device for a memory chip and a storage medium, and relates to the technical field of semiconductors, and the method comprises the steps: applying an electrical excitation signal to each memory bank of a target memory chip one by one, so as to enable each memory bank to continuously perform characteristic heating in sequence; controlling the temperature observation equipment to sequentially collect the multi-view infrared thermal image set of each memory bank, and recording the collected information; performing image preprocessing and data extraction on the multi-view infrared thermal image set to obtain a temperature data set; performing data association analysis according to the temperature data set and the acquired information to obtain a temperature coordinate association data set; and performing three-dimensional curved surface fitting according to the temperature coordinate associated data set to obtain a temperature distribution model of the target memory chip. The working state of each memory bank is accurately controlled, the accuracy of heat source positioning is remarkably improved, the integrity of a chip structure is effectively maintained while the test accuracy is ensured, and the test efficiency is remarkably improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method, system, device, and storage medium for testing the internal heat generation of a memory chip. Background Technology

[0002] With the continuous improvement of electronic device performance, memory chips, as core components for data exchange and storage, are showing a significant increasing trend in integration and operating frequency, leading to a sharp increase in power consumption density. Internal thermal effects of the chip directly affect signal timing stability, data retention characteristics, and leakage parameters, and in extreme cases, may even induce thermal runaway.

[0003] However, existing temperature monitoring technologies primarily rely on contact sensors on the chip surface or infrared thermal imaging systems. These traditional methods not only suffer from response lag but also, because they can only obtain the average temperature value of the package or chip surface, they cannot penetrate multi-layered structures to accurately measure transient temperature fluctuations in microscale regions within the chip. This makes them unsuitable for providing effective guidance for precise thermal management design and dynamic power consumption control. Therefore, there is an urgent need to address the problem of traditional temperature measurement methods' inability to accurately capture temperature changes in minute areas within memory chips. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, this application provides a method, system, device and storage medium for testing the internal heat of memory chips, which effectively solves the problem that traditional temperature measurement methods are difficult to accurately capture temperature changes in minute areas inside memory chips.

[0005] In a first aspect, this application provides a method for testing the internal heat generation of a memory chip, the method comprising: An electrical excitation signal is applied to each memory cell of the target memory chip in turn, so that each memory cell sequentially and continuously generates characteristic heat. The temperature monitoring device sequentially acquires multi-view infrared thermal images of each of the storage cells and records the acquisition information; Image preprocessing and data extraction are performed on the multi-view infrared thermal image set to obtain a temperature dataset; Based on the temperature dataset and the collected information, a data correlation analysis is performed to obtain a temperature coordinate correlation dataset. A three-dimensional surface fitting is performed based on the temperature coordinate association dataset to obtain the temperature distribution model of the target memory chip.

[0006] In an optional implementation, before applying electrical excitation signals to each memory bank of the target memory chip individually, the method further includes: Layered independent activation is performed on each stacked layer of the target memory chip based on the chip select pin signal.

[0007] In an optional implementation, the step of performing layered independent activation of each stacked layer of the target memory chip based on the chip select pin signal includes: Before applying the electrical excitation signal, the chip select pin signal of the target stacked layer of the target memory chip is set to a high level to activate the target stacked layer. After all memory cells in the target stack layer have been activated, the chip select pin signal of the target stack layer of the target memory chip is set to low level, thus turning off the target stack layer. The stacking layers of the target memory chip are traversed until all stacking layers have been activated and deactivated.

[0008] In an optional implementation, applying electrical excitation signals to each memory cell of the target memory chip sequentially to cause each memory cell to generate characteristic heat in turn includes: Set the reference test voltage of the target memory chip and control the target memory chip to run in pre-charge power saving mode for a preset time; Switch the target memory chip to the target test voltage, activate the target word line of the first target memory bank separately, and repeatedly perform the activation precharge operation until the preset number of cycles are reached; Switch the target memory chip back to the reference test voltage, and re-control the target memory chip to run in the pre-charge power saving mode for the preset duration; Switch the target memory chip to the target test voltage, activate the target word line of the second target memory bank separately, and repeatedly perform the activation precharge operation until the preset number of cycles; Repeatedly execute the voltage switching and pre-charge power-saving mode operation of the target memory chip, traverse and activate each memory cell and repeatedly execute the activation pre-charge operation until all memory cells are activated.

[0009] In an optional implementation, the temperature control observation device sequentially acquires multi-view infrared thermal images of each of the storage cells and records the acquired information, including: The angle adjustment range is determined based on the size information of the target memory chip and the field of view of the lens of the temperature observation device. An angle adjustment interval is set according to the angle adjustment range, and multiple shooting points are determined based on the angle adjustment interval; The temperature observation device is controlled to move to each of the shooting points in turn to acquire images of the activated target storage, thereby obtaining the multi-view infrared thermal image set, and recording the acquisition information for each image acquisition, which includes at least the horizontal angle, vertical angle and acquisition time.

[0010] In an optional implementation, the step of performing image preprocessing and data extraction on the multi-view infrared thermal image set to obtain a temperature dataset includes: The infrared thermal images in the multi-view infrared thermal image set are subjected to noise reduction processing to obtain an initial infrared thermal image; Extract the temperature data of the effective area from the initial infrared thermal image to obtain the initial temperature dataset; The initial temperature dataset is validated for consistency based on the temperature distribution pattern of the target memory chip to obtain the temperature dataset.

[0011] In an optional implementation, the step of performing data correlation analysis based on the temperature dataset and the collected information to obtain a temperature coordinate correlation dataset includes: A three-dimensional Cartesian coordinate system is constructed with the geometric center of the target memory chip as the origin; A first mapping relationship is established between the temperature data of each horizontal angle under the same vertical angle and the three-dimensional rectangular coordinate system to obtain the first normalized data. A second mapping relationship is established between the temperature data of each vertical angle under the same horizontal angle and the three-dimensional rectangular coordinate system to obtain the second normalized data; The first normalized data and the second normalized data are integrated to obtain the temperature coordinate associated dataset.

[0012] Secondly, this application provides an internal heat dissipation testing system for a memory chip, the system comprising: The chip testing module is used to apply electrical excitation signals to each memory cell of the target memory chip one by one, so that each memory cell will continuously generate characteristic heat in sequence; The image acquisition module is used to control the temperature observation device to sequentially acquire multi-view infrared thermal images of each of the storage cells and record the acquisition information; The data processing module is used to perform image preprocessing and data extraction on the multi-view infrared thermal image set to obtain a temperature dataset; The data analysis module is used to perform data correlation analysis based on the temperature dataset and the collected information to obtain a temperature coordinate correlation dataset; The model generation module is used to perform three-dimensional surface fitting based on the temperature coordinate association dataset to obtain the temperature distribution model of the target memory chip.

[0013] Thirdly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the internal heat testing method for the memory chip as described in the first aspect of this application.

[0014] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the internal heat testing method for a memory chip as described in the first aspect of this application.

[0015] The internal heat generation testing method, system, equipment, and storage medium for memory chips provided in this application employ a testing approach combining independent excitation of a single memory cell with sleep mode for multiple memory cells. By precisely controlling the operating state of each memory cell, the thermal crosstalk problem caused by concurrent operation of multiple memory cells is effectively avoided. A one-to-one correspondence between thermal signal characteristics and the physical location of the chip's memory cells is achieved, significantly improving the accuracy of heat source localization. Simultaneously, a three-dimensional thermodynamic model is generated using multi-view observation technology and a three-dimensional surface fitting algorithm. This model can intuitively display the thermodynamic characteristics of key structures such as memory cells in the three-dimensional space of the memory chip, including key parameters such as heat intensity distribution, thermal influence range, and heat conduction path. The testing process uses non-contact, non-destructive testing technology, effectively maintaining the integrity of the chip structure while ensuring testing accuracy. Significant improvements in testing efficiency are achieved through parameter adjustment, image acquisition, and algorithm modeling, providing crucial data support for memory chip architecture optimization, yield improvement, and reliability verification. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a first schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application; Figure 3 This is a third schematic diagram of the internal heat generation test method for memory chips provided in the embodiments of this application; Figure 4 This is the fourth schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application; Figure 5 This is the fifth schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application; Figure 6 This is a schematic diagram of the internal heat dissipation testing system for a memory chip provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0018] Explanation of key component symbols: 200. Internal heat dissipation testing system for memory chips; 210. Chip testing module; 220. Image acquisition module; 230. Data processing module; 240. Data analysis module; 250. Model generation module; 300. Electronic device; 310. Processor; 320. Communication interface; 330. Memory; 340. Communication bus. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be further described clearly and completely below with reference to the accompanying drawings of the embodiments. It should be noted that the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0022] With the rapid iteration of electronic device performance, the integration density and operating frequency of memory chips continue to rise, leading to a sharp increase in their internal power consumption density and increasingly prominent local hotspot issues. Due to limitations in chip packaging technology and the complexity of their internal three-dimensional structures, traditional contact measurement methods such as infrared thermometry or external thermocouples can often only obtain the surface or global average temperature, making it difficult to penetrate the packaging layer and accurately capture transient and subtle temperature gradient changes in the core circuit area. Therefore, there is an urgent need to solve the problem that traditional temperature measurement methods cannot accurately capture temperature changes in subtle areas inside memory chips.

[0023] Example 1 This application provides a method for testing the internal heat generation of a memory chip, effectively solving the problem that traditional temperature measurement methods are unable to accurately capture temperature changes in minute areas inside the memory chip. Figure 1 This is a schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application, as shown below. Figure 1 As shown, the method includes the following steps: S100. Apply electrical excitation signals to each memory cell of the target memory chip one by one, so that each memory cell continuously generates characteristic heat in sequence.

[0024] Understandably, the target memory chip can be either packaged or unpackaged. By applying precise electrical excitation signals to the target memory chip and changing the issued test pattern, different areas within the target memory chip can be made to generate heat. This test pattern refers to a sequence of specific instructions, addresses, and data designed to verify the functionality and electrical characteristics of the target memory chip. The test employs a sequential activation method for each memory cell, using changes in voltage and mode parameters to continuously generate characteristic heat in the target memory cell. Figure 2 This is a second schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application, as shown below. Figure 2 As shown, the memory bank test of the target memory chip specifically includes the following steps: S110. Set the reference test voltage of the target memory chip and control the target memory chip to run in the pre-charge power saving mode for a preset time.

[0025] As an optional implementation of this application, the reference test voltage of the target memory chip can be set to 1.7V, and a test pattern for a pre-charge power-saving mode can be loaded simultaneously. The target memory chip is controlled to enter the pre-charge power-saving mode and run in this mode for a preset duration. This preset duration can be set to be greater than or equal to 10 seconds, and can be set according to actual conditions. After the target memory chip has run in the pre-charge power-saving mode for the preset duration, the various memory cells, peripheral circuits, and packages of the target memory chip reach a complete thermal equilibrium state, eliminating initial temperature differences and transient power consumption fluctuations, and the target memory chip as a whole enters a stable power consumption state.

[0026] Understandably, the infrared thermal image measured at this time can characterize the temperature distribution of the target memory chip under non-selective activation, providing a high signal-to-noise ratio reference baseline for temperature changes generated by subsequent individual memory cell excitation, and ensuring the thermal contrast and spatial distinguishability of memory cell-level heat positioning.

[0027] S120. Switch the target memory chip to the target test voltage, activate the target word line of the first target memory bank separately, and repeatedly perform the activation precharge operation until the preset number of cycles.

[0028] In this embodiment, the target memory chip is switched to a target test voltage, which is greater than the reference test voltage, for example, it can be set to 1.9V. An excitation signal is sent to the first target memory bank to activate the target word line of the first target memory bank individually. For example, the first target memory bank is Bank0, and the word line is the signal line connecting the control terminals of all memory cells in the same row. The target word line can be selected as word line WL0. After the target word line is activated, the first target memory bank Bank0 repeatedly performs the activation pre-charge operation until a preset number of cycles is reached. This preset number of cycles can be set to be greater than or equal to 999 times, thereby forcing the first target memory bank Bank0 to continuously heat up and form a recognizable thermal signal, so that the temperature observation device can collect multi-view infrared thermal images.

[0029] It's understandable that activation and precharge are fundamental pre-operations for memory access. All read and write operations must be completed after activation and before precharge. Essentially, this is to establish or disconnect the path between the memory chip's storage cells and the external data bus, enabling efficient data access. Activation is a row selection instruction. Its core function is to input the address of the memory bank and the row address (i.e., the word line address) to allow the memory chip to select the corresponding memory bank, set the word line of the specified row within that memory bank to a high level, and turn on the transistors of all memory cells in that row, allowing the stored charge of the entire row of memory cells to be read into the row buffer. Precharge is a row deactivation and charge reset instruction. Its core function is to set the already-conducted word lines in the activated memory bank to a low level, disconnecting the path between the memory cell and the bit line. Simultaneously, it writes the data in the row buffer back to the original memory cell (if a write operation occurred), releases the charge from the bit line and the row buffer, and returns the memory bank to an idle state, ready to accept the next activation instruction.

[0030] S130. Switch the target memory chip back to the reference test voltage and re-control the target memory chip to run in the pre-charge power saving mode for a preset time.

[0031] In this embodiment, after activating the first target memory bank Bank0 and acquiring the image, the target memory chip is switched back to the reference test voltage of 1.7V, the test pattern of the pre-charge power saving mode is loaded, the target memory chip is controlled to enter the pre-charge power saving mode, and it runs in the pre-charge power saving mode for a preset duration of 10s, thereby eliminating the residual thermal effect of the first target memory bank Bank0 test and restoring the reference temperature of the target memory chip.

[0032] S140. Switch the target memory chip to the target test voltage, activate the target word line of the second target memory separately, and repeatedly perform the activation precharge operation until the preset number of cycles.

[0033] In this embodiment, after the target memory chip recovers to the reference temperature, the target memory chip is switched back to the target test voltage of 1.9V, and an excitation signal is sent to the second target memory bank Bank1 to individually activate the target word line WL0 of the second target memory bank Bank1. After the target word line WL0 is activated, the second target memory bank Bank1 repeatedly performs the activation pre-charge operation until a preset number of cycles is reached, which is greater than or equal to 999 times. This forces the second target memory bank Bank1 to continuously generate heat and form a recognizable thermal signal, so that the temperature observation equipment can collect multi-view infrared thermal images.

[0034] S150: Repeatedly execute the voltage switching and pre-charge power saving mode operation of the target memory chip, traverse and activate each memory bank and perform the activation pre-charge operation in a loop until all memory banks are activated.

[0035] In this embodiment, after the second target memory Bank1 completes activation and image acquisition, the above steps S110-S140 are repeated to reset the benchmark test voltage, control the target memory chip to run in pre-charge power-saving mode for a preset time, traverse and activate each memory and perform activation pre-charge operation in a loop, so that each memory individually and continuously heats up and forms an identifiable thermal signal, until the acquisition of multi-view infrared thermal images of all memory is completed.

[0036] Based on this, the embodiments of this application adopt a thermal excitation strategy of activating only the target memory bank while keeping the others in a dormant state. Only the target memory bank is activated to perform an activation pre-charge operation, while the remaining memory banks are strictly maintained in a low-power dormant state, thereby ensuring a highly localized spatial distribution of heat sources on the surface of the target memory chip. This strategy fundamentally eliminates the thermal diffusion superposition and signal crosstalk caused by the concurrent heating of multiple memory banks, enabling a strict one-to-one mapping between hotspot locations in the infrared thermal image and the physical memory bank layout. This significantly improves the spatial resolution accuracy and repeatability of heat source localization, providing a reproducible physical basis for accurate thermal modeling, fault location, and dynamic thermal management of high-density memories.

[0037] As a further implementation of this application, if the target memory chip is a vertically stacked chip, the method may further include the following steps before step S100: Layered independent activation is performed on each stacked layer of the target memory chip based on the chip select pin signal.

[0038] In this embodiment, based on the realization of heat source location in the memory cell, a layered decoupling and collaborative timing control mechanism for the chip select pin signal is introduced to achieve precise location of heat sources between layers of vertically stacked memory chips. By configuring an independent and controllable chip select pin signal path for each stacked chip and synchronizing it with the electrical excitation signal at the nanosecond level, chip misactivation or heat signal distortion caused by timing deviations is avoided, ensuring exclusive activation of a single layer, effectively overcoming the problem of inter-layer thermal crosstalk, and supporting the reliability analysis and thermal design optimization of advanced packaged chips. Specifically, the steps include the following: First, before applying the electrical excitation signal, the chip select pin signal of the target stack layer of the target memory chip is set to a high level to activate the target stack layer.

[0039] For example, the activation signal of the target stack layer is to set the chip select pin signal to a high level. This activation signal needs to lead the electrical excitation signal and test voltage by 5~10ns to ensure that the chip select control unit of the target stack layer completes initialization first, and then receives subsequent test commands to activate each memory bank of the target stack layer in sequence.

[0040] After all memory cells in the target stack layer have been activated, the chip select pin signal of the target stack layer controlling the target memory chip is set to low level, thus shutting down the target stack layer.

[0041] For example, after all the memory cells in the target stack layer have been activated and images have been acquired, the electrical excitation signal and test voltage are turned off first, and then the chip select pin signal of the target stack layer is set to low level after a delay of 5~10ns, so as to avoid the target memory chip from generating transient heat due to sudden power failure, which would interfere with the thermal imaging data.

[0042] Finally, iterate through each stack layer of the target memory chip until all stack layers have been activated and deactivated.

[0043] Optionally, a timing analyzer can be used to calibrate the chip select pin signals of all stacked layers to ensure that the timing deviation between the chip select pin signals of the new stacked layers and the original control signals is ≤ ±1ns, and that the activation and sleep timings of the chip select pin signals of different stacked layers do not overlap.

[0044] Based on this, by performing independent activation of each stacked layer through the chip select pin signal, the heat-generating location between layers of the vertically stacked chip can be accurately located, providing a basis for chip internal structure analysis and fault location.

[0045] The S200 and temperature monitoring equipment sequentially acquire multi-view infrared thermal images of each storage unit and record the acquired information.

[0046] In this embodiment of the application, the temperature observation device can be a cooled infrared thermometer, which, with its advantages of high sensitivity and high spatial resolution, can accurately detect the heat points inside the target memory chip. Figure 3 This is a third schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application, as shown below. Figure 3 As shown, the temperature measurement of the storage unit specifically includes the following steps: S210. Determine the angle adjustment range based on the size information of the target memory chip and the field of view of the temperature observation device's lens.

[0047] In this embodiment, based on the physical size information of the target memory chip and the geometric constraint relationship between the field of view of the infrared lens of the cooled infrared thermography microscope, the stage can be driven by a precision stepper motor to translate in segments along the X or Y direction to achieve full surface coverage scanning of the target memory chip, thereby determining the angle adjustment range.

[0048] For example, the angle adjustment range can be set to 0~360° in the horizontal direction, that is, the infrared lens of the cooled infrared thermometer can rotate continuously 360° around the vertical axis of the target memory chip, supporting multi-view thermal distribution comparison. The vertical tilt angle is limited to 60°~90°, that is, the angle between the infrared lens of the cooled infrared thermometer and the chip surface is 60°~90°. This avoids the mechanical obstruction of the edge of the target memory chip by the lens body and ensures the perpendicularity of the incident light path, significantly reducing emissivity error and temperature measurement deviation.

[0049] S220: Set the angle adjustment interval according to the angle adjustment range, and determine multiple shooting points based on the angle adjustment interval.

[0050] In this embodiment, the intelligent optimization layout of shooting points can be achieved by dynamically setting the angle adjustment interval. First, based on the horizontal and vertical adjustment range of the infrared lens, combined with the target scene coverage requirements and resolution constraints, the optimal angle step value is adaptively determined. Then, discrete angle combinations are generated at equal intervals to form a structured shooting point set, which takes into account both coverage integrity and sampling efficiency, avoids redundant shooting, and improves the consistency and reproducibility of multi-view data acquisition.

[0051] For example, there are 24 shooting angles in total, with each 15° in the horizontal direction and each 5° in the vertical direction. Each combination of shooting angles corresponds to one shooting point, for a total of 24×7=168 shooting points.

[0052] S230: The temperature observation equipment moves to each shooting point in turn to collect images of the activated target storage body, obtains a multi-view infrared thermal image set, and records the acquisition information for each image acquisition. The acquisition information includes at least the horizontal angle, vertical angle, and acquisition time.

[0053] In this embodiment, a cooled infrared thermography microscope is controlled to move to each shooting point to sequentially acquire images of the activated target storage, thereby obtaining a multi-view infrared thermal image set. At the same time, the horizontal angle, vertical angle and shooting time corresponding to the acquired infrared thermal images are recorded to obtain acquisition information.

[0054] For example, when the first target storage bank Bank0 is activated and the activation pre-charge operation is performed cyclically for a preset number of cycles, the cooled infrared thermography microscope is controlled to move to 168 imaging points to sequentially acquire images of the first target storage bank Bank0, thereby obtaining 168 infrared thermal images. Similarly, when the second target storage bank Bank1 is activated and the activation pre-charge operation is performed cyclically for a preset number of cycles, 168 infrared thermal images can also be obtained, and the image acquisition of the remaining storage banks is performed in the same way.

[0055] Based on this, using a cooled infrared thermography microscope to acquire images of the target memory chip can significantly reduce noise and improve temperature measurement sensitivity, capturing minute temperature changes inside the memory chip. High spatial resolution allows for clear differentiation of thermal radiation signals from fine structures such as memory cells and word lines within the chip. This non-contact, non-destructive testing method balances testing accuracy and chip integrity, eliminating the need for manual temperature measurement and destructive dissection analysis, thus significantly improving testing efficiency.

[0056] S300 performs image preprocessing and data extraction on multi-view infrared thermal images to obtain a temperature dataset.

[0057] In this embodiment of the application, image processing algorithms can be used to denoise the images in the multi-view infrared thermal image set, thereby extracting the temperature dataset of the effective area of ​​the target memory chip. Figure 4 This is the fourth schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application, as shown below. Figure 4 As shown, image preprocessing and data extraction specifically include the following steps: S310. Perform noise reduction processing on the infrared thermal images in the multi-view infrared thermal image set to obtain the initial infrared thermal image.

[0058] As an optional implementation of this application, a combination of median filtering and Gaussian filtering can be used to retain edge features such as temperature abrupt changes at the boundary of the heating zone of the storage device in the infrared thermal image, and to remove noise points in the image, such as random noise from the infrared detector and environmental thermal interference.

[0059] S320. Extract the temperature data of the effective area in the initial infrared thermal image to obtain the initial temperature dataset.

[0060] Optionally, the effective area in the initial infrared thermal image can be set to the chip storage array area, retaining only the temperature data of the chip storage array area, and marking invalid temperature measurement areas, such as chip pins and package shells, to obtain the initial temperature dataset.

[0061] S330. Based on the temperature distribution pattern of the target memory chip, perform consistency verification on the initial temperature dataset to obtain the temperature dataset.

[0062] It is understandable that the internal temperature distribution of memory chips has a continuous and gradient temperature distribution pattern. This temperature distribution pattern is used to verify the consistency of the initial temperature dataset and eliminate abnormal temperature points caused by testing and shooting.

[0063] Based on this, image denoising and effective region extraction significantly improve the signal-to-noise ratio and spatial accuracy of infrared thermograms, effectively suppressing inherent noise of cooled infrared thermography, environmental thermal radiation interference, and lens diffraction artifacts. Simultaneously, retaining only the temperature data of the effective region yields a high-fidelity temperature dataset, improving the ability to resolve interlayer temperature differences.

[0064] S400. Perform data correlation analysis based on the temperature dataset and collected information to obtain a temperature coordinate correlation dataset.

[0065] In this embodiment, the chip's physical structure is used as a hard constraint. Through feature point matching between angles, data normalization, and consistency verification, a precise mapping relationship between the temperature data of each shooting angle and the three-dimensional coordinates of the target memory chip is established. This allows the discrete multi-angle data to form a unified coordinate reference system, eliminating angle offset errors for subsequent three-dimensional surface fitting and modeling. Figure 5 This is the fourth schematic diagram of the internal heat dissipation test method for memory chips provided in the embodiments of this application, as shown below. Figure 5 As shown, data correlation analysis specifically includes the following steps: S410. Construct a three-dimensional rectangular coordinate system with the geometric center of the target memory chip as the origin.

[0066] In this embodiment, a right-handed Cartesian coordinate system is established with the geometric center of the target memory chip as the origin O(0,0,0) to fit the target memory chip structure. The X-axis is along the horizontal width direction of the origin (left-right direction, positive direction to the right), corresponding to the horizontal distribution direction of the target memory chip's storage cells; the Y-axis is along the horizontal height direction of the origin (up-down direction, positive direction upward), corresponding to the vertical distribution direction of the target memory chip's storage cells; the Z-axis is along the depth direction perpendicular to the surface of the target memory chip (chip stacking direction, positive direction inward), corresponding to the distribution direction of the chip stack layers. The X and Y axes are the horizontal plane of the target memory chip, parallel to the imaging plane of the reference viewpoint, and the Z-axis is the vertical plane of the target memory chip. Temperature data from all angles must ultimately be mapped to this three-dimensional coordinate system.

[0067] S420. Establish a first mapping relationship between the temperature data of each horizontal angle under the same vertical angle and the three-dimensional rectangular coordinate system to obtain the first normalized data.

[0068] Optionally, at the same vertical angle, by analyzing the temperature peak location, thermal gradient direction, and thermal diffusion decay rate at different horizontal angles, the spatial orientation of heat sources on the chip surface and the thermal path at the packaging level can be identified. The coordinates and temperatures of hot spots at each horizontal angle are extracted, and based on coordinate calibration parameters and the microscope pose matrix, each hot spot coordinate and temperature is mapped to a set of spatial points on the surface of the target memory chip in a three-dimensional Cartesian coordinate system, establishing a first mapping relationship. First normalized data is generated through interpolation to characterize the surface heat distribution at that vertical angle.

[0069] S430. Establish a second mapping relationship between the temperature data of each vertical angle under the same horizontal angle and the three-dimensional rectangular coordinate system to obtain the second normalized data.

[0070] Optionally, temperature data at various vertical angles can be traversed at the same horizontal angle to extract hotspot coordinates and temperatures at different vertical angles, mapped to a three-dimensional Cartesian coordinate system, construct a second mapping relationship, and generate second normalized data to reflect the thermal response profile along the thickness direction.

[0071] S440. Integrate the first normalized data and the second normalized data to obtain a temperature coordinate associated dataset.

[0072] In this embodiment of the application, after completing the data correlation analysis of horizontal and vertical angles, the first normalized data and the second normalized data of all angles are integrated to generate a unified temperature coordinate correlation dataset, which is the core foundation for constructing a chip three-dimensional temperature coordinate system.

[0073] Based on this, the temperature coordinate association dataset maps all multi-angle and multi-stack layer temperature data to the three-dimensional physical reference coordinate system of the target memory chip. The coordinates of the same physical point are completely consistent across all angles, with no angular offset error. This temperature coordinate association dataset is a four-dimensional structured dataset: XYZT, where X, Y, and Z represent the coordinate values ​​of the X-axis, Y-axis, and Z-axis, respectively, and T represents the temperature value. It also associates the physical structure labels of the target memory chip, including but not limited to memory cell number, stack layer number, and chip select pin number, achieving a triple binding of temperature data, chip physical structure, and test activation logic. All data in this temperature coordinate association dataset has undergone error verification; coordinate and temperature errors are controlled within the adaptation range of infrared thermometry and chip physical structure, with no outliers or distortions, and can be directly used as input for subsequent three-dimensional surface fitting modeling.

[0074] S500: Perform three-dimensional surface fitting based on the temperature coordinate association dataset to obtain the temperature distribution model of the target memory chip.

[0075] As an optional implementation of this application, a three-dimensional surface fitting algorithm can be used to fit the temperature coordinate associated dataset, obtaining a three-dimensional surface map. This approach ensures computational efficiency while reasonably characterizing typical thermal diffusion gradients and local heat source curvature effects within the chip, such as high-temperature bulges at the center of the memory cell or nonlinear attenuation in the Z-axis direction caused by interlayer thermal resistance. Weighted least squares fitting can be employed, embedding hard constraints on the target memory chip structure, such as segmented regions where the bank boundaries are temperature-continuous but derivative-discontinuous, to avoid overfitting. The resulting three-dimensional temperature distribution model not only visualizes the temperature distribution, but its surface normal vectors and Hessian matrix eigenvalues ​​can also quantitatively invert the heat flow direction and local thermal resistance.

[0076] Based on this, by observing from multiple angles and fitting three-dimensional curved surfaces, the target memory chip is upgraded from a planar heat distribution to a three-dimensional thermal model, which intuitively presents the heat intensity, distribution range and heat conduction path of the storage structure and other structures in the target memory chip in three-dimensional space.

[0077] The internal heat generation testing method for memory chips provided in this application combines independent excitation of a single memory bank with sleep mode for multiple memory banks. By precisely controlling the operating state of each memory bank, it effectively avoids thermal crosstalk caused by concurrent operation of multiple memory banks, and achieves a one-to-one correspondence between thermal signal characteristics and the physical location of the chip's memory cells, significantly improving the accuracy of heat source location. Simultaneously, a three-dimensional thermodynamic model is generated using multi-view observation technology and a three-dimensional surface fitting algorithm. This model can intuitively display the thermodynamic characteristics of key structures such as memory banks in the three-dimensional space of the memory chip, including key parameters such as heat intensity distribution, thermal influence range, and heat conduction path.

[0078] Example 2 Based on the same technical concept as Embodiment 1 above, this application provides an internal heat testing system for a memory chip. Figure 6 This is a schematic diagram of the internal heat dissipation testing system for a memory chip provided in an embodiment of this application, as shown below. Figure 6 As shown, the internal heat dissipation testing system 200 for this memory chip includes: The chip testing module 210 is used to apply electrical excitation signals to each memory cell of the target memory chip one by one, so that each memory cell continuously generates characteristic heat in sequence.

[0079] The image acquisition module 220 is used to control the temperature observation device to sequentially acquire multi-view infrared thermal images of each storage unit and record the acquisition information.

[0080] The data processing module 230 is used to perform image preprocessing and data extraction on the multi-view infrared thermal image atlas to obtain a temperature dataset.

[0081] The data analysis module 240 is used to perform data correlation analysis based on the temperature dataset and the collected information to obtain a temperature coordinate correlation dataset.

[0082] The model generation module 250 is used to perform three-dimensional surface fitting based on the temperature coordinates associated with the dataset to obtain the temperature distribution model of the target memory chip.

[0083] The internal heat testing system for memory chips provided in this application adopts non-contact non-destructive testing technology, which effectively maintains the integrity of the chip structure while ensuring testing accuracy. Through parameter adjustment, image acquisition and algorithm modeling, the testing efficiency is significantly improved, providing important data support for memory chip architecture optimization, yield improvement and reliability verification.

[0084] It is understood that the implementation method of the internal heat testing method of memory chip described in Embodiment 1 above is also applicable to this embodiment and can achieve the same technical effect, so it will not be described again here.

[0085] Example 3 Based on the same concept, this application also provides an electronic device. Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 7As shown, the electronic device 300 may include a processor 310, a communication interface 320, a memory 330, and a communication bus 340, wherein the processor 310, the communication interface 320, and the memory 330 communicate with each other via the communication bus 340. The processor 310 can call logical instructions in the memory 330 to execute the steps of the internal heat dissipation test method for the memory chip as described in the above embodiments. For example, it includes: S100. Apply electrical excitation signals to each memory cell of the target memory chip one by one, so that each memory cell continuously generates characteristic heat in sequence. The S200 and temperature monitoring equipment sequentially acquire multi-view infrared thermal images of each storage unit and record the acquisition information. S300 performs image preprocessing and data extraction on multi-view infrared thermal image sets to obtain temperature datasets; S400: Perform data correlation analysis based on the temperature dataset and collected information to obtain a temperature coordinate correlation dataset; S500: Perform three-dimensional surface fitting based on the temperature coordinate association dataset to obtain the temperature distribution model of the target memory chip.

[0086] The processor 310 can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0087] Furthermore, the logical instructions in the aforementioned memory 330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] The memory 330 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0089] Example 4 Based on the same concept, embodiments of this application also provide a computer-readable storage medium storing a computer program. This computer program includes at least one piece of code that can be executed by a main control device to control the main control device to implement the steps of the memory chip internal heat testing method as described in the above embodiments. For example, it includes: S100. Apply electrical excitation signals to each memory cell of the target memory chip one by one, so that each memory cell continuously generates characteristic heat in sequence. The S200 and temperature monitoring equipment sequentially acquire multi-view infrared thermal images of each storage unit and record the acquisition information. S300 performs image preprocessing and data extraction on multi-view infrared thermal image sets to obtain temperature datasets; S400: Perform data correlation analysis based on the temperature dataset and collected information to obtain a temperature coordinate correlation dataset; S500: Perform three-dimensional surface fitting based on the temperature coordinate association dataset to obtain the temperature distribution model of the target memory chip.

[0090] Based on the same technical concept, this application also provides a computer program, which, when executed by a main control device, is used to implement the above-described method embodiments.

[0091] The computer program may be stored, in whole or in part, on a computer-readable storage medium packaged with the processor, or in part or in whole on a memory not packaged with the processor.

[0092] Based on the same technical concept, this application also provides a processor for implementing the above-described method embodiments. The processor can be a chip.

[0093] In summary, the internal heat generation testing method, system, equipment, and storage medium for memory chips provided in this application employ a testing method combining independent excitation of a single memory bank and sleep mode for multiple memory banks. By precisely controlling the operating state of each memory bank, it effectively avoids thermal crosstalk caused by concurrent operation of multiple memory banks, and achieves a one-to-one correspondence between thermal signal characteristics and the physical location of chip memory cells, significantly improving the accuracy of heat source location. Simultaneously, a three-dimensional thermodynamic model is generated through multi-view observation technology and a three-dimensional surface fitting algorithm. This model can intuitively display the thermodynamic characteristics of key structures such as memory banks in the three-dimensional space of the memory chip, including key parameters such as heat intensity distribution, thermal influence range, and heat conduction path. The testing process uses non-contact, non-destructive testing technology, effectively maintaining the integrity of the chip structure while ensuring testing accuracy. Significant improvements in testing efficiency are achieved through parameter adjustment, image acquisition, and algorithm modeling, providing crucial data support for memory chip architecture optimization, yield improvement, and reliability verification.

[0094] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0095] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for testing the internal heat generation of a memory chip, characterized in that, The method includes: An electrical excitation signal is applied to each memory cell of the target memory chip in turn, so that each memory cell sequentially and continuously generates characteristic heat. The temperature monitoring device sequentially acquires multi-view infrared thermal images of each of the storage cells and records the acquisition information; Image preprocessing and data extraction are performed on the multi-view infrared thermal image set to obtain a temperature dataset; Based on the temperature dataset and the collected information, a data correlation analysis is performed to obtain a temperature coordinate correlation dataset. A three-dimensional surface fitting is performed based on the temperature coordinate association dataset to obtain the temperature distribution model of the target memory chip.

2. The method for testing the internal heat generation of a memory chip according to claim 1, characterized in that, Before applying electrical excitation signals to each memory cell of the target memory chip individually, the method further includes: Layered independent activation is performed on each stacked layer of the target memory chip based on the chip select pin signal.

3. The method for testing the internal heat generation of a memory chip according to claim 2, characterized in that, The step of performing layered independent activation of each stacked layer of the target memory chip based on the chip select pin signal includes: Before applying the electrical excitation signal, the chip select pin signal of the target stacked layer of the target memory chip is set to a high level to activate the target stacked layer. After all memory cells in the target stack layer have been activated, the chip select pin signal of the target stack layer of the target memory chip is set to low level, thus turning off the target stack layer. The stacking layers of the target memory chip are traversed until all stacking layers have been activated and deactivated.

4. The method for testing the internal heat generation of a memory chip according to claim 1, characterized in that, The step of applying electrical excitation signals to each memory cell of the target memory chip sequentially to cause each memory cell to generate characteristic heat in turn includes: Set the reference test voltage of the target memory chip and control the target memory chip to run in pre-charge power saving mode for a preset time; Switch the target memory chip to the target test voltage, activate the target word line of the first target memory bank separately, and repeatedly perform the activation precharge operation until the preset number of cycles are reached; Switch the target memory chip back to the reference test voltage, and re-control the target memory chip to run in the pre-charge power saving mode for the preset duration; Switch the target memory chip to the target test voltage, activate the target word line of the second target memory bank separately, and repeatedly perform the activation precharge operation until the preset number of cycles; Repeatedly execute the voltage switching and pre-charge power-saving mode operation of the target memory chip, traverse and activate each memory cell and repeatedly execute the activation pre-charge operation until all memory cells are activated.

5. The method for testing the internal heat generation of a memory chip according to claim 4, characterized in that, The temperature control observation device sequentially acquires multi-view infrared thermal images of each of the storage cells and records the acquired information, including: The angle adjustment range is determined based on the size information of the target memory chip and the field of view of the lens of the temperature observation device. An angle adjustment interval is set according to the angle adjustment range, and multiple shooting points are determined based on the angle adjustment interval; The temperature observation device is controlled to move to each of the shooting points in turn to acquire images of the activated target storage, thereby obtaining the multi-view infrared thermal image set, and recording the acquisition information for each image acquisition, which includes at least the horizontal angle, vertical angle and acquisition time.

6. The method for testing the internal heat generation of a memory chip according to claim 1, characterized in that, The step of performing image preprocessing and data extraction on the multi-view infrared thermal image set to obtain a temperature dataset includes: The infrared thermal images in the multi-view infrared thermal image set are subjected to noise reduction processing to obtain an initial infrared thermal image; Extract the temperature data of the effective area from the initial infrared thermal image to obtain the initial temperature dataset; The initial temperature dataset is validated for consistency based on the temperature distribution pattern of the target memory chip to obtain the temperature dataset.

7. The method for testing the internal heat generation of a memory chip according to claim 6, characterized in that, The step of performing data correlation analysis based on the temperature dataset and the collected information to obtain a temperature coordinate correlation dataset includes: A three-dimensional Cartesian coordinate system is constructed with the geometric center of the target memory chip as the origin; A first mapping relationship is established between the temperature data of each horizontal angle under the same vertical angle and the three-dimensional rectangular coordinate system to obtain the first normalized data. A second mapping relationship is established between the temperature data of each vertical angle under the same horizontal angle and the three-dimensional rectangular coordinate system to obtain the second normalized data; The first normalized data and the second normalized data are integrated to obtain the temperature coordinate associated dataset.

8. An internal heat dissipation testing system for a memory chip, characterized in that, The system includes: The chip testing module is used to apply electrical excitation signals to each memory cell of the target memory chip one by one, so that each memory cell will continuously generate characteristic heat in sequence; The image acquisition module is used to control the temperature observation device to sequentially acquire multi-view infrared thermal images of each of the storage cells and record the acquisition information; The data processing module is used to perform image preprocessing and data extraction on the multi-view infrared thermal image set to obtain a temperature dataset; The data analysis module is used to perform data correlation analysis based on the temperature dataset and the collected information to obtain a temperature coordinate correlation dataset; The model generation module is used to perform three-dimensional surface fitting based on the temperature coordinate association dataset to obtain the temperature distribution model of the target memory chip.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the internal heat testing method for the memory chip as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the internal heat testing method for the memory chip as described in any one of claims 1-7.

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