C-band radio frequency direct acquisition and data storage system of RFSoC architecture

Abstract

The invention relates to the technical field of radio frequency signal processing, and discloses an RFSoC-architecture C-band radio frequency direct acquisition and data storage system, which comprises a high-speed analog-to-digital conversion module, an on-chip programmable logic processing module, a dual-port block memory module, a DDR cache module and an upper computer data acquisition module. A C-band radio frequency signal is directly sampled through an ultra-high-speed ADC (analog-to-digital converter) in an RFSoC (radio frequency system-on-chip), is processed by a programmable logic module, is cached by a two-stage cache structure consisting of a BRAM (bidirectional random access memory) and a DDR (double data rate), and is transmitted to an upper computer through an Ethernet interface to realize real-time receiving, storage and analysis. According to the invention, direct acquisition of a C-band radio frequency signal is realized by adopting an ultra-high-speed time interleaving architecture ADC in an RFSoC, link interference and device noise of a traditional analog down-conversion technology are avoided, and a multi-channel compensation correction mechanism is matched, so that the digital signal acquisition precision is greatly improved; and meanwhile, the internal Tile-level high-speed interface is directly connected with the processing module, so that the loss of an external link is reduced, and the data continuity and stability at a high sampling rate are ensured.

Description

Technical Field

[0001] This invention relates to the field of radio frequency signal processing technology, and in particular to a C-band radio frequency direct acquisition and data storage system based on an RFSoC architecture. Background Technology

[0002] In an active calibrator system, it is necessary to receive radar calibration signals and perform power measurements to provide accurate signal parameters for subsequent signal relay. C-band signals have the characteristics of high frequency and high power, and the accuracy of their reception and measurement directly determines the calibration accuracy.

[0003] In existing technologies, the signal receiving section often uses pass-through analog down-conversion technology. However, this technology can introduce noise from the devices in the RF front-end link, resulting in measurement errors and affecting the accuracy of signal acquisition. In the signal measurement section, FPGA-based data processing is a common solution for radar signal processing. However, to obtain high-precision data, it is necessary to avoid operations such as extraction that may affect data collection. At the same time, a high-performance FPGA is needed to achieve efficient data transmission and buffering.

[0004] The Zynq UltraScale+ RFSoC integrates an ARM processor, a high-speed FPGA, and high-precision RF components onto a single-chip SoC platform. It achieves the fusion of high-performance RF data converters and RF analog technology. It includes 8 RF-ADCs (supporting digital downconversion DUC) and 8 RF-DACs (supporting digital upconversion), supports direct RF acquisition, and has flexible analog design capabilities. It can improve accuracy while reducing power consumption, providing a feasible hardware foundation for solving the problem of high-precision acquisition and storage of C-band signals.

[0005] To address the problem in existing technologies that hinder high-precision direct RF acquisition and signal data storage of C-band signals, thus affecting signal measurement accuracy, this invention proposes a C-band RF direct acquisition and data storage system based on RFSoC to achieve high-precision acquisition, stable storage, and efficient transmission of C-band signals. Summary of the Invention

[0006] To overcome the aforementioned deficiencies of the prior art, the present invention provides a C-band RF direct acquisition and data storage system based on an RFSoC architecture to solve the problems mentioned in the background art.

[0007] This invention provides a C-band radio frequency direct sampling and data storage system based on an RFSoC architecture, comprising a high-speed analog-to-digital converter module, an on-chip programmable logic processing module, a dual-port block memory module, a DDR high-speed cache module, and a host computer data acquisition module. The system directly samples radio frequency signals using an internal ultra-high-speed ADC of the RFSoC. After the programmable logic module completes cache allocation and data width conversion, the data is sequentially cached via BRAM and DDR, and then transmitted to the host computer via an Ethernet interface, achieving real-time reception and storage of directly sampled data.

[0008] The high-speed analog-to-digital conversion module includes a front-end analog input interface, a sample-and-hold circuit, an ADC core, a digital correction module, a digital down-conversion module, and a clock and synchronization module; the on-chip programmable logic processing module is the PL terminal of the RFSoC, including a data access unit, a data format and width conversion unit, a cache scheduling and flow control unit, a multi-channel data alignment and synchronization unit, and a DMA control and data transmission management unit; the dual-port block memory module includes a BRAM array unit, port A access logic, port B access logic, an address pointer management unit, and a data status flag unit; the DDR cache module includes a storage control interface, an AXI bus arbitration unit, a DMA burst read / write scheduling unit, a data block organization module, a sequential access control unit, and a cache allocation module.

[0009] Preferably, the front-end analog input interface of the high-speed analog-to-digital converter module includes a voltage reference circuit, an input buffer / driver, a gain and bias adjustment circuit, and a bandwidth limiting filter, which are used to condition the input analog signal and adapt it to the ADC sampling requirements; the ADC core adopts a time-interleaved ADC architecture, with a maximum sampling rate of up to 5GSPS.

[0010] Preferably, the data access unit of the on-chip programmable logic processing module directly receives the raw sampling data of the high-speed ADCTile inside the RFSoC; the data format and width conversion unit adapts the ADC output format to make the data width match the requirements of BRAM cache and DDR high-speed write link; the cache scheduling and flow control unit realizes the writing, peak shaping and allocation of high-speed data to ensure smooth data flow between different cache paths.

[0011] Preferably, the BRAM array unit of the dual-port block memory module provides on-chip low-latency short-term cache space for high-speed data flow; the address pointer management unit adopts a circular queue cache management method to realize dynamic updates of write pointers and read pointers; the data status flag unit outputs cache full, cache empty, and threshold alarm flags to ensure data read and write reliability.

[0012] Preferably, the DMA burst read / write scheduling unit of the DDR cache module adaptively sets the burst length and write rhythm according to the data pressure; the data block organization module divides the high-speed continuous sampling data into fixed-size data blocks, which facilitates the DDR to perform sequential or segmented storage; the sequential access control unit prevents data overwriting and out-of-order storage; and the cache allocation module adopts a multi-cache area or round-robin cache structure.

[0013] Preferably, the system adopts a BRAM-DDR two-level cache structure. BRAM is used for short-term buffering of high-speed data and peak shaping of burst data traffic, while DDR is used for continuous buffering of large-capacity, long-sequence data streams. Data transfer between the two-level cache is realized through AXIDMA to ensure no data loss under continuous high-speed sampling.

[0014] Preferably, the BRAM cache module includes at least two sets of BlockMemoryGeneratorIP, which serve as on-chip level-one caches for multi-channel data to achieve data routing, timing alignment, and burst write management.

[0015] Preferably, the system achieves high-speed data interaction between the RFSoC and the host computer via an Ethernet data link; the DDR high-speed cache module inside the RFSoC is connected to the Ethernet MAC module via a programmable logic processing module, and the sampled data is encapsulated into network data frames by a UDP data packet unit and sent to the host computer through the Ethernet MAC layer and PHY interface to achieve long-distance, high-bandwidth, and continuous data transmission.

[0016] Preferably, the sampling data of the high-speed analog-to-digital conversion module enters the programmable logic processing module directly through the Tile-level high-speed interface inside the RFSoC, without going through an external digital interface chip; the host computer data acquisition module receives data through a gigabit or 10-gigabit Ethernet interface and stores it in real time as a binary file, CSV file or MAT file, and the host computer is equipped with a frequency domain analysis module to perform real-time spectrum evaluation using FFT or power spectrum estimation algorithms.

[0017] Preferably, the host computer completes communication with the RFSoC through the VITIS tool, and then uses MATLAB to write a control command sending program. The control commands include starting signal acquisition, stopping signal acquisition, setting sampling length, selecting ADC channel, and starting data transmission. The RFSoC runs an embedded program, listens to the corresponding port and parses and executes the control commands, and configures the ADCTile, data path, AXIDMA and Ethernet transmission module.

[0018] Compared with the prior art, the beneficial effects of the present invention are:

[0019] 1. This invention achieves direct acquisition of C-band RF signals by employing an RFSoC internal ultra-high-speed time-interleaved architecture ADC, avoiding link interference and device noise of traditional analog downconversion technology. Combined with a multi-channel compensation and correction mechanism, it significantly improves the accuracy of digital signal acquisition. At the same time, it directly connects to the processing module through an internal Tile-level high-speed interface, reducing external link losses and ensuring data continuity and stability at high sampling rates.

[0020] 2. This invention innovatively adopts a BRAM-DDR two-level cache architecture. BRAM enables short-term buffering of high-speed data and peak smoothing of burst traffic, while DDR achieves stable storage of large-capacity, long-sequence data through multi-buffer design, adaptive burst scheduling, and sequential access control. Combined with AXIDMA high-speed relocation and Ethernet long-distance transmission solutions, it solves the storage bottleneck and transmission interruption problems of high-speed sampling data, ensuring continuous acquisition without data loss.

[0021] 3. This invention innovatively adopts a method that allows the host computer to remotely issue control commands via VITIS or MATLAB, enabling automated operations such as sampling parameter configuration and data acquisition start / stop. The acquired data can be stored in multiple formats such as binary, CSV, and MAT, adapting to the needs of different subsequent algorithm processing. Furthermore, the host computer integrates functions such as FFT spectrum analysis and multi-channel data visualization, enabling signal detection, power calculation, and feature extraction without additional development. It is suitable for application scenarios such as RF calibration and signal measurement, which require high-precision acquisition of parameters such as amplitude and power. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the system of the present invention;

[0023] Figure 2 This is a diagram of the RF direct sampling module based on RFSoC of the present invention;

[0024] Figure 3 This is a structural diagram of the data transmission and storage control engineering of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Example 1

[0027] This embodiment of an RFSoC architecture C-band RF direct acquisition and data storage system includes: a high-speed analog-to-digital conversion module, an on-chip programmable logic processing module, a dual-port block memory module, a DDR high-speed cache module, and a host computer data acquisition module;

[0028] The high-speed analog-to-digital converter module's main function is to receive analog signals, perform preliminary signal processing, and provide them to the ADC for analog-to-digital conversion. It includes a front-end analog input interface, a sample-and-hold circuit, the ADC core, a digital correction module, a digital down-conversion module, and a clock and synchronization module.

[0029] The front-end analog input interface includes a voltage reference circuit, an input buffer / driver, gain and bias adjustment circuits, and a bandwidth limiting filter.

[0030] The sample-and-hold circuit is mainly responsible for sampling continuous analog signals into discrete timing signals, which is a pre-step for subsequent analog-to-digital conversion of the ADC.

[0031] The ADC core employs a time-interleaved ADC architecture in the RFSoC used, achieving a sampling rate of up to 5 GSPS.

[0032] The digital correction module is used for compensation and correction of multiple ADCs and multiple channels during high-speed sampling.

[0033] Digital downconversion is used to perform digital mixing, filtering, decimation, and frequency band selection on broadband radio frequency signals. It mainly includes a digitally controlled oscillator, a digital mixer, a filter, and a decimator.

[0034] The clock and synchronization module mainly provides the clock for the ADC and performs signal synchronization.

[0035] The on-chip programmable logic processing module (PL) is the core of the RFSoC for processing RF direct acquisition data links. It includes a data access unit, a data format and width conversion unit, a buffer scheduling and flow control unit, a multi-channel data alignment and synchronization unit, and a DMA control and data transmission management unit.

[0036] The data access unit is used to directly receive raw sampling data from the high-speed ADCTile inside the RFSoC;

[0037] The data format and width conversion unit is mainly used to adapt the output format of the high-speed ADC so that the data width meets the requirements of the subsequent BRAM cache and DDR high-speed write link.

[0038] The cache scheduling and flow control unit is mainly used to manage the writing, peak shaping and distribution of high-speed data, so as to realize the smooth flow of high-speed direct data between different cache paths;

[0039] The multi-channel data alignment and synchronization unit is used to align the phase and frame boundaries of data between different tiles and different channels.

[0040] The DMA control and data transfer management unit is mainly responsible for configuring the AXIDMA read and write strategies to achieve automated, high-speed data transfer between BRAM and DDR.

[0041] The dual-port block memory module is mainly used in high-speed data processing. It provides temporary storage for high-speed data streams and cross-module data buffering, improving data transmission efficiency and supporting real-time processing. The dual-port block memory module mainly consists of a BRAM array unit, port A access logic, port B access logic, an address pointer management unit, and a data status flag unit.

[0042] Among them, the BRAM array cells are used to provide low-latency short-term cache space on-chip for high-speed data streams;

[0043] The port A access logic is used to receive data write requests from the programmable logic processing module.

[0044] Port B access logic is used to provide a real-time read channel for DMA or subsequent data processing logic;

[0045] The address pointer management unit mainly implements dynamic updates of write pointers and read pointers, as well as cache management based on a circular queue;

[0046] The data status flag unit is used to provide valid flags such as cache full, cache empty, and threshold alarm to ensure the reliability of the data read and write process.

[0047] The DDR cache module is primarily used in the system to achieve large-capacity, continuous, and stable storage of high-speed sampled data. Its main functions include: caching large-capacity high-speed sampled data, achieving stable buffering and speed matching of the data stream, enabling continuous read and write of large-scale data, and providing a source for subsequent data retrieval. The DDR cache module mainly consists of a storage control interface, an AXI bus arbitration unit, a DMA burst read / write scheduling unit, a data block organization module, a sequential access control unit, and a cache allocation module.

[0048] The storage control interface is used for high-speed access to the RFSoC's internal DDR controller.

[0049] The AXI bus arbitration unit is used to handle bandwidth allocation between DMA writes and host computer readbacks.

[0050] The DMA burst read / write scheduling unit is used to adaptively set the burst length and write rhythm according to data pressure;

[0051] The data block organization module is mainly used to divide high-speed continuous sampling data into data blocks of fixed size, which facilitates sequential or segmented storage in DDR.

[0052] The sequential access control unit is used to ensure that data is read and written continuously in sequence, preventing data overwriting and out-of-order processing.

[0053] The cache allocation module is used to create multi-cache or polling cache structures, enabling DDR to maintain stable operation even at high data rates.

[0054] The data caching system also includes a host computer control module, a signal transmission module, and a storage module. These modules are used to control the RF-SOC to transmit and receive signals via the host computer, control the RF-SOC's data output and DDR data caching, transmit data between the RF-SOC and the host computer via the Ethernet port, and finally store the received data systematically.

[0055] The host computer controls the transmission and reception functions in the following way:

[0056] The host computer, via VITIS, can use MATLAB to send control commands to the ARM side of the RF-SOC through Ethernet. These commands include starting signal acquisition, stopping signal acquisition, setting the sampling length, selecting the ADC channel, and initiating data transmission. The RF-SOC runs an embedded program, listens to the port connected to the host computer, parses the control commands, and executes the operations.

[0057] The data transmission and caching functions are implemented as follows:

[0058] After the host computer's control commands are parsed on the ARM side, the RF-SOC begins: configuring the ADCTILE startup, triggering the data path reset within the PL, configuring the length and mode of AXIDMA read / write DDR, starting the DDR write link, and starting the Ethernet transmission module after the data is ready.

[0059] The host computer mainly includes a host computer control command module, a data receiving and parsing module, and a data management and storage module.

[0060] The host computer control instruction module uses the control port of the MATLAB program to send acquisition control instructions to the RFSoC via UDP / TCP socket. The instructions include sampling start command, sampling length setting command, buffer initialization command, and data transmission trigger command. It is used to start and configure the RFSoC's internal ADCTile, programmable logic module, and DDR cache link to realize remote control of the RF direct acquisition process.

[0061] The data receiving and parsing module continuously listens for UDP data packets from the RFSoC through the host computer network interface. It unpacks the received network frames, identifies the channels, verifies the frame count, and splices the data according to the preset data transmission protocol. It restores the original sampling data of the multiple ADCs sent by the RFSoC into the corresponding time-series sampling sequence, realizing real-time reception and parsing of high-speed data.

[0062] The data management and storage module is used to name and manage the parsed multi-channel ADC data according to timestamps and serial numbers, and save it locally in MAT file or binary format, realizing structured storage of large-scale RF sampling data. This module supports automatic generation of catalogs, automatic recording of sampling parameters, and provides continuous storage and batch processing capabilities.

[0063] The visualization analysis module is used to perform processing operations such as time-domain waveform drawing, frequency-domain fast Fourier transform (FFT) analysis, envelope extraction, amplitude and power calculation on the received multi-channel sampling sequences. It supports the synchronous display and comparative analysis of 8 or more ADC data, enabling the host computer to quickly evaluate and visualize the RF direct sampling signals.

[0064] Example 2

[0065] The workflow of the C-band RF direct acquisition and data storage system based on RFSoC of the present invention is as follows:

[0066] The host computer sends control commands (such as starting signal acquisition, setting the sampling length, etc.) to the ARM side of the RFSoC via UDP / TCP sockets. The RFSoC runs an embedded program, listens to the corresponding port, parses the control commands, and executes the relevant operations.

[0067] After the control command is parsed, RFSoC configures ADCTile to start, triggers the data path reset in PL, configures the length and mode of AXIDMA read / write DDR, and starts the DDR write link.

[0068] The front-end analog input interface of the high-speed analog-to-digital converter module receives C-band analog radio frequency signals. After preliminary processing such as gain adjustment and filtering, the continuous analog signal is converted into a discrete timing signal by the sample-and-hold circuit. Then, the ADC core (with a maximum sampling rate of 5GSPS) performs analog-to-digital conversion. During the conversion process, the digital correction module performs error compensation, the digital down-conversion module adjusts the frequency domain of the signal, and the clock and synchronization module ensures the timing synchronization of each link.

[0069] The sampled digital signal enters the on-chip programmable logic processing module directly through the Tile-level high-speed interface inside the RFSoC. After the data access unit receives the data, the data format and width conversion unit performs format adaptation, the buffer scheduling and flow control unit allocates the transmission path, the multi-channel data alignment and synchronization unit realizes data timing alignment, and the DMA control and data transmission management unit configures the AXIDMA read and write strategy.

[0070] The processed high-speed data is written to the BRAM array unit of the dual-port block memory module through the port A access logic. The BRAM array unit performs short-term caching and peak clipping on the data, and then it is read out by the port B access logic and transmitted to the DDR cache module through AXIDMA.

[0071] The DDR cache module receives data through the storage control interface. After being divided into fixed-size data blocks by the data block organization module, the data is stored in the DDR in sequence. The AXI bus arbitration unit coordinates the bandwidth allocation for DMA writing and host computer readback to ensure stable data storage.

[0072] Once the data preparation is complete, the Ethernet transmission module is started. The data in the DDR is connected to the Ethernet MAC module via the programmable logic processing module, encapsulated into network data frames by the UDP data packet unit, and sent to the host computer through the Ethernet MAC layer, PHY interface, and Gigabit / 10 Gigabit Ethernet link.

[0073] The host computer's data receiving and parsing module receives network data frames and performs unpacking, verification, and splicing. The data management and storage module stores the parsed data according to specifications. The visualization analysis module performs time-domain and frequency-domain analysis on the data and displays it, realizing the direct acquisition, storage, and analysis of C-band radio frequency signals.

[0074] While the disclosure is as stated above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of this disclosure, and all such changes and modifications will fall within the protection scope of this invention.

Claims

1. A C-band radio frequency direct acquisition and data storage system with an RFSoC architecture, characterized in that, It includes a high-speed analog-to-digital converter module, an on-chip programmable logic processing module, a dual-port block memory module, a DDR high-speed cache module, and a host computer data acquisition module; the RFSoC directly samples the radio frequency signal through its internal ultra-high-speed ADC, and after the programmable logic module completes the cache allocation and data width conversion, the data is cached in BRAM and DDR in sequence, and then transmitted to the host computer through the Ethernet interface, realizing the real-time reception and storage of directly sampled data; The high-speed analog-to-digital conversion module includes a front-end analog input interface, a sample-and-hold circuit, an ADC core, a digital correction module, a digital down-conversion module, and a clock and synchronization module; the on-chip programmable logic processing module is the PL terminal of the RFSoC, including a data access unit, a data format and width conversion unit, a cache scheduling and flow control unit, a multi-channel data alignment and synchronization unit, and a DMA control and data transmission management unit; the dual-port block memory module includes a BRAM array unit, port A access logic, port B access logic, an address pointer management unit, and a data status flag unit; the DDR cache module includes a storage control interface, an AXI bus arbitration unit, a DMA burst read / write scheduling unit, a data block organization module, a sequential access control unit, and a cache allocation module.

2. The C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 1, characterized in that, The front-end analog input interface of the high-speed analog-to-digital converter module includes a voltage reference circuit, an input buffer / driver, gain and bias adjustment circuits, and a bandwidth limiting filter, which are used to condition the input analog signal and adapt it to the ADC sampling requirements; the ADC core adopts a time-interleaved ADC architecture, with a maximum sampling rate of 5GSPS.

3. The C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 1, characterized in that, The on-chip programmable logic processing module's data access unit directly receives the raw sampling data from the high-speed ADCTile inside the RFSoC; the data format and width conversion unit adapts the ADC output format to match the data width requirements of the BRAM cache and DDR high-speed write link; the cache scheduling and flow control unit realizes the writing, peak shaping and allocation of high-speed data, ensuring smooth data flow between different cache paths.

4. The C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 1, characterized in that, The BRAM array unit of the dual-port block memory module provides on-chip low-latency short-term cache space for high-speed data flow; the address pointer management unit adopts a circular queue cache management method to realize dynamic updates of write pointers and read pointers; the data status flag unit outputs cache full, cache empty, and threshold alarm flags to ensure data read and write reliability.

5. A C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 1, characterized in that, The DMA burst read / write scheduling unit of the DDR cache module adaptively sets the burst length and write rhythm according to the data pressure; the data block organization module divides the high-speed continuous sampling data into fixed-size data blocks, which facilitates the DDR to perform sequential or segmented storage; the sequential access control unit prevents data overwriting and out-of-order storage; and the cache allocation module adopts a multi-cache area or round-robin cache structure.

6. The C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 1, characterized in that, The system adopts a two-level cache structure of BRAM-DDR. BRAM is used for short-term buffering of high-speed data and peak shaping of burst data traffic, while DDR is used for continuous buffering of large-capacity, long-sequence data streams. Data transfer between the two-level cache is realized through AXIDMA to ensure no data loss under continuous high-speed sampling.

7. A C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 6, characterized in that, The BRAM cache module includes at least two sets of BlockMemoryGeneratorIP, which serve as on-chip level-one caches for multi-channel data, enabling data routing, timing alignment, and burst write management.

8. The C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 1, characterized in that, The system enables high-speed data interaction between the RFSoC and the host computer via an Ethernet data link. The DDR high-speed cache module inside the RFSoC is connected to the Ethernet MAC module via a programmable logic processing module. The sampled data is encapsulated into network data frames by the UDP data packet unit and sent to the host computer through the Ethernet MAC layer and PHY interface, realizing long-distance, high-bandwidth, and continuous data transmission.

9. A C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 1, characterized in that, The sampling data from the high-speed analog-to-digital conversion module enters the programmable logic processing module directly through the Tile-level high-speed interface inside the RFSoC, without needing to go through an external digital interface chip; the host computer data acquisition module receives data through a gigabit or 10-gigabit Ethernet interface and stores it in real time as a binary file, CSV file or MAT file, and the host computer is equipped with a frequency domain analysis module to perform real-time spectrum evaluation using FFT or power spectrum estimation algorithms.

10. A C-band RF direct acquisition and data storage system based on an RFSoC architecture according to claim 1, characterized in that, The host computer completes communication with the RFSoC through the VITIS tool, and then uses MATLAB to write a control command sending program. The control commands include starting signal acquisition, stopping signal acquisition, setting sampling length, selecting ADC channel, and starting data transmission. The RFSoC runs an embedded program, listens to the corresponding port and parses and executes the control commands, and configures the ADCTile, data path, AXIDMA and Ethernet transmission module.

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