Voltage output circuit and power management chip
By using an FVF-type LDO structure voltage output circuit, multiple output voltages are generated using a bias loop and a fast response loop, which solves the problem of abnormal leakage current in the chip, realizes leakage-free power supply switching between different voltage domains, and supports chip miniaturization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GIGADEVICE SEMICON (BEIJING) INC
- Filing Date
- 2024-11-08
- Publication Date
- 2026-05-08
AI Technical Summary
Existing technologies using LDOs to generate different voltage sources in chips suffer from abnormal leakage current issues, resulting in a large area occupied by the level conversion circuit, which makes it difficult to meet the area and linearity requirements of highly integrated chips.
The voltage output circuit adopts an FVF type LDO structure, including a bias loop and a fast response loop. It generates multiple output voltages through operational amplifiers and source follower transistors, which are used to power different voltage domains, avoiding level conversion circuit switching and reducing leakage.
It achieves zero leakage current when switching power supply in different voltage domains, reduces the area occupied by the voltage output section in the chip, simplifies the circuit structure, and supports the miniaturization design of the chip.
Smart Images
Figure CN121996008A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit technology, and in particular to a voltage output circuit and a power management chip. Background Technology
[0002] As technology advances, chips become increasingly integrated. Different digital or analog circuit modules within a chip often require more than one power supply voltage. During operation, level shifting circuits are needed to switch signal voltage domains. The larger the chip, the more signals need to be switched, resulting in a larger area occupied by the level shifting circuits.
[0003] Compared to DC-DC converters, LDOs (Low Dropout Linear Regulators) occupy less space and offer higher linearity, making them more suitable for applications where space and linearity are critical, such as portable terminal devices. Current technologies using LDOs to generate different voltage source outputs typically employ gate multiplexing of the LDO power transistors. However, some of these voltage sources may exhibit slight differences in voltage due to varying loads, necessitating level conversion circuitry during switching to prevent abnormal leakage current. This results in a larger overall footprint. Summary of the Invention
[0004] In order to generate different voltage sources while avoiding abnormal leakage and thus reducing the area occupied by the voltage output section in the chip, the present invention provides a voltage output circuit and a power management chip.
[0005] On one hand, the present invention provides a voltage output circuit, the voltage output circuit comprising:
[0006] A first output module includes a bias loop containing an operational amplifier and a first source follower transistor, and a first fast response loop containing the first source follower transistor and a first power transistor. The gate terminal of the first source follower transistor is coupled to the output terminal of the operational amplifier. The first terminal of the first power transistor is coupled to a circuit input voltage, and the second terminal is coupled to the first terminal of the first source follower transistor. The voltage at the second terminal of the first power transistor is the first output voltage. The two input terminals of the operational amplifier are respectively coupled to a feedback voltage of the first output voltage and a reference voltage.
[0007] The second output module includes a second fast response loop containing a second source follower transistor and a second power transistor. The gate terminal of the second source follower transistor is coupled to the output terminal of the operational amplifier. The first terminal of the second power transistor is coupled to the circuit input voltage and the second terminal is coupled to the first terminal of the second source follower transistor. The voltage at the second terminal of the second power transistor is the second output voltage.
[0008] Optionally, the first fast response loop includes a first current mirror unit and a second current mirror unit, wherein the first current mirror unit is used to copy the second terminal current of the first source follower transistor to the second current mirror unit, and the second current mirror unit is used to copy the current copied from the first current mirror unit to the gate terminal of the first power transistor.
[0009] Optionally, the first fast response loop includes a first current source coupled between the gate of the first power transistor and ground.
[0010] Optionally, the second fast response loop includes a third current mirror unit and a fourth current mirror unit, wherein the third current mirror unit is used to copy the second terminal current of the second source follower transistor to the fourth current mirror unit, and the fourth current mirror unit is used to copy the current copied from the third current mirror unit to the gate terminal of the second power transistor.
[0011] Optionally, the second fast response loop includes a second current source coupled between the gate of the second power transistor and ground.
[0012] Optionally, the voltage output circuit further includes:
[0013] The third output module includes a first transistor, a second transistor, a third transistor, a third voltage source, and a fourth voltage source. The first transistor has a first terminal coupled to the first output voltage and its gate terminal coupled to its second terminal. The third voltage source is coupled between the circuit input voltage and the second terminal of the first transistor. The second terminals of the second and third transistors are coupled to the circuit input voltage, and their gate terminals are coupled to the gate terminal of the first transistor. The voltage at the first terminal of the third transistor is the third output voltage. The fourth voltage source is coupled between the third output voltage and ground. Optionally, the third output voltage is used to provide power to the logic circuit.
[0014] Optionally, the first output voltage and the second output voltage are used to provide power in different voltage domains.
[0015] On the other hand, the present invention provides a power management chip, the power management chip including the voltage output circuit described above.
[0016] Optionally, the power management chip is used to provide power in different voltage domains.
[0017] The voltage output circuit provided by this invention includes a first output module and a second output module. The first output module is an FVF type LDO structure, which includes a bias ring and a first fast response ring. The second terminal voltage of the first power transistor is the first output voltage. The second output module includes a second fast response ring. The gate terminal of the second source follower transistor is coupled to the output terminal of the operational amplifier in the first output module. The second terminal voltage of the second power transistor is the second output voltage. Both the first output voltage and the second output voltage have the characteristic of adjusting with load changes. Abnormal leakage is not easy to occur when the output voltage is switched. It can provide power supply for different voltage domains without the need for switching through a level conversion circuit, so that the voltage output section occupies a small area in the chip.
[0018] The power management chip provided by this invention includes the voltage output circuit described above. While being able to output a first output voltage and a second output voltage respectively, it is not prone to abnormal leakage when switching output voltages. It can provide power supply for different voltage domains, does not require a level conversion circuit, and helps to miniaturize the chip. Attached Figure Description
[0019] Figure 1 This is a schematic diagram showing the relationship between the output voltages of a voltage output circuit according to an embodiment of the present invention.
[0020] Figure 2 This is a circuit diagram of the first output module in a voltage output circuit according to an embodiment of the present invention.
[0021] Figure 3 This is a circuit diagram of the second output module in a voltage output circuit according to an embodiment of the present invention.
[0022] Figure 4 This is a circuit diagram of the third output module in a voltage output circuit according to an embodiment of the present invention. Detailed Implementation
[0023] The voltage output circuit and power management chip of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0024] This invention relates to a voltage output circuit and a power management chip including the voltage output circuit. The voltage output circuit generates more than one voltage source with output voltage regulation function based on an FVF-type LDO, and can also generate a voltage source whose output voltage changes with the output voltage of the FVF-type LDO but does not change with the load. (Refer to...) Figure 1The voltage output circuit of this embodiment can generate the following voltage sources: the first is a first output voltage VDD1 generated by the circuit input voltage VIN through an FVF-type LDO; the second is a second output voltage VDD2 with a feedback loop generated by the bias voltage generated by the operational amplifier of the FVF-type LDO and the fast response loop; and the third is a third output voltage VDD3 without a feedback loop generated by the first output voltage VDD1 and the source follower. Furthermore, the power supply in the chip may also include the power required to drive the power transistor to operate under the bias voltage output from the first output voltage VDD1. Further explanation follows.
[0025] Reference Figure 2 and Figure 3 The voltage output circuit of this embodiment of the invention has at least a first output module 100 and a second output module 200 to generate a first output voltage VDD1 and a second output voltage VDD2, respectively.
[0026] like Figure 2 As shown, the first output module 100 is an FVF-LDO architecture, which includes a bias ring BLP containing an operational amplifier EA and a first source follower transistor PM1, and a first fast response ring FLP1 containing the first source follower transistor PM1 and a first power transistor MP. The gate terminal of the first source follower transistor PM1 is coupled to the output terminal of the operational amplifier EA. The first terminal of the first power transistor MP is coupled to the circuit input voltage VIN, and the second terminal is coupled to the first terminal of the first source follower transistor PM1. The voltage at the second terminal of the first power transistor MP is the first output voltage VDD1. The two input terminals of the operational amplifier EA are respectively coupled to the feedback voltage of the first output voltage VDD1 and a reference voltage VREF. The bias ring BLP provides partial DC gain to the first output module 100, facilitating the acquisition of high gain. The first fast response ring FLP1, for example, has the gate terminal of the first power transistor MP as its dominant pole.
[0027] Optionally, the power supply terminal of operational amplifier EA is coupled to the first output voltage VDD1. Compared to using the power supply input voltage VIN to power operational amplifier EA, this can shield the direct influence of the power supply input voltage VIN on operational amplifier EA, which helps to improve DC gain and loop stability. The first power transistor MP and the first source follower transistor PM1 are, for example, PMOS transistors. As an example, in the following embodiment, the source terminal of the first power transistor MP is its first terminal and the drain terminal is its second terminal, and the source terminal of the first source follower transistor PM1 is its first terminal and the drain terminal is its second terminal.
[0028] As an example, the aforementioned first fast response loop FLP1 may include a first current mirror unit 10 and a second current mirror unit 20, wherein the first current mirror unit 10 is used to copy the drain current of the first source follower transistor PM1 to the second current mirror unit 20, and the second current mirror unit 20 is used to copy the current copied from the first current mirror unit 10 to the gate terminal of the first power transistor MP (i.e., the major pole of the first fast response loop FLP1). Figure 2 As shown, the first current mirror unit 20 may include transistors NM1 and NM2, both of which are, for example, NMOS transistors. The drain and gate terminals of transistor NM1 are coupled to the gate terminal of transistor NM2, and the sources of transistors NM1 and NM2 are coupled to ground. The second current mirror unit 20 may include transistors PM2 and PM3, both of which are, for example, PMOS transistors. The drain and gate terminals of transistor PM2 are coupled to the gate terminal of transistor PM3, and the sources of transistors PM2 and PM3 are coupled to the circuit input voltage VIN. Furthermore, the first fast response loop FLP1 may also include a first current source Ibias1, which is coupled between the gate terminal of the first power transistor MP and ground. The gate terminal of the first power transistor MP is coupled to the positive terminal of the first current source Ibias1.
[0029] In the first output module 100, changes in the first output voltage VDD1 can be transmitted to the gate of the first power transistor MP through the first source follower transistor PM1, the first current mirror unit 10, the first current source Ibias1, and the second current mirror unit 20, further affecting the first output voltage VDD1 and thus forming a fast response, i.e., forming a first fast response loop FLP1. The first fast response loop FLP1 has a fast transient response speed and good stability. The first fast response loop FLP1 is the feedback loop of the first output voltage VDD1, enabling the first output voltage VDD1 to have the characteristic of adjusting with load changes. The first output voltage VDD1 provides power to the corresponding voltage domain in the voltage output circuit or the corresponding chip, for example, it can be used to drive a static circuit. By ensuring that the first output voltage VDD1 does not carry a large load and does not drive a high-frequency circuit, the stability of its core static circuit can be guaranteed.
[0030] Reference Figure 3 The second output module 200 includes a second fast response loop FLP2 containing a second source follower transistor PM1' and a second power transistor MP'. The gate terminal of the second source follower transistor PM1' is coupled to the output terminal of the operational amplifier EA. The first terminal of the second power transistor MP' is coupled to the circuit input voltage VIN, and the second terminal is coupled to the first terminal of the second source follower transistor PM1'. The voltage at the second terminal of the second power transistor MP' is the second output voltage VDD2. The second fast response loop FLP2, for example, has the gate terminal of the second power transistor MP' as its dominant pole.
[0031] The second fast response ring FLP2 can adopt the same structure as the first fast response ring FLP1 described above, but the second output module 200 does not have a bias ring BLP as in the first output module 200. In the second output module 200, the output bias AS_BVN of the operational amplifier EA only controls the second fast response ring FLP2 but does not form a bias ring. The second power transistor MP' and the second source follower transistor PM1' are, for example, PMOS transistors. As an example, in the following embodiment, the source terminal of the second power transistor MP' is its first terminal and the drain terminal is its second terminal, and the source terminal of the second source follower transistor PM1' is its first terminal and the drain terminal is its second terminal.
[0032] As an example, the second fast response ring FLP2 may include a third current mirror unit 30 and a fourth current mirror unit 40, wherein the third current mirror unit 30 is used to copy the drain current of the second source follower transistor PM1' to the fourth current mirror unit 40, and the fourth current mirror unit 40 is used to copy the current copied from the third current mirror unit 30 to the gate of the second power transistor MP' (i.e., the major pole of the second fast response ring FLP2). Figure 3 As shown, the third current mirror unit 30 may include transistors NM1' and NM2', both of which are, for example, NMOS transistors. The drain and gate of transistor NM1' are coupled to the gate of transistor NM2', and the sources of transistors NM1' and NM2' are coupled to ground. The fourth current mirror unit 40 may include transistors PM2' and PM3', both of which are, for example, PMOS transistors. The drain and gate of transistor PM2' are coupled to the gate of transistor PM3', and the sources of transistors PM2' and PM3' are coupled to the circuit input voltage VIN. Furthermore, the second fast response ring FLP2 may also include a second current source Ibias2, which is coupled between the gate of the second power transistor MP' and ground. The gate of the second power transistor MP' is coupled to the positive terminal of the second current source Ibias2.
[0033] In the second output module 200, changes in the second output voltage VDD2 can be transmitted to the gate of the second power transistor MP' through the second source follower transistor PM1', the third current mirror unit 30, the second current source Ibias2, and the fourth current mirror unit 40, further affecting the second output voltage VDD2 and thus forming a fast response, i.e., forming a second fast response loop FLP2. The second output module 200 uses the bias voltage generated by the operational amplifier to drive the individual second fast response loop to form the second output voltage VDD2. The second fast response loop FLP2 is the feedback loop of the second output voltage VDD2, enabling the second output voltage VDD2 to have the characteristic of adjusting with load changes. The second output voltage VDD2 provides power to the corresponding voltage domain in the voltage output circuit or corresponding chip, for example, it can be used to drive high-frequency or fast-flipping circuits.
[0034] Reference Figure 4 In some embodiments, the voltage output circuit further includes a third output module 300. The third output module 300 includes a first transistor M1, a second transistor M2, a third transistor M3, a third voltage source Ibias3, and a fourth voltage source Ibias4. The first transistor M1, the second transistor M2, and the third transistor M3 each have a gate terminal, a first terminal, and a second terminal. As an example, the first transistor M1, the second transistor M2, and the third transistor M3 are all NMOS transistors, with the source terminal as the first terminal and the drain terminal as the second terminal.
[0035] In this configuration, the first terminal of the first transistor M1 is coupled to the first output voltage VDD1, and its gate terminal is coupled to the second terminal. The third voltage source Ibias3 is coupled between the circuit input voltage VIN and the second terminal of the first transistor M1. The second terminals of the second transistor M2 and the third transistor M3 are coupled to the circuit input voltage VIN, and their gate terminals are coupled to the gate terminal of the first transistor M1. The voltage at the first terminal of the third transistor M3 is the third output voltage VDD3. The fourth voltage source Ibias4 is coupled between the third output voltage VDD3 and ground.
[0036] In the third output module 300, the first transistor M1, the second transistor M2, and the third voltage source Ibias3 form a current mirror. The current in the branch where the first transistor M1 is located is replicated to the branch of the second transistor M2, forming a current Iload in the branch of the second transistor. Since the gate voltage AS_VBN1 of the first transistor M1 is determined by the first output voltage VDD1, and the gates of the first transistor M1, the second transistor M2, and the third transistor M3 are connected, the gate voltages of the second transistor M2 and the third transistor M3 are basically fixed, and the third output voltage VDD3 changes with the first output voltage VDD1. Furthermore, since the third output voltage VDD3 has no feedback loop and its gate voltage is fixed, its voltage under normal conditions will be slightly lower than the first output voltage VDD1 and the second output voltage VDD2 when it is under load. The third output voltage VDD3 provides power to the corresponding voltage domain in the voltage output circuit or the corresponding chip, for example, it can be used to provide power to logic circuits. When the third output voltage VDD3 is used as the power input signal for the logic circuit, the driving speed is fast, and there is no leakage problem.
[0037] In the voltage output circuit described in the above embodiment, the first output voltage VDD1 and the second output voltage VDD2 both have the characteristic of adjusting with load changes. The jitter of the third output voltage VDD3 will not affect the first output voltage VDD1 and the second output voltage VDD2. Moreover, the third output voltage VDD3 will change with the change of the first output voltage VDD1. Therefore, even without setting a level conversion circuit, the first output voltage VDD1, the second output voltage VDD2, and the third output voltage VDD3 will not have leakage problems. That is, abnormal leakage is not easy to occur when switching output voltages. The power supply crosstalk is small and the driving capability is strong. In the voltage output circuit, the first output voltage VDD1, the second output voltage VDD2, and the third output voltage VDD3 can be used to provide power supply for different voltage domains without the need for switching through a level conversion circuit. This makes the voltage output section occupy a small area in the chip. Furthermore, the above voltage output circuit has a simple structure and is easy to implement.
[0038] According to an embodiment of the present invention, a power management chip includes the voltage output circuit described in the above embodiments. Regarding the voltage output circuit, please refer to the description in the above embodiments and... Figures 1 to 4 understand.
[0039] The power management chip can be used to provide power in different voltage domains. In some embodiments, the power management chip has a first output voltage VDD1 for driving static circuits, a second output voltage VDD2 for driving high-frequency or fast-flipping circuits, and a third output voltage VDD3 for driving logic circuits.
[0040] The power management chip provided by this invention includes the voltage output circuit described above. While being able to output power to different voltage domains separately, it is not prone to abnormal leakage when switching output voltages, and the level conversion circuit can be eliminated, which helps to miniaturize the chip.
[0041] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A voltage output circuit, characterized in that, include: The first output module includes a bias ring containing an operational amplifier and a first source follower transistor, and a first fast response ring containing the first source follower transistor and a first power transistor. The gate terminal of the first source follower transistor is coupled to the output terminal of the operational amplifier. The first terminal of the first power transistor is coupled to the circuit input voltage and the second terminal is coupled to the first terminal of the first source follower transistor. The voltage at the second terminal of the first power transistor is the first output voltage. The two input terminals of the operational amplifier are respectively coupled to the feedback voltage of the first output voltage and a reference voltage. as well as The second output module includes a second fast response loop containing a second source follower transistor and a second power transistor. The gate terminal of the second source follower transistor is coupled to the output terminal of the operational amplifier. The first terminal of the second power transistor is coupled to the circuit input voltage and the second terminal is coupled to the first terminal of the second source follower transistor. The voltage at the second terminal of the second power transistor is the second output voltage.
2. The voltage output circuit as described in claim 1, characterized in that, The first fast response loop includes a first current mirror unit and a second current mirror unit, wherein the first current mirror unit is used to copy the second terminal current of the first source follower transistor to the second current mirror unit, and the second current mirror unit is used to copy the current copied from the first current mirror unit to the gate terminal of the first power transistor.
3. The voltage output circuit as described in claim 1, characterized in that, The first fast response loop includes a first current source, which is coupled between the gate terminal of the first power transistor and ground.
4. The voltage output circuit as described in claim 1, characterized in that, The second fast response loop includes a third current mirror unit and a fourth current mirror unit, wherein the third current mirror unit is used to copy the second terminal current of the second source follower transistor to the fourth current mirror unit, and the fourth current mirror unit is used to copy the current copied from the third current mirror unit to the gate terminal of the second power transistor.
5. The voltage output circuit as described in claim 1, characterized in that, The second fast response loop includes a second current source coupled between the gate of the second power transistor and ground.
6. The voltage output circuit as described in any one of claims 1 to 5, characterized in that, Also includes: The third output module includes a first transistor, a second transistor, a third transistor, a third voltage source, and a fourth voltage source. The first terminal of the first transistor is coupled to the first output voltage, and its gate terminal is coupled to its second terminal. The third voltage source is coupled between the circuit input voltage and the second terminal of the first transistor. The second terminals of the second transistor and the third transistor are coupled to the circuit input voltage, and their gate terminals are coupled to the gate terminal of the first transistor. The voltage at the first terminal of the third transistor is the third output voltage. The fourth voltage source is coupled between the third output voltage and ground.
7. The voltage output circuit as described in claim 6, characterized in that, The third output voltage is used to provide power to the logic circuit.
8. The voltage output circuit as described in any one of claims 1 to 5, characterized in that, The first output voltage and the second output voltage are used to provide power in different voltage domains.
9. A power management chip, characterized in that, Includes the voltage output circuit as described in any one of claims 1 to 8.
10. The power management chip as described in claim 9, characterized in that, The power management chip is used to provide power in different voltage domains.