Transistor device and manufacturing method thereof

Abstract

The invention provides a transistor device and a manufacturing method thereof. The transistor device comprises a channel layer, a barrier layer, a grid electrode, a first electrode, a second electrode, a first connecting block, a second connecting block and a dielectric layer, the barrier layer is stacked on the channel layer, the dielectric layer is stacked on the barrier layer, and the grid electrode is located on the dielectric layer; the contact surface of the channel layer and the barrier layer is provided with two-dimensional electron gas, the two-dimensional electron gas comprises an active region and a resistance region which are spaced from each other, the resistance region is of an annular structure surrounding the active region, and the resistance region is provided with an opening; the first electrode and the second electrode penetrate through the dielectric layer and the barrier layer to be in contact with the active region, the first connecting block and the second connecting block penetrate through the dielectric layer and the barrier layer to be in contact with the two sides of the opening of the resistance region, and the first connecting block is electrically connected with the grid electrode.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a transistor device and a method for manufacturing the same. Background Technology

[0002] In the field of electronic circuit design, transistors (such as high electron mobility transistors (HEMTs)) are usually used in conjunction with resistors, that is, transistors and resistors are connected together through a package to achieve integration.

[0003] However, this integration method not only involves complex manufacturing processes, but also results in a large area occupied by transistors and resistors, which is detrimental to the integration density of the circuit. Summary of the Invention

[0004] This disclosure provides a transistor device and its fabrication method, which can reduce the number of steps involved in using transistors and resistors together and improve integration density. The technical solution is as follows: On one hand, a transistor device is provided, the transistor device comprising: a channel layer, a barrier layer, a gate, a first electrode, a second electrode, a first interconnect block, a second interconnect block, and a dielectric layer; The barrier layer is stacked on the channel layer, the dielectric layer is stacked on the barrier layer, and the gate is located on the dielectric layer; The contact surface between the channel layer and the barrier layer has a two-dimensional electron gas, which includes an active region and a resistive region spaced apart from each other. The resistive region is a ring structure surrounding the active region and has an opening. The first electrode and the second electrode pass through the dielectric layer and the barrier layer to contact the active region. The first connection block and the second connection block pass through the dielectric layer and the barrier layer to contact both sides of the opening of the resistive region. The first connection block is electrically connected to the gate.

[0005] Optionally, the active region is rectangular, circular, or elliptical, and the resistive region is an annular shape composed of straight lines, arcs, or wavy lines.

[0006] Optionally, the annular width of the resistive region is 1~10μm, and the annular circumference of the resistive region is positively correlated with the target resistance value.

[0007] Optionally, the minimum distance between the resistive region and the active region is 100nm~100μm.

[0008] Optionally, the resistor region has two connecting parts at the opening, and the two connecting parts are in ohmic contact with the first connecting block and the second connecting block, respectively.

[0009] Optionally, the transistor device further includes: a first passivation layer, a gate pad, a resistor pad, a first pad, and a second pad; The first passivation layer covers the dielectric layer, the first electrode, the second electrode, the first connector block, and the second connector block; The gate pad passes through the first passivation layer and contacts the first connection block, the resistor pad passes through the first passivation layer and contacts the second connection block, the first pad is electrically connected to the first electrode, and the second pad is electrically connected to the second electrode.

[0010] On the other hand, a method for fabricating a transistor device is provided, the method comprising: A gate dielectric layer is fabricated on an epitaxial layer, the epitaxial layer including a channel layer and a barrier layer, the contact surface between the channel layer and the barrier layer having a two-dimensional electron gas; Ion implantation is performed on the gate dielectric layer and the epitaxial layer to form an active region and a resistive region spaced apart by the two-dimensional electron gas. The resistive region is a ring structure surrounding the active region and has an opening. A gate, a first electrode, a second electrode, a first connecting block, and a second connecting block are fabricated. The gate is located on the dielectric layer. The first electrode and the second electrode pass through the dielectric layer and the barrier layer to contact the active region. The first connecting block and the second connecting block pass through the dielectric layer and the barrier layer to contact both sides of the opening of the resistive region. The first connecting block is electrically connected to the gate.

[0011] Optionally, ion implantation is performed on the gate dielectric layer and the epitaxial layer, including: A second passivation layer is deposited on the gate dielectric layer; The second passivation layer is patterned to cover the positions corresponding to the active region and the resistive region; Under the shielding of the second passivation layer, ion implantation is performed on the gate dielectric layer and the epitaxial layer to remove the two-dimensional electron gas in the ion implantation region.

[0012] Optionally, ion implantation is performed on the gate dielectric layer and the epitaxial layer, including: The gate dielectric layer and the epitaxial layer are subjected to N-ion implantation, with 1 to 5 implantation cycles, an implantation energy of 10 to 300 keV, and an implantation dose of 1E17 to 1E20 cm⁻¹. -2 .

[0013] Optionally, the method further includes: A first passivation layer is fabricated, which covers the dielectric layer, the first electrode, the second electrode, the first connector block, and the second connector block. A gate pad, a resistor pad, a first pad, and a second pad are fabricated. The gate pad passes through the first passivation layer and contacts the first connection block. The resistor pad passes through the first passivation layer and contacts the second connection block. The first pad is electrically connected to the first electrode, and the second pad is electrically connected to the second electrode.

[0014] The beneficial effects of the technical solutions provided in this disclosure include at least the following: In the transistor device provided in this embodiment, the contact surface between the channel layer and the barrier layer has a two-dimensional electron gas. The two-dimensional electron gas includes an active region and a resistive region spaced apart from each other. The active region, together with the gate, the first electrode, and the second electrode, constitutes the transistor structure, while the resistive region is connected with the first connection block and the second connection block to form a resistive structure. That is, by using a two-dimensional electron gas to form a resistor in the transistor, the resistive structure can be formed simultaneously with the fabrication of the transistor device. This not only greatly reduces the fabrication steps and saves on packaging steps, but also significantly reduces the area occupied by the transistor and resistor, thereby improving the integration density. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a transistor device provided in an embodiment of this disclosure; Figure 2 This is a top view schematic diagram of a portion of the film layer of a transistor device provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another transistor device provided in an embodiment of this disclosure; Figure 4 This is a top view schematic diagram of a portion of the film layer of a transistor device provided in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating a method for fabricating a transistor device according to an embodiment of this disclosure; Figure 6 This is a flowchart illustrating a method for fabricating a transistor device according to an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure during the fabrication process of a transistor device according to an embodiment of this disclosure; Figure 8 This is a schematic diagram of the structure during the fabrication process of a transistor device according to an embodiment of this disclosure; Figure 9This is a schematic diagram of the structure during the fabrication process of a transistor device according to an embodiment of this disclosure.

[0017] Figure Labels 100: Substrate; 101: Channel layer; 102: Barrier layer; 103: Gate; 104: First electrode; 105: Second electrode; 106: First interconnect block; 107: Second interconnect block; 108: Dielectric layer; 109: First passivation layer; 110: Gate pad; 111: Resistor pad; 112: First pad; 113: Second pad; 201: Active region; 202: Resistive region; 301: Source-drain groove; 302: Resistive groove; 2020: Connection part. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0019] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0020] The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0021] Similarly, words like "one" or "a" do not indicate a quantity limitation, but rather that at least one exists. Words like "include" or "contain" mean that the elements or objects preceding "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects.

[0022] Words like "connect" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms like "up," "down," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships; when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0023] Figure 1 This is a schematic diagram of the structure of a transistor device provided in an embodiment of this disclosure. Figure 2 This is a top view schematic diagram of a portion of the film layer of a transistor device provided in an embodiment of this disclosure. Figure 1 It can be Figure 2 The cross-sectional view corresponding to point A-A' in the middle.

[0024] See Figure 1and Figure 2 The transistor includes: a channel layer 101, a barrier layer 102, a gate 103, a first electrode 104, a second electrode 105, a first interconnect block 106, a second interconnect block 107, and a dielectric layer 108.

[0025] The barrier layer 102 is stacked on the channel layer 101, the dielectric layer 108 is stacked on the barrier layer 102, and the gate 103 is located on the dielectric layer 108. The contact surface between the channel layer 101 and the barrier layer 102 has a two-dimensional electron gas, which includes an active region 201 and a resistive region 202 spaced apart from each other. The resistive region 202 is a ring structure surrounding the active region 201 and has an opening. The first electrode 104 and the second electrode 105 pass through the dielectric layer 108 and the barrier layer 102 and contact the active region 201. The first connecting block 106 and the second connecting block 107 pass through the dielectric layer 108 and the barrier layer 102 and contact both sides of the opening of the resistive region 202. The first connecting block 106 is electrically connected to the gate 103.

[0026] In the transistor device provided in this embodiment, the contact surface between the channel layer and the barrier layer has a two-dimensional electron gas. The two-dimensional electron gas includes an active region and a resistive region spaced apart from each other. The active region, together with the gate, the first electrode, and the second electrode, constitutes the transistor structure, while the resistive region is connected with the first connection block and the second connection block to form a resistive structure. That is, by using a two-dimensional electron gas to form a resistor in the transistor, the resistive structure can be formed simultaneously with the fabrication of the transistor device. This not only greatly reduces the fabrication steps and saves on packaging steps, but also significantly reduces the area occupied by the transistor and resistor, thereby improving the integration density.

[0027] In this embodiment of the disclosure, the transistor device is a HEMT device, such as a Metal Insulator Semiconductor (MIS) HEMT device, which is a depletion-mode gallium nitride power device.

[0028] The resistor is connected to the gate of the transistor and can be used as a clamping resistor for the transistor.

[0029] like Figure 2 As shown, the transistor may include a plurality of control cycles arranged along a first direction a, each control cycle including a gate, a first electrode, and a second electrode. Figure 1 The image shows one of the control cycles.

[0030] In addition, all the first electrodes 104 are electrically connected, all the second electrodes 105 are electrically connected, and all the gates 103 are electrically connected.

[0031] For example, the first electrode is the source and the second electrode is the drain.

[0032] like Figure 2 As shown in the embodiments of this disclosure, the active region 201 is rectangular, circular or elliptical, and the resistive region 202 is an annular shape composed of straight lines, arcs or wavy lines.

[0033] In one example, the active region 201 and the resistive region 202 correspond in shape. For example, the active region 201 is rectangular, and the resistive regions 202 are both rectangular rings; or, the active region 201 is circular, and the resistive region 202 is a ring; or, the active region 201 is elliptical, and the resistive region 202 is an elliptical ring.

[0034] In another example, the shapes of the active region 201 and the resistive region 202 do not correspond. For example, the active region 201 is circular, and the resistive region 202 is a rectangular ring; or, the active region 201 is rectangular, and the resistive region 202 is a ring formed by wavy lines.

[0035] In this example, the rectangular active region can meet the design requirements of a large number of transistors, while the ring-shaped wavy line of the resistor region can make the length of the resistor region large enough to provide a sufficiently large resistance as a clamping resistor.

[0036] For example, the annular width of the resistor region 202 is 1~10μm, and the annular circumference of the resistor region 202 is positively correlated with the target resistance value.

[0037] In this implementation, the annular width of the resistor region 202 is designed to be 1~10 micrometers. This ensures sufficient area for resistance while avoiding excessive use of the epitaxial layer width, which would result in an oversized structure.

[0038] For example, the annular width of the resistor region 202 is designed to be 4, 5, or 6 μm.

[0039] In this embodiment of the disclosure, the length and width of the active region 201 are not limited. The length and width of the active region 201 are defined according to the specific device design. For example, the size of a gallium nitride power device with a 300 milliohm resistor is different from that of a gallium nitride power device with a 30 milliohm resistor. It needs to be designed according to actual needs.

[0040] The dimensions of the resistance region 202 can be set according to the target resistance of the resistor to be manufactured. Generally, the sheet resistance Rsq of a two-dimensional electron gas is 300~700Ω / sq, calculated according to the target resistance R=Rsq*L / W, where W is the aforementioned annular width and L is the annular circumference. Therefore, the annular circumference of the resistance region 202 is positively correlated with the target resistance value.

[0041] When using a ring formed by wavy lines, the wave density of the wavy lines can be determined based on the circumference of the ring. The larger the circumference of the ring, the denser the wave density of the wavy lines should be.

[0042] For example, the minimum distance between the resistive region 202 and the active region 201 is 100nm~100μm.

[0043] In this implementation, the minimum spacing of the above values ​​is used to ensure that the distance between the resistive region and the active region is as small as possible, which can avoid short circuits between the active region and the resistive region and minimize the device size.

[0044] For example, the minimum distance between the resistive region 202 and the active region 201 is 1 or 10 μm. Within the above numerical range, a smaller distance requires higher precision from the equipment. Using a distance at the micrometer level balances the requirements for electrical performance, size, and manufacturing precision.

[0045] See you again Figure 1 The resistor region 202 has a connecting portion 2020 at its opening, which is used to more easily connect the first connecting block 106 and the second connecting block 107. The two connecting portions 2020 are in ohmic contact with the first connecting block 106 and the second connecting block 107 respectively, which ensures the connection between the resistor region and the metal electrode layer, thereby ensuring that the resistor region is connected and subsequent packaging is achieved.

[0046] See you again Figure 1 The opening of the resistor region 202 is located on one side of the annular structure extending along the first direction.

[0047] See you again Figure 1 The transistor device also includes a substrate 100, on which a channel layer 101 is located.

[0048] Optionally, the transistor device further includes a buffer layer located between the substrate 100 and the channel 101.

[0049] Figure 3 This is a schematic diagram of another transistor device provided in an embodiment of this disclosure. Figure 4 This is a top view schematic diagram of a portion of the film layer of a transistor device provided in an embodiment of this disclosure. Figure 3 It can be Figure 4 The cross-sectional view corresponding to point A-A' in the middle.

[0050] See Figure 3 and Figure 4 The transistor device may also include a first passivation layer 109, a gate pad 110, a resistor pad 111, a first pad 112, and a second pad 113.

[0051] The first passivation layer 109 covers the dielectric layer 108, the first electrode 104, the second electrode 105, the first connecting block 106, and the second connecting block 107.

[0052] The gate pad 110 passes through the first passivation layer 109 and contacts the first connecting block 106. The resistor pad 111 passes through the first passivation layer 109 and contacts the second connecting block 107. The first pad 112 is electrically connected to the first electrode 104, and the second pad 113 is electrically connected to the second electrode 105.

[0053] The above-described pad design facilitates the packaging of this transistor device with other electronic components.

[0054] Multiple gates can be connected via external traces and then connected to gate pads via external traces; alternatively, multiple gates can be connected via a connection structure on the same gate layer and then connected to gate pads via external traces. The first connection block 106 and the gate 103 are electrically connected via gate pad 110.

[0055] Multiple first electrodes can be connected via external traces and then connected to the first pad via external traces.

[0056] Multiple second electrodes can be connected via external traces and then connected to second pads via external traces. Alternatively, multiple second electrodes can be connected to second pads via a metal connection structure that passes through the first passivation layer.

[0057] like Figure 4 As shown, gate pad 110, resistor pad 111, and first pad 112 are arranged in a row at intervals; second pad 113 is arranged in another row; the two rows are arranged at intervals and in parallel.

[0058] This design facilitates packaging, and due to the aforementioned arrangement of the second pads, multiple second electrodes can be directly connected to the second pads via a metal connection structure that passes through the first passivation layer.

[0059] like Figure 4 As shown, the area of ​​the second pad is greater than the sum of the areas of the gate pad 110, the resistor pad 111, and the first pad 112.

[0060] The area of ​​the first pad 112 is larger than the area of ​​the gate pad 110, and the area of ​​the gate pad 110 is equal to the area of ​​the resistor pad 111.

[0061] like Figure 4 As shown, the gate pad 110 and resistor pad 111 are square. The first pad 112 and the second pad 113 are rectangular.

[0062] like Figure 4 As shown, in the second direction b, the distance between the first pad 112 and the second pad 113 is greater than the width of the first pad 112 and the second pad 113.

[0063] In the second direction b, the widths of the gate pad 110, the resistor pad 111, the first pad 112, and the second pad 113 are equal.

[0064] In this embodiment of the disclosure, the substrate 100 may be a Si substrate, a silicon carbide substrate, or a sapphire substrate.

[0065] For example, substrate 100 is a Si substrate.

[0066] In this embodiment of the disclosure, the buffer layer includes a buffer layer formed of at least one of AlGaN, GaN, and AlN.

[0067] In this embodiment of the disclosure, the channel layer 101 is a GaN channel layer, and the barrier layer 102 is an AlGaN layer.

[0068] In this embodiment of the disclosure, the gate 103, the first electrode 104, the first connection block 106, and the second connection block 107 may include a Ti alloy layer, an Al alloy layer, or a stack of Ti alloy and Al alloy.

[0069] In this embodiment of the disclosure, the dielectric layer 108 may be an Al2O3 layer, an AlN layer, a SiN layer, a SiO2 layer, an HfO2 layer, or other dielectric layers.

[0070] In this embodiment of the disclosure, the first passivation layer 109 may be a SiN layer, a SiO2 layer, or a stack of SiN and SiO2 layers.

[0071] In this embodiment of the disclosure, the gate pad 110, the resistor pad 111, the first pad 112, and the second pad 113 may include a TiN / Al / TiN stack.

[0072] Figure 5 This is a flowchart illustrating a method for fabricating a transistor device according to an embodiment of this disclosure. See also... Figure 5 The method includes the following steps: 31. A gate dielectric layer is fabricated on an epitaxial layer, the epitaxial layer comprising a channel layer and a barrier layer, wherein the contact surface between the channel layer and the barrier layer has a two-dimensional electron gas.

[0073] 32. Ion implantation is performed on the gate dielectric layer and the epitaxial layer to form an active region and a resistive region spaced apart by the two-dimensional electron gas. The resistive region is a ring structure surrounding the active region and has an opening.

[0074] 33. Fabricate a gate, a first electrode, a second electrode, a first connecting block, and a second connecting block. The gate is located on the dielectric layer. The first electrode and the second electrode pass through the dielectric layer and the barrier layer to contact the active region. The first connecting block and the second connecting block pass through the dielectric layer and the barrier layer to contact both sides of the opening of the resistive region. The first connecting block is electrically connected to the gate.

[0075] In the transistor device provided in this embodiment, the contact surface between the channel layer and the barrier layer has a two-dimensional electron gas. The two-dimensional electron gas includes an active region and a resistive region spaced apart from each other. The active region, together with the gate, the first electrode, and the second electrode, constitutes the transistor structure, while the resistive region is connected with the first connection block and the second connection block to form a resistive structure. That is, by using a two-dimensional electron gas to form a resistor in the transistor, the resistive structure can be formed simultaneously with the fabrication of the transistor device. This not only greatly reduces the fabrication steps and saves on packaging steps, but also significantly reduces the area occupied by the transistor and resistor, thereby improving the integration density.

[0076] Figure 6 This is a flowchart illustrating a method for fabricating a transistor device according to an embodiment of this disclosure. See also... Figure 6 The flowchart of this method includes: 41. Provide a substrate.

[0077] For example, the substrate may be a Si substrate, a silicon carbide substrate, or a sapphire substrate.

[0078] 42. Deposit a stacked channel layer and barrier layer on a substrate.

[0079] For example, the channel layer is a GaN channel layer and the barrier layer is an AlGaN layer.

[0080] Optionally, prior to depositing the channel layer, the method further includes: A buffer layer is fabricated on the substrate.

[0081] The buffer layer includes a buffer layer formed from at least one of AlGaN, GaN, and AlN.

[0082] 43. Fabricate the gate dielectric layer.

[0083] The dielectric layer covers the barrier layer.

[0084] In the embodiments of this disclosure, the dielectric layer may be an Al2O3 layer, an AlN layer, a SiN layer, a SiO2 layer, an HfO2 layer, or other dielectric layers.

[0085] 44: Ion implantation is performed on the gate dielectric layer and the epitaxial layer.

[0086] The contact surface between the channel layer and the barrier layer has a two-dimensional electron gas, which includes an active region and a resistive region spaced apart from each other. The resistive region is a ring structure surrounding the active region and has an opening.

[0087] In one example, step 44 includes: The first step is to deposit a second passivation layer on the gate dielectric layer.

[0088] In this embodiment of the disclosure, the second passivation layer may be a SiN layer, a SiO2 layer, or a stack of SiN and SiO2 layers.

[0089] The second step is to perform patterning on the second passivation layer, covering the positions corresponding to the active region and the resistive region.

[0090] For example, photoresist is formed on the surface of the second passivation layer; then photolithography is performed, and the resulting photoresist pattern covers the positions corresponding to the active region and the resistive region; then the second passivation layer is etched under the photoresist coverage to form the same shape as the photoresist. The photoresist plus the second passivation layer is used as a mask for the next step of ion implantation.

[0091] The third step involves ion implantation of the gate dielectric layer and the epitaxial layer under the shielding of the second passivation layer to remove the two-dimensional electron gas in the ion implantation region.

[0092] That is, the covered area will not be implanted with ions, thus preserving the two-dimensional electron gas, which serves as the active region and the resistive region.

[0093] After ion implantation is completed, the photoresist and the second passivation layer are removed.

[0094] In the above process, a passivation layer is deposited and patterned, and together with photoresist, it serves as a protective layer. Ion implantation is then performed to ensure that the electrical performance of the active and resistive regions is not affected.

[0095] Exemplarily, ion implantation is performed on the gate dielectric layer and the epitaxial layer, including: The gate dielectric layer and the epitaxial layer are subjected to N-ion implantation, with 1 to 5 implantation cycles, an implantation energy of 10 to 300 keV, and an implantation dose of 1E17 to 1E20 cm⁻¹.-2 .

[0096] In this implementation, the above parameters are used for ion implantation to ensure that the two-dimensional electron gas in the ion implantation region is removed.

[0097] For example, N-ion implantation is performed on the barrier layer in three stages, with an implantation energy of 100 keV and an implantation dose of 1E18 cm⁻¹. -2 .

[0098] In other examples, ion implantation can be achieved using only photoresist as a mask layer, or by using photoresist plus other masks.

[0099] Figure 7 This is a schematic diagram illustrating the structure during the fabrication process of a transistor device according to an embodiment of this disclosure. See also... Figure 7 The above ion implantation process forms an active region 201 and a resistive region 202.

[0100] 45. Fabricate a gate, a first electrode, a second electrode, a first connecting block, and a second connecting block.

[0101] The gate is located on the barrier layer, the first electrode and the second electrode pass through the dielectric layer and the barrier layer to contact the active region, and the first connection block and the second connection block pass through the dielectric layer and the barrier layer to contact both sides of the opening of the resistive region.

[0102] In the embodiments disclosed herein, the gate, the first electrode, the first connection block, and the second connection block may include a Ti alloy layer, an Al alloy layer, or a stack of Ti alloy and Al alloy.

[0103] In one example, step 45 may include: Ohmic and resistive contact areas are defined by photolithography; grooves are formed through the dielectric and barrier layers by dry etching.

[0104] The photoresist mask pattern for the electrode is formed by photolithography; a Ti / Al / TiW metal stack is formed by evaporation and lift-off process (or physical vapor deposition + dry etching process) to serve as the gate, first electrode, second electrode, first interconnect block and second interconnect block.

[0105] In other examples, the electrodes described above can also be fabricated in steps, for example, by first fabricating the gate, and then fabricating the first electrode, the first electrode block, the first connecting block, and the second connecting block after the gate is fabricated.

[0106] Figure 8 This is a schematic diagram illustrating the structure during the fabrication process of a transistor device according to an embodiment of this disclosure. See also... Figure 8The source / drain trench 301 and resistor trench 302 are formed by photolithography and etching.

[0107] Figure 9 This is a schematic diagram illustrating the structure during the fabrication process of a transistor device according to an embodiment of this disclosure. See also... Figure 9 The gate 103, the first electrode 104, the first connecting block 106, and the second connecting block 107 are formed through a vapor deposition and stripping process.

[0108] 46. ​​Create the first passivation layer.

[0109] The first passivation layer covers the dielectric layer, the first electrode, the second electrode, the first connection block, and the second connection block.

[0110] In this embodiment of the disclosure, the first passivation layer may be a SiN layer, a SiO2 layer, or a stack of SiN and SiO2 layers.

[0111] 47. Fabricate the gate pad, resistor pad, first pad, and second pad.

[0112] The gate pad passes through the first passivation layer and contacts the first connection block, the resistor pad passes through the first passivation layer and contacts the second connection block, the first pad is electrically connected to the first electrode, and the second pad is electrically connected to the second electrode. The first connection block is electrically connected to the gate through the gate pad.

[0113] In this embodiment of the disclosure, the gate pad, the resistor pad, the first pad, and the second pad may include a TiN / Al / TiN stack.

[0114] In one example, step 47 may include: Through photolithography and etching, vias are formed that penetrate the first passivation layer; a TiN / Al / TiN metal stack is formed using a sputtering lift-off process, serving as the gate pad, resistor pad, first pad, and second pad.

[0115] This disclosure provides a method for forming a clamping resistor using a two-dimensional electron gas HEMT via ion implantation.

[0116] In typical HEMT (High-Energy Medium-Density) processes, ion implantation is used to inject nitrogen atoms into regions outside the active area of ​​the device, disrupting the lattice structure of the AlGaN barrier layer to remove the two-dimensional electron gas. However, in this embodiment, a ring-shaped two-dimensional electron gas region is retained outside the active area. The sheet resistance of this two-dimensional electron gas is typically several hundred ohms per square block. The width and length of the two-dimensional electron gas region can be calculated based on the required resistance. The required resistor pattern is then added to the photomask design of the HEMT active area implantation layer to fabricate the resistor. This process is 100% compatible with HEMT active area processes and ohmic contact processes.

[0117] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A transistor device, characterized in that, The transistor device includes: a channel layer (101), a barrier layer (102), a gate (103), a first electrode (104), a second electrode (105), a first interconnect block (106), a second interconnect block (107), and a dielectric layer (108). The barrier layer (102) is stacked on the channel layer (101), the dielectric layer (108) is stacked on the barrier layer (102), and the gate (103) is located on the dielectric layer (108); The contact surface between the channel layer (101) and the barrier layer (102) has a two-dimensional electron gas, which includes an active region (201) and a resistive region (202) spaced apart from each other. The resistive region (202) is a ring structure surrounding the active region (201) and has an opening. The first electrode (104) and the second electrode (105) pass through the dielectric layer (108) and the barrier layer (102) and contact the active region (201). The first connecting block (106) and the second connecting block (107) pass through the dielectric layer (108) and the barrier layer (102) and contact both sides of the opening of the resistive region (202). The first connecting block (106) is electrically connected to the gate (103).

2. The transistor device according to claim 1, characterized in that, The active region (201) is rectangular, circular or elliptical, and the resistive region (202) is a ring formed by straight lines, arcs or wavy lines.

3. The transistor device according to claim 1, characterized in that, The annular width of the resistor region (202) is 1~10μm, and the annular circumference of the resistor region (202) is positively correlated with the target resistance value.

4. The transistor device according to claim 1, characterized in that, The minimum distance between the resistive region (202) and the active region (201) is 100nm~100μm.

5. The transistor device according to claim 1, characterized in that, The resistance region (202) has two connecting parts (2020) at the opening, and the two connecting parts (2020) are in ohmic contact with the first connecting block (106) and the second connecting block (107) respectively.

6. The transistor device according to any one of claims 1 to 5, characterized in that, The transistor device further includes: a first passivation layer (109), a gate pad (110), a resistor pad (111), a first pad (112), and a second pad (113). The first passivation layer (109) covers the dielectric layer (108), the first electrode (104), the second electrode (105), the first connecting block (106), and the second connecting block (107). The gate pad (110) passes through the first passivation layer (109) and contacts the first connection block (106), the resistor pad (111) passes through the first passivation layer (109) and contacts the second connection block (107), the first pad (112) is electrically connected to the first electrode (104), and the second pad (113) is electrically connected to the second electrode (105).

7. A method for fabricating a transistor device, characterized in that, The method includes: A gate dielectric layer is fabricated on an epitaxial layer, the epitaxial layer including a channel layer and a barrier layer, the contact surface between the channel layer and the barrier layer having a two-dimensional electron gas; Ion implantation is performed on the gate dielectric layer and the epitaxial layer to form an active region and a resistive region spaced apart by the two-dimensional electron gas. The resistive region is a ring structure surrounding the active region and has an opening. A gate, a first electrode, a second electrode, a first connecting block, and a second connecting block are fabricated. The gate is located on the dielectric layer. The first electrode and the second electrode pass through the dielectric layer and the barrier layer to contact the active region. The first connecting block and the second connecting block pass through the dielectric layer and the barrier layer to contact both sides of the opening of the resistive region. The first connecting block is electrically connected to the gate.

8. The method according to claim 7, characterized in that, Ion implantation is performed on the gate dielectric layer and the epitaxial layer, including: A second passivation layer is deposited on the gate dielectric layer; The second passivation layer is patterned to cover the positions corresponding to the active region and the resistive region; Under the shielding of the second passivation layer, ion implantation is performed on the gate dielectric layer and the epitaxial layer to remove the two-dimensional electron gas in the ion implantation region.

9. The method according to claim 8, characterized in that, Ion implantation is performed on the gate dielectric layer and the epitaxial layer, including: The gate dielectric layer and the epitaxial layer are subjected to N-ion implantation, with 1 to 5 implantation cycles, an implantation energy of 10 to 300 keV, and an implantation dose of 1E17 to 1E20 cm⁻¹. -2 .

10. The method according to any one of claims 7 to 9, characterized in that, The method further includes: A first passivation layer is fabricated, which covers the dielectric layer, the first electrode, the second electrode, the first connector block, and the second connector block. A gate pad, a resistor pad, a first pad, and a second pad are fabricated. The gate pad passes through the first passivation layer and contacts the first connection block. The resistor pad passes through the first passivation layer and contacts the second connection block. The first pad is electrically connected to the first electrode, and the second pad is electrically connected to the second electrode.

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