Clock surge detection circuit

Abstract

The clock surge detection circuit comprises a clock generator, a counter and a detection unit. The clock generator receives an input clock signal and generates a reference clock signal having a frequency higher than that of the input clock signal when the input clock signal is at a first voltage. The counter counts a current accumulation number of the number of cycles passed by the reference clock signal when the input clock signal is at the first voltage. The detection unit calculates a difference value between a previous accumulation number and a current accumulation number after the input clock signal is changed from the first voltage to the second voltage. The detection unit generates an alarm signal according to a difference value between a previous current accumulation number and a current accumulation number, and stores the current accumulation number as the previous accumulation number.

Description

Technical Field

[0001] The present invention discloses a surge detection circuit, and more particularly a surge detection circuit capable of detecting surges in clock signals. Background Technology

[0002] Clock signals are crucial components in electronic circuits, serving as a timing reference for the synchronized operation of various components within a system. The precise periodicity of clock signals ensures coordinated data processing, facilitating the seamless execution of complex computational tasks. Therefore, even small deviations or distortions (i.e., spikes) in the clock signal can adversely affect circuit performance. For example, spikes can lead to inaccurate system states, incorrect data sampling, and signal interference, potentially causing circuit failure or malfunction. Therefore, detecting clock signal spikes to prevent system failure or malfunction is of paramount importance. Summary of the Invention

[0003] One embodiment of this disclosure provides a clock surge detection circuit. The clock surge detection circuit includes a clock generator, a counter, a detection unit, and a timing control unit. The clock generator receives an input clock signal and generates a first reference clock signal when the input clock signal is at a first voltage. The frequency of the reference clock signal is higher than the frequency of the input clock signal. The counter counts the current accumulated number of cycles elapsed by the reference clock signal when the input clock signal is at the first voltage. After the input clock signal changes from the first voltage to a second voltage, the detection unit calculates the difference between the previous accumulated number and the current accumulated number, and after updating the difference between the previous accumulated number and the current accumulated number, generates an alarm signal based on the difference between the previous accumulated number and the current accumulated number, and stores the current accumulated number as the previous accumulated number. Attached Figure Description

[0004] A more complete understanding of the contents disclosed herein can be derived by referring to the embodiments and claims when considering in relation to the figures, wherein the same reference numerals refer to similar elements throughout the figures.

[0005] Figure 1 This illustrates a clock surge detection circuit according to an embodiment of the present disclosure; Figure 2 An embodiment according to the present disclosure is shown. Figure 1 The signal timing diagram of the clock surge detection circuit is shown below; Figure 3 This shows the logic circuit according to an embodiment of the present disclosure; Figure 4 This illustrates a clock surge detection circuit according to an embodiment of the present disclosure; Figure 5 This invention discloses a method for detecting clock surges in an input clock signal according to an embodiment of the present disclosure. Detailed Implementation

[0006] Figure 1 This illustration shows a clock surge detection circuit 100 according to an embodiment of the present disclosure. The clock surge detection circuit 100 includes a clock generator 110, a counter 120, and a detection unit 130. In this embodiment, the clock surge detection circuit 100 may be designed to detect an input clock signal SIG that switches between voltages V1 and V2. CKIN glitch in the middle.

[0007] Clock generator 110 can receive input clock signal SIG CKIN When the input clock signal SIG CKIN A reference clock signal SIG is generated under voltage V1. REF1 and at the input clock signal SIG CKIN The generation of the reference clock signal SIG stops when the voltage V2 is reached. REF1 That is, the clock generator 110 can be activated by the input clock signal SIG. CKIN Enabled when at voltage V1, and can be activated by input clock signal SIG. CKIN It is deactivated when the voltage is V2. In this embodiment, the voltage V1 may be higher than the voltage V2; however, this disclosure is not limited thereto.

[0008] In this embodiment, the reference clock signal SIG REF1 It can have a higher input clock signal SIG CKIN The frequency of the input clock signal SIG. Counter 120 can count the frequency of the input clock signal SIG. CKIN When the voltage is V1, the reference clock signal SIG REF1 The current accumulated number of cycles is used to measure the input clock signal SIG. CKIN The duration under voltage V1. For example, counter 120 can be referenced to clock signal SIG. REF1 The counter increments by 1 on each rising or falling edge. In this case, the counter 120 can be based on the reference clock signal SIG. REF1 Input clock signal SIG CKIN The length of this duration is measured by the number of cycles that elapse within the duration maintained at voltage V1. In this embodiment, since voltage V1 is higher than voltage V2, the input clock signal SIG is... CKIN The duration maintained at voltage V1 can also be referred to as the input clock signal SIG. CKIN The "ontime" of the input clock signal SIG. CKINThe duration maintained at voltage V2 can be referred to as the input clock signal SIG. CKIN The "off time".

[0009] Generally speaking, if the input clock signal SIG CKIN If there is no surge, then the input clock signal SIG is used. CKIN The duration maintained at voltage V1 should be equal to the next input clock signal SIG. CKIN The duration of conduction under voltage V1, i.e., the successive conduction times, should have the same length. However, if the input clock signal SIG... CKIN If there is a surge, then input clock signal SIG. CKIN The two durations maintained at voltage V1 may differ; in other words, the successive on-times may have different lengths. Therefore, by comparing the input clock signal SIG... CKIN By maintaining the voltage V1 for the length of the two consecutive durations (i.e., the length of the two consecutive conduction times), the surge occurring during this duration can be detected.

[0010] Figure 2 This diagram shows the signal timing of a clock surge detection circuit 100 according to an embodiment of the present disclosure. Figure 2 As shown, in the input clock signal SIG CKIN Duration DA1, reference clock signal SIG REF1 A total of 8 cycles were completed, while the input clock signal SIG... CKIN In the next duration DA2, the reference clock signal SIG REF1 Similarly, after 8 cycles, it means that the lengths of the two consecutive durations DA1 and DA2 are essentially equal, and therefore the input clock signal SIG... CKIN There were no sudden waves.

[0011] However, in the input clock signal SIG CKIN During the duration DA2, the reference clock signal SIG REF1 Eight cycles have passed, and the input clock signal SIG... CKIN In the next duration DA3, the reference clock signal SIG REF1 This means that only 5 cycles have elapsed, indicating that the durations of the two consecutive cycles are different, and therefore, the input clock signal SIG... CKIN It may be affected by a sudden wave.

[0012] In this embodiment, when the input clock signal SIG CKIN While maintaining voltage V1, counter 120 can continuously count based on the clock signal SIG. REF1The number of cycles elapsed (i.e., the current accumulated number NC1) is used to measure the current input clock signal SIG. CKIN The duration of the conduction time. Next, the input clock signal SIG... CKIN After the voltage changes from V1 to V2 (i.e., from the on time to the off time), the detection unit 130 can calculate the difference D1 between the current accumulated number NC1 obtained by the counter 120 and the previous accumulated number NP1 stored in the temporary register 132.

[0013] Subsequently, the detection unit 130 can further generate an alarm signal SIG based on the difference D1 between the current accumulated number NC1 and the previous accumulated number NP1. AL1 The current accumulated number NC1 is stored in the temporary register 132 as the previous accumulated number NP1 for the next detection.

[0014] For example, if the difference D1 between the current accumulated number NC1 and the previous accumulated number NP1 is greater than a predetermined value (e.g., 1 or 2), the detection unit 130 can determine that a surge has occurred and generate an alarm signal SIG accordingly. AL1 However, if the difference D1 between the current accumulated number NC1 and the previous accumulated number NP1 is not greater than a predetermined value, the detection unit 130 can determine that the input clock signal SIG... CKIN If there is no surge, then no alarm signal SIG will be generated. AL1 .

[0015] In some embodiments, the predetermined value used to determine whether a surge has occurred can be related to the input clock signal SIG. CKIN Frequency and reference clock signal SIG REF1 The frequency ratio is related to the system's tolerance. For example, in some cases, if the reference clock signal SIG... REF1 The frequency is higher than the input clock signal SIG CKIN Since the frequency is high, the difference between one or two cycles may not be significant, so the detection unit 130 can determine that there is no surge. Furthermore, in some cases where there are stricter requirements for the accuracy of the clock signal, the preset value can be relatively small to detect surges more sensitively. Therefore, the preset value can be set according to requirements.

[0016] In some embodiments, to control the operating timing of the detection unit 130, the clock surge detection circuit 100 may further include a timing control unit 140, which generates a control signal to trigger the detection unit 130 to perform a corresponding operation. For example, such as Figure 1 and Figure 2 As shown, the timing control unit 140 can respond to the input clock signal SIG CKINWhen the voltage changes from V1 to V2, a timing control signal SIG is generated. SEQ1 Furthermore, the timing control unit 140 can further delay the timing control signal SIG. SEQ1 To generate the first control signal SIG CT1 ,like Figure 2 As shown, the first detection unit 130 can detect the input clock signal SIG. CKIN The first control signal SIG is received at time point T1 during the shutdown time. CT1 This is triggered to update the difference D1 between the current accumulation number NC1 and the previous accumulation number NP1.

[0017] Furthermore, the timing control unit 140 can delay the first control signal SIG CT1 To generate the second control signal SIG CT2 ,like Figure 2 As shown, the detection unit 130 can detect the input clock signal SIG CKIN The second control signal SIG is received at time point T2 during the shutdown period. CT2 Triggered to generate the first alarm signal SIG AL1 (If a surge is detected), the current accumulated number NC1 is stored as the previous accumulated number NP1 for the next detection.

[0018] Furthermore, in this embodiment, the timing control unit 140 can delay the second control signal SIG. CT2 To generate the third control signal SIG CT3 , and such Figure 2 As shown, counter 120 can be activated by the input clock signal SIG. CKIN The third control signal SIG was received at time point T3 during the shutdown period. CT3 And then it was reset.

[0019] In other words, the timing control unit 140 can determine the timing based on the input clock signal SIG. CKIN Generate control signal SIG CT1 SIG CT2 and SIG CT3 This is to control the operating timing of the detection unit 130 and the counter 120. For example... Figure 2 As shown, the control signal SIG CT1 SIG CT2 and SIG CT3 The pulses can be emitted sequentially at time points T1, T2, and T3, and the determination of the surge can be made using the input clock signal SIG. CKIN During the duration of voltage V2 (i.e., during the input clock signal SIG) CKIN It is completed within the off-time. Therefore, the input clock signal SIG CKINThe conduction time can be regarded as a counting phase, in which counter 120 can count the reference clock signal SIG. REF1 The accumulated number of cycles, while the input clock signal SIG CKIN The shutdown time can be regarded as the determination phase, in which the detection unit 130 can detect the surge based on the counting results performed in the counting phase and prepare for the next detection.

[0020] exist Figure 1 In this embodiment, the timing control unit 140 may include an inverter 142, an SR latch 146, and a delay control unit 148. The inverter 142 can activate the input clock signal SIG by... CKIN Inverting to generate an inverted input clock signal SIG IVCK SR latch 146 includes a function for receiving an inverted input clock signal SIG. IVCK The setting terminal S is used to receive the third control signal SIG. CT3 The reset terminal R is used to output the timing control signal SIG. SEQ1 The data output terminal Q. In some embodiments, the SR latch 146 may be implemented by two cross-coupled NOR gates. However, this disclosure is not limited thereto. In some embodiments, the inverter 142 and the SR latch 146 may be combined and implemented as a negative edge-triggered SR latch.

[0021] The delay control unit 148 can adjust the timing control signal SIG according to the timing control signal. SEQ1 Generate the first control signal SIG CT1 Second control signal SIG CT2 and the third control signal SIG CT3 In some embodiments, the delay control unit 148 may include three delay elements 1482, 1484, and 1486, each of which can generate an output by delaying its input. In some embodiments, the delay elements may include two cascaded inverters; however, this disclosure is not limited thereto.

[0022] The detection unit 130 includes a temporary register 132, a subtractor 134, and a comparison logic circuit 136. Upon input of the clock signal SIG... CKINDuring the off-time, subtractor 134 can subtract the previous accumulated number NP1 stored in register 132 from the current accumulated number NC1 obtained by counter 120, or subtract the current accumulated number NC1 from the previous accumulated number NP1, in order to calculate the difference D1 between the current accumulated number NC1 and the previous accumulated number NP1. In some embodiments, subtractor 134 may include a carry look-ahead subtractor 1341 and register 1342, and register 1342 in subtractor 134 may be a flip-flop, which has a data input terminal D, a data output terminal Q, and an edge trigger terminal. In this case, carry look-ahead subtractor 1341 may be a combinational logic circuit, and can continuously perform subtraction operations on the current accumulated number NC1 and the previous accumulated number NP1 to continuously update the subtraction calculation result. In addition, register 1342 in subtractor 134 may be controlled by a first control signal SIG. CT1 Triggered. That is, the difference D1 between the current accumulated number NC1 and the previous accumulated number NP1 can be triggered by the first control signal SIG. CT1 The rising edge is stored in temporary register 1342. In some embodiments, to ensure the correctness of the calculation results, the timing control signal SIG... SEQ1 With the first control signal SIG CT1 The delay between them should be at least longer than the update time required for the subtractor 134 to perform the subtraction operation.

[0023] Next, also at the input clock signal SIG CKIN During the shutdown period, when the register 132 receives the second control signal SIG CT2 When the current accumulated number NC1 is received, the temporary register 132 can store the current accumulated number NC1 as the previous accumulated number NP1 (i.e., update the previous accumulated number for the next detection). Furthermore, upon receiving the second control signal SIG... CT2 Then, the comparison logic circuit 136 can check whether the difference D1 between the current accumulated number NC1 and the previous accumulated number NP1 is greater than a predetermined value, and can input the clock signal SIG when the difference D1 is greater than the predetermined value (i.e., a surge is detected). CKIN An alarm signal SIG is generated during the shutdown period. AL1 In some embodiments, the comparison logic circuit 136 may include logic circuit 1361 and a register 1362, and the register 1362 in the comparison logic circuit 136 may be a flip-flop. In this case, logic circuit 1361 may be a combinational logic circuit, and can continuously produce a comparison result CR1 between the difference D1 calculated by subtractor 134 and a predetermined value. In this case, register 1362 may be controlled by a second control signal SIG. CT2Triggered. That is, the comparison result CR1 between the difference D1 and the predetermined value can be triggered by the second control signal SIG. CT2 The rising edge is stored in register 1362. Therefore, register 1362 can output an alarm signal SIG based on the comparison result CR1. AL1 In some embodiments, to ensure the correctness of the comparison result, the first control signal SIG... CT1 With the second control signal SIG CT2 The delay between them should be at least longer than the computation time of the comparison logic circuit 136, so as to ensure that the comparison logic circuit 136 can complete the comparison operation.

[0024] The operations performed by the detection unit 130 through temporary registers 132, 1342, and 1362 can be controlled by the SIG signal. CT1 With SIG CT2 Sequential and specific control ensures the accuracy of surge detection.

[0025] In some embodiments, the logic circuit 1361 of the comparison logic circuit 136 can be simplified by using a few logic gates, without the need to use a register to store a predetermined value and to perform a bitwise comparison of the difference D1 with the predetermined value. Figure 3 This illustrates a logic circuit 1361 according to an embodiment of the present disclosure. Figure 3 In the embodiment shown, the difference D1 can be represented by a 5-bit complement of 2, with a predetermined value of 1. Therefore, the logic circuit 1361 of the comparison logic circuit 136 can output an alarm signal SIG when the difference D1 is not equal to "5'b00001" (i.e., decimal "1"), "5'b00000" (i.e., decimal "0"), or "5'b11111" (i.e., decimal "31" and the complement of 2 "-1"). AL1 In other words, when the decimal difference D1 is not equal to "0", "1", or "31", it means that the difference D1 is greater than a predetermined value, and the comparison logic circuit 136 can output an alarm signal SIG. AL1 In this case, according to the truth table of logic circuit 1361, logic circuit 1361 can be implemented using two NOT OR gates NOR1 and NOR2 and one AND gate AND1. Specifically, AND gate AND1 can receive the five bits D1[0], D1[1], D1[2], D1[3] and D1[4] of the difference D1 as its input, NOR gate NOR1 can receive the four largest bits D1[1], D1[2], D1[3] and D1[4] of the difference D1 as its input, and NOR gate NOR2 can receive the output of AND gate AND1 and the output of NOR gate NOR1 as its input. In this way, NOR gate NOR2 can output the comparison result CR1.

[0026] It should be noted that Figure 1 The structure of the clock surge detection circuit 100 shown is for illustrative purposes and is not intended to limit the scope of this disclosure. For example, in some embodiments, the detection unit 130 and the timing control unit 140 may also be implemented with different structures.

[0027] In this embodiment, the clock surge detection circuit 100 can detect whether there is a surge between two consecutive conduction times. However, this disclosure is not limited thereto. In some embodiments, the input clock signal SIG CKIN Surges can also occur during the duration of voltage V2 (i.e., two consecutive off times), and the clock surge detector 100 can also be used to detect the input clock signal SIG. CKIN Invert the clock signal and use the inverted input clock signal SIG. IVCK It is used as its input signal to detect the input clock signal SIG. CKIN The surge occurring during the turn-off time. Furthermore, in some embodiments, to detect surges in the input clock signal SIG... CKIN The surge occurring between the on-time and off-time can be used to replicate another set of elements based on the elements shown in the surge detection circuit 100, and input clock signal SIG. CKIN The inverted version is used as the input signal to detect the input clock signal SIG. CKIN The surge that occurs during the off-time.

[0028] Figure 4 This illustration shows a clock surge detection circuit 200 according to an embodiment of the present disclosure. The clock surge detection circuit 200 differs from the clock surge detection circuit 100 in that the clock surge detection circuit 200 further includes an inverter 250, a clock generator 260, a counter 270, a detection unit 280, and a timing control unit 290.

[0029] In this embodiment, the clock generator 110, counter 120, detection unit 130, and timing control unit 140 can be used to detect the input clock signal SIG. CKIN The surge that occurs during the conduction time, and the inverter 250, clock generator 260, counter 270, detection unit 280 and timing control unit 290 can be used to detect the input clock signal SIG. CKIN The surge that occurs during the off-time.

[0030] Specifically, inverter 250 can enable the input clock signal SIG by... CKIN Invert to generate the inverted input clock signal SIG IVCK Clock generator 260 can receive inverted input clock signal SIG. IVCK And inverting the input clock signal SIGIVCK When the voltage is V1, a reference clock signal SIG is generated. REF2 and make the reference clock signal SIG REF2 The frequency is higher than the inverting input clock signal SIG IVCK The frequency of the inverted input clock signal SIG. In this case, counter 270 can count the frequency of the inverted input clock signal SIG. IVCK At voltage V1, the reference clock signal SIG REF2 The current accumulated number of cycles elapsed, NC2. That is, the reference clock signal SIG. REF2 It can be used as a measurement input clock signal SIG CKIN The duration of the off-time (i.e., the inverting input clock signal SIG) IVCK Reference for the duration of voltage V1.

[0031] In addition, the detection unit 280 can input an inverted clock signal SIG. IVCK After the voltage changes from V1 to V2, the difference D2 between the previous accumulated number NP2 and the current accumulated number NC2 counted by counter 270 is calculated. After the difference D2 between the previous accumulated number NP2 and the current accumulated number NC2 is updated, the detection unit 280 can determine the inverted input clock signal SIG based on the difference D2. IVCK The two on-times before and after (i.e., the input clock signal SIG) CKIN Whether a surge occurs during the two shutdown periods (before and after), and generate an alarm signal SIG when a surge is detected. AL2 Furthermore, the detection unit 280 can further store the current accumulated number NC2 as a previous accumulated number NP2 for the next detection. In some embodiments, the detection unit 280 may have... Figure 1 The detection unit 130 shown has the same structure.

[0032] In this embodiment, the timing control unit 290 can generate control signals to control the operating timing of the detection unit 280. In some embodiments, the timing control unit 290 may have... Figure 1 The timing control unit 290 has the same structure as the timing control unit 140 shown. For example, the timing control unit 290 can input an inverted clock signal SIG. IVCK When the voltage changes from V1 to V2, a timing control signal is generated, and a control signal SIG is generated by delaying the timing control signal. CT4 In this case, the detection unit 280 determines the control signal SIG. CT4 This is triggered to update the difference D2 between the previous accumulated number NP2 and the current accumulated number NC2.

[0033] Furthermore, the timing control unit 290 can utilize the delay control signal SIG CT4Generate control signal SIG CT5 And the detection unit 280 based on the control signal SIG CT5 Triggered to generate an alarm signal SIG AL2 (If a surge is detected), the current accumulated number NC2 is stored as the previously accumulated number NP2. Furthermore, the timing control unit 290 can use the delay control signal SIG... CT5 Generate control signal SIG CT6 Furthermore, counter 270 can receive the control signal SIG. CT6 It was reset at that time.

[0034] Furthermore, in this embodiment, the clock surge detection circuit 200 may further include an OR gate OR1, and its two input terminals may be coupled to the outputs of detection units 130 and 280. In this case, the clock surge detection circuit 200 can detect the alarm signal SIG. AL1 When emitted by detection unit 130, or in alarm signal SIG AL2 When detected by the detection unit 280, an alarm signal SIG is output through the output terminal of the OR gate OR1. AL3 .

[0035] Figure 5 Display for detecting input clock signal SIG according to an embodiment of the present disclosure CKIN Method M1 for detecting clock surges. Method M1 includes steps S110 to S150. In some embodiments, method M1 may be performed using clock surge detection circuit 100 or 200. For example, in step S110, clock generator 110 may detect clock surges at input clock signal SIG. CKIN The reference clock signal SIG is generated at voltage V1. REF1 and make the reference clock signal SIG REF1 The frequency is higher than the input clock signal SIG CKIN The frequency.

[0036] In step S120, counter 120 counts the input clock signal SIG. CKIN At voltage V1, the reference clock signal SIG REF1 The current accumulated number NC1 of the elapsed cycles is used to measure the input clock signal SIG. CKIN The voltage V1 is maintained for a specified duration. In step S130, the detection unit 130 can detect the input clock signal SIG. CKIN After the voltage changes from V1 to V2, the difference D1 between the previous accumulated number NP1 and the current accumulated number NC1 is calculated. Then, the input clock signal SIG... CKINDuring the shutdown period, after the difference D1 between the previous accumulated number NP1 and the current accumulated number NC1 is updated, the detection unit 130 can detect whether there is any surge based on the difference D1 between the previous accumulated number NP1 and the current accumulated number NC1, and generate an alarm signal SIG when a surge is detected in step S140. AL1 Furthermore, in step S150, the detection unit 130 can store the current accumulated number NC1 as the previous accumulated number NP1 in preparation for the next detection.

[0037] In some embodiments, to control the operating timing of the detection unit 130, method M1 may further include causing the timing control unit 140 to respond to the input clock signal SIG. CKIN When the voltage changes from V1 to V2, a timing control signal SIG is generated. SEQ1 And according to the timing control signal SIG SEQ1 Generate control signal SIG CT1 SIG CT2 and SIG CT3 Accordingly, the detection unit 130 can receive the control signal SIG CT1 When step S130 is performed, the difference D1 between the previous accumulated number NP1 and the current accumulated number NC1 is updated, and the control signal SIG is received. CT2 Steps S140 and S150 are performed during this time. Afterwards, counter 120 can receive the control signal SIG. CT3 Reset in time.

[0038] In this embodiment, method M1 can detect whether there is a surge between two consecutive conduction times. However, the present invention is not limited thereto. In some embodiments, method M1 also detects the surge by using the input clock signal SIG. CKIN Inverting to detect the input clock signal SIG CKIN A surge occurs during the turn-off time, and an inverted input clock signal SIG is used. IVCK As its input signal, it is used to perform steps S110 to S150.

[0039] In summary, the clock surge detection circuit and method provided by the embodiments of this disclosure can measure the duration of two on-times or off-times before and after an input clock signal using a reference clock signal with a higher frequency, and detect whether a surge has occurred by observing whether the difference between the two durations is greater than a predetermined value. The clock surge detection circuit and method allow users to detect surges with the required tolerance by appropriately selecting the frequency and predetermined value of the reference clock signal, and thus can be applied to a variety of applications.

[0040] Symbol Explanation 100: Clock surge detection circuit 110, 260: Clock generator 120, 270: Counters 130: Detection Unit 132, 1342, 1362: Temporary registers 134: Subtractor 136: Comparison Logic Circuit 140, 290: Timing control unit 142, 250: Inverters 146: SR latch 148: Delay Control Unit 200: Clock surge detection circuit 280: Detection Unit 1341: Carry-lookahead subtractor 1361: Logic Circuits 1482, 1484, 1486: Delay elements AND1: and gate CR1: Comparison Results D1, D2: Difference D1[0], D1[1], D1[2], D1[3], D1[4]: bits DA1, DA2, DA3: Duration M1: Method NC1, NC2: Current accumulated number NOR1, NOR2: NOT gate NP1, NP2: Previous accumulated numbers OR1: OR gate D: Data input terminal Q: Data output end R: Reset end S: Setting end S110, S120, S130, S140, S150: Steps SIG AL1 SIG AL2 SIG AL3 Alarm signal SIG CKIN Input clock signal SIG CT1， SIG CT2， SIG CT3 Control signals SIG CT4 SIG CT5 SIG CT6 Control signals SIGIVCK Inverting input clock signal SIG REF1 SIG REF2 Reference clock signal SIG SEQ1 Timing control signals T1, T2, T3: Time points V1, V2: Voltage

Claims

1. A clock surge detection circuit, comprising: A first clock generator is configured to receive an input clock signal and generate a first reference clock signal when the input clock signal is at a first voltage, wherein the frequency of the first reference clock signal is higher than the frequency of the input clock signal. A first counter is configured to count a first current accumulation number of cycles elapsed by the first reference clock signal when the input clock signal is in the counting phase of the first voltage; as well as The first detection unit is configured to calculate the difference between a first previous accumulated number and a first current accumulated number after the input clock signal changes from the first voltage to the second voltage in a determination phase later than the counting phase, and after calculating the difference between the first previous accumulated number and the first current accumulated number, store the first current accumulated number as the first previous accumulated number, and generate a first alarm signal based on the difference between the first previous accumulated number and the first current accumulated number.

2. The clock surge detection circuit of claim 1, further comprising: A first timing control unit is configured to generate a first timing control signal when the input clock signal changes from the first voltage to the second voltage, and to generate a first control signal by delaying the first timing control signal during the determination phase. The first detection unit is triggered by the first control signal to calculate the difference between the first previously accumulated number and the first current accumulated number.

3. The clock surge detection circuit of claim 2, wherein the first timing control unit is further configured to generate a second control signal by delaying the first control signal during the determination phase; The first detection unit is triggered by the second control signal to generate the first alarm signal and stores the first current accumulated number as the first previous accumulated number.

4. The clock surge detection circuit of claim 3, wherein the first timing control unit is further configured to generate a third control signal by delaying the second control signal during the determination phase; The first counter is reset when the third control signal is received.

5. The clock surge detection circuit of claim 4, wherein the first timing control unit comprises: An SR latch includes a setting terminal configured to receive an inverted input clock signal, a reset terminal configured to receive the third control signal, and a data output terminal configured to output the first timing control signal after the input clock signal changes to the second voltage; and A delay control unit configured to generate the first control signal, the second control signal, and the third control signal based on the first timing control signal.

6. The clock surge detection circuit of claim 3, wherein the first detection unit comprises: A register configured to, upon receiving the second control signal, store the first current accumulated number as the first previously accumulated number; and A subtractor configured to subtract the first previous accumulated number from the first current accumulated number, or to subtract the first current accumulated number from the first previous accumulated number, thereby calculating the difference between the first previous accumulated number and the first current accumulated number upon receiving the first control signal.

7. The clock surge detection circuit of claim 6, wherein the first delay between the first timing control signal and the first control signal is longer than the calculation time of the subtractor.

8. The clock surge detection circuit of claim 6, wherein the subtractor comprises: A carry-lookahead subtractor configured to continuously subtract the first current accumulated number from the first previous accumulated number to calculate the difference between the first previous accumulated number and the first current accumulated number; and A register, configured to be triggered by the first control signal, to store the difference between the first previously accumulated number and the first currently accumulated number.

9. The clock surge detection circuit of claim 6, wherein the first detection unit further comprises: a comparison logic circuit configured to generate the first alarm signal in the determination phase when receiving the second control signal and when the difference between the first previously accumulated number and the first currently accumulated number is greater than a predetermined value.

10. The clock surge detection circuit of claim 9, wherein the comparison logic circuit comprises: A logic circuit configured to continuously obtain a comparison result between the difference calculated by the subtractor and the predetermined value; and A register, configured to be triggered by the second control signal, to store the comparison result between the difference calculated by the subtractor and the predetermined value.

11. The clock surge detection circuit of claim 9, wherein the second delay between the first control signal and the second control signal is longer than the calculation time of the comparison logic circuit.

12. The clock surge detection circuit of claim 1, wherein the first detection unit generates the first alarm signal when the difference between the first previously accumulated number and the first currently accumulated number is greater than a predetermined value during the determination phase.

13. The clock surge detection circuit of claim 1, wherein the first clock generator is deactivated when the input clock signal is at the second voltage.

14. The clock surge detection circuit of claim 1, further comprising: A third inverter is configured to generate an inverted input clock signal by inverting the input clock signal. A second clock generator is configured to receive the inverted input clock signal and generate a second reference clock signal when the inverted input clock signal is at the first voltage, wherein the frequency of the second reference clock signal is higher than the frequency of the inverted input clock signal. A second counter, configured to count a second current accumulation number of cycles of the second reference clock signal; as well as The second detection unit is configured to calculate the difference between the second previous accumulated number and the second current accumulated number after the inverting input clock signal changes from the first voltage to the second voltage, and after calculating the difference between the second previous accumulated number and the second current accumulated number, generate a second alarm signal based on the difference between the second previous accumulated number and the second current accumulated number, and store the second current accumulated number as the second previous accumulated number.

15. The clock surge detection circuit of claim 14, further comprising: The second timing control unit is configured to generate a second timing control signal when the inverted input clock signal changes from the first voltage to the second voltage, and to generate a fourth control signal by delaying the second timing control signal; The second detection unit is triggered by the fourth control signal to calculate the difference between the second previous accumulated number and the second current accumulated number.

16. The clock surge detection circuit of claim 15, wherein the second timing control unit is further configured to generate a fifth control signal by delaying the fourth control signal, and to generate a sixth control signal by delaying the fifth control signal; The second detection unit is triggered by the fifth control signal to generate the second alarm signal, and stores the second current accumulated number as the second previous accumulated number, and the second counter is reset when the sixth control signal is received.

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