Method for realizing black box function based on DSP 28335 external expansion SRAM and FLASH

Abstract

The invention relates to a method and device for realizing a black box function based on DSP 28335 external expansion SRAM and FLASH, electronic equipment and a storage medium. The method comprises the following steps of: externally connecting a static random access memory (SRAM) and a flash memory FLASH for a DSP28335 chip through an XINTF interface; recording preset operation data of the DSP28335 chip by the expanded SRAM on the basis of a preset expanded SRAM data recording process; storing the data recorded by the externally expanded SRAM by the externally expanded FLASH based on a preset externally expanded FLASH data storage process; and reading the data recorded by the externally expanded SRAM by the externally expanded FLASH based on a preset externally expanded FLASH data reading process. According to the method, the SRAM and the FLASH are externally expanded based on the DSP 28335, so that operation data recording in a period of time before a fault is realized, and subsequent data analysis and abnormal problem positioning are facilitated.

Description

Technical Field

[0001] This disclosure relates to the field of new energy vehicle power generation systems, and more specifically, to a method, apparatus, electronic device, and computer-readable storage medium for implementing a "black box" function based on an external SRAM and FLASH of a DSP 28335. Background Technology

[0002] When a serious fault occurs in the engine assembly or GCU (motor controller) of the power generation system, the "black box" can record data in real time for a period of time before the serious fault occurs, which is convenient for professionals to analyze fault information. The recording of key data in the operation of the automotive power generation system is extremely important. When a serious fault occurs in the system, the "black box" can record the key data operating status before the fault occurs in a timely manner. The data will not be lost after power failure, which is convenient for subsequent fault cause analysis and problem localization.

[0003] Existing technologies for implementing fault data logging functionality based on the TMS320F28335 include:

[0004] Using the TMS320F28335's on-chip SRAM and FLASH has the advantage of making full use of on-chip resources and shortening software development and porting time. However, the disadvantages are more obvious in this project. Although the 28335 has 256K x 16-bit FLASH and 34K x 16-bit SRAM, the program and data space may not be enough for complex applications, which will limit the development of subsequent functions.

[0005] When a system malfunctions, the fault data is stored in the EEPROM. Subsequently, the problem can be analyzed and located by viewing the historical fault records stored in the EEPROM. This method is mostly used to record the data at the moment of the fault. The stored data is relatively small, and it cannot generate fault data curves or trace the running data in the 5 seconds or even 10 seconds before the fault. Therefore, it is relatively limited in its help for fault analysis and location.

[0006] Therefore, one or more methods are needed to solve the above problems.

[0007] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0008] The purpose of this disclosure is to provide a method, apparatus, electronic device, and computer-readable storage medium for implementing a "black box" function based on external SRAM and FLASH of DSP 28335, thereby overcoming at least to some extent one or more problems caused by the limitations and defects of related technologies.

[0009] According to one aspect of this disclosure, a method for implementing "black box" functionality based on external SRAM and FLASH of a DSP 28335 is provided, comprising:

[0010] The DSP28335 chip is externally connected to a static random access memory (SRAM) and a flash memory (FLASH) via the XINTF interface.

[0011] The external SRAM is used to record the preset operating data of the DSP28335 chip based on the preset external SRAM data recording process.

[0012] The data recorded in the external SRAM is saved by using the external FLASH data saving process based on the preset external FLASH data saving process.

[0013] The data recorded in the expanded SRAM is read from the expanded FLASH based on a preset expanded FLASH data reading process.

[0014] In one exemplary embodiment of this disclosure, the method further includes:

[0015] The 20 address lines and 4 GPIO ports of the DSP28335 chip are used as the address lines XA20-XA23 of the external FLASH chip.

[0016] In one exemplary embodiment of this disclosure, the preset operating data in the method is: the voltage, current, and temperature data of the DSP28335 chip.

[0017] In one exemplary embodiment of this disclosure, the method further includes:

[0018] The XRD pin of the DSP28335 chip is connected to the read enable control signal OE# of the external FLASH and SRAM, respectively;

[0019] The XWE0 pin of the DSP28335 chip is connected to the write protection control signal WE# of the external FLASH and SRAM, respectively;

[0020] The GPIO pins of the DSP28335 chip are connected to the external FLASH RY / BY pins. When this pin is high, FLASH operation is enabled.

[0021] In one exemplary embodiment of this disclosure, the preset external SRAM data recording process in the method further includes:

[0022] Process 101: Set the total number of SRAM records, which includes the number of members in each group and the total number of groups;

[0023] Procedure 102: Initialize SRAM data to 0;

[0024] Condition 101: If a serious fault occurs, the F28335 will no longer update data to SRAM; otherwise, critical data will continue to be updated.

[0025] Process 103: If a fault occurs, SRAM will no longer be enabled, and data updates will stop;

[0026] Process 104: Without faults, after each set of data is recorded, the address is incremented to prepare for recording the next set of data;

[0027] Process 105: Start recording a new set of data based on the address in Process 104;

[0028] Condition 102: If the data recorded in SRAM exceeds the set total value, the old data needs to be updated according to the "first-in, first-out" principle; otherwise, the address is incremented to prepare for the next data recording.

[0029] Process 106: Update the old data of the original record in sequence according to the first-in, first-out principle;

[0030] Step 107: Determine that the data recorded in SRAM has not exceeded the total number, increment the address, and wait for the next set of parameters to be updated;

[0031] Process 108: When the program execution cycle is reached, record a new set of data.

[0032] In one exemplary embodiment of this disclosure, the preset external FLASH data storage process in the method further includes:

[0033] Procedure 201: Read the total number of historical faults from FLASH;

[0034] Procedure 202: Select the cumulative fault count storage address. The cumulative fault count storage address is placed on the first page of FLASH, and sector 0 is selected.

[0035] Procedure 203: Erase sector 0. The FLASH memory needs to be erased before each write operation.

[0036] Procedure 204: Increment the total number of historical failures by 1 and write it to FLASH to complete the saving of the total number of historical failures;

[0037] Process 205: Increment the total number of historical faults read in Process 201 by 1, and select the starting address for storing new fault data;

[0038] Procedure 206: After determining the address in Procedure 205, begin erasing the corresponding sectors;

[0039] Procedure 207: Preparations before writing fault data to FLASH;

[0040] Judgment condition 201: When the SRAM is not full and the set number of data is not filled, the data is saved to the FLASH according to the first-in-first-out order; otherwise, subsequent steps are required.

[0041] Process 208: If condition 201 is not met, process 208 is executed. Data is directly read from SRAM and cached in an array with a length of 256. If the number of reads exceeds 256, the maximum of 256 is taken; otherwise, the actual remaining number of reads in SRAM is taken.

[0042] Step 209: Write the startup command according to the FLASH datasheet, and after allocating the FLASH address, write the array data in Step 208 into the FLASH in sequence;

[0043] Process 2010: When condition 201 is true, process 10 is executed to cache the unupdated SRAM data into the array. For details, please refer to the description of condition 201 and process 208.

[0044] Process 2011: Write the startup command according to the FLASH datasheet, and after allocating the FLASH address, write the array data in Process 2010 into the FLASH in sequence;

[0045] Process 2012: Read the updated SRAM data and cache the updated SRAM data in an array;

[0046] Process 2013: After writing the startup command according to the FLASH datasheet and allocating the FLASH address, write the array data in Process 2012 into the FLASH in sequence;

[0047] Process 2014: After completing the previous steps to record the data before the fault, write the software fault code when the fault occurs.

[0048] In one exemplary embodiment of this disclosure, the preset external FLASH data reading process in the method further includes:

[0049] Procedure 301: Read the first four data points of the Nth data set, starting with N equal to 0;

[0050] Procedure 302: Send the data read in procedure 301 to the external bus via CAN communication;

[0051] Condition 301: If the data from 1-4 FLASH groups read from N has not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0052] Procedure 303: Read data from the 5th to the 8th data points of the Nth data set, starting with N equal to 0;

[0053] Procedure 304: Send the data read in procedure 303 to the external bus via CAN communication;

[0054] Condition 302: If the 5-8 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0055] Procedure 305: Read data from the 9th to the 12th data points of the Nth data set, starting with N equal to 0;

[0056] Procedure 306: Send the data read in procedure 305 to the external bus via CAN communication;

[0057] Condition 303: If the 9-12 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0058] Procedure 307: Read data points 13-16 of the Nth data set, starting with N equal to 0;

[0059] Procedure 308: Send the data read in procedure 307 to the external bus via CAN communication;

[0060] Condition 304: If the 13-16 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0061] Procedure 309: N = N + 1, that is, calculate the sequence number of the next set of data to be sent;

[0062] Condition 305: If N equals the set value, meaning all the data recorded in FLASH has been read once, then the data reading ends; otherwise, repeat process 301.

[0063] Procedure 3010: Stop reading FLASH data, set N to 0.

[0064] In one aspect of this disclosure, an apparatus for implementing a "black box" function based on external SRAM and FLASH of a DSP 28335 is provided, comprising:

[0065] The chip connection module is used to connect a static random access memory (SRAM) and a flash memory (FLASH) to the DSP28335 chip via the XINTF interface.

[0066] The data recording module is used to record the preset operating data of the DSP28335 chip by using the external SRAM based on the preset external SRAM data recording process.

[0067] The data storage module is used to save the data recorded in the external SRAM based on the preset external FLASH data storage process.

[0068] The data reading module is used to read the data recorded in the external SRAM based on the preset external FLASH data reading process.

[0069] In one aspect of this disclosure, an electronic device is provided, comprising:

[0070] Processor; and

[0071] A memory storing computer-readable instructions that, when executed by the processor, implement the method according to any one of the preceding claims.

[0072] In one aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method according to any one of the preceding claims.

[0073] This disclosure discloses an exemplary embodiment of a method for implementing a "black box" function based on external SRAM and FLASH memory of a DSP 28335. The method includes: externally connecting a Static Random Access Memory (SRAM) and a Flash Memory (FLASH) to the DSP 28335 chip via an XINTF interface; recording preset operating data of the DSP 28335 chip in the external SRAM according to a preset external SRAM data recording procedure; saving the data recorded in the external SRAM to the external FLASH memory according to a preset external FLASH data saving procedure; and reading the data recorded in the external SRAM to the external FLASH memory according to a preset external FLASH data reading procedure. This disclosure, by using external SRAM and FLASH memory of the DSP 28335, enables the recording of operating data for a period of time prior to a fault, which is beneficial for subsequent data analysis and anomaly localization.

[0074] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0075] The above and other features and advantages of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0076] Figure 1A flowchart is shown illustrating a method for implementing a "black box" function based on an external SRAM and FLASH of a DSP 28335 according to an exemplary embodiment of the present disclosure;

[0077] Figure 2 The diagram illustrates the pin connections of the external SRAM, FLASH, and F28335 for a method of implementing a "black box" function based on an external SRAM and FLASH of a DSP 28335 according to an exemplary embodiment of the present disclosure.

[0078] Figure 3 The diagram illustrates an external SRAM data recording control flowchart of a method for implementing a "black box" function based on an external SRAM and FLASH of a DSP 28335, according to an exemplary embodiment of the present disclosure.

[0079] Figure 4 The diagram illustrates an exemplary embodiment of the present disclosure of a method for implementing a "black box" function based on external SRAM and FLASH of a DSP 28335, including the external FLASH data storage process.

[0080] Figure 5 The diagram illustrates an exemplary embodiment of the present disclosure of a method for implementing a "black box" function based on external SRAM and FLASH of a DSP 28335, including an external FLASH data reading flowchart.

[0081] Figure 6 A structural block diagram of an apparatus for implementing a "black box" function based on an external SRAM and FLASH of a DSP 28335, according to an exemplary embodiment of the present disclosure, is shown.

[0082] Figure 7 A block diagram of an electronic device according to an exemplary embodiment of the present disclosure is shown schematically;

[0083] Figure 8 The illustration shows a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0084] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0085] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0086] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0087] In this example embodiment, a method for implementing "black box" functionality based on external SRAM and FLASH of a DSP 28335 is first provided; see reference. Figure 1 As shown, the method for implementing "black box" functionality based on external SRAM and FLASH of DSP 28335 may include the following steps:

[0088] Step S110 involves connecting a static random access memory (SRAM) and a flash memory (FLASH) to the DSP28335 chip via the XINTF interface.

[0089] Step S120: The external SRAM is used to record the preset operating data of the DSP28335 chip based on the preset external SRAM data recording process.

[0090] Step S130: The data recorded in the expanded SRAM is saved by the expanded FLASH based on the preset expanded FLASH data saving process;

[0091] Step S140: The data recorded in the expanded SRAM is read from the expanded FLASH based on the preset expanded FLASH data reading process.

[0092] This disclosure discloses an exemplary embodiment of a method for implementing a "black box" function based on external SRAM and FLASH memory of a DSP 28335. The method includes: externally connecting a Static Random Access Memory (SRAM) and a Flash Memory (FLASH) to the DSP 28335 chip via an XINTF interface; recording preset operating data of the DSP 28335 chip in the external SRAM according to a preset external SRAM data recording procedure; saving the data recorded in the external SRAM to the external FLASH memory according to a preset external FLASH data saving procedure; and reading the data recorded in the external SRAM to the external FLASH memory according to a preset external FLASH data reading procedure. This disclosure, by using external SRAM and FLASH memory of the DSP 28335, enables the recording of operating data for a period of time prior to a fault, which is beneficial for subsequent data analysis and anomaly localization.

[0093] The following will further explain a method for implementing a "black box" function based on external SRAM and FLASH of DSP 28335 in this example embodiment.

[0094] Example 1:

[0095] In this example embodiment, the DSP 28335 described in this disclosure is the TMS320F28335 digital signal processor, hereinafter referred to as 28335. The external interface XINTF of the 28335 chip adopts a non-multiplexed asynchronous bus, which can be used to expand SRAM, FLASH modules, etc. In this project, the on-chip SRAM and FLASH of the 28335 are used for program development. Externally, an SRAM (Static Random Access Memory) and FLASH (Flash Memory) are expanded through the XINTF interface. The expanded SRAM is mainly used to record key operating parameters such as current, voltage, and temperature in the power generation system in real time. The key parameters are temporarily stored in the expanded SRAM to avoid occupying the chip's operating space. More data can be stored as needed to improve software execution efficiency. When the power generation system experiences a serious fault shutdown, the expanded SRAM stops recording data and saves the data recorded in the SRAM for a period of time before the fault and the corresponding fault codes to the expanded FLASH. When performing fault backtracking analysis, the host computer can read the historical fault data curves and corresponding fault codes from the expanded FLASH for analysis.

[0096] In step S110, a static random access memory (SRAM) and a flash memory (FLASH) can be externally connected to the DSP28335 chip via the XINTF interface.

[0097] In this example embodiment, the method further includes:

[0098] The 20 address lines and 4 GPIO ports of the DSP28335 chip are used as the address lines XA20-XA23 of the external FLASH chip.

[0099] In this example embodiment, the preset operating data in the method is: the voltage, current, and temperature data of the DSP28335 chip.

[0100] In this example embodiment, the method further includes:

[0101] The XRD pin of the DSP28335 chip is connected to the read enable control signal OE# of the external FLASH and SRAM, respectively;

[0102] The XWE0 pin of the DSP28335 chip is connected to the write protection control signal WE# of the external FLASH and SRAM, respectively;

[0103] The GPIO pins of the DSP28335 chip are connected to the external FLASH RY / BY pins. When this pin is high, FLASH operation is enabled.

[0104] In step S120, the external SRAM can record the preset operating data of the DSP28335 chip based on the preset external SRAM data recording process.

[0105] In this example embodiment, the preset external SRAM data recording process in the method further includes:

[0106] Process 101: Set the total number of SRAM records, which includes the number of members in each group and the total number of groups;

[0107] Procedure 102: Initialize SRAM data to 0;

[0108] Condition 101: If a serious fault occurs, the F28335 will no longer update data to SRAM; otherwise, critical data will continue to be updated.

[0109] Process 103: If a fault occurs, SRAM will no longer be enabled, and data updates will stop;

[0110] Process 104: Without faults, after each set of data is recorded, the address is incremented to prepare for recording the next set of data;

[0111] Process 105: Start recording a new set of data based on the address in Process 104;

[0112] Condition 102: If the data recorded in SRAM exceeds the set total value, the old data needs to be updated according to the "first-in, first-out" principle; otherwise, the address is incremented to prepare for the next data recording.

[0113] Process 106: Update the old data of the original record in sequence according to the first-in, first-out principle;

[0114] Step 107: Determine that the data recorded in SRAM has not exceeded the total number, increment the address, and wait for the next set of parameters to be updated;

[0115] Process 108: When the program execution cycle is reached, record a new set of data.

[0116] In step S130, the data recorded in the external SRAM can be saved by the external FLASH based on the preset external FLASH data saving process.

[0117] In this example embodiment, the preset external FLASH data storage process in the method further includes:

[0118] Procedure 201: Read the total number of historical faults from FLASH;

[0119] Procedure 202: Select the cumulative fault count storage address. The cumulative fault count storage address is placed on the first page of FLASH, and sector 0 is selected.

[0120] Process 203: Erase sector 0. The FLASH needs to be erased before each write operation.

[0121] Procedure 204: Increment the total number of historical failures by 1 and write it to FLASH to complete the saving of the total number of historical failures;

[0122] Process 205: Increment the total number of historical faults read in Process 201 by 1, and select the starting address for storing new fault data;

[0123] Procedure 206: After determining the address in Procedure 205, begin erasing the corresponding sectors;

[0124] Procedure 207: Preparations before writing fault data to FLASH;

[0125] Judgment condition 201: When the SRAM is not full and the set number of data is not filled, the data is saved to the FLASH according to the first-in-first-out order; otherwise, subsequent steps are required.

[0126] Process 208: If condition 201 is not met, process 208 is executed. Data is directly read from SRAM and cached in an array with a length of 256. If the number of reads exceeds 256, the maximum of 256 is taken; otherwise, the actual remaining number of reads in SRAM is taken.

[0127] Step 209: Write the startup command according to the FLASH datasheet, and after allocating the FLASH address, write the array data in Step 208 into the FLASH in sequence;

[0128] Process 2010: When condition 201 is true, process 10 is executed to cache the unupdated SRAM data into the array. For details, please refer to the description of condition 201 and process 208.

[0129] Process 2011: Write the startup command according to the FLASH datasheet, and after allocating the FLASH address, write the array data in Process 2010 into the FLASH in sequence;

[0130] Process 2012: Read the updated SRAM data and cache the updated SRAM data in an array;

[0131] Process 2013: After writing the startup command according to the FLASH datasheet and allocating the FLASH address, write the array data in Process 2012 into the FLASH in sequence;

[0132] Process 2014: After completing the previous steps to record the data before the fault, write the software fault code when the fault occurs.

[0133] In step S140, the data recorded in the external SRAM can be read from the external FLASH based on a preset external FLASH data reading process.

[0134] In this example embodiment, the preset external FLASH data reading process in the method further includes:

[0135] Procedure 301: Read the first four data points of the Nth data set, starting with N equal to 0;

[0136] Procedure 302: Send the data read in procedure 301 to the external bus via CAN communication;

[0137] Condition 301: If the data from 1-4 FLASH groups read from N has not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0138] Procedure 303: Read data from the 5th to the 8th data points of the Nth data set, starting with N equal to 0;

[0139] Procedure 304: Send the data read in procedure 303 to the external bus via CAN communication;

[0140] Condition 302: If the 5-8 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0141] Procedure 305: Read data from the 9th to the 12th data points of the Nth data set, starting with N equal to 0;

[0142] Procedure 306: Send the data read in procedure 305 to the external bus via CAN communication;

[0143] Condition 303: If the 9-12 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0144] Procedure 307: Read data points 13-16 of the Nth data set, starting with N equal to 0;

[0145] Procedure 308: Send the data read in procedure 307 to the external bus via CAN communication;

[0146] Condition 304: If the 13-16 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0147] Procedure 309: N = N + 1, that is, calculate the sequence number of the next set of data to be sent;

[0148] Condition 305: If N equals the set value, meaning all the data recorded in FLASH has been read once, then the data reading ends; otherwise, repeat process 301.

[0149] Procedure 3010: Stop reading FLASH data, set N to 0.

[0150] Example 2:

[0151] In the embodiments of this example, as Figure 2 As shown, the TMS320F28335 chip is connected to the external SRAM and FLASH as follows:

[0152] 1. The XA0-XA19 pins of the TMS320F28335 chip are connected to the external FLASH and external SRAM A0-A19. The external FLASH in this project has 24 address line pins, while the F28335 only has 20 address lines. Therefore, 4 additional GPIO ports need to be configured as FLASH address lines XA20-XA23.

[0153] 2. The F28335 chip's data lines XD0-XD15 are connected to the external FLASH and external SRAM data lines DQ0-DQ15, respectively. During normal system operation, the F28335 transmits key data such as voltage, current, and temperature to the SRAM for storage via the data lines. If the system experiences a serious fault and shuts down, the SRAM stops updating data, and the F28335 chip reads the SRAM data in batches and saves it to the relevant addresses in the FLASH.

[0154] 3. The external memory of the F28335 can be mapped to three memory areas: Zone0, Zone6, and Zone7. The clock signal XZCS6 of Zone6 controls the external FLASH chip select signal CE#, and the clock signal XZCS7 of Zone7 controls the external SRAM chip select signal CE#.

[0155] 4. The F28335 XRD pin is connected to the read enable control signal OE# of the external FLASH and SRAM, respectively.

[0156] 5. The F28335 XWE0 pin is connected to the write protection control signal WE# of the external FLASH and SRAM, respectively.

[0157] 6. The F28335 GPIO pin is connected to the external FLASH RY / BY pin. FLASH operation is only allowed when this pin is high.

[0158] 7. RESET is a reset signal, active high.

[0159] 8. SRAM is a static random access memory. The data stored in it will not be lost as long as power is on. The data will be lost when power is off. FLASH is a long-life non-volatile memory. The data stored in it will not be lost when power is off.

[0160] 9. When used together, the two systems can transfer key parameters to SRAM in real time when there is no fault, improving the processing efficiency of the F28335 program. When a serious fault occurs in the system, the F28335 reads the data from the SRAM for a period of time before the fault (3 seconds in this project) and stores it sequentially in the external FLASH to avoid data loss after power failure.

[0161] In the embodiments of this example, as Figure 3 The diagram shows the flow chart for external SRAM data recording control, and the specific implementation steps of the corresponding technical solution are described below.

[0162] Procedure 101: Set the total number of SRAM record data, which includes the number of members in each group and the total number of groups. The specific method is as follows:

[0163] 1. Set the number of parameters in a group. In this project, each group contains 15 key parameters, including voltage, current, temperature, and speed. These 15 parameters form a loop group.

[0164] 2. Set the total number of groups. In this project, we set it to 20,000 groups.

[0165] 3. The total number of SRAM records = 15 * 20000, the total number of records is 300,000.

[0166] Procedure 102: Initialize SRAM data to 0.

[0167] Condition 101: If a serious fault occurs, the F28335 will no longer update data to SRAM; otherwise, critical data will continue to be updated.

[0168] Process 103: If a fault occurs, SRAM will no longer be enabled, and data updates will stop.

[0169] Process 104: Without faults, after each set of data is recorded, the address is incremented to prepare for recording the next set of data.

[0170] Process 105: Start recording a new set of data based on the address in Process 104.

[0171] Condition 102: Data recording falls into two categories. If the amount of data recorded in SRAM exceeds the set total value, the old data needs to be updated according to the "first-in, first-out" principle (updating one set of data at a time, i.e., 15 key data); otherwise, the address is incremented to prepare for the next data recording.

[0172] Process 106: Update the old data of the original record in sequence according to the "first-in, first-out" principle (update a set of data each time, i.e., 15 key data).

[0173] Process 107: If the data recorded in SRAM does not exceed the total number, increment the address and wait for the next set of parameters to be updated.

[0174] Process 108: When the program execution cycle is reached, record a new set of data.

[0175] In the embodiments of this example, as Figure 4 The diagram shows the control flowchart for external FLASH data recording, and the specific implementation steps of the corresponding technical solution are described below.

[0176] Procedure 201: Read the total number of historical faults from FLASH. This step is the basic reference for the address allocation of historical fault records.

[0177] FLASH address allocation follows these principles:

[0178] 1. The FLASH address can be divided into 16 "blocks", each "block" has 16 sectors, and each sector is 65536 in size. This project only needs to take the first 8 "blocks".

[0179] 2. Each "block" can store two fault records corresponding to the total number of records. The address range of the first fault record is sector 1-sector 7 of the first "block" (458,752 records in total), and the address range of the second fault record is sector 8-sector 14 of the first "block" (458,752 records in total); and so on. The address range of the 15th fault record is sector 1-sector 7 of the 8th "block", and the address range of the 16th fault record is sector 8-sector 14 of the 8th "block". If the historical records exceed 16, the system will cycle back to updating from the first fault record.

[0180] 3. The cumulative number of failures is stored at the address of the first "block", the first address of sector 0.

[0181] Process 202: Select the cumulative fault count storage address. The cumulative fault count storage address for this project is placed on the first page of FLASH. Select sector 0.

[0182] Process 203: Erase sector 0. The FLASH needs to be erased before each write operation.

[0183] Process 204: Increment the total number of historical faults by 1 and write it to FLASH to complete the saving of the total number of historical faults. It should be noted that after the number of historical faults exceeds 16, it will be updated to 1 to facilitate the subsequent update of new fault data addresses.

[0184] Process 205: Increment the total number of historical faults read in Process 201 by 1, and select the starting address for storing new fault data. For details, please refer to the supplementary explanation in Process 1.

[0185] Process 206: After determining the address in Process 205, start erasing the corresponding sector. For the allocation of fault data recording sectors, please refer to the supplementary explanation in Process 1.

[0186] Process 207: Preparations before writing fault data to FLASH.

[0187] Judgment condition 201: When the SRAM is not full and the set number of data is not filled, the data is saved to FLASH according to the "first-in, first-out" order; otherwise, subsequent steps are required.

[0188] Example of conditional judgment 201: Suppose the SRAM is set to store a total of 10,000 data entries. If a serious fault occurs after storing 9,000 entries, simply write the 9,000 entries to the external FLASH memory in sequence. If the number of data entries exceeds 10,000, and a serious fault occurs after storing 11,000 data entries in the SRAM, then first record 10,000 - (11,000 - 10,000) = 9,000 data entries in sequence, and then record the latest recorded (11,000 - 10,000) = 1,000 data entries in sequence to the FLASH memory.

[0189] Process 208: If condition 201 is not met, process 208 is executed. Data is directly read from SRAM and cached in an array with a length of 256. If the number of reads exceeds 256, the maximum of 256 is taken; otherwise, the actual remaining number of reads from SRAM is taken.

[0190] Step 209: Write the startup command according to the FLASH datasheet, and after allocating the FLASH address, write the array data in Step 208 into the FLASH in sequence.

[0191] Process 2010: When condition 201 is true, process 10 is executed to cache the unupdated SRAM data into the array. For details, please refer to the description of condition 201 and process 208.

[0192] Process 2011: Write the startup command according to the FLASH datasheet, and after allocating the FLASH address, write the array data in Process 2010 into the FLASH in sequence.

[0193] Process 2012: Read the updated SRAM data and cache the updated SRAM data in an array. For details, please refer to the explanation of condition judgment 201 and process 208.

[0194] Process 2013: After writing the startup command according to the FLASH datasheet and allocating the FLASH address, write the array data in Process 2012 into the FLASH in sequence.

[0195] Process 2014: After completing the previous steps to record the data before the fault, write the software fault code when the fault occurs.

[0196] In the embodiments of this example, as Figure 5 The diagram shows the flowchart for reading and sending data from the external FLASH memory, along with the specific implementation steps of the corresponding technical solution. The description is as follows:

[0197] Process 301: Read the first 1-4 data points of the Nth data set, starting with N equal to 0.

[0198] Process 302: Send the data read in process 301 to the external bus via CAN communication.

[0199] Condition 301: If the data from 1-4 FLASH groups of N has not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0200] Process 303: Read the 5th to 8th data points of the Nth data set, starting with N equal to 0.

[0201] Process 304: Send the data read in process 303 to the external bus via CAN communication.

[0202] Condition 302: If the 5-8 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0203] Process 305: Read data from the 9th to the 12th data in the Nth data set, starting with N equal to 0.

[0204] Process 306: Send the data read in process 305 to the external bus via CAN communication.

[0205] Condition 303: If the 9-12 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0206] Process 307: Read data from the 13th to the 16th data from the Nth data set, starting with N equal to 0.

[0207] Process 308: Send the data read in process 307 to the external bus via CAN communication.

[0208] Condition 304: If the 13-16 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step.

[0209] Process 309: N = N + 1, that is, calculate the sequence number of the next set of data to be sent.

[0210] Condition 305: If N equals the set value, meaning all the data recorded in FLASH has been read once, then the data reading ends; otherwise, the previous reading process repeats.

[0211] Procedure 3010: Stop reading FLASH data, set N to 0.

[0212] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0213] Furthermore, this example embodiment also provides a device for implementing "black box" functionality based on external SRAM and FLASH of a DSP 28335. (See reference...) Figure 6 As shown, the device 200, which implements a "black box" function based on external SRAM and FLASH of DSP 28335, may include: a chip connection module 210, a data recording module 220, a data storage module 230, and a data reading module 240. Wherein:

[0214] Chip connection module 210 is used to connect a static random access memory (SRAM) and a flash memory (FLASH) to the DSP28335 chip via the XINTF interface.

[0215] The data recording module 220 is used to record the preset operating data of the DSP28335 chip by using the external SRAM based on the preset external SRAM data recording process.

[0216] The data storage module 230 is used to store the data recorded in the external SRAM based on the preset external FLASH data storage process.

[0217] The data reading module 240 is used to read the data recorded in the external SRAM based on the preset external FLASH data reading process.

[0218] The specific details of each of the above-mentioned device modules that implement the "black box" function based on the external SRAM and FLASH of DSP 28335 have been described in detail in the corresponding method for implementing the "black box" function based on the external SRAM and FLASH of DSP 28335, so they will not be repeated here.

[0219] It should be noted that although the above detailed description mentions several modules or units of the device 200 that implements the "black box" function based on the DSP 28335's external SRAM and FLASH, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0220] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0221] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented as entirely hardware embodiments, entirely software embodiments (including firmware, microcode, etc.), or embodiments combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.”

[0222] The following reference Figure 7 To describe an electronic device 300 according to such an embodiment of the present invention. Figure 7 The electronic device 300 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0223] like Figure 7 As shown, the electronic device 300 is presented in the form of a general-purpose computing device. The components of the electronic device 300 may include, but are not limited to: at least one processing unit 310, at least one storage unit 320, a bus 330 connecting different system components (including storage unit 320 and processing unit 310), and a display unit 340.

[0224] The storage unit stores program code that can be executed by the processing unit 310, causing the processing unit 310 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 310 can perform actions such as... Figure 1 Steps S110 to S140 are shown in the diagram.

[0225] Storage unit 320 may include readable media in the form of volatile storage units, such as random access memory (RAM) 3201 and / or cache memory 3202, and may further include read-only memory (ROM) 3203.

[0226] Storage unit 320 may also include a program / utility 3204 having a set (at least one) program module 3205, such program module 3205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0227] Bus 330 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0228] Electronic device 300 can also communicate with one or more external devices 370 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 300, and / or with any device that enables electronic device 300 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 350. Furthermore, electronic device 300 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 360. As shown, network adapter 360 communicates with other modules of electronic device 300 via bus 330. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 300, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0229] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0230] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section above.

[0231] refer to Figure 8 As shown, a program product 400 for implementing the above-described method according to an embodiment of the present invention is described. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0232] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0233] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0234] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0235] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0236] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0237] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0238] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for implementing "black box" functionality based on external SRAM and FLASH of a DSP 28335, characterized in that, The method includes: The DSP28335 chip is externally connected to a static random access memory (SRAM) and a flash memory (FLASH) via the XINTF interface. The external SRAM is used to record the preset operating data of the DSP28335 chip based on the preset external SRAM data recording process. The data recorded in the external SRAM is saved by using the external FLASH data saving process based on the preset external FLASH data saving process. The data recorded in the expanded SRAM is read from the expanded FLASH based on a preset expanded FLASH data reading process.

2. The method as described in claim 1, characterized in that, The method further includes: The 20 address lines and 4 GPIO ports of the DSP28335 chip are used as the address lines XA20-XA23 of the external FLASH chip.

3. The method as described in claim 1, characterized in that, The preset operating data in the method are: the voltage, current, and temperature data of the DSP28335 chip.

4. The method as described in claim 1, characterized in that, The method further includes: The XRD pin of the DSP28335 chip is connected to the read enable control signal OE# of the external FLASH and SRAM, respectively; The XWE0 pin of the DSP28335 chip is connected to the write protection control signal WE# of the external FLASH and SRAM, respectively; The GPIO pins of the DSP28335 chip are connected to the external FLASH RY / BY pins. When this pin is high, FLASH operation is enabled.

5. The method as described in claim 1, characterized in that, The pre-defined external SRAM data recording process in the method also includes: Process 101: Set the total number of SRAM records, which includes the number of members in each group and the total number of groups; Procedure 102: Initialize SRAM data to 0; Condition 101: If a serious fault occurs, the F28335 will no longer update data to SRAM; otherwise, critical data will continue to be updated. Process 103: If a fault occurs, SRAM will no longer be enabled, and data updates will stop; Process 104: Without faults, after each set of data is recorded, the address is incremented to prepare for recording the next set of data; Process 105: Start recording a new set of data based on the address in Process 104; Condition 102: If the data recorded in SRAM exceeds the set total value, the old data needs to be updated according to the "first-in, first-out" principle; otherwise, the address is incremented to prepare for the next data recording. Process 106: Update the old data of the original record in sequence according to the first-in, first-out principle; Step 107: Determine that the data recorded in SRAM has not exceeded the total number, increment the address, and wait for the next set of parameters to be updated; Process 108: When the program execution cycle is reached, record a new set of data.

6. The method as described in claim 1, characterized in that, The pre-defined external FLASH data storage process in the method also includes: Procedure 201: Read the total number of historical faults from FLASH; Procedure 202: Select the cumulative fault count storage address. The cumulative fault count storage address is placed on the first page of FLASH, and sector 0 is selected. Procedure 203: Erase sector 0. The FLASH memory needs to be erased before each write operation. Procedure 204: Increment the total number of historical failures by 1 and write it to FLASH to complete the saving of the total number of historical failures; Process 205: Increment the total number of historical faults read in Process 201 by 1, and select the starting address for storing new fault data; Procedure 206: After determining the address in Procedure 205, begin erasing the corresponding sectors; Procedure 207: Preparations before writing fault data to FLASH; Judgment condition 201: When the SRAM is not full and the set number of data is not filled, the data is saved to the FLASH according to the first-in-first-out order; otherwise, subsequent steps are required. Process 208: If condition 201 is not met, process 208 is executed. Data is directly read from SRAM and cached in an array with a length of 256. If the number of reads exceeds 256, the maximum of 256 is taken; otherwise, the actual remaining number of reads in SRAM is taken. Step 209: Write the startup command according to the FLASH datasheet, and after allocating the FLASH address, write the array data in Step 208 into the FLASH in sequence; Process 2010: When condition 201 is met, process 2010 is executed to cache the unupdated SRAM data in an array. The caching method is the same as that described in process 208. Process 2011: Write the startup command according to the FLASH datasheet, and after allocating the FLASH address, write the array data in Process 2010 into the FLASH in sequence; Process 2012: Read the updated SRAM data and cache the updated SRAM data in an array; Process 2013: After writing the startup command according to the FLASH datasheet and allocating the FLASH address, write the array data in Process 2012 into the FLASH in sequence; Process 2014: After completing the previous steps to record the data before the fault, write the software fault code when the fault occurs.

7. The method as described in claim 1, characterized in that, The pre-defined external FLASH data reading process in the method also includes: Procedure 301: Read the first four data points of the Nth data set, starting with N equal to 0; Procedure 302: Send the data read in procedure 301 to the external bus via CAN communication; Condition 301: If the data from 1-4 FLASH groups read from N has not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step. Procedure 303: Read data from the 5th to the 8th data points of the Nth data set, starting with N equal to 0; Procedure 304: Send the data read in procedure 303 to the external bus via CAN communication; Condition 302: If the 5-8 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step. Procedure 305: Read data from the 9th to the 12th data points of the Nth data set, starting with N equal to 0; Procedure 306: Send the data read in procedure 305 to the external bus via CAN communication; Condition 303: If the 9-12 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step. Procedure 307: Read data points 13-16 of the Nth data set, starting with N equal to 0; Procedure 308: Send the data read in procedure 307 to the external bus via CAN communication; Condition 304: If the 13-16 FLASH data from group N have not yet been sent to the bus via CAN, wait until the transmission is complete. During the waiting period, no new data will be read. Otherwise, proceed to the next step. Procedure 309: N = N + 1, that is, calculate the sequence number of the next set of data to be sent; Condition 305: If N equals the set value, meaning all the data recorded in FLASH has been read once, then the data reading ends; otherwise, repeat process 301. Procedure 3010: Stop reading FLASH data, set N to 0.

8. A device for implementing "black box" functionality based on external SRAM and FLASH of a DSP 28335, characterized in that, The device includes: The chip connection module is used to connect a static random access memory (SRAM) and a flash memory (FLASH) to the DSP28335 chip via the XINTF interface. The data recording module is used to record the preset operating data of the DSP28335 chip by using the external SRAM based on the preset external SRAM data recording process. The data storage module is used to save the data recorded in the external SRAM based on the preset external FLASH data storage process. The data reading module is used to read the data recorded in the external SRAM based on the preset external FLASH data reading process.

9. An electronic device, characterized in that, include Processor; and A memory storing computer-readable instructions that, when executed by the processor, implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 7.

Images