High-precision fractional frequency division circuit based on multi-phase clock

Abstract

The invention discloses a high-precision fractional frequency division circuit based on a multiphase clock, which belongs to the field of integrated circuits and comprises a delay phase-locked loop, a selector, a phase interpolator, a sampling circuit and a digital control circuit. The delay phase-locked loop generates multi-phase clock signals, comprises a voltage-controlled delay line formed by cascading delay units, a phase frequency detector, a charge pump and a low-pass filter, avoids jitter accumulation generated by a traditional voltage-controlled oscillator, is more suitable for being applied to high-frequency scenes, and is higher in locking speed, lower in power consumption, easier to integrate and higher in anti-noise performance. The phase interpolator realizes fractional frequency division by changing the phase of an input signal, each rising edge of an output clock after frequency division is aligned with the edge of a theoretical value, accurate control of the phase is realized, phase stray can be reduced while high precision is realized, and the purity of the output signal is optimized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-precision fractional frequency divider circuit based on a multiphase clock. Background Technology

[0002] In recent years, the rapid development of technologies such as wireless communication, satellite positioning, radar navigation, and computers has placed higher demands on data transmission speed and quality. Phase-locked loops (PLLs) provide local oscillator signals for wireless transceiver systems; the frequency range, resolution, and phase noise of the PLL directly affect the performance of the entire system.

[0003] The minimum resolution of the output frequency of an integer frequency divider phase-locked loop is the reference frequency, while a fractional frequency divider phase-locked loop can achieve smaller frequency steps, has higher resolution, and can achieve more precise frequency adjustment, thus gaining widespread application.

[0004] Delayed phase-locked loops (PLLs) use a delay line instead of an oscillator to achieve clock synchronization. A frequency and phase detector compares the phase of the reference clock with the feedback clock, and a control voltage is generated through a charge pump and a low-pass filter to regulate the delay chain. Fractal-number frequency division based on a delayed phase-locked loop eliminates the need for a delta-sigma modulator, enabling high accuracy while suppressing quantization noise. Summary of the Invention

[0005] The purpose of this invention is to provide a high-precision fractional frequency divider circuit based on a multiphase clock to solve the problems in the background art.

[0006] To solve the above-mentioned technical problems, the present invention provides a high-precision fractional frequency divider circuit based on a multi-phase clock, comprising: A delay phase-locked loop (PLL) is used to generate a multi-phase clock signal by inputting a reference signal. The selector selects a set of adjacent clock signals from the clock signals with the same frequency but different phases output by the delay phase-locked loop. A single-ended to differential circuit generates four clock signals from a set of adjacent clock signals output from the selector and inputs them to the phase interpolator. The phase interpolator interpolates a phase clock between the four input clock signals to achieve precise phase control and generate a fractional-division clock signal. The digital control circuit generates control signals for the selector and phase interpolator, as well as an integer-divided clock signal, through reference signals, integer-divided frequency control words, and fractional-divided frequency control words. The sampling circuit samples the integer-divided clock signal using the fractional-divided clock signal to achieve the required fractional-divided frequency.

[0007] In one embodiment, the delay phase-locked loop includes a voltage-controlled delay line composed of a plurality of cascaded delay units, a frequency and phase detector, a charge pump, and a low-pass filter. A voltage-controlled delay line generates a multiphase clock; The frequency and phase detector compares the phase of the reference signal and the clock output from the last delay unit, and outputs four pulse signals UP, UPN, DN, and DNN to control the charge pump to charge or discharge. The current generated by the charge pump is used to generate a voltage control signal V through a low-pass filter. Ctrl The input is the delay unit in the voltage-controlled delay line.

[0008] In one embodiment, the delay unit includes PMOS transistors MP1 to MP8 and NMOS transistors MN1 to MN8; The sources of PMOS transistors MP1 through MP4 are all connected to the control voltage V output from a low-pass filter. ctrl The sources of PMOS transistors MP5 to MP8 are all connected to the power supply voltage VDD; the sources of NMOS transistors MN1 to MN8 are all connected to GND; and the gates of PMOS transistor MP1 and NMOS transistor MN1 are all connected to the input signal VDD. in1 The gates of both PMOS transistor MP4 and NMOS transistor MN4 are connected to the input signal V. in2 ; The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1, and together they are connected to the gates of PMOS transistor MP2 and NMOS transistor MN2, the gates of PMOS transistor MP5 and NMOS transistor MN5, and the drains of PMOS transistor MP6 and NMOS transistor MN6; the drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4, and together they are connected to the gates of PMOS transistor MP3 and NMOS transistor MN3, the gates of PMOS transistor MP6 and NMOS transistor MN6, and the drains of PMOS transistor MP5 and NMOS transistor MN5. The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN2, and then connected to the gate of NMOS transistor MN7. The drain of NMOS transistor MN7 is simultaneously connected to the drain and gate of PMOS transistor MP7, and the gate of PMOS transistor MP8. The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN8, and the output is V. out .

[0009] In one embodiment, the charge pump includes PMOS transistors MP1 to MP4, NMOS transistors MN1 to MN4, and operational amplifier AMP1; The sources of PMOS transistors MP1 and MP2 are both connected to the power supply voltage VDD. The gate of PMOS transistor MP1 is connected to its own drain and then to the drain of NMOS transistor MN3. The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP1. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP3 and the source of PMOS transistor MP4. The gate of PMOS transistor MP3 is connected to the UP signal output by the frequency and phase detector. The drain of PMOS transistor MP3 is connected to the drain of NMOS transistor MN1 and the output of amplifier AMP1. The output of amplifier AMP1 is connected to its own positive input. The gate of PMOS transistor MP4 is connected to the UPN signal output by the frequency and phase detector. The drain of PMOS transistor MP4 is simultaneously connected to the drain of NMOS transistor MN2 and the negative input terminal of amplifier AMP1, and the output is OUT. The gate of NMOS transistor MN1 is connected to the DN signal output by the frequency and phase detector. The source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and then connected to the drain of NMOS transistor MN4. The gate of NMOS transistor MN2 is connected to the DNN signal output by the frequency and phase detector. The gates of NMOS transistor MN3 and NMOS transistor MN4 are connected to the bias voltage Vb1. The sources of NMOS transistor MN3 and NMOS transistor MN4 are both connected to GND.

[0010] In one embodiment, the phase interpolator includes resistors R1 to R2, NMOS transistors MN1 to MN52, and inverters INV1 to INV16. The first end of resistor R1 and the first end of R2 are both connected to the power supply voltage VDD. The second end of resistor R1 is connected to the drain of NMOS transistor MN1 and the output is OUT. The second end of resistor R2 is connected to the drain of NMOS transistor MN2 and the output is OUTN. The gate of NMOS transistor MN1 is connected to the input clock signal Vp1. The gate of NMOS transistor MN2 is connected to the input clock signal Vn1. The source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and then connected to the drain of NMOS transistor MN7. The source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN6 and then connected to the gate of NMOS transistor MN7. The source of NMOS transistor MN7 is connected to GND. The drain of NMOS transistor MN5 is connected to the bias voltage Vb2. The control signal ctrl_PI

[15] is input to the gate of NMOS transistor MN6. The control signal ctrl_PI

[15] is input to the gate of NMOS transistor MN5 after passing through inverter INV1. The source of NMOS transistor MN6 is connected to GND. The gate of NMOS transistor MN3 is connected to the input clock signal Vp2, the gate of NMOS transistor MN4 is connected to the input clock signal Vn2, the source of NMOS transistor MN3 is connected to the source of NMOS transistor MN4 and then connected to the drain of NMOS transistor MN7, the source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN9 and then connected to the gate of NMOS transistor MN10, the source of NMOS transistor MN10 is connected to GND, the drain of NMOS transistor MN10 is connected to the drain of NMOS transistor MN7, the drain of NMOS transistor MN8 is connected to the bias voltage Vb2, the control signal ctrl_PI

[14] is input to the gate of NMOS transistor MN9, the control signal ctrl_PI

[14] is input to the gate of NMOS transistor MN8 after passing through inverter INV2, and the source of NMOS transistor MN9 is connected to GND; Three NMOS transistors and one inverter constitute a unit. There are a total of sixteen units in this unit. In the last unit, the drain of NMOS transistor MN52 is connected to the source of NMOS transistor MN3 and the source of NMOS transistor MN4. The source of NMOS transistor MN50 is connected to the drain of NMOS transistor MN51 and then connected to the gate of NMOS transistor MN52. The source of NMOS transistor MN52 is connected to GND. The drain of NMOS transistor MN50 is connected to the bias voltage Vb2. The control signal ctrl_PI[0] is input to the gate of NMOS transistor MN51. The control signal ctrl_PI[0] is input to the gate of NMOS transistor MN50 after passing through inverter INV16. The source of NMOS transistor MN51 is connected to GND.

[0011] In one embodiment, the digital control circuit includes a first digital control module, a second digital control module, and a third digital control module. A reference signal, a fractional frequency divider control word, and an integer frequency divider control word are input to the first digital control module to generate a control signal ctrl_MUX for the selector, which is then input to the second digital control module. A 16-bit control word PI_SEL is input to both the second and third digital control modules. The second digital control module generates a control signal ctrl_PI for the phase interpolator, which is then input to the third digital control module. The third digital control module generates an integer frequency divider signal clk_int, which is then input to the sampling circuit.

[0012] This invention provides a high-precision fractional frequency divider circuit based on a multi-phase clock, comprising a delay phase-locked loop (PLL), a selector, a single-ended to differential converter, a phase interpolator, a sampling circuit, and a digital control circuit. The PLL uses a voltage-controlled delay line (VCD) instead of a voltage-controlled oscillator (VCO) to adjust the phase, avoiding the jitter accumulation caused by traditional VCOs, making it more suitable for high-frequency applications. Furthermore, it offers faster locking speed, lower power consumption, easier integration, and stronger noise immunity. This invention achieves fractional frequency division by simply changing the phase of the input signal through phase interpolation. Each rising edge of the output clock after division is aligned with the theoretical value edge, reducing phase spurious signals while achieving high precision and optimizing the purity of the output signal. Attached Figure Description

[0013] Figure 1 A schematic diagram of the high-precision fractional frequency divider circuit based on a multiphase clock of the present invention is shown.

[0014] Figure 2 A schematic diagram of the delayed phase-locked loop of the present invention is shown.

[0015] Figure 3 A schematic diagram of the delay unit constituting the voltage-controlled delay line of the present invention is shown.

[0016] Figure 4 A schematic diagram of the charge pump in the delayed phase-locked loop of the present invention is shown.

[0017] Figure 5 The waveform diagram of the multi-phase clock generated by the delay phase-locked loop of the present invention is shown.

[0018] Figure 6 A simplified circuit diagram of the phase interpolator of the present invention is shown.

[0019] Figure 7 A schematic diagram of the digital control circuit structure of the present invention is shown. Detailed Implementation

[0020] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a high-precision fractional frequency divider circuit based on a multi-phase clock, as proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0021] This invention proposes a high-precision fractional frequency divider circuit based on a multiphase clock, the structure of which is as follows: Figure 1 As shown, it includes: a delay phase-locked loop (PLL), a selector, a single-ended to differential converter, a phase interpolator, a sampling circuit, and a digital control circuit. The reference signal `fref` is input to the PLL to generate clock signals `clk1` to `clk` with the same frequency but different phases. 16The reference signal fref and the fractional frequency divider control word ctrl_frac and the integer frequency divider control word ctrl_int are simultaneously input into the digital control circuit to generate the control signal ctrl_MUX from clk1 to clk1. 16 Select a set of adjacent clocks (clk) n with clk n+1 After passing through a single-ended to differential converter, four clock signals Vp1, Vn1, Vp2, and Vn2 are generated. The digital control circuit generates a control signal ctrl_PI to control the phase interpolator to interpolate the phase clocks of the four clock signals, resulting in fractional-divided clock signals clk_frac_n and clk_frac_p. The sampling circuit uses the fractional-divided clock signal to sample the integer-divided clock signal clk_int output by the digital control circuit to obtain the required clock signal clk_out.

[0022] The circuit structure of a delay phase-locked loop is as follows: Figure 2 As shown, the system includes a voltage-controlled delay line (VCDL), a phase-frequency detector (PFD), a charge pump (CP), and a low-pass filter (LPF). The phase-frequency detector compares the reference signal fref with the clock signal clk output from the VCDL. 16 The phase, based on fref and clk 16 The phase relationship generates pulse signals UP, UPN, DN, and DNN to control the charging or discharging of the charge pump. The low-pass filter includes capacitors C1 and C2 and resistor R1, with capacitor C1 connected in series with resistor R1 and then in parallel with capacitor C2. The low-pass filter can filter out high-frequency phase noise and convert the current signal generated by the charge pump into a voltage V. ctrl This voltage V ctrl The input voltage-controlled delay line controls the delay time, forming a feedback loop.

[0023] A voltage-controlled delay line (VCDL) consists of sixteen cascaded delay units. For the principle of a single delay unit, please refer to [link / reference needed]. Figure 3 This includes PMOS transistors MP1-MP8 and NMOS transistors MN1-MN8. The sources of PMOS transistors MP1-MP4 are all connected to the control voltage V output by a low-pass filter. ctrl The sources of PMOS transistors MP5 to MP8 are all connected to the power supply voltage VDD; the sources of NMOS transistors MN1 to MN8 are all connected to GND; and the gates of PMOS transistor MP1 and NMOS transistor MN1 are all connected to the input signal VDD. in1 The gates of both PMOS transistor MP4 and NMOS transistor MN4 are connected to the input signal V. in2The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1, which together connects to the gates of PMOS transistor MP2 and NMOS transistor MN2, the gates of PMOS transistor MP5 and NMOS transistor MN5, and the drains of PMOS transistor MP6 and NMOS transistor MN6. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4, which together connects to the gates of PMOS transistor MP3 and NMOS transistor MN3, the gates of PMOS transistor MP6 and NMOS transistor MN6, and the drains of PMOS transistor MP5 and NMOS transistor MN5. The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN2, and then to the gate of NMOS transistor MN7. The drain of NMOS transistor MN7 is simultaneously connected to the drain of PMOS transistor MP7, the gate of PMOS transistor MP7, and the gate of PMOS transistor MP8. The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN8, and the output is V. out The delay unit can adjust the signal transmission delay time, achieving precise control over the delay amount and generating multi-phase clock signals.

[0024] For the principle of charge pump in delay phase-locked loop, please refer to [link / reference]. Figure 4This includes PMOS transistors MP1-MP4, NMOS transistors MN1-MN4, and operational amplifier AMP1. The sources of PMOS transistors MP1 and MP2 are both connected to the power supply voltage VDD. The gate and drain of PMOS transistor MP1 are connected to the drain of NMOS transistor MN3. The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP1. The drain of PMOS transistor MP2 is simultaneously connected to the sources of PMOS transistors MP3 and MP4. The gate of PMOS transistor MP3 is connected to the UP signal output from a frequency and phase detector. The drain of PMOS transistor MP3 is simultaneously connected to the drain of NMOS transistor MN1 and the output of amplifier AMP1. The output of amplifier AMP1... The output terminal is connected to its own positive input terminal; the gate of PMOS transistor MP4 is connected to the UPN signal output by the frequency and phase detector, and the drain of PMOS transistor MP4 is connected to both the drain of NMOS transistor MN2 and the negative input terminal of amplifier AMP1, with an output of OUT; the gate of NMOS transistor MN1 is connected to the DN signal output by the frequency and phase detector, the source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and then to the drain of NMOS transistor MN4, the gate of NMOS transistor MN2 is connected to the DNN signal output by the frequency and phase detector, the gates of NMOS transistor MN3 and NMOS transistor MN4 are connected to the bias voltage Vb1, and the sources of NMOS transistors MN3 and MN4 are both connected to GND. The charge pump adopts a drain-based current redirection structure, which can effectively solve the charge shunting problem and improve the switching speed, while keeping the current flowing into the power supply and ground constant, resulting in less crosstalk to the power supply. To reduce the mismatch between the PMOS and NMOS current sources, a rail-to-rail unity-gain operational amplifier is introduced to enable the UP and DOWN currents to track each other, thereby reducing the influence of the output voltage on the charging and discharging current.

[0025] The waveform of the multi-phase clock generated by the delay phase-locked loop is as follows: Figure 5 As shown, when the delay phase-locked loop is locked, clk and clk 16 Clock signals clk with the same frequency but differing by one reference clock cycle can be any two adjacent clock signals. n with clk n+1 The phase difference is π / 8 rad.

[0026] Simplified circuit of phase interpolator as follows Figure 6The circuit includes resistors R1 to R2, NMOS transistors MN1 to MN52, and inverters INV1 to INV16. The first end of resistors R1 and R2 are connected to the power supply voltage VDD. The second end of resistor R1 is connected to the drain of NMOS transistor MN1 and outputs OUT. The second end of resistor R2 is connected to the drain of NMOS transistor MN2 and outputs OUTN. The gate of NMOS transistor MN1 is connected to the input clock signal Vp1. The gate of NMOS transistor MN2 is connected to the input clock signal Vn1. The source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and then connected to the drain of NMOS transistor MN7. The source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN6 and then connected to the gate of NMOS transistor MN7. The source of NMOS transistor MN7 is connected to GND. The drain of NMOS transistor MN5 is connected to the bias voltage Vb2. The control signal ctrl_PI

[15] is input to the gate of NMOS transistor MN6. The control signal ctrl _PI

[15] is input to the gate of NMOS transistor MN5 after passing through inverter INV1, and the source of NMOS transistor MN6 is connected to GND; the gate of NMOS transistor MN3 is connected to the input clock signal Vp2, the gate of NMOS transistor MN4 is connected to the input clock signal Vn2, the source of NMOS transistor MN3 is connected to the source of NMOS transistor MN4 and then connected to the drain of NMOS transistor MN7, the source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN9 and then connected to the gate of NMOS transistor MN10, the source of NMOS transistor MN10 is connected to GND, the drain of NMOS transistor MN10 is connected to the drain of NMOS transistor MN7, the drain of NMOS transistor MN8 is connected to the bias voltage Vb2, the control signal ctrl_PI

[14] is input to the gate of NMOS transistor MN9, the control signal ctrl_PI

[14] is input to the gate of NMOS transistor MN8 after passing through inverter INV2, and the source of NMOS transistor MN9 is connected to GND. Three NMOS transistors and one inverter constitute a unit, and there are sixteen units in total. In the last unit, the drain of NMOS transistor MN52 is connected to the source of NMOS transistor MN3 and the source of NMOS transistor MN4. The source of NMOS transistor MN50 is connected to the drain of NMOS transistor MN51 and then connected to the gate of NMOS transistor MN52. The source of NMOS transistor MN52 is connected to GND. The drain of NMOS transistor MN50 is connected to the bias voltage Vb2. The control signal ctrl_PI[0] is input to the gate of NMOS transistor MN51. The control signal ctrl_PI[0] is input to the gate of NMOS transistor MN50 after passing through inverter INV16. The source of NMOS transistor MN51 is connected to GND. The phase interpolator performs phase interpolation on two pairs of differential clock signals Vp1, Vn1, Vp2 and Vn2. The control signal ctrl_PI controls the weight of the difference. By adjusting the size of the tail current, the phase of the output clock signal is changed to realize the required fractional frequency division signal.

[0027] Digital control circuits have a three-level structure, such as Figure 7 As shown, the reference signal fref, the fractional frequency divider control word ctrl_frac, and the integer frequency divider control word ctrl_int are input to the digital control module 1, which generates the control signal ctrl_MUX for the selector and inputs it to the digital control module 2. The sixteen-bit control word PI_SEL is input to both the digital control module 2 and the digital control module 3. The digital control module 2 generates the control signal ctrl_PI for the phase interpolator and inputs it to the digital control module 3. The digital control module 3 generates the integer frequency divider signal clk_int and inputs it to the sampling circuit.

[0028] This invention uses a delayed phase-locked loop through voltage V ctrl The control delay unit dynamically adjusts the transmission delay of the clock signal to generate clock signals clk1 to clk with the same frequency but different phases. 16 This design avoids the jitter accumulation caused by voltage-controlled oscillators, making it more suitable for high-frequency applications. It also features faster locking speed, lower power consumption, easier integration, and stronger noise immunity. By using a phase interpolator to change the phase of the input signal to achieve fractional frequency division, each rising edge of the output clock after division is aligned with the theoretical value edge, achieving precise phase control. This reduces phase spurious signals while achieving high precision, optimizing the purity of the output signal.

[0029] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-precision fractional frequency divider circuit based on a multi-phase clock, characterized in that, include: A delay phase-locked loop (PLL) is used to generate a multi-phase clock signal by inputting a reference signal. The selector selects a set of adjacent clock signals from the clock signals with the same frequency but different phases output by the delay phase-locked loop. A single-ended to differential circuit generates four clock signals from a set of adjacent clock signals output from the selector and inputs them to the phase interpolator. The phase interpolator interpolates a phase clock between the four input clock signals to achieve precise phase control and generate a fractional-division clock signal. The digital control circuit generates control signals for the selector and phase interpolator, as well as an integer-divided clock signal, through reference signals, integer-divided frequency control words, and fractional-divided frequency control words. The sampling circuit samples the integer-divided clock signal using the fractional-divided clock signal to achieve the required fractional-divided frequency.

2. The high-precision fractional frequency divider circuit based on a multi-phase clock as described in claim 1, characterized in that, The delay phase-locked loop includes a voltage-controlled delay line composed of several cascaded delay units, a frequency and phase detector, a charge pump, and a low-pass filter. A voltage-controlled delay line generates a multiphase clock; The frequency and phase detector compares the phase of the reference signal and the clock output from the last delay unit, and outputs four pulse signals UP, UPN, DN, and DNN to control the charge pump to charge or discharge. The current generated by the charge pump is used to generate a voltage control signal V through a low-pass filter. Ctrl The input is the delay unit in the voltage-controlled delay line.

3. The high-precision fractional frequency divider circuit based on a multi-phase clock as described in claim 2, characterized in that, The delay unit includes PMOS transistors MP1 to MP8 and NMOS transistors MN1 to MN8; The sources of PMOS transistors MP1 through MP4 are all connected to the control voltage V output from a low-pass filter. ctrl The sources of PMOS transistors MP5 to MP8 are all connected to the power supply voltage VDD; the sources of NMOS transistors MN1 to MN8 are all connected to GND; and the gates of PMOS transistor MP1 and NMOS transistor MN1 are all connected to the input signal VDD. in1 The gates of both PMOS transistor MP4 and NMOS transistor MN4 are connected to the input signal V. in2 ; The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1, and together they are connected to the gates of PMOS transistor MP2 and NMOS transistor MN2, the gates of PMOS transistor MP5 and NMOS transistor MN5, and the drains of PMOS transistor MP6 and NMOS transistor MN6; the drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4, and together they are connected to the gates of PMOS transistor MP3 and NMOS transistor MN3, the gates of PMOS transistor MP6 and NMOS transistor MN6, and the drains of PMOS transistor MP5 and NMOS transistor MN5. The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN2, and then connected to the gate of NMOS transistor MN7. The drain of NMOS transistor MN7 is simultaneously connected to the drain and gate of PMOS transistor MP7, and the gate of PMOS transistor MP8. The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN8, and the output is V. out .

4. The high-precision fractional frequency divider circuit based on a multi-phase clock as described in claim 2, characterized in that, The charge pump includes PMOS transistors MP1 to MP4, NMOS transistors MN1 to MN4, and operational amplifier AMP1; The sources of PMOS transistors MP1 and MP2 are both connected to the power supply voltage VDD. The gate of PMOS transistor MP1 is connected to its own drain and then to the drain of NMOS transistor MN3. The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP1. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP3 and the source of PMOS transistor MP4. The gate of PMOS transistor MP3 is connected to the UP signal output by the frequency and phase detector. The drain of PMOS transistor MP3 is connected to the drain of NMOS transistor MN1 and the output of amplifier AMP1. The output of amplifier AMP1 is connected to its own positive input. The gate of PMOS transistor MP4 is connected to the UPN signal output by the frequency and phase detector. The drain of PMOS transistor MP4 is simultaneously connected to the drain of NMOS transistor MN2 and the negative input terminal of amplifier AMP1, and the output is OUT. The gate of NMOS transistor MN1 is connected to the DN signal output by the frequency and phase detector. The source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and then connected to the drain of NMOS transistor MN4. The gate of NMOS transistor MN2 is connected to the DNN signal output by the frequency and phase detector. The gates of NMOS transistor MN3 and NMOS transistor MN4 are connected to the bias voltage Vb1. The sources of NMOS transistor MN3 and NMOS transistor MN4 are both connected to GND.

5. The high-precision fractional frequency divider circuit based on a multi-phase clock as described in claim 1, characterized in that, The phase interpolator includes resistors R1 to R2, NMOS transistors MN1 to MN52, and inverters INV1 to INV16. The first end of resistor R1 and the first end of R2 are both connected to the power supply voltage VDD. The second end of resistor R1 is connected to the drain of NMOS transistor MN1 and the output is OUT. The second end of resistor R2 is connected to the drain of NMOS transistor MN2 and the output is OUTN. The gate of NMOS transistor MN1 is connected to the input clock signal Vp1. The gate of NMOS transistor MN2 is connected to the input clock signal Vn1. The source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and then connected to the drain of NMOS transistor MN7. The source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN6 and then connected to the gate of NMOS transistor MN7. The source of NMOS transistor MN7 is connected to GND. The drain of NMOS transistor MN5 is connected to the bias voltage Vb2. The control signal ctrl_PI[15] is input to the gate of NMOS transistor MN6. The control signal ctrl_PI[15] is input to the gate of NMOS transistor MN5 after passing through inverter INV1. The source of NMOS transistor MN6 is connected to GND. The gate of NMOS transistor MN3 is connected to the input clock signal Vp2, the gate of NMOS transistor MN4 is connected to the input clock signal Vn2, the source of NMOS transistor MN3 is connected to the source of NMOS transistor MN4 and then connected to the drain of NMOS transistor MN7, the source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN9 and then connected to the gate of NMOS transistor MN10, the source of NMOS transistor MN10 is connected to GND, the drain of NMOS transistor MN10 is connected to the drain of NMOS transistor MN7, the drain of NMOS transistor MN8 is connected to the bias voltage Vb2, the control signal ctrl_PI[14] is input to the gate of NMOS transistor MN9, the control signal ctrl_PI[14] is input to the gate of NMOS transistor MN8 after passing through inverter INV2, and the source of NMOS transistor MN9 is connected to GND; Three NMOS transistors and one inverter constitute a unit. There are a total of sixteen units in this unit. In the last unit, the drain of NMOS transistor MN52 is connected to the source of NMOS transistor MN3 and the source of NMOS transistor MN4. The source of NMOS transistor MN50 is connected to the drain of NMOS transistor MN51 and then connected to the gate of NMOS transistor MN52. The source of NMOS transistor MN52 is connected to GND. The drain of NMOS transistor MN50 is connected to the bias voltage Vb2. The control signal ctrl_PI[0] is input to the gate of NMOS transistor MN51. The control signal ctrl_PI[0] is input to the gate of NMOS transistor MN50 after passing through inverter INV16. The source of NMOS transistor MN51 is connected to GND.

6. The high-precision fractional frequency divider circuit based on a multi-phase clock as described in claim 1, characterized in that, The digital control circuit includes a first digital control module, a second digital control module, and a third digital control module. A reference signal, a fractional frequency divider control word, and an integer frequency divider control word are input to the first digital control module to generate a control signal ctrl_MUX for the selector, which is then input to the second digital control module. A sixteen-bit control word PI_SEL is input to both the second and third digital control modules. The second digital control module generates a control signal ctrl_PI for the phase interpolator, which is then input to the third digital control module. The third digital control module generates an integer frequency divider signal clk_int, which is then input to the sampling circuit.

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