Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The semiconductor structure comprises: a memory array, wherein the memory array comprises a first sub-array and a second sub-array; the first sub-array comprises first semiconductor columns which extend along a first direction and are arranged at intervals along a second direction and a third direction; the second sub-array comprises second semiconductor columns which extend along the first direction and are arranged at intervals along the second direction and the third direction; in the same storage array, the first end parts of the first semiconductor columns arranged along the second direction in the first sub-array and the second end parts of the second semiconductor columns arranged along the second direction in the second sub-array are coupled to the same bit line; any two of the first direction, the second direction and the third direction intersect with each other.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor structure and its manufacturing method, a memory, and a memory system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) consists of multiple memory cells, each typically including a transistor and a capacitor. The gate of the transistor is coupled to the word line, the source (or drain) of the transistor is coupled to the bit line, and the drain (or source) of the transistor is coupled to the capacitor. As DRAM structures continue to shrink, three-dimensional structures have been used to spatially expand DRAM, forming 3D DRAM. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a memory, and a memory system.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising: a memory array, the memory array including a first subarray and a second subarray; the first subarray including: first semiconductor pillars extending along a first direction and evenly spaced along a second direction and a third direction; the second subarray including: second semiconductor pillars extending along the first direction and evenly spaced along the second direction and the third direction; in the same memory array, a first end of the first semiconductor pillars arranged along the second direction in the first subarray and a second end of the second semiconductor pillars arranged along the second direction in the second subarray are coupled to the same bit line; wherein any two of the first direction, the second direction and the third direction intersect.

[0006] In some embodiments, the first semiconductor pillar includes a first end and a third end disposed opposite to each other along the first direction; the second semiconductor pillar includes a second end and a fourth end disposed opposite to each other along the first direction; wherein, in the same memory array, the first subarray and the second subarray are arranged along the first direction, and the distance between the first end and the second end of the first semiconductor pillar and the second semiconductor pillar arranged along the first direction is less than the distance between the third end and the fourth end.

[0007] In some embodiments, in the same memory array, the bit lines extend along the second direction and are spaced apart along the third direction; the first end and the second end are mirror-symmetric about the bit lines; the third end and the fourth end are mirror-symmetric about the bit lines.

[0008] In some embodiments, the semiconductor structure further includes: a first gate structure disposed on at least one sidewall of the first semiconductor pillar; the first gate structure of the first semiconductor pillar arranged along the third direction coupled to the same first word line, the first word line extending along the third direction and spaced apart along the second direction; a second gate structure disposed on at least one sidewall of the second semiconductor pillar; and the second gate structure of the second semiconductor pillar arranged along the third direction coupled to the same second word line, the second word line extending along the third direction and spaced apart along the second direction.

[0009] In some embodiments, a plurality of the memory arrays are arranged along the first direction to form a memory block; the semiconductor structure further includes: a first conductive line, wherein first word lines in different memory arrays in the same memory block are coupled to the same first conductive line; and a second conductive line, wherein second word lines in different memory arrays in the same memory block are coupled to the same second conductive line.

[0010] In some embodiments, the number of the first conductive lines in the same memory block is the same as the number of the first semiconductor pillars arranged along the second direction in each of the first subarrays; the number of the second conductive lines in the same memory block is the same as the number of the second semiconductor pillars arranged along the second direction in each of the second subarrays.

[0011] In some embodiments, the semiconductor structure further includes: a first connection portion disposed between the first conductive line and the first word line, one end of the first connection portion being coupled to the first word line and the other end of the first connection portion being coupled to the first conductive line; and a second connection portion disposed between the second conductive line and the second word line, one end of the second connection portion being coupled to the second word line and the other end of the second connection portion being coupled to the second conductive line.

[0012] In some embodiments, both the first conductive line and the second conductive line extend along the first direction, and the first conductive line and the second conductive line are arranged alternately along the second direction.

[0013] In some embodiments, the semiconductor structure further includes: a first conductive portion disposed on the side of the first conductive line away from the first semiconductor pillar and coupled to the first conductive line; and a second conductive portion disposed on the side of the second conductive line away from the second semiconductor pillar and coupled to the second conductive line.

[0014] In some embodiments, the first conductive line and the second conductive line are aligned in the second direction; the first conductive portion and the second conductive portion are both disposed on the same side of the storage block in the first direction, and the first conductive portion and the second conductive portion are offset in the second direction.

[0015] In some embodiments, the first conductive line and the second conductive line are aligned in the second direction; the first conductive portion and the second conductive portion are both disposed on the same side of the storage block in the first direction, and the first conductive portion and the second conductive portion are aligned in the second direction.

[0016] In some embodiments, the first conductive line and the second conductive line are offset in the second direction; the first conductive portion and the second conductive portion are both disposed on the same side of the storage block in the first direction, and the first conductive portion and the second conductive portion are offset in the second direction.

[0017] In some embodiments, the first conductive line and the second conductive line are offset in the second direction; the first conductive portion and the second conductive portion are both disposed on different sides of the storage block in the first direction.

[0018] In some embodiments, the semiconductor structure further includes: a first capacitor disposed on the side of the first semiconductor post near the third end and coupled to the third end; and a second capacitor disposed on the side of the second semiconductor post near the fourth end and coupled to the fourth end.

[0019] Secondly, embodiments of this disclosure provide a memory, the memory comprising: a semiconductor structure as described in the above technical solutions; and peripheral circuitry coupled to the semiconductor structure.

[0020] In some embodiments, the memory includes: three-dimensional dynamic random access memory (3D DRAM).

[0021] Thirdly, embodiments of this disclosure provide a memory system, the memory system including: a memory as described in the above technical solutions; and a controller coupled to the memory and configured to control the memory.

[0022] Fourthly, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising: forming a memory array, the memory array including a first subarray and a second subarray, the first subarray including first semiconductor pillars extending along a first direction and evenly spaced along a second direction and a third direction; the second subarray including second semiconductor pillars extending along the first direction and evenly spaced along the second direction and the third direction; forming a bit line between the first subarray and the second subarray; in the same memory array, a first end of the first semiconductor pillar arranged along the second direction in the first subarray and a second end of the second semiconductor pillar arranged along the second direction in the second subarray are coupled to the same bit line; wherein any two of the first direction, the second direction and the third direction intersect.

[0023] In some embodiments, before forming a bit line between the first subarray and the second subarray, the method further includes: forming a first gate structure on at least one sidewall of the first semiconductor pillar; coupling the first gate structure of the first semiconductor pillar arranged along the third direction to the same first word line, the first word line extending along the third direction and spaced apart along the second direction; forming a second gate structure on at least one sidewall of the second semiconductor pillar; coupling the second gate structure of the second semiconductor pillar arranged along the third direction to the same second word line, the second word line extending along the third direction and spaced apart along the second direction.

[0024] In some embodiments, the first semiconductor pillar includes a first end and a third end disposed opposite to each other along the first direction; the second semiconductor pillar includes a second end and a fourth end disposed opposite to each other along the first direction; the step of forming a bit line between the first subarray and the second subarray includes: forming a bit line groove between a first end of the first semiconductor pillar and a second end of the second semiconductor pillar; filling the bit line groove with a conductive material to form a bit line; wherein, in the same memory array, the bit lines extend along the second direction and are spaced apart along the third direction.

[0025] In some embodiments, after forming a bit line between the first subarray and the second subarray, the method further includes: forming a first capacitor on the side of the first semiconductor pillar near the third end, the third end being coupled to the first capacitor; and forming a second capacitor on the side of the second semiconductor pillar near the fourth end, the fourth end being coupled to the second capacitor.

[0026] In some embodiments, the method further includes: forming a first connection portion on one side of the first semiconductor pillar along the third direction, the first connection portion being coupled to the first word line; and forming a second connection portion on one side of the second semiconductor pillar along the third direction, the second connection portion being coupled to the second word line.

[0027] In some embodiments, a plurality of the memory arrays are arranged along the first direction to form a memory block; the method further includes: forming a first conductive line on the side of the first connection portion away from the first semiconductor pillar, wherein the first word lines of different memory arrays in the same memory block are coupled to the same first conductive line through the first connection portion; forming a second conductive line on the side of the second connection portion away from the second semiconductor pillar, wherein the second word lines of different memory arrays in the same memory block are coupled to the same second conductive line through the second connection portion.

[0028] In some embodiments, both the first conductive line and the second conductive line extend along the first direction, and the first conductive line and the second conductive line are arranged alternately along the second direction.

[0029] In some embodiments, the method further includes: forming a first conductive portion on the side of the first conductive line away from the first connection portion, and the first conductive portion being coupled to the first conductive line; forming a second conductive portion on the side of the second conductive line away from the second connection portion, and the second conductive portion being coupled to the second conductive line.

[0030] This disclosure provides a semiconductor structure and its manufacturing method, a memory, and a memory system. In this embodiment, the memory array includes a first subarray and a second subarray. The first subarray includes first semiconductor pillars extending along a first direction and evenly spaced along a second direction and a third direction. The second subarray includes second semiconductor pillars extending along the first direction and evenly spaced along the second direction and a third direction. In the same memory array, the first end of the first semiconductor pillars in the first subarray arranged along the second direction and the second end of the second semiconductor pillars in the second subarray arranged along the second direction are coupled to the same bit line. Thus, the first and second subarrays in the same memory array can share the bit line, achieving a 50% reduction in the size of the bit line along the second direction while maintaining the same number of memory cells connected by the bit line, thereby improving the integration density of the semiconductor structure. Attached Figure Description

[0031] Figure 1 A schematic diagram of the structure of a three-dimensional dynamic random access memory provided for some embodiments;

[0032] Figure 2A Circuit diagrams of a three-dimensional dynamic random access memory provided for other embodiments;

[0033] Figure 2B A top view of a three-dimensional dynamic random access memory provided for other embodiments;

[0034] Figure 3A Top view of the semiconductor structure provided in the embodiments of this disclosure Figure 1 ;

[0035] Figure 3B A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0036] Figure 4A Schematic diagram of the arrangement of the first conductive part and the second conductive part provided in the embodiments of this disclosure Figure 1 ;

[0037] Figure 4B Schematic diagram 2 showing the arrangement of the first conductive part and the second conductive part according to an embodiment of this disclosure;

[0038] Figure 4C Schematic diagram three showing the arrangement of the first conductive part and the second conductive part according to an embodiment of this disclosure;

[0039] Figure 4D Schematic diagram four showing the arrangement of the first and second conductive parts according to embodiments of this disclosure;

[0040] Figure 5 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0041] Figures 6A to 6M A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the manufacturing process;

[0042] Figure 7 A block diagram of a memory provided for embodiments of this disclosure;

[0043] Figure 8 A block diagram of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0045] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0046] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. And the discussion of a second element, component, area, layer, or part does not imply that the first element, component, area, layer, or part necessarily exists in this disclosure.

[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0050] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0051] Before introducing the embodiments of this disclosure, the various directions that may be involved in the following text are defined. The extension direction of the semiconductor pillars in the transistor is defined as the first direction (i.e., the X direction), and the arrangement direction of the transistors is defined as the intersecting second direction (i.e., the Y direction) and third direction (i.e., the Z direction); wherein, any two of the X, Y, and Z directions intersect. In some embodiments, any two of the X, Y, and Z directions are perpendicular to each other. The following description will take the example of any two of the X, Y, and Z directions being perpendicular to each other.

[0052] refer to Figure 1 , Figure 1 A schematic diagram of the structure of a three-dimensional dynamic random access memory provided for some embodiments. For example... Figure 1 As shown, the memory 100 may include a memory block, and a memory block may include a memory array. Each memory array may include: a plurality of semiconductor pillars 102 extending along the X direction and spaced apart along the Y and Z directions, each semiconductor pillar 102 having two ends arranged opposite to each other along the X direction, and the two ends of each semiconductor pillar 102 arranged opposite to each other along the X direction may respectively form a source and a drain; one end (i.e., the source or drain) of the plurality of semiconductor pillars 102 arranged along the Y direction is coupled to the same bit line 104, and the plurality of bit lines 104 extend along the Y direction and are spaced apart along the Z direction; gate structures are provided on two sidewalls of the semiconductor pillars 102 arranged opposite to each other along the Y direction; the gate structures of the plurality of semiconductor pillars 102 arranged along the Z direction are coupled to form the same word line 106, and the plurality of word lines 106 extend along the Z direction and are spaced apart along the Y direction; the other end (i.e., the drain or the source) of the semiconductor pillars 102 is coupled to a capacitor 108.

[0053] In the above technical solution, the multiple bit lines 104 in the memory 100 extend along the Y direction and are arranged at intervals along the Z direction. That is, the architecture of the memory 100 is a bit line stacking (BL Stacking) architecture, which can also be called a bit line lying-down architecture.

[0054] In other embodiments, multiple semiconductor pillars in the memory extend along the X direction and are spaced apart along the Y and Z directions; multiple word lines in the memory extend along the Y direction and are spaced apart along the Z direction; and multiple bit lines extend along the Z direction and are spaced apart along the Y direction. Here, the memory architecture is a word line stacking (WL Stacking) architecture, also known as a word line lying-down architecture.

[0055] However, regardless of whether the memory architecture is bit-line stacked or word-line stacked, the dimension of the memory array along the X-direction is the sum of the dimensions of the semiconductor pillars and capacitors along the X-direction. If a memory block includes a memory array, this results in a small dimension of the memory block along the X-direction, insufficient to accommodate a sense amplifier (SA) and word line decoder (WLD) below the memory block. Furthermore, to increase the storage capacity of the memory block, the dimension of the memory array along the Z-direction can be increased. However, increasing the dimension of the memory array along the Z-direction may increase the difficulty of the manufacturing process.

[0056] Based on the above technical issues, word lines in different storage arrays can be coupled using word line parallel connections to form storage blocks with larger storage capacity; that is, a storage block can include multiple storage arrays.

[0057] refer to Figure 2A , Figure 2A Circuit diagrams of a three-dimensional dynamic random access memory provided for other embodiments. For example... Figure 2A As shown, the memory 200 may include a memory block, and a memory block may include two memory arrays. Each memory array may include a plurality of transistors 202 spaced apart along the Y and Z directions (e.g., ...). Figure 2A (As shown in the dashed circle), transistor 202 includes a source, a drain, and a gate; the sources (or drains) of multiple transistors 202 arranged along the Y direction are coupled to the same bit line 204, and the multiple bit lines 204 extend along the Y direction and are spaced apart along the Z direction; the gates of multiple transistors 202 arranged along the Z direction are coupled to the same word line 206, and the multiple word lines 206 extend along the Z direction and are spaced apart along the Y direction; the drain (or source) of the transistor is coupled to capacitor 208 (e.g., ...). Figure 2A(As shown in the dashed box). Here, word lines 206 in the two memory arrays are coupled by word line 210 (WLStrapping Line) to increase the storage capacity of the memory block.

[0058] refer to Figure 2B , Figure 2B A top view of a three-dimensional dynamic random access memory provided for other embodiments. Figure 2B Four memory arrays are illustrated, each corresponding to one of four sets of bit lines: BL1, BL2, BL3, and BL4. Each set of bit lines includes multiple bit lines 204, which extend along the Y direction and are spaced apart along the Z direction. Here, word lines 206 in the four memory arrays are coupled together by word line parallel lines 210.

[0059] However, the integration level of the memory in the above-mentioned technical solutions needs to be further improved.

[0060] In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a memory, and a memory system.

[0061] refer to Figure 3A , Figure 3A Top view of the semiconductor structure provided in the embodiments of this disclosure Figure 1 .like Figure 3A As shown, this disclosure provides a semiconductor structure 300, which includes a memory array 302, comprising a first subarray 304 and a second subarray 306. The first subarray 304 includes first semiconductor pillars 308 extending along the X direction and spaced apart along the Y and Z directions. The second subarray 306 includes second semiconductor pillars 310 extending along the X direction and spaced apart along the Y and Z directions. In the same memory array 302, the first end 312 of the first semiconductor pillars 308 arranged along the Y direction in the first subarray 304 and the second end 314 of the second semiconductor pillars 310 arranged along the Y direction in the second subarray 306 are coupled to the same bit line 316.

[0062] Here, the first subarray 304 may include a plurality of first semiconductor pillars 308, each extending along the X direction and spaced apart along the Y and Z directions. Each first semiconductor pillar 308 has a first end 312 and a third end 318 disposed opposite to each other along the X direction, and a first channel region 322 disposed between the first end 312 and the third end 318. The first end 312 may have a source or a drain, and correspondingly, the third end 318 may have a drain or a source. Therefore, the first semiconductor pillar 308 includes a source and a drain disposed opposite to each other along the X direction, and a first channel region 322 disposed between the source and the drain.

[0063] Here, the first semiconductor pillar 308 can serve as the transistor pillar of the memory cell in the first subarray 304. In some embodiments, the first end 312 can be the source and the third end 318 can be the drain. In other embodiments, the first end 312 can be the drain and the third end 318 can be the source.

[0064] Here, the second subarray 306 may include a plurality of second semiconductor pillars 310, each extending along the X direction and spaced apart along the Y and Z directions. Each second semiconductor pillar 310 has a second end 314 and a fourth end 320 disposed opposite to each other along the X direction, and a second channel region 324 disposed between the second end 314 and the fourth end 320. The second end 320 may have a source or a drain, and correspondingly, the fourth end 320 may have a drain or a source. Therefore, the second semiconductor pillar 310 includes a source and a drain disposed opposite to each other along the X direction, and a second channel region 324 disposed between the source and the drain.

[0065] Here, the second semiconductor pillar 310 can serve as the transistor pillar of the memory cell in the second subarray 306. In some embodiments, the second end 314 can be the source and the fourth end 320 can be the drain. In other embodiments, the second end 314 can be the drain and the fourth end 320 can be the source.

[0066] Here, in the same memory array 302, the first end 312 of the first semiconductor pillar 308 arranged along the Y direction in the first subarray 304 and the second end 314 of the second semiconductor pillar 310 arranged along the Y direction in the second subarray 306 are coupled to the same bit line 316. That is, the plurality of first ends 312 arranged along the Y direction in the first subarray 304 and the plurality of second ends 314 arranged along the Y direction in the second subarray 306 are coupled to the same bit line 316. In the same memory array 302, the first subarray 304 and the second subarray 306 are arranged side by side along the X direction, and the multiple bit lines 316 all extend along the Y direction and are spaced apart along the Z direction.

[0067] Thus, in the same memory array 302, the first subarray 304 and the second subarray 306 share the bit line 316, thereby halving the size of the bit line 316 along the Y direction while maintaining the same number of memory cells coupled to it. For example, compared to eight semiconductor pillars arranged along the Y direction with one end coupled to the same bit line, Figure 3A The diagram illustrates that the first ends 312 of the four first semiconductor pillars 308 arranged along the Y direction and the second ends 314 of the four second semiconductor pillars 310 arranged along the Y direction are all coupled to the same bit line 316. In this embodiment of the present disclosure, since the first subarray and the second subarray can share the bit line, the integration density of the semiconductor structure can be improved.

[0068] Furthermore, compared to Figure 2B The illustrated bit line groups BL1 and BL2 are arranged side-by-side along the X direction, and there may be coupling between them. In this embodiment, the first subarray and the second subarray can share bit lines, thereby reducing the coupling between the bit lines.

[0069] In some embodiments, in the same memory array 302, the first subarray 304 and the second subarray 306 are arranged along the X direction, and the distance between the first end 312 and the second end 314 of the first semiconductor pillar 308 and the second semiconductor pillar 310 arranged along the X direction is less than the distance between the third end 318 and the fourth end 320.

[0070] In some embodiments, the source and drain of the transistor in the first subarray 304 can be formed by doping the first end 312 and the third end 314 of the first semiconductor pillar 308; and the source and drain of the transistor in the second subarray 306 can be formed by doping the second end 314 and the fourth end 320 of the second semiconductor pillar 310.

[0071] Here, in the same memory array 302, since the first subarray 304 and the second subarray 306 are arranged side-by-side along the X direction, the first semiconductor pillar 308 and the second semiconductor pillar 310 are also arranged side-by-side along the X direction. The first semiconductor pillar 308 has a first end 312 near the bit line 316 and a third end 318 away from the bit line 316, and the second semiconductor pillar 310 has a second end 314 near the bit line 316 and a fourth end 320 away from the bit line 316. Therefore, the distance between the first end 312 and the second end 314 is smaller than the distance between the third end 318 and the fourth end 320.

[0072] In some embodiments, in the same memory array 302, the first end 312 and the second end 314 are mirror-symmetric about the bit line 316; the third end 318 and the fourth end 320 are mirror-symmetric about the bit line 316.

[0073] Here, the first semiconductor pillar 308 and the second semiconductor pillar 310 can be considered as mirror images of each other about the bit line 316, that is, the first semiconductor pillar 308 and the second semiconductor pillar 310 can be folded along the bit line 316. It should be noted that the first semiconductor pillar 308 and the second semiconductor pillar 310 can be manufactured in the same process, thereby simplifying the manufacturing process.

[0074] In some embodiments, the semiconductor structure 300 further includes: a first gate structure 326 disposed on at least one sidewall of the first semiconductor pillar 308; the first gate structure 326 of the first semiconductor pillar 308 arranged along the Z direction is coupled to the same first word line 330, and the plurality of first word lines 330 extend along the Z direction and are spaced apart along the Y direction; a second gate structure 328 disposed on at least one sidewall of the second semiconductor pillar 310; the second gate structure 328 of the second semiconductor pillar 310 arranged along the Z direction is coupled to the same second word line 332, and the plurality of second word lines 332 extend along the Z direction and are spaced apart along the Y direction.

[0075] Here, the orthographic projection shape of the first semiconductor pillar 308 in the YZ plane can be circular, square, or other shapes. This disclosure does not impose any special limitations on the orthographic projection shape of the first semiconductor pillar 308 in the YZ plane. Similarly, this disclosure does not impose any special limitations on the orthographic projection shape of the second semiconductor pillar 310 in the YZ plane. Taking a square orthographic projection shape of the first semiconductor pillar 308 in the YZ plane as an example, the first semiconductor pillar 308 may include two sidewalls arranged opposite each other along the Y direction and two sidewalls arranged opposite each other along the Z direction.

[0076] Here, the first gate structure 326 may include a first gate dielectric layer covering at least one sidewall of the first semiconductor pillar 308 and a first gate electrode layer covering the first gate dielectric layer. The second gate structure 328 may include a second gate dielectric layer covering at least one sidewall of the second semiconductor pillar 310 and a second gate electrode layer covering the second gate dielectric layer. The first gate structure 326 (or the second gate structure 328) may cover one sidewall, two sidewalls, three sidewalls, or four sidewalls to form a single-gate structure, a dual-gate structure, a triple-gate structure, or a gate all-around (GAA) structure, respectively. This disclosure does not impose any particular limitation on this.

[0077] In some embodiments, the first gate structure (or the second gate structure) may also form a mirror-symmetric gate structure. The first gate structures of the first semiconductor pillars adjacent along the Y direction are disposed on different sides of the first semiconductor pillars along the Y direction; the second gate structures of the second semiconductor pillars adjacent along the Y direction are disposed on different sides of the second semiconductor pillars along the Y direction.

[0078] In some embodiments, the semiconductor structure 300 further includes: a first capacitor 348 disposed on the side of the first semiconductor pillar 308 near the third end 318 and coupled to the third end 318; and a second capacitor 350 disposed on the side of the second semiconductor pillar 310 near the fourth end 320 and coupled to the fourth end 320.

[0079] Here, the first capacitor 348 and the second capacitor 350 can be considered as mirror images of each other about bit line 316. It should be noted that the first capacitor 348 and the second capacitor 350 can be manufactured in the same process, thus simplifying the manufacturing process.

[0080] Here, the first capacitor 348 may include a first electrode, a second electrode, and a first dielectric layer disposed between the first electrode and the second electrode; wherein the first electrode may be coupled to the third end 318 of the first semiconductor pillar 308, and the second electrode may be coupled to a common terminal. The second capacitor 350 may include a third electrode, a fourth electrode, and a second dielectric layer disposed between the third electrode and the fourth electrode; wherein the third electrode may be coupled to the fourth end 320 of the second semiconductor pillar 310, and the fourth electrode may be coupled to a common terminal.

[0081] For ease of explanation, Figure 3A The structure of the first capacitor 348 shown in the diagram is enlarged. The first capacitor 348 may include: a first semiconductor pillar 308 extending into the first capacitor formation region; a metal silicide layer 352 covering the sidewalls of the first semiconductor pillar 308; a first dielectric layer 354 disposed on the sidewalls of the metal silicide layer 352; and a conductive layer 356 disposed on the sidewalls of the first dielectric layer 354. The first semiconductor pillar 352 and the metal silicide layer 352 disposed on its sidewalls together serve as the first electrode, and the conductive layer 356 serves as the second electrode. A filling layer 358 may also be provided between adjacent first semiconductor pillars 308 arranged along the Y direction. The process for forming the first capacitor 348 will be described in detail later in the section on the manufacturing method of the semiconductor structure.

[0082] refer to Figure 3B , Figure 3B A second top view of a semiconductor structure provided in an embodiment of this disclosure. (See diagram below.) Figure 3B As shown, in some embodiments, the memory block 334 may include multiple memory arrays (e.g., two memory arrays) arranged along the X direction, and each memory array 302 may include a first subarray 304 and a second subarray 306 arranged along the X direction. The semiconductor structure 300 also includes: a first conductive line 336, to which first word lines 330 in different memory arrays 302 within the same memory block 334 are coupled; and a second conductive line 338, to which second word lines 332 in different memory arrays 302 within the same memory block 334 are coupled. Here, the first conductive line 336 and the second conductive line 338 may be disposed on one side of the first semiconductor pillar 308 and the second semiconductor pillar 310 along the Z direction.

[0083] Here, the memory block 334 is defined to include C memory arrays 302. Each memory array 302's first subarray 304 may include M first semiconductor pillars 308 arranged along the Y direction and N first semiconductor pillars 308 arranged along the Z direction, for a total of M*N first semiconductor pillars 308. Each memory array 302's second subarray 306 may also include M*N second semiconductor pillars 310. Therefore, each memory array 302 includes 2*M*N memory cells, and each memory block 334 includes 2*M*N*C memory cells; where M, N, and C are all positive integers. The number of bit lines, first word lines, second word lines, first conductive lines, and second conductive lines will be explained below.

[0084] Firstly, in the same memory array 302, M first semiconductor pillars 308 and M second semiconductor pillars 310 arranged along the Y direction are coupled to the same bit line 316. The number of bit lines 316 is the same as the number of first semiconductor pillars 308 (or second semiconductor pillars 310) arranged along the Z direction. Therefore, the number of bit lines 316 in the same memory array 302 is N; the number of bit lines 316 in the same memory block 334 is N*C. In other words, each bit line 316 corresponds to 2M memory cells.

[0085] Secondly, within the same storage array 302, the number of first word lines 330 in the first subarray 304 is M, and the number of second word lines 332 in the second subarray 306 is also M. Within the same storage block 334, the number of first word lines 330 is M*C, and the number of second word lines 332 is M*C. In other words, each first word line 330 corresponds to N storage units, and each second word line corresponds to N storage units.

[0086] Thirdly, the number of first conductive lines 336 in the same memory block 334 is the same as the number of first semiconductor pillars 308 arranged along the Y direction in each first subarray 304, that is, the number of first conductive lines is M. In other words, each first conductive line 336 corresponds to N*C memory cells. The number of second conductive lines 338 in the same memory block 334 is the same as the number of second semiconductor pillars 310 arranged along the Y direction in each second subarray 306, that is, the number of second conductive lines is M. In other words, each second conductive line 338 corresponds to N*C memory cells.

[0087] Here, in the semiconductor structure 300, a memory cell can be selected using the first conductive line 336 (or the second conductive line 338) and the bit line 316, thereby operating on that memory cell. The first conductive line 336 and the second conductive line 338 can also be referred to as word lines in parallel connection. The first conductive line 336 can couple the first word lines 330 in different memory arrays 302, and the second conductive line 338 can couple the second word lines 332 in different memory arrays 302, so that a memory block 334 can include multiple memory arrays 302, and each memory array 302 includes a first subarray 304 and a second subarray 306, thereby increasing the storage capacity of the memory block 334.

[0088] Compared to Figure 1 The illustration shows that by increasing the size of the storage array along the Z direction to increase the storage capacity of the storage array, in the embodiments of this disclosure, in the same storage block, the size of the storage array along the Z direction can be reduced and the storage capacity of the storage block can be increased by coupling the first word lines in different first sub-arrays through the first conductive line and coupling the second word lines in different second sub-arrays through the second conductive line, thereby reducing the difficulty of the manufacturing process.

[0089] In some embodiments, both the first conductive line 336 and the second conductive line 338 extend along the X direction, and the first conductive line 336 and the second conductive line 338 are arranged alternately along the Y direction. Here, the memory block 334 may include a plurality of memory arrays 302 arranged along the X direction, each memory array 302 including a first subarray 304 and a second subarray 306 arranged side by side along the X direction, that is, the first subarray 304 and the second subarray 306 in the memory block 334 are arranged alternately along the X direction. In the same memory block 334, the first semiconductor pillar 308 and the second semiconductor pillar 310 are arranged alternately along the X direction, and among the first semiconductor pillars 308 and the second semiconductor pillars 310 arranged alternately along the X direction, a plurality of first semiconductor pillars 308 correspond to the same first conductive line 336, and a plurality of second semiconductor pillars 310 correspond to the same second conductive line 338.

[0090] In some embodiments, the semiconductor structure 300 further includes: a first connection portion 340 disposed between the first conductive line 336 and the first word line 330, one end of the first connection portion 340 being coupled to the first word line 330 and the other end of the first connection portion 340 being coupled to the first conductive line 336; and a second connection portion 342 disposed between the second conductive line 338 and the second word line 332, one end of the second connection portion 342 being coupled to the second word line 332 and the other end of the second connection portion 342 being coupled to the second conductive line 338.

[0091] Here, the first connecting part 340 is used to electrically connect the first word line 330 and the first conductive line 336; the second connecting part 342 is used to electrically connect the second word line 332 and the second conductive line 338.

[0092] In some embodiments, the first connecting portion 340 and the second connecting portion 342 may include conductive materials.

[0093] In some embodiments, the semiconductor structure 300 further includes: a first conductive portion 344 disposed on the side of the first conductive line 336 away from the first semiconductor pillar 308 and coupled to the first conductive line 336; and a second conductive portion 346 disposed on the side of the second conductive line 338 away from the second semiconductor pillar 310 and coupled to the second conductive line 338.

[0094] Here, the first connecting part 340 and the first conductive part 344 can be provided on both sides of the first conductive line 336 that are arranged opposite to each other along the Z direction. The first conductive part 344 can be used to draw out the electrical signal of the first conductive line 336. The second connecting part 342 and the second conductive part 346 can be provided on both sides of the second conductive line 338 that are arranged opposite to each other along the Z direction. The second conductive part 346 can be used to draw out the electrical signal of the second conductive line 338.

[0095] Figures 4A to 4D The different arrangements of the first and second conductive parts are illustrated below. Figures 4A to 4D The different arrangements of the first and second conductive parts are explained in detail.

[0096] like Figure 4A As shown, in some embodiments, the first conductive line 336a and the second conductive line 338a are aligned in the Y direction; the first conductive portion 344a and the second conductive portion 346a (as shown) Figure 4A The first conductive part 344a and the second conductive part 346a are located on the same side of the storage block 334 in the X direction, and are offset in the Y direction. (The part shown in the dashed box in the middle)

[0097] Here, both the first conductive line 336a and the second conductive line 338a extend along the X direction and have the same dimensions along the X direction. The first conductive line 336a and the second conductive line 338a are arranged alternately along the Y direction, and the two sides of the first conductive line 336a and the second conductive line 338a arranged opposite each other along the X direction are aligned, that is, the first conductive line 336a and the second conductive line 338a are not offset in the Y direction. Alignment in the Y direction (or no offset in the Y direction) means that the straight line formed by connecting the left endpoints of the first conductive line 336a and the second conductive line 338a arranged alternately along the Y direction extends along the Y direction, and the straight line formed by connecting the right endpoints of the first conductive line 336a and the second conductive line 338a arranged alternately along the Y direction extends along the Y direction.

[0098] Here, the storage block 334 has two sides arranged opposite each other along the X direction, and the first conductive part 344a and the second conductive part 346a are both provided on the same side of the storage block 334 in the X direction, for example... Figure 4A The diagram illustrates that both the first conductive portion 344a and the second conductive portion 346a are located on the right side of the storage block 334 (i.e., in the positive X direction). Of course, in other embodiments, the first conductive portion 344a and the second conductive portion 346a may also be located on the left side of the storage block 334 (i.e., in the negative X direction), and this disclosure does not impose any special limitation on this.

[0099] Here, the plurality of first conductive parts 344a corresponding to the plurality of first conductive lines 336a are aligned in the Y direction, and the plurality of second conductive parts 346a corresponding to the plurality of second conductive lines 338a are aligned in the Y direction. The first conductive parts 344a and the second conductive parts 346a are offset in the Y direction, for example... Figure 4A The diagram illustrates that the first conductive portion 344a is located to the right of the second conductive portion 346a (i.e., in the positive X direction). Of course, in other embodiments, the first conductive portion 344a may also be located to the left of the second conductive portion 346a (i.e., in the negative X direction), and this disclosure does not impose any particular limitation thereon. Connecting the first conductive portion 344a and the second conductive portion 346a sequentially can form a zig-zag straight line. The offset between the first conductive portion 344a and the second conductive portion 346a in the Y direction helps to reduce the coupling effect between the first conductive portion 344a and the second conductive portion 346a.

[0100] like Figure 4B As shown, in some embodiments, the first conductive line 336b and the second conductive line 338b are aligned in the Y direction; the first conductive portion 344b and the second conductive portion 346b are both disposed on the same side of the storage block 334 in the X direction, and the first conductive portion 344b and the second conductive portion 346b are aligned in the Y direction.

[0101] Here, both the first conductive line 336b and the second conductive line 338b extend along the X direction and have the same dimensions along the X direction. The first conductive line 336b and the second conductive line 338b are arranged alternately along the Y direction, and the two sides of the first conductive line 336b and the second conductive line 338b that are opposite each other along the X direction are aligned, that is, the first conductive line 336b and the second conductive line 338b are not offset in the Y direction.

[0102] Here, the storage block 334 has two sides disposed opposite to each other along the X direction, and the first conductive part 344b and the second conductive part 346b are both disposed on the same side of the storage block 334 in the X direction, for example... Figure 4BThe diagram illustrates that both the first conductive portion 344b and the second conductive portion 346b are located on the right side of the storage block 334 (i.e., in the positive X direction). Of course, in other embodiments, the first conductive portion 344b and the second conductive portion 346b may also be located on the left side of the storage block 334 (i.e., in the negative X direction), and this disclosure does not impose any special limitation on this.

[0103] Here, the multiple first conductive lines 336b and their corresponding multiple first conductive portions 344b are aligned in the Y direction, and the multiple second conductive lines 338b and their corresponding multiple second conductive portions 346b are aligned in the Y direction. Alignment in the Y direction means that the straight line formed by connecting the alternating first conductive portions 344b and second conductive portions 346b along the Y direction extends along the Y direction.

[0104] like Figure 4C As shown, in some embodiments, the first conductive line 336c and the second conductive line 338c are offset in the Y direction; the first conductive part 344c and the second conductive part 346c are both disposed on the same side of the storage block 334 in the X direction, and the first conductive part 344c and the second conductive part 346c are offset in the Y direction.

[0105] Here, both the first conductive line 336c and the second conductive line 338c extend along the X direction and are alternately arranged along the Y direction. The two sides of the first conductive line 336c and the second conductive line 338c, which are positioned opposite each other along the X direction, are offset in the Y direction. This offset in the Y direction means that connecting the left endpoints of the alternating first conductive line 336c and the second conductive line 338c along the Y direction forms a zigzag straight line, and connecting the right endpoints of the alternating first conductive line 336c and the second conductive line 338c along the Y direction also forms a zigzag straight line. This offset in the Y direction helps reduce the coupling effect between the first conductive line 336c and the second conductive line 338c.

[0106] Here, the storage block 334 has two sides disposed opposite to each other along the X direction, and the first conductive part 344c and the second conductive part 346c are both disposed on the same side of the storage block 334 in the X direction, for example... Figure 4C The diagram illustrates that both the first conductive portion 344c and the second conductive portion 346c are located on the right side of the storage block 334 (i.e., in the positive X direction). Of course, in other embodiments, the first conductive portion 344c and the second conductive portion 346c may also be located on the left side of the storage block 334 (i.e., in the negative X direction), and this disclosure does not impose any special limitation on this.

[0107] Here, the multiple first conductive lines 336c corresponding to the multiple first conductive portions 344c are aligned in the Y direction, and the multiple second conductive lines 338c corresponding to the multiple second conductive portions 346c are aligned in the Y direction. The first conductive portions 344c and the second conductive portions 346c are offset in the Y direction, for example... Figure 4C The diagram illustrates that the first conductive portion 344c is located to the right of the second conductive portion 346c (i.e., in the positive X direction). Of course, in other embodiments, the first conductive portion 344c may also be located to the left of the second conductive portion 346c (i.e., in the negative X direction), and this disclosure does not impose any particular limitation thereon. Connecting the first conductive portion 344c and the second conductive portion 346c sequentially can form a zig-zag straight line.

[0108] like Figure 4D As shown, in some embodiments, the first conductive line 336d and the second conductive line 338d are offset in the Y direction; the first conductive part 344d and the second conductive part 346d are both provided on different sides of the storage block 334 in the X direction.

[0109] Here, both the first conductive line 336d and the second conductive line 338d extend along the X direction and are alternately arranged along the Y direction. The two sides of the first conductive line 336d and the second conductive line 338d, which are positioned opposite each other along the X direction, are offset in the Y direction. This offset in the Y direction means that connecting the left endpoints of the alternately arranged first conductive line 336d and the second conductive line 338d along the Y direction forms a zigzag straight line, and connecting the right endpoints of the alternately arranged first conductive line 336d and the second conductive line 338d along the Y direction also forms a zigzag straight line.

[0110] Here, the storage block 334 has two sides disposed opposite to each other along the X direction, and the first conductive portion 344d and the second conductive portion 346d are respectively disposed on different sides of the storage block 334 in the X direction, for example... Figure 4D The diagram illustrates that the first conductive portion 344d is located on the right side of the storage block 334 (i.e., in the positive X direction), and the second conductive portion 346d is located on the left side of the storage block 334 (i.e., in the negative X direction). Of course, in other embodiments, the first conductive portion 344d may also be located on the left side of the storage block 334 (i.e., in the negative X direction), and the second conductive portion 346d may also be located on the right side of the storage block 334 (i.e., in the positive X direction). This disclosure does not impose any particular limitation on this. Distributing the first conductive portion 344d and the second conductive portion 346d on different sides of the storage block 334 in the X direction helps to reduce the coupling effect between adjacent first conductive portions 344d and adjacent second conductive portions 346d.

[0111] Here, the multiple first conductive lines 336d corresponding to the multiple first conductive parts 344d are aligned in the Y direction, and the straight line formed by sequentially connecting the first conductive parts 344d extends in the Y direction; the multiple second conductive lines 338d corresponding to the multiple second conductive parts 346d are aligned in the Y direction, and the straight line formed by sequentially connecting the second conductive parts 346d extends in the Y direction.

[0112] refer to Figure 5 , Figure 5 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure. Figure 5 As shown in the embodiments of this disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0113] Step S510: Form a memory array, the memory array including a first subarray and a second subarray, the first subarray including first semiconductor pillars extending along a first direction and evenly spaced along a second direction and a third direction; the second subarray including second semiconductor pillars extending along the first direction and evenly spaced along the second direction and a third direction.

[0114] Step S520: A bit line is formed between the first subarray and the second subarray; in the same memory array, the first end of the first semiconductor pillar arranged along the second direction in the first subarray and the second end of the second semiconductor pillar arranged along the second direction in the second subarray are coupled to the same bit line; wherein any two of the first direction, the second direction and the third direction intersect.

[0115] It should be noted that the manufacturing processes for forming the first and second subarrays can be the same, which will be discussed below. Figures 6A to 6M The manufacturing process of the first subarray is described in detail. The manufacturing process of the second subarray can be found in the description of the first subarray.

[0116] In this embodiment of the present disclosure, in step S510, a memory array is formed. The memory array includes a first subarray and a second subarray. The first subarray includes first semiconductor pillars extending along the X direction and evenly spaced along the Y and Z directions. The second subarray includes second semiconductor pillars extending along the X direction and evenly spaced along the Y and Z directions. The following will be combined with... Figure 6A and Figure 6B The process of forming the first semiconductor pillar is explained in detail.

[0117] like Figure 6AAs shown, a semiconductor layer and a first sacrificial layer are alternately stacked along the Z direction; the semiconductor layer and the first sacrificial layer are etched along the Z direction to form a first groove extending along the X direction and arranged along the Y direction; wherein, the etched semiconductor layer forms a first semiconductor pillar 408, and a plurality of first semiconductor pillars 408 extend along the X direction and are spaced apart along the Y and Z directions; a first insulating material is filled in the first groove to form a first insulating layer 412.

[0118] Here, the material of the semiconductor layer may include, but is not limited to, silicon.

[0119] Combination Figure 6A , Figure 6B and Figure 6G As shown, adjacent first semiconductor pillars 408 along the Y direction can be separated by an isolation structure 410. The isolation structure 410 may include a first insulating layer 412 and a first spacer 414, a second spacer 416, and a third spacer 418 disposed within the first insulating layer 412; wherein the second spacer 416 and the third spacer 418 are disposed at opposite ends of the first insulating layer 412 along the X direction, and the first spacer 414 is disposed between the second spacer 416 and the third spacer 418. The first spacer 414 includes a second insulating layer 420 and a fourth insulating layer 424 disposed opposite each other along the Y direction, and a third insulating layer 422 disposed between the second insulating layer 420 and the fourth insulating layer 424. The second spacer includes a fifth insulating layer 426 and a sixth insulating layer 428, with the fifth insulating layer 426 disposed between the first spacer 414 and the sixth insulating layer 428. The third spacer 418 includes a seventh insulating layer 430 and an eighth insulating layer 432, with the eighth insulating layer 432 disposed between the first spacer 414 and the seventh insulating layer 430.

[0120] Here, the materials of the third insulating layer 422 in the first spacer 414, the sixth insulating layer 428 in the second spacer 416, and the seventh insulating layer 430 in the third spacer 418 can be the same, and all are of the first type of material. The materials of the second insulating layer 420 and the fourth insulating layer 424 in the first spacer 414, the fifth insulating layer 426 in the second spacer 416, and the eighth insulating layer 432 in the third spacer 418 can be the same, and all are of the second type of material. The first type of material and the second type of material are different, and in the same etching process, the first type of material and the second type of material can have different etching rates.

[0121] Return to reference Figure 6AAs shown, the portion of the first semiconductor pillar 408 corresponding to the first insulating layer 412 between the first spacer 414 and the second spacer 416 is the first semiconductor pillar forming region 404; the portion of the first semiconductor pillar 408 corresponding to the first insulating layer 412 between the first spacer 414 and the third spacer 418 is the first capacitor forming region 406; a bit line forming region 402 is also provided on the side of the first semiconductor pillar forming region 404 away from the first capacitor forming region 406, that is, the bit line forming region 402, the first semiconductor pillar forming region 404 and the first capacitor forming region 406 are arranged sequentially along the X direction.

[0122] Here, the first semiconductor pillar 408 has a first end near the bit line forming region 402, and the first end can be coupled to the bit line; the first semiconductor pillar 408 has a third end near the first capacitor forming region 406, and the third end can be coupled to the first capacitor.

[0123] In some embodiments, prior to step S520, the method further includes: forming a first gate structure on at least one sidewall of a first semiconductor pillar; coupling the first gate structure of the first semiconductor pillar arranged along the Z direction to a first word line, the first word lines extending along the Z direction and spaced apart along the Y direction; forming a second gate structure on at least one sidewall of a second semiconductor pillar; coupling the second gate structure of the second semiconductor pillar arranged along the Z direction to a second word line, the second word lines extending along the Z direction and spaced apart along the Y direction. The following will combine... Figure 6B The process of forming the first gate structure and the first word line is explained in detail.

[0124] like Figure 6B As shown, the first insulating layer 412 located between the first spacer 414 and the second spacer 416 is removed to form a second groove; the first sacrificial layer between adjacent first semiconductor pillars along the Z direction is removed through the second groove to form a first gap, and the second groove and the first gap are connected; a first gate dielectric layer 434 is formed in the space formed by the second groove and the first gap; an initial gate electrode layer 436 is formed in the space formed by the second groove and the first gap; and a first dielectric material is filled in the space formed by the second groove and the first gap to form a first dielectric layer 438.

[0125] Here, the process for forming the first gate dielectric layer 434 may include an in-situ oxidation process. For example, the portion of the first semiconductor pillar 408 exposed by the second trench and the first gap is oxidized to form the first gate dielectric layer 434.

[0126] Here, the material of the initial gate electrode layer 436 may include a conductive material, such as a metallic material.

[0127] Here, the material of the first dielectric layer 438 may include, but is not limited to, silicon oxide.

[0128] Here, the process for forming the initial gate electrode layer 436 and the first dielectric layer 438 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0129] like Figure 6C As shown, the fourth insulating layer 424 in the first spacer 414 is removed to form the third groove 440; and the fifth insulating layer 426 in the second spacer 416 is removed to form the fourth groove 442. Here, both the third groove 440 and the fourth groove 442 expose a portion of the initial gate electrode layer 436.

[0130] Here, since the third insulating layer 422 and the fourth insulating layer 424 in the first spacer 414 are made of materials with different etching rates, damage to the third insulating layer 422 can be avoided during the process of removing the fourth insulating layer 424 to form the third groove 440; since the fifth insulating layer 426 and the sixth insulating layer 428 in the second spacer 416 are made of materials with different etching rates, damage to the sixth insulating layer 428 can be avoided during the process of removing the fifth insulating layer 426 to form the fourth groove 442.

[0131] In some embodiments, forming the third groove 440 and forming the fourth groove 442 can be performed in the same process. Here, the materials of the fourth insulating layer 424 and the fifth insulating layer 426 can be the same.

[0132] Here, the process for removing the fourth insulating layer 424 and the fifth insulating layer 426 may include, but is not limited to, wet etching.

[0133] like Figure 6D As shown, the exposed portion of the initial gate electrode layer 436 is removed through the third groove 440 and the fourth groove 442, and the etched initial gate electrode layer forms the first gate electrode layer 444; wherein, the first gate dielectric layer 434 and the first gate electrode layer 444 together form the first gate structure 446. The first gate structure 446 of the first semiconductor pillars 408 arranged along the Z direction is coupled to form the first word line 448.

[0134] like Figure 6E As shown, a second dielectric material is filled in the third groove 440 to form a second dielectric layer 450; and a third dielectric material is filled in the fourth groove 442 to form a third dielectric layer 452.

[0135] Here, the formation of the second dielectric layer 450 and the formation of the third dielectric layer 452 can be performed in the same process. Here, the materials of the second dielectric layer 450 and the third dielectric layer 452 can be the same. Figure 6E The diagram shows that the third insulating layer 422, the second dielectric layer 450, the sixth insulating layer 428, and the third dielectric layer 452 are made of the same material, that is, they have the same filling pattern.

[0136] Here, the process for forming the second dielectric layer 450 and the third dielectric layer 452 may include, but is not limited to, CVD, PVD, ALD or any combination thereof.

[0137] In some embodiments, the first semiconductor pillar includes a first end and a third end disposed opposite to each other along the X direction; the second semiconductor pillar includes a second end and a fourth end disposed opposite to each other along the X direction; step S520 includes: forming a bit line groove between the first end of the first semiconductor pillar and the second end of the second semiconductor pillar; filling the bit line groove with conductive material to form a bit line; wherein, in the same memory array, the bit lines extend along the Y direction and are spaced apart along the Z direction.

[0138] like Figure 6F As shown, the semiconductor layer in the bit line forming region 402 is removed to form a bit line groove; a conductive material is filled in the bit line groove to form a bit line 456; the first sacrificial layer between adjacent bit lines 456 along the Z direction can also be removed to form a second gap; an insulating material is filled in the second gap to form a bit line isolation structure, replacing the first sacrificial layer between adjacent bit lines 456 along the Z direction with a bit line isolation structure.

[0139] Here, in the same memory array, bit lines 456 extend along the Y direction and are spaced apart along the Z direction; the first ends 454 of the plurality of first semiconductor pillars 408 arranged along the Y direction are coupled to the same bit line 456. It should be noted that the manufacturing processes of the first semiconductor pillars and the second semiconductor pillars are carried out simultaneously. A bit line groove is formed between the first ends of the first semiconductor pillars and the second ends of the second semiconductor pillars arranged side by side along the X direction. Subsequently, conductive material is filled into the bit line groove, and the first ends 454 of the plurality of first semiconductor pillars 408 arranged along the Y direction and the second source and drain of the plurality of second semiconductor pillars arranged along the Y direction are coupled to the same bit line 456.

[0140] Here, the material of bit line 456 may include a conductive material.

[0141] In some embodiments, after step S520, the method further includes: forming a first capacitor on the side of the first semiconductor pillar near the third end, with the third end coupled to the first capacitor; and forming a second capacitor on the side of the second semiconductor pillar near the fourth end, with the fourth end coupled to the second capacitor.

[0142] like Figure 6G and Figure 6H As shown, in the first capacitor forming region 406, the first insulating layer 412 is removed to form a fifth groove 458; the first sacrificial layer between adjacent first semiconductor pillars 408 along the Z direction is removed through the fifth groove 458 to form a third gap, and the fifth groove 458 and the third gap are connected.

[0143] like Figure 6I As shown, a metal layer 460 is formed in the space formed by the fifth groove 458 and the third gap. Here, the metal layer 460 includes a first portion disposed opposite to each other along the X direction and a second portion disposed opposite to each other along the Y direction. The first portion is in contact with the eighth insulating layer 432 and the second insulating layer 420, respectively, and the second portion is in contact with the sidewall of the first semiconductor pillars 408 arranged along the Y direction.

[0144] like Figure 6J As shown, by adjusting the reaction conditions, a chemical reaction occurs between the metal layer 460 and the first semiconductor pillar 408 in contact with it to form a metal silicide layer 472. The first portion of the metal layer is not in contact with the semiconductor material; therefore, the first portion of the metal layer 460 remains a metallic material. The second portion of the metal layer is in contact with the semiconductor material; therefore, the second portion of the metal layer forms the metal silicide layer 472.

[0145] Still Figure 6J As shown, sacrificial material is filled into the space formed by the fifth groove 458 and the third gap to form a second sacrificial layer 462; the eighth insulating layer 432 in the third spacer 418 is removed to form a sixth groove 464; and the second insulating layer 420 in the first spacer 414 is removed to form a seventh groove 466. Both the sixth groove 464 and the seventh groove 466 expose a first portion of the metal layer 460.

[0146] Here, since the seventh insulating layer 430 and the eighth insulating layer 432 in the third spacer 418 are materials with different etching rates, damage to the seventh insulating layer 430 can be avoided during the process of removing the eighth insulating layer 432 to form the sixth groove 464; since the second insulating layer 420 and the third insulating layer 422 in the first spacer 414 are materials with different etching rates, damage to the third insulating layer 422 can be avoided during the process of removing the second insulating layer 420 to form the seventh groove 466.

[0147] In some embodiments, forming the sixth groove 464 and forming the seventh groove 466 can be performed in the same process. Here, the materials of the eighth insulating layer 432 and the second insulating layer 420 can be the same.

[0148] Here, the process for removing the eighth insulating layer 432 and the second insulating layer 420 may include, but is not limited to, wet etching.

[0149] like Figure 6K As shown, the unreacted metal layer 460 is removed through the sixth groove 464 and the seventh groove 466, that is, the first portion of the metal layer is removed through the sixth groove 464 and the seventh groove 466. A fourth dielectric material is filled into the sixth groove 464 to form a fourth dielectric layer 468; and a fifth dielectric material is filled into the seventh groove 466 to form a fifth dielectric layer 470; the second sacrificial layer 462 is removed.

[0150] Here, the formation of the fourth dielectric layer 468 and the formation of the fifth dielectric layer 470 can be performed in the same process. Here, the materials of the fourth dielectric layer 468 and the fifth dielectric layer 470 can be the same. Figure 6K The diagram shows that the third insulating layer 422, the second dielectric layer 450, the fifth dielectric layer 470, the seventh insulating layer 430, and the fourth dielectric layer 468 are made of the same material, that is, they have the same filling pattern.

[0151] Here, the process for forming the fourth dielectric layer 468 and the fifth dielectric layer 470 may include, but is not limited to, CVD, PVD, ALD or any combination thereof.

[0152] like Figure 6L As shown, a first dielectric layer 474 is formed in the fifth groove 458; a conductive material is filled in the fifth groove 458 to form a conductive layer 476; and a dielectric material is filled in the fifth groove 458 to form a filling layer 484. At this time, the metal silicide layer 472, the first dielectric layer 474, and the conductive layer 476 do not completely fill the fifth groove 458, and the remaining space in the fifth groove 458 still needs to be filled by the filling layer 484.

[0153] Here, the first dielectric layer 474 can be a high-k material, that is, a material whose dielectric constant is greater than that of silicon oxide.

[0154] In other embodiments, a first dielectric layer is formed in the fifth groove; a conductive material is then filled in the fifth groove to form a conductive layer. At this point, the metal silicide layer, the first dielectric layer, and the conductive layer have filled the fifth groove.

[0155] like Figure 6MAs shown, a portion of the first semiconductor pillar 408 located in the first capacitor forming region 406 and the metal silicide layer 472 in contact with the portion of the first semiconductor pillar 408 can serve as the first electrode of the first capacitor 482. The first electrode is coupled to the third end 480 of the first semiconductor pillar 408. The conductive layer 476 forms the second electrode of the first capacitor 482, and the second electrode is coupled to a common terminal. Here, in the first semiconductor pillar forming region 404, the first semiconductor pillar 408 includes a first end 454 and a third end 480 disposed opposite each other along the X direction, and a first channel region 478 disposed between the first end 454 and the third end 480. The first end 454 is coupled to the bit line 456, and the third end 480 is coupled to the first capacitor 482.

[0156] In other embodiments, a portion of the first semiconductor pillar located in the first capacitor formation region may be removed, and then a metal material may be deposited as the first electrode of the first capacitor. In this case, the first electrode formed by the metal material can be coupled to the third end of the first semiconductor pillar. This disclosure does not impose any particular limitations on the structure of the first capacitor or the process for forming the first capacitor, and the appropriate method can be selected based on the actual situation.

[0157] Return to reference Figure 3B As shown, in some embodiments, the method further includes: forming a first connection portion 340 on one side of the first semiconductor pillar 308 along the Z direction, the first connection portion 340 being coupled to a first word line 330; and forming a second connection portion 342 on one side of the second semiconductor pillar 310 along the Z direction, the second connection portion 342 being coupled to a second word line 332.

[0158] Exemplarily, forming the first connection portion and the second connection portion may include the following steps: forming a sixth dielectric layer on one side of the memory block along the Z direction; etching the sixth dielectric layer to form a first connection hole exposing a first word line and a second connection hole exposing a second word line; filling the first connection hole and the second connection hole with conductive material to form the first connection portion and the second connection portion, respectively. Wherein, the first subarray and the second subarray in the memory block are arranged alternately along the X direction, the first connection portion corresponding to the first subarray is arranged along the Y direction, and the second connection portion corresponding to the second subarray is arranged along the Y direction. In other words, in the same memory block, the first connection portion is arranged along the Y direction, the second connection portion is arranged along the Y direction, and the first connection portion and the second connection portion are arranged alternately along the X direction. The above steps for forming the first connection portion and the second connection portion are for illustrative purposes only and do not constitute a limitation on the scope of protection of this disclosure.

[0159] Return to reference Figure 3BAs shown, in some embodiments, multiple memory arrays 302 are arranged along the X direction to form a memory block 334; the method further includes: forming a first conductive line 336 on the side of the first connection portion 340 away from the first semiconductor pillar 308, and first word lines 330 in different memory arrays 302 in the same memory block 334 are coupled to the same first conductive line 336 through the first connection portion 340; forming a second conductive line 338 on the side of the second connection portion 342 away from the second semiconductor pillar, and second word lines 332 in different memory arrays 302 in the same memory block 334 are coupled to the same second conductive line 338 through the second connection portion 342.

[0160] Exemplarily, forming the first conductive line and the second conductive line may include the following steps: forming a seventh dielectric layer on a sixth dielectric layer; etching the seventh dielectric layer along the Z direction to form an eighth groove and a ninth groove extending along the X direction and alternately arranged along the Y direction, the bottom of the eighth groove exposing a first connection portion arranged along the X direction, and the bottom of the ninth groove exposing a second connection portion arranged along the X direction; filling the eighth groove and the ninth groove with conductive material to form the first conductive line and the second conductive line, respectively. In the same memory block, multiple first connection portions arranged along the X direction can be coupled to the same first conductive line, and multiple second connection portions arranged along the X direction can be coupled to the same second conductive line. The steps for forming the first conductive line and the second conductive line described above are for illustrative purposes only and do not constitute a limitation on the scope of this disclosure.

[0161] Return to reference Figure 3B As shown, in some embodiments, the first conductive line 336 and the second conductive line 338 both extend along the X direction, and the first conductive line 336 and the second conductive line 338 are arranged alternately along the Y direction.

[0162] Return to reference Figure 3B As shown, in some embodiments, the method further includes: forming a first conductive portion 344 on the side of the first conductive line 336 away from the first connection portion 340, and the first conductive portion 344 being coupled to the first conductive line 336; forming a second conductive portion 346 on the side of the second conductive line 338 away from the second connection portion 342, and the second conductive portion 346 being coupled to the second conductive line 338.

[0163] For example, forming the first conductive portion and the second conductive portion may include the following steps: forming an eighth dielectric layer on a seventh dielectric layer; etching the eighth dielectric layer along the Z direction to form a first conductive hole exposing a first conductive line and a second conductive hole exposing a second conductive line; filling the first conductive hole and the second conductive hole with conductive material to form the first conductive portion and the second conductive portion, respectively. The steps for forming the first conductive portion and the second conductive portion described above are for illustrative purposes only and do not constitute a limitation on the scope of protection of this disclosure.

[0164] refer to Figure 7 , Figure 7 A block diagram of a memory provided for an embodiment of this disclosure. (As shown) Figure 7 As shown, this disclosure provides a memory 500, which includes: a semiconductor structure 300 as described above; and peripheral circuitry 502 coupled to the semiconductor structure 300.

[0165] Here, the peripheral circuit 502 may include an address buffer, a row decoder, a column decoder, a sense amplifier, and an input / output buffer.

[0166] Here, the address buffer can be used to receive the row address or column address of the memory cell. The address buffer can send the row address to the row decoder and the column address to the column decoder. The row decoder selects at least one of a plurality of word lines connected to the memory block (i.e., the first conductive line and the second conductive line) based on the row address received from the address buffer, and the row decoder activates the selected word line in response to a control signal. The column decoder selects at least one of a plurality of bit lines connected to the memory block, and the column decoder activates the selected bit line in response to a control signal.

[0167] Here, each memory block includes multiple memory cells connected to word lines and bit lines. A sense amplifier senses voltage changes in the active bit lines and amplifies those voltage changes to generate output data. An input / output buffer outputs data to an external device, such as a controller, via data lines based on the voltage amplified by the sense amplifier.

[0168] In some embodiments, the memory 500 includes 3D DRAM.

[0169] refer to Figure 8 , Figure 8 A block diagram of a memory system provided for an embodiment of this disclosure. (See diagram below.) Figure 8 As shown, this disclosure provides a memory system 600, which includes: a memory 500 as described above; and a controller 602 coupled to the memory 500 and configured to control the memory 500.

[0170] Here, the controller 602 can provide various signals to the memory 500 through the memory interface to control memory operations (e.g., write and read operations). For example, the controller 602 can access the data DATA of the memory 500 by providing the memory 500 with the command CMD and the address ADDR. As an example, the command CMD may include an activation command for normal memory operations, a precharge command, and / or a refresh command for refresh operations.

[0171] This disclosure provides a semiconductor structure and its manufacturing method, a memory, and a memory system. In this embodiment, the memory array includes a first subarray and a second subarray. The first subarray includes first semiconductor pillars extending along a first direction and evenly spaced along a second direction and a third direction. The second subarray includes second semiconductor pillars extending along the first direction and evenly spaced along the second direction and a third direction. In the same memory array, the first end of the first semiconductor pillars in the first subarray arranged along the second direction and the second end of the second semiconductor pillars in the second subarray arranged along the second direction are coupled to the same bit line. Thus, the first and second subarrays in the same memory array can share the bit line, achieving a 50% reduction in the size of the bit line along the second direction while maintaining the same number of memory cells connected by the bit line, thereby improving the integration density of the semiconductor structure.

[0172] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0173] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: a memory array, the memory array including a first subarray and a second subarray; The first subarray includes: first semiconductor pillars extending along a first direction and evenly spaced along a second direction and a third direction; The second subarray includes: second semiconductor pillars extending along the first direction and evenly spaced along the second direction and the third direction; In the same memory array, the first end of the first semiconductor pillar arranged along the second direction in the first subarray and the second end of the second semiconductor pillar arranged along the second direction in the second subarray are coupled to the same bit line; wherein any two of the first direction, the second direction and the third direction intersect.

2. The semiconductor structure according to claim 1, characterized in that, The first semiconductor pillar includes a first end and a third end disposed opposite to each other along the first direction; the second semiconductor pillar includes a second end and a fourth end disposed opposite to each other along the first direction; In the same memory array, the first subarray and the second subarray are arranged along the first direction, and the distance between the first end and the second end of the first semiconductor pillar and the second semiconductor pillar arranged along the first direction is less than the distance between the third end and the fourth end.

3. The semiconductor structure according to claim 2, characterized in that, In the same memory array, the bit lines extend along the second direction and are spaced apart along the third direction; The first end and the second end are mirror-symmetric about the bit line; the third end and the fourth end are mirror-symmetric about the bit line.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first gate structure is disposed on at least one sidewall of the first semiconductor pillar; the first gate structure of the first semiconductor pillar arranged along the third direction is coupled to the same first word line, the first word line extending along the third direction and spaced apart along the second direction; A second gate structure is disposed on at least one sidewall of the second semiconductor pillar; the second gate structure of the second semiconductor pillar arranged along the third direction is coupled to the same second word line, the second word line extending along the third direction and spaced apart along the second direction.

5. The semiconductor structure according to claim 4, characterized in that, Multiple storage arrays are arranged along the first direction to form a storage block; The semiconductor structure also includes: The first conductive line, the first word lines in different memory arrays in the same memory block are coupled to the same first conductive line; The second conductive line, wherein the second word line in different memory arrays within the same memory block is coupled to the same second conductive line.

6. The semiconductor structure according to claim 5, characterized in that, The number of the first conductive lines in the same memory block is the same as the number of the first semiconductor pillars arranged along the second direction in each of the first sub-arrays; The number of the second conductive lines in the same memory block is the same as the number of the second semiconductor pillars arranged along the second direction in each of the second sub-arrays.

7. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure also includes: A first connection portion is provided between the first conductive line and the first word line, one end of the first connection portion is coupled to the first word line and the other end of the first connection portion is coupled to the first conductive line; A second connection portion is provided between the second conductive line and the second word line, one end of the second connection portion is coupled to the second word line and the other end of the second connection portion is coupled to the second conductive line.

8. The semiconductor structure according to claim 5, characterized in that, Both the first conductive line and the second conductive line extend along the first direction, and the first conductive line and the second conductive line are arranged alternately along the second direction.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: A first conductive portion is disposed on the side of the first conductive line away from the first semiconductor pillar and coupled to the first conductive line; A second conductive portion is disposed on the side of the second conductive line away from the second semiconductor pillar and coupled to the second conductive line.

10. The semiconductor structure according to claim 9, characterized in that, The first conductive line and the second conductive line are aligned in the second direction; the first conductive portion and the second conductive portion are both disposed on the same side of the storage block in the first direction, and the first conductive portion and the second conductive portion are offset in the second direction.

11. The semiconductor structure according to claim 9, characterized in that, The first conductive line and the second conductive line are aligned in the second direction; the first conductive portion and the second conductive portion are both disposed on the same side of the storage block in the first direction, and the first conductive portion and the second conductive portion are aligned in the second direction.

12. The semiconductor structure according to claim 9, characterized in that, The first conductive line and the second conductive line are offset in the second direction; the first conductive part and the second conductive part are both provided on the same side of the storage block in the first direction, and the first conductive part and the second conductive part are offset in the second direction.

13. The semiconductor structure according to claim 9, characterized in that, The first conductive line and the second conductive line are offset in the second direction; the first conductive part and the second conductive part are both located on different sides of the storage block in the first direction.

14. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: A first capacitor is disposed on the side of the first semiconductor pillar near the third end and coupled to the third end; A second capacitor is disposed on the side of the second semiconductor pillar near the fourth end and coupled to the fourth end.

15. A memory, characterized in that, The memory includes: The semiconductor structure as described in any one of claims 1 to 14; and The peripheral circuitry is coupled to the semiconductor structure.

16. The memory according to claim 15, characterized in that, The memory includes: three-dimensional dynamic random access memory (3D DRAM).

17. A memory system, characterized in that, The memory system includes: The memory as described in claim 15 or 16; and A controller coupled to the memory and configured to control the memory.

18. A method for manufacturing a semiconductor structure, characterized in that, The method includes: A memory array is formed, the memory array including a first subarray and a second subarray, the first subarray including a first semiconductor pillar extending along a first direction and evenly spaced along a second direction and a third direction; the second subarray including a second semiconductor pillar extending along the first direction and evenly spaced along the second direction and the third direction. A bit line is formed between the first subarray and the second subarray; in the same memory array, the first end of the first semiconductor pillar arranged along the second direction in the first subarray and the second end of the second semiconductor pillar arranged along the second direction in the second subarray are coupled to the same bit line; wherein any two of the first direction, the second direction and the third direction intersect.

19. The manufacturing method according to claim 18, characterized in that, Before forming a bit line between the first subarray and the second subarray, the method further includes: A first gate structure is formed on at least one sidewall of the first semiconductor pillar; the first gate structure of the first semiconductor pillar arranged along the third direction is coupled to the same first word line, the first word line extending along the third direction and spaced apart along the second direction; A second gate structure is formed on at least one sidewall of the second semiconductor pillar; the second gate structure of the second semiconductor pillar arranged along the third direction is coupled to the same second word line, the second word line extending along the third direction and spaced apart along the second direction.

20. The manufacturing method according to claim 19, characterized in that, The first semiconductor pillar includes a first end and a third end disposed opposite to each other along the first direction; the second semiconductor pillar includes a second end and a fourth end disposed opposite to each other along the first direction; forming a bit line between the first subarray and the second subarray includes: A bit line groove is formed between the first end of the first semiconductor pillar and the second end of the second semiconductor pillar; Conductive material is filled into the bit line groove to form a bit line; wherein, in the same memory array, the bit lines extend along the second direction and are spaced apart along the third direction.

21. The manufacturing method according to claim 20, characterized in that, After forming a bit line between the first subarray and the second subarray, the method further includes: A first capacitor is formed on the side of the first semiconductor pillar near the third end, and the third end is coupled to the first capacitor; A second capacitor is formed on the side of the second semiconductor pillar near the fourth end, and the fourth end is coupled to the second capacitor.

22. The manufacturing method according to claim 21, characterized in that, The method further includes: A first connection portion is formed on one side of the first semiconductor pillar along the third direction, and the first connection portion is coupled to the first word line; A second connection portion is formed on one side of the second semiconductor pillar along the third direction, and the second connection portion is coupled to the second word line.

23. The manufacturing method according to claim 22, characterized in that, The method further includes: Multiple storage arrays are arranged along the first direction to form a storage block; A first conductive line is formed on the side of the first connection portion away from the first semiconductor pillar, and the first word lines in different memory arrays in the same memory block are coupled to the same first conductive line through the first connection portion. A second conductive line is formed on the side of the second connection portion away from the second semiconductor pillar, and the second word lines in different memory arrays in the same memory block are coupled to the same second conductive line through the second connection portion.

24. The manufacturing method according to claim 23, characterized in that, Both the first conductive line and the second conductive line extend along the first direction, and the first conductive line and the second conductive line are arranged alternately along the second direction.

25. The manufacturing method according to claim 24, characterized in that, The method further includes: A first conductive portion is formed on the side of the first conductive line away from the first connecting portion, and the first conductive portion is coupled to the first conductive line; A second conductive portion is formed on the side of the second conductive line away from the second connection portion, and the second conductive portion is coupled to the second conductive line.

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