Growth substrate wafer for high performance GaN switching power device, epitaxial wafer using same, and method of manufacturing same
By forming SiOx protrusions on a Si(111) substrate and growing a GaN-based merging layer using the ELOG method, the problem of high TDD on large-diameter Si substrates was solved, high-quality GaN epitaxial wafers were realized, device performance and reliability were improved, and production costs were reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WAVELORD CO LTD
- Filing Date
- 2025-11-05
- Publication Date
- 2026-05-08
AI Technical Summary
When growing GaN epitaxial layers on large-diameter silicon growth substrates, there is a high through-dislocation density (TDD) problem, which leads to device performance degradation and decreased reliability.
Using a SiOx protrusion patterned Si substrate and an epitaxial lateral transition growth (ELOG) method, SiOx protrusions are formed on a Si(111) substrate and a GaN-based merging layer is grown on them. The SiOx protrusions are used as a mask to prevent vertical propagation of penetrating dislocations, and a low TDD GaN layer is formed by lateral growth and merging.
Significantly reduces TDD to less than 10⁸/cm², improves leakage current and dynamic on-resistance, enhances breakdown voltage and device reliability, and provides high-performance GaN power devices with high productivity and cost-effectiveness.
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Figure CN122002871A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to high-performance switching power devices using gallium nitride (GaN), and more specifically, to patterned silicon substrates (PSiS) for forming high-quality GaN epitaxial layers on silicon (Si) growth substrates, and epitaxial wafers that significantly reduce threading dislocation density (TDD) using said substrates, and methods for manufacturing the same. Background Technology
[0002] Gallium nitride (GaN) compound semiconductors are wide-bandgap materials that, compared to traditional semiconductor materials such as silicon (Si) and gallium arsenide (GaAs), have a higher breakdown field, excellent thermal conductivity, and high carrier mobility.
[0003] Because of these properties, it can achieve high power density in a smaller size and is attracting attention as a key material for next-generation power semiconductor devices.
[0004] In order for GaN power semiconductors to be competitive in the market, normally closed operation with high blocking voltage and low leakage current is essential.
[0005] The ideal structure to achieve this is a vertical structure device (vertical FET) with a thick epitaxial region. However, due to the difficulty in commercializing GaN homogeneous growth substrates (GaN-on-GaN) and the low efficiency of ion implantation processes, horizontal structure high electron mobility transistors (HEMTs) that grow thin films on heterogeneous growth substrates are currently the main materials used for fabrication.
[0006] At this point, heterogeneous growth substrates such as sapphire, silicon (Si), and silicon carbide (SiC) are used. However, due to the mismatch in lattice constant and thermal expansion coefficient between the GaN epitaxial layer and the growth substrate, a level of 10... 7 ~10 10 / cm 2 The device exhibits a very high through-dislocation density (TDD). These through-dislocations are a persistent problem that severely and adversely affects device performance and reliability. Specifically, through-dislocations cause a variety of problems.
[0007] (1) Increased leakage current: Through-hole dislocations (screw and mixed dislocations) containing screw components serve as the main leakage path, which degrades the off-state characteristics of the device.
[0008] (2) Blocking voltage reduction: Through-through dislocations act as "hot spots", causing electric field congestion at specific points in the device, resulting in premature breakdown of the device before reaching its inherent breakdown voltage.
[0009] (3) Reduced switching frequency: Through-dislocations act as scattering and trapping centers in the electron's path, reducing carrier mobility. This performance degradation is particularly pronounced in horizontal HEMT structures where the current flows laterally to the through-dislocations.
[0010] (4) Increased dynamic on-resistance (RON): During high-voltage switch operation, charge is trapped in defects, including penetrating dislocations, and then slowly released, causing a temporary increase in on-resistance immediately after the switch is turned on. This is the main reason for the increase in power loss.
[0011] (5) Decreased reliability: Crystal defects such as through dislocations become the starting point for various degradation mechanisms such as gate edge degradation, hot electron generation, and thin film delamination when the device is operating in a high electric field and high temperature environment, thereby shortening the device life.
[0012] Therefore, in order to commercialize high-performance, high-reliability GaN power devices, there is an urgent need to develop technologies that can control TDD to less than 10 on large-diameter 8-inch or 12-inch Si substrates. 8 / cm 2 High-quality epitaxial growth technology. Summary of the Invention
[0013] Technical issues
[0014] This invention is designed to solve the problems of the prior art as described above, and its main purpose is to solve the problem of high through-dislocation density (TDD) that occurs when growing GaN epitaxial layers on large-diameter silicon (Si) growth substrates.
[0015] Specifically, the purpose of this invention is to significantly reduce TDD to less than 10. 8 / cm 2 This is to provide high-quality GaNHEMT epitaxial wafers, which can improve electrical characteristics such as leakage current and dynamic on-resistance, and enhance breakdown voltage and reliability.
[0016] Furthermore, another objective of this invention is to provide a growth substrate wafer for high-performance GaN power devices and a method for manufacturing the same, which is applicable to large-diameter wafer processes of 8-inch and 12-inch wafers, providing high productivity and cost-effectiveness.
[0017] Technical solution
[0018] According to an embodiment of the present invention, a growth substrate wafer for a high-performance GaN switching power device is provided, the growth substrate wafer comprising: a Si(111) growth substrate; a first AlN nucleation layer formed on the Si(111) growth substrate; and a plurality of SiOx protrusions discontinuously spaced apart on the first AlN nucleation layer, wherein the surface of the first AlN nucleation layer is exposed in the region between the plurality of SiOx protrusions.
[0019] In this paper, the shape of SiOx protrusions is characterized by being lenticular, truncated, dome, conical, polygonal, or cubic.
[0020] Furthermore, it is characterized by including a SiNx protective film formed between the first AlN nucleation layer and the plurality of SiOx protrusions.
[0021] According to an embodiment of the present invention, an epitaxial wafer using a growth substrate wafer is provided, the epitaxial wafer comprising: a GaN-based merged growth layer grown from the exposed surface of a first AlN nucleation layer between the plurality of SiOx protrusions, covering the tops of the SiOx protrusions and merging with each other; and a GaN HEMT device active layer formed on the GaN-based merged growth layer.
[0022] In this paper, the GaN-based merged growth layer can be configured as an undoped GaN (uGaN) monolayer.
[0023] Alternatively, the GaN-based merged growth layer can be configured as a multilayer structure in which uGaN layers and AlN layers or AlGaN layers are stacked alternately.
[0024] Additionally, it may include an Al(z)Ga(1-z)N stress control layer formed between the GaN-based merged growth layer and the GaN HEMT device active layer.
[0025] In addition, it may include a second AlN nucleation layer formed between the plurality of SiOx protrusions and the GaN-based merged growth layer, covering the exposed surface of the first AlN nucleation layer and the surface of the SiOx protrusions.
[0026] According to an embodiment of the present invention, a method for manufacturing an epitaxial wafer is provided, the method comprising the steps of: (a) preparing a Si(111) growth substrate; (b) forming a first AlN nucleation layer on the Si(111) growth substrate; (c) depositing a SiOx thin film on the first AlN nucleation layer; (d) patterning the SiOx thin film to form a plurality of discontinuously spaced SiOx protrusions; (e) forming a GaN-based merged growth layer by laterally growing (epitaxylateral overgrowth, ELOG) GaN-based material from the first AlN nucleation layer exposed between the SiOx protrusions and merging it over the SiOx protrusions; and (f) stacking a GaN HEMT (high electron mobility transistor) device active layer on the GaN-based merged growth layer.
[0027] In this document, step (e) may include forming a GaN-based merged growth layer by alternately and repeatedly growing uGaN layers, as well as one of AlN and AlGaN layers.
[0028] Additionally, the method may include a step between step (d) and step (e) of forming a second AlN nucleation layer on the first AlN nucleation layer and the plurality of SiOx protrusions.
[0029] Beneficial effects
[0030] According to the present invention, the following effects can be obtained.
[0031] First, by using the ELOG method to form SiOx protrusion patterns on a Si(111) growth substrate, the propagation of through dislocations caused by lattice mismatch with the Si substrate onto the active layer of the upper device can be effectively prevented. This enables the fabrication of active layers with less than 10 8 / cm 2 High-quality GaN HEMT epitaxial wafers with high penetration dislocation density (TDD).
[0032] Secondly, with the significant reduction in TDD, factors that degrade the electrical performance of the device, such as leakage current and dynamic on-resistance, are eliminated, thereby maximizing the performance of GaN switching power devices.
[0033] Third, the lower defect density in the device improves the breakdown voltage characteristics, greatly enhances the operational reliability under high electric fields and high temperatures, and extends the device's lifespan.
[0034] Fourth, by using inexpensive and easily scalable large-diameter Si(111) substrates instead of expensive sapphire or SiC substrates, a cost-effective solution is provided for manufacturing high-performance GaN power devices more economically. Attached Figure Description
[0035] Figure 1 This is a diagram illustrating the structure of a PSiS growth substrate wafer according to an embodiment of the present invention.
[0036] Figure 2 It is shown Figure 1 A diagram of a variation.
[0037] Figure 3 It shows the use Figure 1 The diagram shows the structure of the GaN-based merged growth layer formed on the PSiS growth substrate wafer.
[0038] Figure 4 It is shown in Figure 3 An epitaxial wafer with a HEMT structure is stacked on a GaN-based merged growth layer.
[0039] Figure 5 and Figure 6 It means Figure 3 A diagram of a variation. Detailed Implementation
[0040] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0041] This invention includes several organically combined technical configurations to effectively control through-dislocations, a persistent problem in GaN-on-Si technology.
[0042] First, refer to Figure 1 and Figure 2 The technical significance of the PSiS (patterned Si substrate) growth substrate, which is the core of this invention, lies in the fact that it provides a physical template that fundamentally prevents the propagation of penetrating dislocations originating from the Si substrate (10).
[0043] Multiple SiOx protrusions (30) formed on the AlN nucleation layer (20) serve as a mask to prevent through dislocations, and the geometry of these protrusions (30) (e.g., domes, cones, etc.) optimizes the lateral growth kinetics of the GaN crystal during the subsequent ELOG (epitaxylateral overgrowth) process to induce defect-free merging.
[0044] Furthermore, by adding a SiNx protective film (25) during the SiOx protrusion (30) formation process to protect the AlN nucleation layer (20), the quality and process stability of the initial GaN growth can be ensured.
[0045] This has the effect of establishing an ideal foundation for high-quality GaN growth while using inexpensive large-diameter Si substrates (10).
[0046] Next, refer to Figures 3 to 6The epitaxial wafer completed by applying the ELOG method on the PSiS growth substrate (10) is of great significance as the final product of this invention.
[0047] The “GaN-based merged growth layer (40)” formed by covering SiOx protrusions (30) is used as a high-quality buffer layer with significantly reduced through dislocation density.
[0048] In particular, process efficiency can be improved by configuring the merged growth layer (40) as a uGaN monolayer with high material diffusivity, or advanced techniques can be implemented by applying uGaN / AlN (or AlGaN) multilayer structures to filter out even laterally extended residual dislocations.
[0049] Furthermore, by introducing a second AlN nucleation layer (35) to improve growth uniformity and introducing an Al(z)Ga(1-z)N stress control layer (50) to address wafer bending issues in large-diameter wafers, this configuration ultimately maximizes device characteristics and mass production productivity.
[0050] Due to the high-quality underlying structure, the active layer (60) of the GaN HEMT device formed thereon exhibits excellent electrical characteristics.
[0051] Furthermore, the PSiS structure and radial ELOG method proposed in this invention utilize the principle that SiOx protrusions act as masks to prevent through-dislocations from vertically extending from the Si substrate, and high-quality dislocation-free GaN regions are ensured through lateral growth, which are then merged. This allows for a significant reduction in TDD across the entire epitaxial wafer.
[0052] The embodiments of the present invention will be described below.
[0053] Implementation Method 1: Structure and Fabrication of PSiS Growth Substrate Wafers
[0054] refer to Figure 1 In step ①, a Si (111) wafer is prepared as a growth substrate (10).
[0055] Si(111) substrates (10) can be easily scaled to large diameters such as 4 inches, 6 inches, 8 inches, 12 inches, and there are no particular limitations on their thickness.
[0056] Next, in step ②, a first AlN nucleation layer (20) is formed on the Si(111) substrate (10).
[0057] The AlN nucleation layer (20) plays an important role in suppressing the Si-Ga reaction (reflow etching) that occurs when the Si substrate (10) reacts with gallium (Ga) atoms in a high-temperature hydrogen atmosphere during the subsequent GaN growth process.
[0058] The AlN nucleation layer (20) is preferably formed using chemical vapor deposition (CVD) methods such as MOCVD or HVPE with a thickness of less than 0.5 μm, or it can be formed by combining physical vapor deposition (PVD) methods such as MBE or sputtering with a thermal treatment process.
[0059] Subsequently, in step ③, an amorphous SiOx thin film is deposited in order to form a protrusion (30) that will be used as a mask for the ELOG process.
[0060] SiOx thin films are preferably deposited to a thickness of less than 2 μm using PECVD or ALD processes.
[0061] At this time, as Figure 2 As shown, in order to protect the AlN nucleation layer (20) from the subsequent dry etching process, a SiNx protective film (25) can be introduced before the SiOx film deposition.
[0062] Finally, in step ④, the SiOx film is selectively etched using photolithography and dry etching processes to form multiple SiOx protrusions (30) with predetermined shapes and arrangements.
[0063] This completes the PSiS growth substrate wafer according to the present invention.
[0064] The shape of the SiOx protrusions (30) can be designed in various forms, such as lens shape, truncated shape, dome shape, cone shape, polygon or cubic shape, which can induce lateral growth and effectively prevent through dislocations in the ELOG process.
[0065] The arrangement of the SiOx protrusions (30) can mainly consider a hexagonal structure.
[0066] The size scale of the SiOx protrusions (30), such as size, spacing, height, etc., is preferably in the range of a few micrometers to tens to hundreds of nanometers.
[0067] Implementation Method 2: Epitaxial wafer (multilayer merged growth structure) using a PSiS substrate
[0068] refer to Figure 3 The core of this implementation is to form a GaN-based merged growth layer (40) with low TDD through a radial ELOG process.
[0069] First, the growth of GaN-based materials begins with the exposure of AlN nucleation layers (20) between SiOx protrusions (30).
[0070] At this point, the penetrating dislocations originate from the exposed AlN region, but as growth proceeds, the GaN crystal grows laterally, covering the SiOx protrusions (30) (lateral overgrowth).
[0071] The SiOx protrusions (30) serve as a mask to block the vertical expansion of penetrating dislocations originating below, and the lateral growth regions form high-quality crystals with almost no penetrating dislocations.
[0072] When the lateral growth regions originating from adjacent protrusions (30) meet and merge, a flat GaN-based merged growth layer (40) with low TDD is completed on the entire wafer surface.
[0073] In this invention, to maximize the TDD reduction effect, the GaN-based composite growth layer (40) can be formed into a multilayer structure of uGaN (undoped GaN) and AlN, such as... Figure 3 As shown.
[0074] For example, a uGaN layer (h1) of predetermined thickness and a thin AlN layer (h2) of less than 5 nm are paired, and this pair is repeatedly deposited several times to grow to a height above the SiOx protrusion (30), thereby achieving complete planarization.
[0075] uGaN has a high material diffusivity, which is beneficial for lateral growth, and the thin AlN layers inserted therein are used to bend or annihilate the remaining penetrating dislocations, further improving the TDD reduction efficiency.
[0076] refer to Figure 4 After the GaN-based merged growth layer (40) is formed flat, an additional Al(z)Ga(1-z)N stress control layer (50) can be grown to control wafer bending and total stress as needed.
[0077] Finally, the final epitaxial wafer is completed by sequentially stacking GaN HEMT device active layers (60) in which the actual devices operate, such as GaN channel layer (61), AlGaN barrier layer (62) and p-GaN E-mode layer (63) on top.
[0078] Before forming the active layer (60) of the GaN HEMT device, which includes the GaN channel layer (61), the high-resistivity region can be formed as a single-layer or multi-layer film made of GaN or AlN material, and in the case of GaN material, dopants such as carbon (C) or iron (Fe) are intentionally introduced.
[0079] Implementation method 3: Epitaxial wafer including a second nucleation layer
[0080] Figure 5 and Figure 6 Another embodiment of the invention is shown.
[0081] This embodiment is basically similar to embodiment 2, but is characterized in that a second nucleation layer (35) is formed on the entire surface of the PSiS growth substrate before growing the GaN-based merging growth layer (40).
[0082] Specifically, an AlN thin film smaller than 20 nm is deposited as a second nucleation layer (35) on the PSiS substrate that forms SiOx protrusions (30).
[0083] The second nucleation layer (35) covers the exposed surfaces of the first AlN nucleation layer (20) and the SiOx protrusions (30) between the SiOx protrusions (30), forming a continuous film.
[0084] Then, use uGaN( Figure 5 ) or uGaN / AlN multilayer structure ( Figure 6 )Execute the ELOG process.
[0085] The second nucleation layer (35) is used to more uniformly control the initial nucleation conditions of GaN across the entire wafer surface, enabling a more stable and reproducible ELOG process. The remaining process steps are the same as in Embodiment 2.
Claims
1. A growth substrate wafer for high-performance GaN switching power devices, the growth substrate wafer comprising: Si(111) growth substrate; A first AlN nucleation layer is formed on the Si(111) growth substrate; and A plurality of SiOx protrusions are discontinuously spaced apart on the first AlN nucleation layer, wherein the surface of the first AlN nucleation layer is exposed in the region between the plurality of SiOx protrusions.
2. The growth substrate wafer according to claim 1, wherein, The shape of the SiOx protrusion is lens-shaped, truncated, dome-shaped, conical, polygonal, or cubic.
3. The growth substrate wafer according to claim 1, wherein the growth substrate wafer further comprises a SiNx protective film formed between the first AlN nucleation layer and the plurality of SiOx protrusions.
4. An epitaxial wafer using the growth substrate wafer of claim 1, the epitaxial wafer comprising: GaN-based merged growth layers grow from the exposed surface of the first AlN nucleation layer between the plurality of SiOx protrusions, covering the tops of the SiOx protrusions and merging with each other; and The active layer of the GaN HEMT device is formed on the GaN-based merged growth layer.
5. The epitaxial wafer according to claim 4, wherein, The GaN-based merged growth layer is an undoped GaN (uGaN) monolayer.
6. The epitaxial wafer according to claim 4, wherein, The GaN-based merged growth layer is a multilayer structure in which uGaN layers and AlN layers or AlGaN layers are stacked alternately.
7. The epitaxial wafer according to claim 4, wherein the epitaxial wafer further comprises an Al(z)Ga(1-z)N stress control layer formed between the GaN-based merged growth layer and the GaN HEMT device active layer.
8. The epitaxial wafer of claim 4, further comprising a second AlN nucleation layer formed between the plurality of SiOx protrusions and the GaN-based merged growth layer, and covering the exposed surface of the first AlN nucleation layer and the surface of the SiOx protrusions.
9. A method for fabricating an epitaxial wafer using a growth substrate wafer for high-performance GaN switching power devices, the method comprising the following steps: (a) Preparation of Si(111) growth substrate; (b) A first AlN nucleation layer is formed on the Si(111) growth substrate; (c) Deposit a SiOx thin film on the first AlN nucleation layer; (d) Patterning the SiOx thin film to form a plurality of discontinuously spaced SiOx protrusions; (e) A GaN-based merged growth layer is formed by laterally growing (epi-epitaxylateral overgrowth, ELOG) GaN-based material from the first AlN nucleation layer exposed between the SiOx protrusions and merging it over the SiOx protrusions; and (f) Stacking the GaN HEMT device active layer on the GaN-based merged growth layer.
10. The method according to claim 9, wherein, Step (e) includes forming a GaN-based merged growth layer by alternately and repeatedly growing uGaN layers, as well as one of AlN and AlGaN layers.
11. The method of claim 9, further comprising the step of forming a second AlN nucleation layer on the first AlN nucleation layer and the plurality of SiOx protrusions between steps (d) and (e).