Gate structure and manufacturing method thereof
By introducing a combined protection structure of a hard mask layer and a second spacer into the gate structure, the problems of memory cell exposure and word line leakage current caused by mask pattern position misalignment are solved, achieving higher flash memory reliability and lower production cost and energy consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2024-12-05
- Publication Date
- 2026-05-08
AI Technical Summary
In the prior art, the offset of the mask pattern position causes the top surface of the memory cell to be exposed, allowing contaminants to enter the memory cell, damaging the spacers, and causing word line leakage current problems. Furthermore, the top surface of the mask material layer is recessed during the planarization process, which fails to protect the memory cell.
A hard mask layer and a second spacer are introduced into the gate structure to protect the top cap layer and the first spacer, prevent contaminants from entering, and avoid mask pattern position displacement. A stable protective structure is formed by the combination of multiple spacers and hard mask layers.
It effectively prevents contaminants from entering the gate assembly, protects the spacers of the memory cells, reduces word line leakage current, lowers manufacturing costs and energy consumption, improves the reliability and miniaturization capability of flash memory, and reduces carbon emissions.
Smart Images
Figure CN122002877A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a gate structure and its manufacturing method. Background Technology
[0002] Generally, after forming the memory cells of a flash memory, spacers are formed on the sidewalls of the cells. Then, to increase data retention, a mask material layer is formed on the cells and spacers, and this mask material layer is patterned to create a mask pattern on the cells that connects to the spacers. However, if the mask pattern is misaligned, part of the top surface of the memory cell will be exposed. This allows contaminants (such as metal ions) from subsequent processes to enter the cell, impacting component performance and reliability.
[0003] Furthermore, during the planarization process following the formation of the aforementioned mask material layer, dishing can easily occur on the top surface of the mask material layer. This can prevent proper protection of the spacers in the memory cells, potentially damaging them in subsequent processes. Consequently, word line leakage current issues may occur during flash memory testing or operation. Summary of the Invention
[0004] This invention relates to a gate structure and its manufacturing method, which can improve the problem that mask patterns cannot adequately protect memory cells or spacers of memory cells.
[0005] The gate structure of the present invention includes a gate assembly, a first spacer, a top cap layer, a hard mask layer, and a second spacer. The gate assembly is disposed on a substrate. The first spacer is disposed on a sidewall of the gate assembly. The top cap layer is disposed on the top surface of the gate assembly. The hard mask layer is disposed on the top cap layer. The second spacer is disposed on a sidewall of the hard mask layer, a sidewall of the top cap layer, and a sidewall of the first spacer.
[0006] The method for manufacturing the gate structure of the present invention includes the following steps: A gate assembly, a capping layer, and a hard mask layer are sequentially formed on a substrate. A first spacer is formed on the sidewall of the gate assembly. A second spacer is formed on the sidewall of the hard mask layer, the sidewall of the capping layer, and the sidewall of the first spacer.
[0007] Based on the above, in the gate structure of the present invention, a hard mask layer is disposed on the top cap layer, and a second spacer is disposed on the sidewalls of the hard mask layer and the top cap layer, as well as on the first spacer. Therefore, the top cap layer can be protected by the hard mask layer and the second spacer, and the first spacer can also be protected by the second spacer. In this way, contaminants (e.g., metal ions) can be effectively prevented from penetrating the top cap layer or the first spacer into the gate assembly in subsequent processes, and the spacers of the memory cells can be well protected. Attached Figure Description
[0008] Figures 1A to 1C This is a schematic cross-sectional view of the manufacturing process of the gate structure according to the first embodiment of the present invention;
[0009] Figures 2A to 2D This is a schematic cross-sectional view of the manufacturing process of the gate structure according to the second embodiment of the present invention;
[0010] Figures 3A to 3C This is a schematic cross-sectional view of the manufacturing process of the gate structure according to the third embodiment of the present invention. Detailed Implementation
[0011] In the following description, when a component is described as being disposed "on" another component, the component may be in direct contact with the other component, or there may be other components between them.
[0012] In the following embodiments, when the gate structure is part of flash memory (e.g., NOR flash memory), the gate assembly may include a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially disposed on a substrate, but the present invention is not limited thereto.
[0013] The following will be based on Figures 1A to 1C The manufacturing process of the gate structure according to the first embodiment of the present invention is described below. (Refer to...) Figure 1A Dielectric layer 102, conductive layer 104, dielectric layer 106, conductive layer 108, dielectric layer 110 and dielectric layer 112 are sequentially formed on substrate 100.
[0014] In this embodiment, the substrate 100 is, for example, a silicon substrate or silicon-on-insulator, but the invention is not limited thereto. The dielectric layer 102 is, for example, an oxide layer, which can be formed by, for example, thermal oxidation or chemical vapor deposition. The dielectric layer 102 can be used to form a tunnel dielectric layer for a gate structure. The conductive layers 104 and 108 are, for example, polysilicon layers, wherein the conductive layer 104 can be used to form a floating gate for a gate structure, and the conductive layer 108 can be used to form a control gate for a gate structure. The dielectric layer 106 is, for example, an oxide layer, which can be used to form an inter-gate dielectric layer for a gate structure. In other embodiments, the dielectric layer 106 may include a composite structure composed of an oxide layer / nitride layer / oxide layer (O / N / O). The dielectric layer 110 is, for example, an oxide layer, which can be used to form a capping layer protecting the conductive layer 108. The dielectric layer 112 is, for example, a nitride layer, which can be used to form a hard mask layer. Depending on the function of the capping layer and the hard mask layer, the material of dielectric layer 110 is different from that of dielectric layer 112. Conductive layers 104, 108, and dielectric layers 106, 110, and 112 can be formed by, for example, chemical vapor deposition processes.
[0015] Next, refer to Figure 1BA patterning process is performed to remove portions of dielectric layer 102, conductive layer 104, dielectric layer 106, conductive layer 108, dielectric layer 110, and dielectric layer 112 to form a gate assembly 109 including a tunnel dielectric layer 102A, a floating gate 104A, an inter-gate dielectric layer 106A, and a control gate 108A, as well as a capping layer 110A and a hard mask layer 112A located on the top surface of the gate assembly 109.
[0016] Then, a first spacer 114 is formed on the sidewall of the gate assembly 109 to protect the gate assembly 109 from damage caused by subsequent processes. In this embodiment, the material of the first spacer 114 is, for example, an oxide, and its formation method is, for example, a thermal oxidation process. Furthermore, in this embodiment, the top surface of the first spacer 114 is coplanar with the top surface of the control gate 108A, but the invention is not limited thereto. In other embodiments, the top surface of the first spacer 114 may be coplanar with the top surface of the capping layer 110A, that is, the first spacer 114 may be further formed on the sidewall of the capping layer 110A.
[0017] Then, refer to Figure 1C A second spacer 116 is formed on the sidewall of the hard mask layer 112A, the sidewall of the top cover layer 110A, and the first spacer 114. In this embodiment, the material of the second spacer 116 is, for example, a nitride.
[0018] In the gate structure 10 of this embodiment, the second spacer 116 is disposed on the sidewall of the hard mask layer 112A, the sidewall of the capping layer 110A, and the first spacer 114. That is, the second spacer 116 extends from the surface of the substrate 100 to be coplanar with the top surface of the hard mask layer 112A. Furthermore, the material of the second spacer 116 is different from the materials of the capping layer 110A and the first spacer 114. Therefore, the capping layer 110A can be effectively protected by the hard mask layer 112A and the second spacer 116, and the first spacer 114 can also be effectively protected by the second spacer 116 to prevent contaminants (e.g., metal ions) in subsequent processes from passing through the capping layer 110A or the first spacer 114 and entering the gate assembly 109.
[0019] Furthermore, in this embodiment, since the top surface of the second spacer 116 is coplanar with the top surface of the hard mask layer 112A, the second spacer 116 can have sufficient thickness to block contaminants (e.g., metal ions) in subsequent processes from passing through the top cover layer 110A or the first spacer 114 when viewed from above the top cover layer 110A and the first spacer 114.
[0020] On the other hand, in this embodiment, during the formation of the hard mask layer 112A and the top cover layer 110A, the hard mask layer 112A can serve as a mask defining the top cover layer 110A. Therefore, after the hard mask layer 112A and the top cover layer 110A are formed, the sidewall of the hard mask layer 112A will be aligned with the sidewall of the top cover layer 110A, and the positional offset of the hard mask layer 112A will not occur. This will prevent the top surface of the top cover layer 110A from being exposed and thus avoid damage to the top cover layer 110A in subsequent processes.
[0021] In this embodiment, the second spacer 116 is a single film layer (e.g., a nitride layer), but the invention is not limited thereto. In other embodiments, the second spacer 116 may be a multilayer structure composed of at least two of oxide layers, nitride layers, and air gaps. The composition of the multilayer structure is not limited, as long as the material of the multilayer structure is sufficient to protect the top cover layer 110A and the first spacer 114.
[0022] In the first embodiment, the hard mask layer 112A disposed on the top cover layer 110A may be a single film layer, but the present invention is not limited thereto. In other embodiments, the hard mask layer disposed on the top cover layer 110A may include a first sub-hard mask layer and a second sub-hard mask layer disposed in the first sub-hard mask layer, which will be described in detail below.
[0023] The following is Figures 2A to 2D The manufacturing process of the gate structure according to the second embodiment of the present invention will be described. In this embodiment, the same components as in the first embodiment will be indicated by the same reference numerals and will not be described further.
[0024] Reference Figure 2A After forming the gate structure 10 of the first embodiment, a sacrificial layer 118 is formed on the substrate 100. The sacrificial layer 118 covers the second spacer 116 and the hard mask layer 112A. In this embodiment, the material of the sacrificial layer 118 is, for example, polysilicon, but the invention is not limited thereto. In other embodiments, the sacrificial layer 118 may be formed of other materials, as long as they have an etch selectivity ratio with the materials of the second spacer 116 and the hard mask layer 112A.
[0025] Next, refer to Figure 2B The sacrificial layer 118 can be partially removed using a process such as chemical mechanical polishing (CMP) until the top surface of the hard mask layer 112A is exposed. Then, an anisotropic etching process is performed, for example, to remove the hard mask layer 112A to form a recess R1. That is, in this embodiment, the recess R1 is defined by a second spacer 116 formed on the sidewall of the hard mask layer 112A and a top cap layer 110A located below the hard mask layer 112A.
[0026] Then, refer to Figure 2C A first mask material layer 120 is conformally formed on the sacrificial layer 118 and in the groove R1. In this embodiment, the material of the first mask material layer 120 is different from the material of the top cover layer 110A, but may be the same as the material of the second spacer 116. The material of the first mask material layer 120 is, for example, a nitride. Next, a second mask material layer 122 is formed on the first mask material layer 120, such that the second mask material layer 122 fills the groove R. In this embodiment, the material of the second mask material layer 122 is different from the material of the first mask material layer 120, but may be the same as the material of the top cover layer 110A. The material of the second mask material layer 122 is, for example, an oxide.
[0027] Then, refer to Figure 2D The first mask material layer 120 and the second mask material layer 122 outside the recess R1 are removed to form a first sub-hard mask layer 120A and a second sub-hard mask layer 122A in the recess R1. The first sub-hard mask layer 120A is located between the second sub-hard mask layer 122A and the sidewall and bottom surface of the recess R1. In other words, the second sub-hard mask layer 122A is formed in the first sub-hard mask layer 120A, and the top surfaces of the first sub-hard mask layer 120A and the second sub-hard mask layer 122A and the top surface of the second spacer 116 are coplanar. Furthermore, in this embodiment, the interface between the sidewall of the second sub-hard mask layer 122A and the first sub-hard mask layer 120A is substantially planar. Then, the sacrificial layer 118 is removed to form the gate structure 20 of this embodiment.
[0028] In the gate structure 20 of this embodiment, a hard mask layer consisting of a first sub-hard mask layer 120A and a second sub-hard mask layer 122A located within the first sub-hard mask layer 120A is formed on the capping layer 110A, and a second spacer 116 is disposed on the sidewall of the hard mask layer, the sidewall of the capping layer 110A, and the first spacer 114. Therefore, the capping layer 110A can be effectively protected by the hard mask layer and the second spacer 116, and the first spacer 114 can also be effectively protected by the second spacer 116 to prevent contaminants (e.g., metal ions) in subsequent processes from passing through the capping layer 110A or the first spacer 114 and entering the gate assembly 109.
[0029] The following is Figures 3A to 3C The manufacturing process of the gate structure according to the third embodiment of the present invention will be described. In this embodiment, the same components as in the second embodiment will be indicated by the same reference numerals and will not be described further.
[0030] Reference Figure 3A ,exist Figure 2BAfter removing a portion of the sacrificial layer 118, a portion of the hard mask layer 112A is removed to form a first sub-hard mask layer 112B with a groove R2. In this embodiment, the formed groove R2 may have curved sidewalls. In this embodiment, the first sub-hard mask layer 112B can be formed by adjusting the etching parameters during an anisotropic etching process of the hard mask layer 112A, but the invention is not limited thereto. By forming a groove R2 with curved sidewalls, especially in miniaturized devices, it facilitates the subsequent filling of the second mask material layer 122 and provides better protection for the gate assembly 109.
[0031] Next, refer to Figure 3B A second mask material layer 122 is formed on the first sub-hard mask layer 112B, such that the second mask material layer 122 fills the groove R2.
[0032] Then, refer to Figure 3C The second mask material layer 122 outside the recess R2 is removed to form a second sub-hard mask layer 122B in the recess R2. In other words, the second sub-hard mask layer 122B is formed in the first sub-hard mask layer 112B, and the top surfaces of the first sub-hard mask layer 112B, the second sub-hard mask layer 122B, and the second spacer 116 are coplanar. Furthermore, in this embodiment, the interface between the sidewall of the second sub-hard mask layer 122B and the first sub-hard mask layer 112B is curved. Then, the sacrificial layer 118 is removed to form the gate structure 30 of this embodiment.
[0033] In the gate structure 30 of this embodiment, a hard mask layer consisting of a first sub-hard mask layer 112B and a second sub-hard mask layer 122B located within the first sub-hard mask layer 112B is formed on the capping layer 110A, and a second spacer 116 is disposed on the sidewall of the hard mask layer, the sidewall of the capping layer 110A, and the first spacer 114. Therefore, the capping layer 110A can be effectively protected by the hard mask layer and the second spacer 116, and the first spacer 114 can also be effectively protected by the second spacer 116 to prevent contaminants (e.g., metal ions) in subsequent processes from passing through the capping layer 110A or the first spacer 114 and entering the gate assembly 109.
[0034] Furthermore, in an embodiment not shown, in forming such Figure 2B After the groove R1 shown, the first mask material layer 120 can completely fill the groove R1 without the need to set the second mask material layer 122.
[0035] According to the above embodiments of the present invention, the problem of partial exposure of the top surface of the memory cell due to mask pattern displacement, as seen in the prior art, is eliminated. Furthermore, since the second spacer is disposed on the sidewall of the hard mask layer, the sidewall of the top cover layer, and the first spacer, word line leakage current is improved. Moreover, compared to the prior art which requires independent patterning of the mask material layer, the gate structure manufacturing method of the present invention eliminates the lithography and etching steps associated with this process, thus reducing manufacturing costs and environmental impact. Furthermore, the present invention is applicable to the fabrication of miniaturized gate structures to increase the total number of chips on a wafer. Therefore, the present invention can reduce the production cost and energy consumption of manufacturing a single IC, as well as the energy consumption of subsequent packaging, thereby reducing carbon emissions in the flash memory manufacturing process. In addition, since the reliability of the flash memory is improved according to the present invention, the present invention provides a green semiconductor technology.
[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A gate structure, characterized in that, include: Gate assembly, disposed on substrate; A first spacer is disposed on the sidewall of the gate assembly; A top cover layer is disposed on the top surface of the gate assembly; A hard mask layer is disposed on the top cover layer; as well as The second spacer is disposed on the sidewall of the hard mask layer, the sidewall of the top cover layer, and the first spacer.
2. The gate structure according to claim 1, characterized in that, The top surface of the second spacer and the top surface of the hard mask layer are coplanar.
3. The gate structure according to claim 1, characterized in that, The material of the first spacer is different from the material of the second spacer.
4. The gate structure according to claim 1, characterized in that, The material of the top cover layer is different from the material of the second spacer.
5. The gate structure according to claim 1, characterized in that, The material of the hard mask layer is the same as the material of the second spacer.
6. The gate structure according to claim 1, characterized in that, The hard mask layer includes a first sub-hard mask layer and a second sub-hard mask layer, wherein the second sub-hard mask layer is disposed within the first sub-hard mask layer.
7. The gate structure according to claim 6, characterized in that, The top surface of the second spacer, the top surface of the first sub-hard mask layer, and the top surface of the second sub-hard mask layer are coplanar.
8. The gate structure according to claim 6, characterized in that, The material of the first sub-hard mask layer is different from that of the second sub-hard mask layer, and the first sub-hard mask layer and the second spacer are made of the same material.
9. The gate structure according to claim 6, characterized in that, The interface between the sidewall of the second sub-hard mask layer and the first sub-hard mask layer is planar.
10. The gate structure according to claim 6, characterized in that, The interface between the sidewall of the second sub-hard mask layer and the first sub-hard mask layer is curved.
11. The gate structure according to claim 1, characterized in that, The gate assembly includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate, which are sequentially disposed on the substrate.
12. A method for manufacturing a gate structure, characterized in that, include: A gate assembly, a top cap layer, and a hard mask layer are sequentially formed on a substrate; A first spacer is formed on the sidewall of the gate assembly; as well as A second spacer is formed on the sidewall of the hard mask layer, the sidewall of the top cover layer, and the first spacer.
13. The method for manufacturing a gate structure according to claim 12, characterized in that, The top surface of the second spacer and the top surface of the hard mask layer are coplanar.
14. The method for manufacturing a gate structure according to claim 12, characterized in that, After forming the second spacer, the process also includes: A sacrificial layer is formed on the substrate, wherein the sacrificial layer covers the second spacer and the hard mask layer; Remove a portion of the sacrificial layer until the top surface of the hard mask layer is exposed; Remove the hard mask layer to form a groove; A first mask material layer is conventionally formed on the sacrificial layer and in the groove; A second mask material layer is formed on the first mask material layer, wherein the second mask material layer fills the groove; and Remove the first mask material layer and the second mask material layer outside the groove to form a first sub-hard mask layer and a second sub-hard mask layer in the groove, wherein the first sub-hard mask layer is located between the second sub-hard mask layer and the sidewall and bottom surface of the groove.
15. The method for manufacturing a gate structure according to claim 14, characterized in that, The top surface of the second spacer, the top surface of the first sub-hard mask layer, and the top surface of the second sub-hard mask layer are coplanar.
16. The method for manufacturing a gate structure according to claim 14, characterized in that, The interface between the sidewall of the second sub-hard mask layer and the first sub-hard mask layer is planar.
17. The method for manufacturing a gate structure according to claim 12, characterized in that, After forming the second spacer, the process also includes: A sacrificial layer is formed on the substrate, wherein the sacrificial layer covers the second spacer and the hard mask layer; Remove a portion of the sacrificial layer until the top surface of the hard mask layer is exposed; Remove a portion of the hard mask layer to form a first sub-hard mask layer with grooves; and A second sub-hard mask layer is formed in the groove.
18. The method for manufacturing a gate structure according to claim 17, characterized in that, The method of removing part of the hard mask layer includes performing an anisotropic etching process.
19. The method for manufacturing a gate structure according to claim 17, characterized in that, The interface between the sidewall of the second sub-hard mask layer and the first sub-hard mask layer is curved.
20. The method for manufacturing a gate structure according to claim 12, characterized in that, The gate assembly includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate, which are sequentially formed on the substrate.