SOI-based GaN concave gate half-bridge integrated device and preparation method thereof

Abstract

The invention relates to an SOI-based GaN concave gate half-bridge integrated device and a preparation method thereof. The SOI-based GaN concave gate half-bridge integrated device comprises an SOI substrate, an AlN layer, a GaN layer, an AlGaN layer and a second insulating dielectric layer which are sequentially arranged from bottom to top, the SOI substrate comprises substrate silicon, a first insulating medium layer and top silicon; the second insulating dielectric layer is etched, source electrode metal and drain electrode metal grow, and a deep groove below a source electrode is etched and penetrates through the second insulating dielectric layer to the AlN layer; etching the second insulating medium layer and a part of the AlGaN layer in the concave gate region, growing a gate insulating medium and then growing gate metal to form a gate; the field plate metal grows above the source electrode metal and the grid electrode metal and is filled with a third insulating dielectric layer; a deep groove is formed in the middle of the device, penetrates through the third insulating medium layer to the top layer silicon, and is filled with an insulating medium; filling the top of the device with a fourth insulating dielectric layer; and obtaining the half-bridge integrated device through the top through hole and an interconnection process.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to an SOI-based GaN concave-gate half-bridge integrated device and its fabrication method. Background Technology

[0002] With the development of power semiconductor devices, power devices made of wide-bandgap semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC) are being used more and more widely. GaN-based power devices, especially heterojunctions with high-mobility two-dimensional electron gas (2DEG) channels (such as AlGaN / GaN), have become candidate materials for a new generation of power conversion systems with high conversion efficiency and high power density due to their excellent material properties such as wide bandgap, high critical breakdown field strength and high operating temperature.

[0003] In semiconductor devices, SOI (Silicon On Insulator) technology has gradually become one of the key technologies for improving integrated circuit performance due to its superior electrical isolation, low parasitic capacitance, and high radiation resistance. Traditional half-bridge circuits typically use MOSFETs as switching devices. However, with the increase in power density and operating frequency, traditional MOSFET devices face many challenges, such as high switching losses, high leakage current, and switching speed limitations caused by capacitance effects. Therefore, using GaN HEMT devices can effectively solve these problems, providing better switching performance and energy efficiency.

[0004] Concave-gate HEMT structures enable enhancement-mode devices and more precise control of threshold voltage, while half-bridge integration technology offers significant advantages in power electronics and other fields, particularly in improving efficiency, reducing circuit size, and lowering costs. By integrating SOI-based concave-gate HEMT half-bridges, the low leakage current and high withstand voltage of SOI technology can be fully utilized, reducing switching losses while simultaneously improving system power density and thermal efficiency. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an SOI-based GaN concave gate half-bridge integrated device and its fabrication method, so as to improve the power density and efficiency of the system, reduce switching losses, and reduce parasitic parameters.

[0006] To address the aforementioned technical problems, this invention provides an SOI-based GaN recessed-gate half-bridge integrated device, comprising, from bottom to top, an SOI substrate, an AlN layer, a GaN layer, an AlGaN layer, and a second insulating dielectric layer; the SOI substrate includes a base silicon, a first insulating dielectric layer, and a top silicon layer; the second insulating dielectric layer is etched to grow source metal and drain metal, wherein a deep trench is etched below the source, penetrating from the second insulating dielectric layer to the AlN layer; the second insulating dielectric layer and part of the AlGaN layer in the recessed gate region are etched, and a gate insulating dielectric is grown followed by a gate metal to form the gate; a field plate metal is grown above the source metal and the gate metal and fills a third insulating dielectric layer; a deep trench is provided in the middle of the half-bridge integrated device, penetrating from the third insulating dielectric layer to the top silicon layer, and the deep trench is filled with an insulating dielectric; a fourth insulating dielectric layer is filled on the top of the device; the SOI-based GaN recessed-gate half-bridge integrated device is obtained through top vias and interconnect processes.

[0007] Preferably, the source metal and drain metal include one or more of W, TiN, Al, Ni, Ti, Au, Mo, or Pt.

[0008] Preferably, the gate metal includes one or more of W, TiN, Al, Ni, Ti, Au, Mo, or Pt.

[0009] Preferably, the insulating medium comprises one or more stacked structures selected from SiO2, Al2O3, HfO2, La2O3, ZrO2, or Si3N4.

[0010] The present invention also provides a method for fabricating the above-mentioned SOI-based GaN concave-gate half-bridge integrated device, comprising:

[0011] (1) Using SOI-based GaN HEMT technology, an AlN layer, a GaN layer, an AlGaN layer, and a second insulating dielectric layer are sequentially grown on an SOI substrate to obtain an SOI-based GaN HEMT device, wherein the SOI substrate includes a base silicon, a first insulating dielectric layer, and a top silicon layer.

[0012] (2) Etch the second insulating dielectric layer to grow source metal and drain metal, wherein deep trench etching is performed below the source, penetrating the second insulating dielectric layer, AlGaN layer, GaN layer, AlN layer, and terminating at the top silicon layer;

[0013] (3) Etch the second insulating dielectric layer and part of the AlGaN layer in the recessed gate region, grow the gate insulating dielectric and then grow the gate metal to form the gate;

[0014] (4) A field plate metal is grown above the source metal and the gate metal and a third insulating dielectric layer is filled;

[0015] (5) Deep trench etching is performed in the middle of the device, penetrating the third insulating dielectric layer, the second insulating dielectric layer, the AlGaN layer, the GaN layer, the AlN layer, the top silicon layer, and terminating at the first insulating dielectric layer.

[0016] (6) Fill the deep groove in the middle of the device with an insulating medium to achieve isolation between the high and low sides of the device;

[0017] (7) Fill the top of the device with a fourth insulating dielectric layer;

[0018] (8) By using top vias and interconnection processes, the source on the high side of the device is connected to the drain on the low side, and the source on the low side and the drain on the high side are led out respectively, thus obtaining the SOI-based GaN recessed gate half-bridge integrated device.

[0019] Preferably, the growth method of the insulating medium in steps (1), (3), (4), (6), and (7) includes chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation, sputtering, etc.

[0020] Preferably, the etching methods in steps (2), (3) and (5) include ICP or RIE, and the etching atmosphere is one or more of SF6, CHF3, BCl3, CF4, C4F8, Cl2 or He.

[0021] Preferably, the metal growth method in steps (2), (3), and (4) includes magnetron sputtering or electron beam evaporation.

[0022] Beneficial effects

[0023] (1) Excellent high-frequency performance: The concave gate design can reduce parasitic capacitance and optimize electric field distribution. In addition, the performance of GaN itself makes it have significant advantages in high-frequency applications.

[0024] (2) Low on-resistance: GaN devices have lower on-resistance than traditional Si-based MOSFETs, which can reduce power loss and improve overall energy efficiency, especially in high-voltage and high-current applications.

[0025] (3) High control precision: The concave gate design enhances the gate's control capability over the channel, achieving enhanced device while improving the device's threshold voltage control stability and switching speed.

[0026] (4) Low substrate leakage current and high withstand voltage: By integrating SOI-based recessed gate HEMT devices into a half-bridge circuit, the low leakage current and high withstand voltage performance of SOI technology can be fully utilized, while improving the power density and thermal efficiency of the system.

[0027] (5) Good isolation: The upper and lower tubes are isolated by deep trench etching technology, and the source and substrate are at the same potential, which can avoid substrate crosstalk. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of the SOI-based GaN concave gate half-bridge integrated device of the present invention.

[0029] Figure 2 This is a schematic diagram of the SOI-based GaN HEMT device of the present invention.

[0030] Figure 3 This is a schematic diagram of the device structure after the source metal and drain metal of the present invention are grown.

[0031] Figure 4 This is a schematic diagram of the device fabricated after the gate in this invention.

[0032] Figure 5 This is a schematic diagram of the structure of the device after the growth field plate metal of the present invention is filled with insulating medium.

[0033] Figure 6 This is a schematic diagram of the device structure after deep trench etching in the middle of the device according to the present invention.

[0034] Figure 7 This is a schematic diagram of the structure of the device after the deep groove in the middle of the device is filled with an insulating medium according to the present invention.

[0035] Figure 8 This is a schematic diagram of the structure of the device after the top of the device is filled with an insulating medium according to the present invention.

[0036] Reference numerals: 1-Base silicon, 2-First insulating dielectric layer, 3-Top silicon, 4-AlN layer, 5-GaN layer, 6-AlGaN layer, 7-Second insulating dielectric layer, 8-Source metal, 9-Drain metal, 10-Gate insulating dielectric, 11-Gate metal, 12-Field plate metal, 13-Third insulating dielectric layer, 14-Fourth insulating dielectric layer. Detailed Implementation

[0037] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0038] Example

[0039] In this embodiment, the SOI-based GaN recessed gate half-bridge integrated device is as follows: Figure 1As shown, the device includes, from bottom to top, an SOI substrate, an AlN layer 4, a GaN layer 5, an AlGaN layer 6, and a second insulating dielectric layer 7. The SOI substrate includes a base silicon 1, a first insulating dielectric layer 2, and a top silicon layer 3. The second insulating dielectric layer 7 is etched to grow a source metal 8 and a drain metal 9, wherein a deep trench is etched below the source, penetrating from the second insulating dielectric layer 7 to the AlN layer 4. The second insulating dielectric layer 7 and part of the AlGaN layer 6 in the recessed gate region are etched, and a gate insulating dielectric 10 is grown, followed by a gate metal 11 to form the gate. A field plate metal 12 is grown above the source metal 8 and the gate metal 11 and filled with a third insulating dielectric layer 13. A deep trench is provided in the middle of the half-bridge integrated device, penetrating from the third insulating dielectric layer 13 to the top silicon layer 3, and the deep trench is filled with an insulating dielectric. A fourth insulating dielectric layer 14 is filled on top of the device. The SOI-based GaN recessed gate half-bridge integrated device is obtained through top vias and interconnection processes.

[0040] The SOI-based GaN concave-gate half-bridge integrated device described above is fabricated according to the following steps:

[0041] (1) As Figure 2 As shown, using the SOI-based GaN HEMT process, an AlN layer 4, a GaN layer 5, an AlGaN layer 6, and a second insulating dielectric layer 7 are sequentially grown on an SOI substrate to obtain an SOI-based GaN HEMT device. The SOI substrate includes a base silicon 1, a first insulating dielectric layer 2, and a top silicon 3.

[0042] (2) Figure 3 As shown, the second insulating dielectric layer 7 is etched to grow the source metal 8 and the drain metal 9. A deep trench is etched below the source, penetrating the second insulating dielectric layer 7, the AlGaN layer 6, the GaN layer 5, and the AlN layer 4, and terminating at the top silicon layer 3.

[0043] (3) Figure 4 As shown, the second insulating dielectric layer 7 and part of the AlGaN layer 6 are etched in the recessed gate region, and the gate insulating dielectric 10 is grown and then the gate metal 11 is grown to form the gate.

[0044] (4) Figure 5 As shown, a field plate metal 12 is grown above the source metal 8 and the gate metal 11 and filled with a third insulating dielectric layer 13;

[0045] (5) Figure 6 As shown, a deep trench is etched in the middle of the device, penetrating the third insulating dielectric layer 13, the second insulating dielectric layer 7, the AlGaN layer 6, the GaN layer 5, the AlN layer 4, the top silicon layer 3, and terminating at the first insulating dielectric layer 2.

[0046] (6) Figure 7As shown, the deep groove in the middle of the device is filled with an insulating medium to achieve isolation between the high and low sides of the device.

[0047] (7) Figure 8 As shown, a fourth insulating dielectric layer 14 is filled on top of the device;

[0048] (8) By using top vias and interconnection processes, the source on the high side of the device is connected to the drain on the low side, and the source on the low side and the drain on the high side are led out respectively, thus obtaining the SOI-based GaN recessed gate half-bridge integrated device.

Claims

1. An SOI-based GaN concave-gate half-bridge integrated device, characterized in that, The structure includes, from bottom to top, an SOI substrate, an AlN layer (4), a GaN layer (5), an AlGaN layer (6), and a second insulating dielectric layer (7); the SOI substrate includes a base silicon (1), a first insulating dielectric layer (2), and a top silicon layer (3); the second insulating dielectric layer (7) is etched to grow source metal (8) and drain metal (9), wherein a deep trench etching is performed below the source, penetrating from the second insulating dielectric layer (7) to the AlN layer (4); the second insulating dielectric layer (7) and part of the AlGaN layer in the recessed gate region are etched. N-layer (6) is formed by growing a gate insulating dielectric (10) and then growing a gate metal (11); a field plate metal (12) is grown above the source metal (8) and the gate metal (11) and filled with a third insulating dielectric layer (13); a deep trench is provided in the middle of the half-bridge integrated device, penetrating the third insulating dielectric layer (13) to the top silicon (3), and an insulating dielectric is filled in the deep trench; a fourth insulating dielectric layer (14) is filled on the top of the device; an SOI-based GaN recessed gate half-bridge integrated device is obtained through top vias and interconnection processes.

2. The SOI-based GaN concave-gate half-bridge integrated device according to claim 1, characterized in that, The source metal (8) and drain metal (9) include one or more of W, TiN, Al, Ni, Ti, Au, Mo or Pt.

3. The SOI-based GaN concave-gate half-bridge integrated device according to claim 1, characterized in that, The gate metal (10) includes one or more of W, TiN, Al, Ni, Ti, Au, Mo or Pt.

4. The SOI-based GaN concave-gate half-bridge integrated device according to claim 1, characterized in that, The insulating medium includes one or more stacked structures selected from SiO2, Al2O3, HfO2, La2O3, ZrO2, or Si3N4.

5. A method for fabricating an SOI-based GaN concave-gate half-bridge integrated device as described in any one of claims 1-4, comprising: (1) Using SOI-based GaN HEMT technology, AlN layer (4), GaN layer (5), AlGaN layer (6) and second insulating dielectric layer (7) are grown sequentially on SOI substrate to obtain SOI-based GaN HEMT device, wherein SOI substrate includes base silicon (1), first insulating dielectric layer (2) and top silicon (3). (2) Etch the second insulating dielectric layer (7) and grow the source metal (8) and drain metal (9). Deep trench etching is performed below the source, penetrating the second insulating dielectric layer (7), AlGaN layer (6), GaN layer (5), AlN layer (4) and terminating at the top silicon layer (3). (3) Etch the second insulating dielectric layer (7) and part of the AlGaN layer (6) in the recessed gate region, grow the gate insulating dielectric (10) and then grow the gate metal (11) to form the gate; (4) A field plate metal (12) is grown over the source metal (8) and the gate metal (11) and a third insulating dielectric layer (13) is filled in; (5) Deep trench etching is performed in the middle of the device, penetrating the third insulating dielectric layer (13), the second insulating dielectric layer (7), the AlGaN layer (6), the GaN layer (5), the AlN layer (4), the top silicon layer (3), and terminating at the first insulating dielectric layer (2). (6) Fill the deep groove in the middle of the device with an insulating medium to achieve isolation between the high and low sides of the device; (7) Fill the top of the device with a fourth insulating dielectric layer (14); (8) By using top vias and interconnection processes, the source on the high side of the device is connected to the drain on the low side, and the source on the low side and the drain on the high side are led out respectively, thus obtaining the SOI-based GaN recessed gate half-bridge integrated device.

6. The method for fabricating an SOI-based GaN concave-gate half-bridge integrated device according to claim 5, characterized in that, The methods for growing the insulating medium in steps (1), (3), (4), (6), and (7) include chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation, and sputtering.

7. The method for fabricating an SOI-based GaN concave-gate half-bridge integrated device according to claim 5, characterized in that, The etching methods in steps (2), (3), and (5) include ICP or RIE, and the etching atmosphere includes one or more of SF6, CHF3, BCl3, CF4, C4F8, Cl2, or He.

8. The method for fabricating an SOI-based GaN concave-gate half-bridge integrated device according to claim 5, characterized in that, The metal growth methods in steps (2), (3), and (4) include magnetron sputtering or electron beam evaporation.

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