Semiconductor device

Abstract

A semiconductor device includes: a substrate; a plurality of transistor structures disposed on the substrate and spaced apart from each other in a first direction parallel to a surface of the substrate, each of the plurality of transistor structures including a lower active pattern and an upper active pattern spaced apart from the lower active pattern in a second direction intersecting the first direction; a gate dicing film disposed between two adjacent transistor structures of the plurality of transistor structures; and a first layer and a second layer disposed for each lower active pattern, the first layer surrounding at least a first portion of the lower active pattern, the second layer disposed on each first layer. Each of the plurality of transistor structures includes a first work function film surrounding a first portion of the lower active pattern and a second work function film surrounding at least a first portion of the upper active pattern and extending in a first direction, and a gate cutting film penetrating the second work function film and extending in a second direction. A gap is formed between the first portion of the second work function film and the second portion of the second work function film.

Description

Cross-reference to related applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0153650, filed with the Korean Intellectual Property Office on November 1, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The example embodiment relates to a semiconductor device. Background Technology

[0003] FinFETs and nanosheet field-effect transistors have been introduced as integrated circuit technologies with high-density devices and high performance. A FinFET includes a channel layer surrounded on at least three sides by a gate structure and has one or more vertical fin structures configured to extend horizontally. Regarding nanosheet field-effect transistors, for example, gate-all-around (GAA) transistors or multi-bridge channel (MBC) transistors are known, and nanosheet field-effect transistors include one or more nanosheet channel layers vertically stacked on a substrate, and a gate structure surrounding the periphery of each nanosheet channel layer.

[0004] Meanwhile, to improve device density, 3D stacked field-effect transistors (3DSFETs) have been proposed, in which lower nanosheet field-effect transistors and upper nanosheet field-effect transistors are stacked. Recently, due to the shrinking size of semiconductor devices, the size of standard cells included in integrated circuits has been continuously reduced, and for devices including cross-coupled structures, design rules generally cannot be violated to achieve smaller standard cells. Summary of the Invention

[0005] On the one hand, a semiconductor device is provided whose integration density can be increased by reducing its size, and whose electrical reliability can be improved.

[0006] The technical tasks to be achieved in this example embodiment are not limited to those described above or below, and those skilled in the art can infer other technical tasks from the following example embodiments.

[0007] According to one aspect, a semiconductor device includes: a substrate; a plurality of transistor structures disposed on the substrate and spaced apart from each other in a first direction parallel to the surface of the substrate, each of the plurality of transistor structures including a lower active pattern and an upper active pattern spaced apart from the lower active pattern in a second direction intersecting the first direction; a gate cleaving film disposed between two adjacent transistor structures of the plurality of transistor structures; a first layer and a second layer disposed for each lower active pattern, the first layer at least surrounding the lower active pattern, and the second layer disposed on each of the first layers. Each of the plurality of transistor structures includes a first work function film and a second work function film, the first work function film surrounding a first portion of the lower active pattern, the second work function film at least surrounding a first portion of the upper active pattern and extending along the first direction, and the gate cleaving film penetrating the second work function film to form a gap between the first portion and the second portion of the second work function film.

[0008] According to one aspect, a semiconductor device includes: a substrate; a plurality of transistor structures disposed on the substrate and spaced apart from each other in a first direction parallel to a surface of the substrate, each transistor structure including: a lower active pattern including a plurality of thin sheets spaced apart from each other in a second direction intersecting the first direction; an upper active pattern spaced apart from the lower active pattern in the second direction and including a plurality of thin sheets spaced apart from each other in the second direction; a separating insulating film disposed between the lower active pattern and the upper active pattern; a gate dicing film disposed between adjacent transistor structures in the plurality of transistor structures; a first layer surrounding at least a portion of each lower active pattern in the lower active pattern; and a second layer disposed on the first layer. The gate dicing film penetrates the work function film in the second direction to fill gaps in the work function film.

[0009] According to one aspect, a semiconductor device includes: a substrate; a plurality of transistor structures disposed on the substrate and spaced apart from each other in a first direction parallel to a surface of the substrate, each transistor structure including: a lower active pattern including a plurality of thin sheets spaced apart from each other in a second direction intersecting the first direction; an upper active pattern spaced apart from the lower active pattern in the second direction and including a plurality of thin sheets spaced apart from each other in the second direction; a separation insulating film disposed between the lower active pattern and the upper active pattern; a gate dicing film disposed between adjacent transistor structures in the plurality of transistor structures; a first layer surrounding at least a portion of each lower active pattern in the lower active pattern; and a second layer disposed on the first layer. The gate dicing film penetrates a second work function film in the second direction such that the second work function film has a gap therein relative to the first direction, and the length of the gate dicing film relative to the first direction decreases as the gate dicing film approaches the substrate, the gate dicing film including a bottom surface closer to the substrate than the uppermost surface of the separation insulating film, a portion of the first work function film having a gap formed therebetween between the plurality of transistor structures, and the separation insulating film contacting the second work function film.

[0010] Additional aspects of the exemplary embodiments will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of this disclosure. Attached Figure Description

[0011] These and / or other aspects, features, and advantages of the present invention will become apparent and more readily understood from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a layout diagram of a semiconductor device according to an example embodiment;

[0013] Figure 2 It is shown that, according to the example embodiment, along Figure 1 A diagram of the cross section intercepted by line I-I';

[0014] Figure 3 yes Figure 2 A magnified view of part P;

[0015] Figure 4 It is shown that, according to the example embodiment, along Figure 1 Another view of the cross section intercepted by line I-I';

[0016] Figure 5 yes Figure 4 A magnified view of part of Q;

[0017] Figure 6 yes Figure 4 A magnified view of part of R;

[0018] Figure 7 This is a diagram illustrating a first transistor structure including a common gate structure (with the dummy gate structure around the active pattern removed) and a second transistor structure including a split gate structure according to an example embodiment;

[0019] Figure 8 This is a diagram illustrating a sacrificial film formed between upper active patterns according to an exemplary embodiment;

[0020] Figure 9 This is a diagram illustrating the formation of a gate dielectric film according to an example embodiment;

[0021] Figure 10 This is a diagram illustrating a sacrificial film formed between upper active patterns according to an exemplary embodiment;

[0022] Figure 11 This is a diagram illustrating the state of forming the first work function membrane according to an example embodiment;

[0023] Figure 12 This is a diagram illustrating a method of manufacturing a semiconductor device according to a first example embodiment, and shows a state in which a mask is formed before cutting a portion of a first work function film, leaving a portion between a first transistor structure and a second transistor structure;

[0024] Figure 13 This is a diagram illustrating a method of manufacturing a semiconductor device according to a first example embodiment, and shows a state in which a portion of a first work function film disposed between a first transistor structure and a second transistor structure is cut to form a groove and a first layer comprising an insulating material is deposited.

[0025] Figure 14 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows the state after a polymer layer is formed following the removal of a first layer formed on a second transistor structure;

[0026] Figure 15 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows a state in which the portion of the first work function film formed on the second transistor structure is removed;

[0027] Figure 16 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows a state after the first layer formed on the first transistor structure has been removed following the removal of the polymer layer;

[0028] Figure 17 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows a state of re-depositing a first layer comprising an insulating material;

[0029] Figure 18 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows a state after the polymer layer is formed, in which portions of the first layer formed on the first transistor structure and the second transistor structure are removed;

[0030] Figure 19 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows the state after the polymer layer has been removed, with a second layer comprising an insulating material deposited.

[0031] Figure 20 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first exemplary embodiment, and shows the state of removing portions of the second layer formed on the first transistor structure and the second transistor structure, and removing portions of the first work function film formed on the first transistor structure;

[0032] Figure 21 This is a diagram illustrating a method of manufacturing a semiconductor device according to a first example embodiment, and shows a state in which a portion of the second layer is removed, such that the first work function film in the first transistor structure is exposed from the second layer;

[0033] Figure 22 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows the state after the sacrificial film formed between the upper active patterns is removed;

[0034] Figure 23 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows the state of forming a second work function film;

[0035] Figure 24 This is a diagram illustrating a method of manufacturing a semiconductor device according to a first example embodiment, and shows a cutting groove formed by removing a portion of a second work function film between a first transistor structure and a second transistor structure.

[0036] Figure 25 This is a diagram illustrating a method for manufacturing a semiconductor device according to a first example embodiment, and shows the state of forming a gate dicing film by filling the formed dicing grooves;

[0037] Figure 26 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows the state of depositing layer 1' comprising insulating material;

[0038] Figure 27This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows the state after the polymer layer is formed following the removal of layer 1' formed in the second transistor structure;

[0039] Figure 28 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows a state in which the portion of the first work function film formed on the second transistor structure is removed;

[0040] Figure 29 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows the state after the polymer layer has been removed, in which layer 1' formed in the first transistor structure has been removed;

[0041] Figure 30 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows a state of re-depositing a first layer comprising a conductive material;

[0042] Figure 31 This is a diagram illustrating a method of manufacturing a semiconductor device according to a second example embodiment, and shows a state in which a mask is formed before cutting a portion of a first work function film and a portion of a first layer, leaving a portion between a first transistor structure and a second transistor structure;

[0043] Figure 32 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows the state of forming a groove and forming a polymer layer by cutting a portion of the first work function film disposed between the first transistor structure and the second transistor structure;

[0044] Figure 33 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows a state in which the portion of the first layer formed on the first transistor structure and the second transistor structure is removed;

[0045] Figure 34 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows a state after a second layer comprising an insulating material has been deposited following the removal of the polymer layer;

[0046] Figure 35 This is a diagram illustrating a method of manufacturing a semiconductor device according to a second example embodiment, and shows a state in which a mask is formed while retaining a first transistor structure region, a portion of a second layer is removed such that the first layer is exposed from the second layer in the first transistor structure, and a portion of a first work function film is removed.

[0047] Figure 36This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows the state after removing the portion of the second layer formed on the second transistor structure.

[0048] Figure 37 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows the state after the sacrificial film formed between the upper active patterns has been removed;

[0049] Figure 38 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows the state in which the second work function film is formed;

[0050] Figure 39 This is a diagram illustrating a method of manufacturing a semiconductor device according to a second example embodiment, and shows a dicing groove formed by removing a portion of the second work function film located between the first transistor structure and the second transistor structure; and

[0051] Figure 40 This is a diagram illustrating a method for manufacturing a semiconductor device according to a second example embodiment, and shows the state of forming a gate dicing film by filling the formed dicing groove. Detailed Implementation

[0052] The accompanying drawings shown in this disclosure are based on exemplary embodiments only, and the ratios of the width, length, and height (or thickness) of each element are used to describe the exemplary embodiments in detail, and therefore these ratios may differ from actual embodiments. Furthermore, in the coordinate system shown in the drawings, each axis may be perpendicular to each other, and the direction in which the arrow points may be a "+" direction, while the direction opposite to the direction indicated by the arrow (rotated 180 degrees) may be a "-" direction. Unless specifically specified, describing items as extending along a direction (e.g., a first direction, a second direction, a horizontal direction, or a vertical direction) is intended to encompass both "+" and "-" directions. To indicate "+" or "-" directions, "+" or "-" symbols will be used, or terms such as positive direction or negative direction will be used.

[0053] The same reference numerals or symbols shown in each of the accompanying drawings may indicate parts or components that perform substantially the same function. For ease of description and understanding, different embodiments may be described using the same reference numerals or symbols. For example, even if components or elements with the same reference numerals are shown in multiple drawings, these multiple drawings may not all represent a single exemplary embodiment.

[0054] It will be understood that when an element is referred to as "connected" or "coupled" to another element, "adjacent" to another element, or "on" another element, the element may be directly connected or coupled to that other element, directly "adjacent" to that other element, or directly on that other element, or there may be intermediate elements present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, "directly adjacent" to another element, or "in contact" with another element (or in any form using the term "in contact"), there are no intermediate elements at the connection point, coupling point, contact point, or adjacent point.

[0055] Furthermore, in this disclosure, when an element is described as being "on the upper surface" or "on the upper part" of another element, it can be understood as existing above in the vertical direction, for example, in the accompanying drawings ( Figure 2 The two elements are above each other in the +D2 direction and may be in contact or directly connected, but it can also be understood that there is another element between them. This also applies even when one element is described in this disclosure as being "above / on top of" another element.

[0056] Furthermore, in this disclosure, when an element is described as being "on the lower part" or "on the bottom surface" of another element, it can be understood as existing below based on the vertical direction, for example, in the accompanying drawings ( Figure 2 The term is based on the -D2 direction and is further below, and these two elements can be in contact or directly connected, but it can also be understood that there is another element between them. This also applies even when one element is described as being "below / under" another element.

[0057] Other similar expressions describing the positional relationships between elements can also be interpreted in a similar manner as described above.

[0058] Items described in the singular herein may be provided in the plural, for example, as can be seen in the accompanying drawings. Therefore, unless the context otherwise requires, it should be understood that the description of a single item provided in the plural applies to the remaining numerous items. The terms “having,” “may have,” “comprising,” and “may include,” as used herein, indicate the presence of a corresponding feature (e.g., an element such as a numerical value, function, operation, or component) and do not exclude the presence of additional features. Furthermore, throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context otherwise requires. On the other hand, the term “composed of” indicates that the component is formed solely by the listed elements.

[0059] Furthermore, in the following description, terms such as upper side, upper surface, lower side, lower surface, side, front side, and back side are used based on the orientation shown in the accompanying drawings. If the orientation of the object changes, it may be described in a different way.

[0060] Ordinal numbers such as "first," "second," and "third" can be simply used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first") in a particular claim may be described elsewhere with a different ordinal number (e.g., "second") in the specification or another claim.

[0061] Terms such as “identical,” “equal,” “plane,” “coplanar,” “parallel,” and “perpendicular” as used herein encompass similarity or near-identity, including variations that may occur due to conventional manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term “substantially” may be used herein to emphasize that meaning.

[0062] Unless otherwise stated, the units of the properties described in this disclosure may be in the International System of Units (SI).

[0063] The accompanying drawings of the semiconductor device according to the example embodiments illustrate a FinFET or nanosheet field-effect transistor, but this disclosure is not limited thereto. In the example embodiments, the semiconductor device may include one or more of a tunnel FET, a 3D transistor, and a vertical FET. In the example embodiments, the semiconductor device may include a planar transistor. Furthermore, in the example embodiments, the semiconductor device may be applied to a 2D material-based transistor (a 2D material-based FET) and its heterostructure. In the example embodiments, the semiconductor device may include at least one of a bipolar junction transistor and a lateral double-diffused FET.

[0064] Furthermore, in the following description, exemplary embodiments of the technical concept according to the present invention will be described with reference to the accompanying drawings. Additionally, for the sake of brevity, existing elements, structures, or layers of the semiconductor device according to the exemplary embodiments may be described in detail, or may not be described at all. For example, descriptions of one or more source / drain regions, contact structures, isolation structures of field-effect transistors, other structures, and / or materials constituting these structures included in the semiconductor device may be omitted when they are not relevant to the novelty features of the exemplary embodiments.

[0065] Figure 1 This is an exemplary layout diagram of a semiconductor device 10 according to an example embodiment of the present disclosure. Figure 1The item shown is part of a semiconductor device 10, which may be a semiconductor chip or die formed from a wafer, and includes integrated circuits formed thereon. Figure 2 It is shown that, according to one embodiment, along Figure 1 A diagram of the cross section intercepted by line I-I'. Figure 3 yes Figure 2 A magnified view of part P. Figure 4 It illustrates the different embodiments along Figure 1 The cross section intercepted by line I-I' or with Figure 2 Another figure shows different parts of a semiconductor device 10 with a different structure. Figure 5 yes Figure 4 A magnified view of part of Q. Figure 6 yes Figure 4 A magnified view of part R.

[0066] In this disclosure, the first direction D1 can be a direction parallel to the surface 100S of the substrate. The second direction D2 can be a direction intersecting the first direction D1. The second direction D2 can also be a direction perpendicular to the surface 100S of the substrate. The third direction D3 can be a direction intersecting the first direction D1 and the second direction D2. The third direction D3 can also be a direction parallel to the surface 100S of the substrate. In an example embodiment, the first direction D1 and the second direction D2 can be perpendicular, and the second direction D2 and the third direction D3 can be perpendicular, and the first direction D1 and the third direction D3 can also be perpendicular.

[0067] In an example embodiment, the semiconductor device 10 may include a substrate 100, a plurality of transistor structures (a first transistor structure FET1 and a second transistor structure FET2), a gate dicing film CT, a first layer L1, and a second layer L2. Each transistor structure FET1 and FET2 may be a 3D stacked field-effect transistor, including, for example, two transistors vertically stacked on top of each other. Figures 2-4 The circuitry can be, for example, a set of cross-coupled transistors.

[0068] In an example embodiment, substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, substrate 100 may be a silicon substrate, or substrate 100 may include other materials, such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, substrate 100 is not limited thereto. Since in some embodiments substrate 100 may include at least one semiconductor layer, it may be a semiconductor substrate.

[0069] In an example embodiment, semiconductor device 10 may include a first active region AR1, a second active region AR2, and a field region FR. In an example embodiment, each of the first active region AR1 and the second active region AR2 may extend longitudinally along a third direction D3. An item, layer, or portion of an item or layer described as extending "longitudinally" or "along" a particular direction has a length in that particular direction and a width perpendicular to that direction, wherein the length is greater than the width. The first active region AR1 and the second active region AR2 may be spaced apart from each other in a first direction D1. In an example embodiment, the field region FR is disposed between the first active region AR1 and the second active region AR2 to separate the first active region AR1 and the second active region AR2. The field region FR may form a boundary with the first active region AR1 and the second active region AR2.

[0070] In the example embodiment, the field area FR may be defined by existing trenches, but is not limited thereto. In the example embodiment, the field area FR may have a shallow trench isolation (STI) structure, but the field area FR is not limited thereto.

[0071] In an example embodiment, a device separation film STI (not shown) may be disposed around a first active region AR1 and a second active region AR2 that are spaced apart from each other. The region in the device separation film STI between the first active region AR1 and the second active region AR2 may be a field region FR. In an example embodiment, in the semiconductor device 10, the region forming the first active pattern AP1 may be the first active region AR1, and the region forming the second active pattern AP2 may be the second active region AR2. The region separating the first active pattern AP1 and the second active pattern AP2 may be the field region FR. The first active pattern AP1 and the second active pattern AP2 may include fin structures or nanosheets, while the field region FR may be a region that does not include fin structures or nanosheets.

[0072] In an example embodiment, the first active pattern AP1 may include a first lower active pattern AP1_BT and a first upper active pattern AP1_UT spaced apart from the first lower active pattern AP1_BT in the second direction D2. In an example embodiment, the second active pattern AP2 may include a second lower active pattern AP2_BT and a second upper active pattern AP2_UT spaced apart from the second lower active pattern AP2_BT in the second direction D2. In this disclosure, the first lower active pattern AP1_BT and the second lower active pattern AP2_BT may be lower active patterns, and the first upper active pattern AP1_UT and the second upper active pattern AP2_UT may be upper active patterns.

[0073] In an example embodiment, each of the lower active pattern (e.g., the first lower active pattern AP1_BT and the second lower active pattern AP2_BT) and the upper active pattern (e.g., the first upper active pattern AP1_UT and the second upper active pattern AP2_UT) may independently include one or more sheets. In an example embodiment, each of the lower active pattern (e.g., the first lower active pattern AP1_BT and the second lower active pattern AP2_BT) and the upper active pattern (e.g., the first upper active pattern AP1_UT and the second upper active pattern AP2_UT) may include multiple sheets. Here, the multiple sheets may be spaced apart from each other, and for example, the multiple sheets may be spaced apart from each other in a second direction D2. Furthermore, the sheets may extend along a third direction D3, for example, longitudinally. The accompanying drawings illustrate that each of the lower active patterns (e.g., the first lower active pattern AP1_BT and the second lower active pattern AP2_BT) and the upper active patterns (e.g., the first upper active pattern AP1_UT and the second upper active pattern AP2_UT) comprises three sheets, but the illustration is for illustrative purposes only and the present disclosure is not limited thereto.

[0074] In an example embodiment, each of the lower active pattern (e.g., the first lower active pattern AP1_BT and the second lower active pattern AP2_BT) and the upper active pattern (e.g., the first upper active pattern AP1_UT and the second upper active pattern AP2_UT) may independently include a p-channel metal-oxide-semiconductor (PMOS) or an n-channel metal-oxide-semiconductor (NMOS). For example, the lower active pattern (the first lower active pattern AP1_BT and the second lower active pattern AP2_BT) may include a PMOS, and the upper active pattern (the first upper active pattern AP1_UT and the second upper active pattern AP2_UT) may include an NMOS. For example, the thin film forming the first lower active pattern AP1_BT can be the active region of a first PMOS transistor, the thin film forming the first upper active pattern AP1_UT can be the active region of a first NMOS transistor, the thin film forming the second lower active pattern AP2_BT can be the active region of a second PMOS transistor, and the thin film forming the second upper active pattern AP2_UT can be the active region of a second NMOS transistor. For example, Figure 2 The four transistors shown can be connected in a cross-coupled manner (not fully shown). However, the types of transistors and the ways in which they are connected are not limited to these examples.

[0075] In an example embodiment, each of the lower active pattern (first lower active pattern AP1_BT and second lower active pattern AP2_BT) and the upper active pattern (first upper active pattern AP1_UT and second upper active pattern AP2_UT) may independently include at least one of silicon (Si) and germanium (Ge). In another example embodiment, each of the lower active pattern (first lower active pattern AP1_BT and second lower active pattern AP2_BT) and the upper active pattern (first upper active pattern AP1_UT and second upper active pattern AP2_UT) may independently include a compound semiconductor. In this disclosure, the compound semiconductor may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. More specifically, the compound semiconductor may include a binary or ternary compound of a group IV element comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). In example, the III-V compound semiconductor may be a binary, ternary, or quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with at least one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements.

[0076] In an example embodiment, the semiconductor device 10 may include a plurality of gate lines PC, each gate line PC being configured to extend along a first direction D1. Each gate line PC may be electrically connected to a first active pattern AP1 and a second active pattern AP2. At least some of the gate lines PC may be cut relative to the first direction D1, which is the direction of extension. When viewed from a second direction D2, the cut area of ​​the gate line PC may overlap with the field region FR. When the gate line PC is cut, it may include two gate line portions, each of which can be independently considered as a gate line.

[0077] In an example embodiment, the semiconductor device 10 may include multiple gate lines PC. In an example embodiment, there may be three or fewer gate lines PC, or two or fewer, and preferably, two gate lines PC may be present in a standard cell. The multiple gate lines PC may be spaced apart from each other on a third-direction D3. In an example embodiment, the gate lines PC may include a first work function film WFM1 and a second work function film WFM2.

[0078] In an example embodiment, the gate line PC may include a conductive material. In this disclosure, the conductive material may have a density greater than 10. 6The conductivity is measured in S / m. For example, conductive materials can include at least one of metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, and conductive metal oxides. For example, conductive materials can include those selected from titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (TaCN). The material comprises at least one of the following groups: tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), and vanadium (V). However, this disclosure is not limited thereto. Conductive metal oxides and conductive metal nitrides may include the oxidized forms of the above-mentioned substances, but this disclosure is not limited thereto.

[0079] In the example embodiment, the gate line PC may include not only the first work function film WFM1 and the second work function film WFM2, but also the gate dielectric film 130 and the gate capping film GP. The conductive portion or gate line portion of each gate line PC may be a gate electrode, which is used to transmit signals or power.

[0080] In an example embodiment, some of the gate line portions of the gate line PC, including the diced regions, may be electrically connected to the first active pattern AP1, while others may be electrically connected to the second active pattern AP2. In an example embodiment, the gate line PC may surround the first active pattern AP1. Furthermore, the gate line PC may surround the second active pattern AP2.

[0081] In an example embodiment, the semiconductor device 10 may include a plurality of transistor structures (a first transistor structure FET1 and a second transistor structure FET2) disposed on a substrate 100. Each transistor structure may be a transistor stack (e.g., a stack of transistors stacked vertically on top of each other). That is, the plurality of transistor structures may be a transistor stack. The plurality of transistor structures (the first transistor structure FET1 and the second transistor structure FET2) may be configured to be spaced apart from each other in a first direction D1. Each of the plurality of transistor structures (the first transistor structure FET1 and the second transistor structure FET2) may include a lower active pattern (a first lower active pattern AP1_BT or a second lower active pattern AP2_BT, each lower active pattern forming the active pattern of a corresponding transistor) and an upper active pattern (a first upper active pattern AP1_UT or a second upper active pattern AP2_UT, each upper active pattern forming the active pattern of a corresponding transistor).

[0082] In one example embodiment, the semiconductor device 10 may include a fin pattern 101 disposed on or on a substrate 100. The fin pattern 101 may be formed in each of a first active region AR1 and a second active region AR2. The fin pattern 101 may protrude from the substrate 100 and extend longitudinally in a third direction D3. For example, the fin pattern 101 may be formed by etching a portion of the substrate 100 as part of the substrate 100. Furthermore, for example, the fin pattern 101 may include an epitaxial layer grown from the substrate 100. The fin pattern 101 may include two or more elemental semiconductor materials, such as silicon and germanium. In another example embodiment, the fin pattern 101 may include a compound semiconductor. The fin pattern 101 may be a fin, or it may be a fin-shaped pattern.

[0083] In an example embodiment, each fin pattern 101 may be provided with a lower active pattern (e.g., a first lower active pattern AP1_BT or a second lower active pattern AP2_BT) and an upper active pattern (e.g., a first upper active pattern AP1_UT or a second upper active pattern AP2_UT) included in a plurality of transistor structures (a first transistor structure FET1 and a second transistor structure FET2).

[0084] In an example embodiment, the semiconductor device 10 may include a field insulating film 105 disposed in the field region FR. The field insulating film 105 may be disposed on a substrate 100. For example, the field insulating film 105 may be disposed on a region of the substrate 100 that does not overlap with the first active pattern AP1 and the second active pattern AP2 when viewed from the second direction D2. In an example embodiment, the field insulating film 105 may cover the sidewalls of the fin pattern 101. The field insulating film 105 may be configured such that its upper surface is substantially at the same level as the upper surface of the fin pattern 101 relative to the second direction D2. Contrary to the illustration, in another example embodiment, the field insulating film 105 may only cover a portion of the sidewalls of the fin pattern 101. In this case, a portion of the sidewalls of the fin pattern 101 may protrude further than the field insulating film 105 in the second direction D2. In an example embodiment, the field insulating film 105 may be a single-layer film, and in another example embodiment, the field insulating film 105 may be a multilayer film.

[0085] In an example embodiment, the field insulating film 105 may include an insulating material. In this disclosure, the insulating material may have 10 -6 Conductivity of S / m or lower. There are no specific limitations on conductivity in this disclosure, but it can be measured, for example, by ASTM E1004. In exemplary embodiments, the insulating material may include at least one selected from the group consisting of silicon oxide, silicon germanium oxide, germanium oxide, silicon oxynitride, silicon nitride, high-k materials with a dielectric constant greater than that of silicon oxide, and low-k materials with a dielectric constant lower than that of silicon oxide. For example, high-k materials may include one or more selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, high-k materials are not limited thereto. For example, low-k materials may include one or more of the following groups: tetraethyl orthosilicate fluoride (FTEOS), hydrosiloxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonil silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoams (such as polypropylene oxide), carbon-doped silica (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, and mesoporous silica. However, low-k materials are not limited to this.

[0086] In an example embodiment, the gate dielectric film 130 may be configured to extend along the upper surface of the field insulating film 105 and the upper surface of the fin pattern 101. The gate dielectric film 130 may wrap around (e.g., in cross-sectional view, surround) the first active pattern AP1 and the second active pattern AP2. The gate dielectric film 130 may be disposed along the periphery of the sheets included in the first active pattern AP1 and the second active pattern AP2. The gate dielectric film 130 may include an insulating material and may include at least one selected from the group consisting of silicon oxide, germanium silicon oxide, germanium oxide, silicon oxynitride, silicon nitride, and high-k materials. In an example embodiment, the gate dielectric film 130 may be a single-layer film, or in another example embodiment, the gate dielectric film 130 may be a multilayer film.

[0087] In an example embodiment, a portion of the gate dielectric film 130 may be disposed between the sheets included in the first active pattern AP1, between the sheets included in the second active pattern AP2, between the first active pattern AP1 and the fin pattern 101, and between the second active pattern AP2 and the fin pattern 101.

[0088] In an example embodiment, the gate dicing film CT can be disposed between multiple transistor structures (e.g., between two transistor structures such as a first transistor structure FET1 and a second transistor structure FET2). For example, the gate dicing film CT can be disposed between the first transistor structure FET1 and the second transistor structure FET2. In an example embodiment, the gate dicing film CT can have a length in a first direction D1 that gradually decreases as the gate dicing film CT approaches the substrate 100. The gate dicing film CT can include an insulating material. The gate dicing film CT can only be directly disposed between the first upper active pattern AP1_UT and the second upper active pattern AP2_UT (e.g., at the same vertical level), and not directly disposed between the first lower active pattern AP1_BT and the second lower active pattern AP2_BT.

[0089] In an example embodiment, each of the plurality of transistor structures (first transistor structure FET1 and second transistor structure FET2) may include a first work function film WFM1 surrounding at least a portion of a lower active pattern (first lower active pattern AP1_BT and second lower active pattern AP2_BT). Each of the plurality of transistor structures (first transistor structure FET1 and second transistor structure FET2) may include a second work function film WFM2 surrounding at least a portion of an upper active pattern (first upper active pattern AP1_UT and second upper active pattern AP2_UT). The second work function film WFM2 may extend longitudinally along a first direction D1.

[0090] In an example embodiment, each of the first work function film WFM1 and the second work function film WFM2 may independently include a work function metal, which includes at least one selected from the group consisting of titanium (Ti), aluminum (Al), tantalum (Ta), tungsten (W), molybdenum (Mo), copper (Cu), cobalt (Co), palladium (Pd), and platinum (Pt). Therefore, the first work function film WFM1 and the second work function film WFM2 may be formed from the same material or from different materials among those described above. The first work function film WFM1 and the second work function film WFM2 may include at least one of a work function metal nitride and a work function metal carbide.

[0091] In the example embodiment, each of the first work function film WFM1 and the second work function film WFM2 can be composed of NMOS or PMOS. For example, the first work function film WFM1 can form part of the PMOS portion of the semiconductor device 10, and the second work function film WFM2 can form part of the NMOS portion of the semiconductor device 10. Furthermore, in an alternative example embodiment, for example, the first work function film WFM1 can form part of the NMOS portion of the semiconductor device 10, and the second work function film WFM2 can form part of the PMOS portion of the semiconductor device 10. In the example embodiment, the first work function film WFM1 and the second work function film WFM2 can be single-layer films, as shown in the figures, although in other embodiments, the first work function film WFM1 and the second work function film WFM2 can be multilayer films.

[0092] In an example embodiment, a portion of the first work function film WFM1 can be cut between multiple transistor structures (first transistor structure FET1 and second transistor structure FET2). For example, the first work function film WFM1 disposed between the first transistor structure FET1 and the second transistor structure FET2 can be cut along a second direction D2, such that a gap is formed in the first work function film WFM1 in the first direction D1 between the portion connected to the first transistor structure FET1 and the portion connected to the second transistor FET2. By cutting the first work function film WFM1, which serves as the lower gate, along the second direction D2, the semiconductor device 10 can have a structure in which the lower gate is isolated between the first transistor structure FET1 and the second transistor structure FET2.

[0093] In an example embodiment, the first layer L1 may surround at least a portion of the lower active patterns (first lower active pattern AP1_BT and second lower active pattern AP2_BT). For example, the first layer L1 may surround at least a portion of each of the first lower active pattern AP1_BT and the second lower active pattern AP2_BT.

[0094] In an example embodiment, at least a portion of the first layer L1 may be disposed on the first work function membrane WFM1. The first layer L1 may contact the first work function membrane WFM1. The first layer L1 may be spaced apart from the second work function membrane WFM2 in the second direction D2.

[0095] In an example embodiment, a second layer L2 may be disposed on top of a first layer L1. The second layer L2 may include an insulating material. For example, the second layer L2 may include silicon nitride.

[0096] In an example embodiment, the second layer L2 may contact a portion of the second work function film WFM2. The second layer L2 may contact a portion of the first work function film WFM1. The second layer L2 may contact the bottom surface CT_BS of the gate dicing film. The second layer L2 may be configured to extend along a first direction D1. The semiconductor device 10 may have the following structure: the upper portion of the plurality of transistor structures (first transistor structure FET1 and second transistor structure FET2), including the upper active pattern (first upper active pattern AP1_UT and second upper active pattern AP2_UT), is isolated from the lower portion of the plurality of transistor structures (first transistor structure FET1 and second transistor structure FET2), including the lower active pattern (first lower active pattern AP1_BT and second lower active pattern AP2_BT), through the second layer L2.

[0097] In an example embodiment, the gate dicing film CT can penetrate the second work function film WFM2, such that the second work function film WFM2 is diced along the second direction D2. For example, the gate dicing film CT can penetrate the entire second work function film WFM2. The second work function film WFM2, which serves as the upper gate, can be diced and disposed by the gate dicing film CT along the second direction D2. By dicing the second work function film WFM2 using the gate dicing film CT, the semiconductor device 10 can have a structure in which the upper gate is isolated between the first transistor structure FET1 and the second transistor structure FET2.

[0098] In an example embodiment, at least in the region of the first transistor structure FET1, the bottom surface CT_BS (e.g., the bottommost surface) of the gate cleaving film may be closer to the substrate 100 than the top surface 115_US (e.g., the topmost surface) of the separation insulating film.

[0099] In an example embodiment, the semiconductor device 10 may include a separating insulating film 115 disposed between a lower active pattern (a first lower active pattern AP1_BT and a second lower active pattern AP2_BT) and an upper active pattern (a first upper active pattern AP1_UT and a second upper active pattern AP2_UT). The separating insulating film 115 may include an insulating material. The separating insulating film 115 may be in contact with a second work function film WFM2. Each transistor structure (e.g., a first transistor structure FET1 and a second transistor structure FET2) may include a separating insulating film 115 separating its upper and lower portions.

[0100] In exemplary embodiments, at least some of the transistor structures (first transistor structure FET1 and second transistor structure FET2) may include a common gate structure. For example, in some embodiments, the transistor structure including the common gate structure may be the first transistor structure FET1. In this specification, the first transistor structure FET1 may be referred to as the common gate transistor structure. In exemplary embodiments, the common gate structure may include, and be formed, a region where the first work function film WFM1 and the second work function film WFM2 are in contact with each other. In another exemplary embodiment, the common gate structure may include the first work function film WFM1 and the second work function film WFM2, for example, the first work function film WFM1 and the second work function film WFM2 are electrically connected based on the contact region where they are in contact with each other.

[0101] In example embodiments, at least some of the transistor structures (first transistor structure FET1 and second transistor structure FET2) may include a split-gate structure. For example, in some embodiments, the transistor structure including the split-gate structure may be the second transistor structure FET2. In this specification, the second transistor structure FET2 may be referred to as a split-gate transistor structure. In example embodiments, the split-gate structure may include a first work function film WFM1 and a second work function film WFM2 that are electrically separated (e.g., isolated) from each other. For example, the split-gate structure may include a first work function film WFM1 and a second work function film WFM2 that are electrically separated and physically separated along a second direction D2, thereby being electrically isolated from each other. In example embodiments, in the split-gate structure, the upper surface WFM1_US (e.g., the uppermost surface) of the first work function film is closer to the substrate 100 than the bottom surface WFM2_BS (e.g., the bottommost surface) of the second work function film is closer to the substrate 100.

[0102] In an example embodiment, the semiconductor device 10 includes a plurality of transistor structures, wherein at least some of the plurality of transistor structures may be a first transistor structure FET1. Furthermore, the semiconductor device 10 may include a plurality of transistor structures, wherein at least some of the plurality of transistor structures may be a second transistor structure FET2. In an example embodiment, the semiconductor device 10 may include, for example, a first transistor structure FET1 and a second transistor structure FET2 arranged in a repeating pattern.

[0103] The accompanying drawings illustrate a first transistor structure FET1 including a first lower active pattern AP1_BT and a first upper active pattern AP1_UT, and a second transistor structure FET2 including a second lower active pattern AP2_BT and a second upper active pattern AP2_UT. However, this illustration is for illustrative purposes only. The first active pattern AP1 includes a first lower active pattern AP1_BT and a first upper active pattern AP1_UT, and the second active pattern AP2 includes a second lower active pattern AP2_BT and a second upper active pattern AP2_UT. An example embodiment of a semiconductor device 10 including a first transistor structure FET1 and a second transistor structure FET2 is described based on the accompanying drawings. However, in some embodiments, the multiple transistor structures included in the semiconductor device 10 may all be first transistor structures FET1, or all may be second transistor structures FET2, wherein the included transistor structures are separated by a gate dicing film. In these examples, it is still possible to use... Figure 2 The structure, except that the height of the first work function metal WFM1 can be the same for all transistors (for example, in the case of the first transistor structure FET1, it extends into the second work function metal WFM2, or in the case of the second transistor structure FET2, a gap is formed between the first work function metal WFM1 and the second work function metal WFM2).

[0104] In an example embodiment, the first transistor structure FET1 may include a separating insulating film 115 located between a lower active pattern AP1_BT (e.g., a first lower active pattern AP1_BT) and an upper active pattern AP1_UT (e.g., a first upper active pattern AP1_UT). In an example embodiment, the second transistor structure FET2 may include a separating insulating film 115 located between a lower active pattern AP2_BT (e.g., a second lower active pattern AP2_BT) and an upper active pattern AP2_UT (e.g., a second upper active pattern AP2_UT). The separating insulating film 115 included in the first transistor structure FET1 and the separating insulating film 115 included in the second transistor structure FET2 may be separable from each other. For example, the separating insulating film 115 included in the first transistor structure FET1 and the separating insulating film 115 included in the second transistor structure FET2 may be separable from each other with respect to a first direction D1. For example, each separating insulating film 115 may be formed of a specific material, and different insulating materials (e.g., the material forming the second layer L2) may be formed therebetween.

[0105] In an example embodiment, in the first transistor structure FET1, the surface area of ​​the region where the second work function film WFM2 and the second layer L2 are in contact (e.g., the entire contact area where the second work function film WFM2 and the second layer L2 are in contact with each other) can be greater than the surface area of ​​the region where the first work function film WFM1 and the second work function film WFM2 are in contact (e.g., the entire contact area where the first work function film WFM1 and the second work function film WFM2 are in contact with each other).

[0106] In an example embodiment, in the first transistor structure FET1, in the second direction D2, the bottom surface WFM2_BS (e.g., the bottommost surface) of the second work function film may be closer to the substrate 100 than the top surface WFM1_US (e.g., the topmost surface) of the first work function film is closer to the substrate 100.

[0107] In an example embodiment, in the second transistor structure FET2, the length T1 between the upper surface WFM1_US of the first work function film and the bottom surface WFM2_BS of the second work function film in the second direction D2 can be less than 5.8 nm, less than or equal to 5.6 nm, or less than or equal to 5.5 nm, and can be greater than 0, such as greater than 1 nm.

[0108] In an example embodiment, in the second transistor structure FET2, along the second direction D2, the ratio (T1 / T2) of the length T1 between the upper surface WFM1_US of the first work function film and the bottom surface WFM2_BS of the second work function film to the length T2 of the separating insulating film 115 can be less than or equal to 0.5, less than or equal to 0.45, less than or equal to 0.4, less than or equal to 0.35, less than or equal to 0.3, less than or equal to 0.25, or less than or equal to 0.2. For example, the ratio T1 / T2 can be 0.2 or greater, and can be 0.5 or less.

[0109] Reference Figure 2 and Figure 3 In the example embodiment, each of the first layer L1 and the second layer L2 can independently include insulating material. Here, a portion of the first layer L1 can be continuously disposed along a first direction D1 between multiple transistor structures (first transistor structure FET1 and second transistor structure FET2). This can reduce the difficulty of the manufacturing process.

[0110] In an example embodiment, the first layer L1 may include an insulating material, and in the first transistor structure FET1, the upper surface L1_US (e.g., the uppermost surface) of the first layer may be closer to the substrate 100 than the bottom surface WFM2_BS (e.g., the bottommost surface) of the second work function film is closer to the substrate 100.

[0111] In an example embodiment, the first layer L1 may include an insulating material, the semiconductor device 10 may include a first transistor structure FET1 and a second transistor structure FET2, and the thickness (e.g., maximum thickness) of the second work function film WFM2 of the first transistor structure FET1 in the second direction D2 may be substantially the same as the thickness (e.g., maximum thickness) of the second work function film WFM2 of the second transistor structure FET2 in the second direction D2.

[0112] Reference Figures 4 to 6 In an example embodiment, the first layer L1 may include a conductive material, and the second layer L2 may include an insulating material. Here, a portion of the first layer L1 may be cut along the second direction D2 between the plurality of transistor structures (first transistor structure FET1 and second transistor structure FET2). In the example embodiment, as the contact area between the second layer L2 and the second work function film WFM2 increases, the contact resistance may increase, and by including a conductive material in the first layer L1, the increase in contact resistance can be minimized. Furthermore, by cutting the first layer L1, which includes conductive material, between the plurality of transistor structures (first transistor structure FET1 and second transistor structure FET2) along the second direction D2, a structure in which the lower gate is isolated between the first transistor structure FET1 and the second transistor structure FET2 can be formed.

[0113] In an example embodiment, the first layer L1 may include a conductive material, and in the first transistor structure FET1, the bottom surface WFM2_BS of the second work function film may be closer to the substrate 100 than the top surface L1_US of the first layer is closer to the substrate 100.

[0114] In an example embodiment, the first layer L1 may include a conductive material, the semiconductor device 10 may include a first transistor structure FET1 and a second transistor structure FET2, and the thickness (e.g., maximum thickness) of the second work function film WFM2 of the first transistor structure FET1 in the second direction D2 may be greater than the thickness (e.g., maximum thickness) of the second work function film WFM2 of the second transistor structure FET2 in the second direction D2.

[0115] In an example embodiment, the first layer L1 may include a conductive material, and in the first transistor structure FET1, the first work function film WFM1 may include a recessed portion WMF1_G at the interface with the second work function film WFM2, for example, as shown. Figure 6 As shown.

[0116] In an example embodiment, the semiconductor device 10 may include multiple wirings WL. The wirings WL may include power lines supplying power to the semiconductor device 10 and signal lines transmitting electrical signals. In an example embodiment, the wirings WL may each have a single-layer structure, but as shown in the figure, the wirings WL may have a multi-layer structure including a wiring filler film WL_f and a wiring barrier film WL_b. In an example embodiment, the wiring filler film WL_f may include one selected from the group consisting of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo). In an example embodiment, the wiring barrier film WL_b may include at least one selected from the group consisting of tantalum (Ta) and tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), nickel boride (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and 2D materials. In this disclosure, the 2D material may be a metallic material and / or a semiconductor material. The 2D material may include 2D allotropes or 2D compounds. For example, the 2D material may include at least one selected from graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), but the 2D material is not limited thereto. In other words, the 2D materials described above are listed only as examples, and therefore, the 2D materials that may be included in the semiconductor device 10 of this disclosure are not limited to the materials described above.

[0117] In an example embodiment, the semiconductor device 10 may include a gate contact CB. The gate contact CB may be electrically connected to a wiring WL, and the second work function film WFM2 may be electrically connected to the wiring WL. In an example embodiment, each gate contact CB may have a single-layer structure, but as shown, the gate contact CB may have a multilayer structure including a gate contact filling film CB_f and a gate contact blocking film CB_b. In an example embodiment, the materials included in the gate contact filling film CB_f can be referenced to the materials included in the aforementioned wiring filling film WL_f. In an example embodiment, the materials included in the gate contact blocking film CB_b can be referenced to the materials included in the aforementioned wiring blocking film WL_b.

[0118] In an example embodiment, a portion of the gate contact CB may be disposed within the gate capping film GP. The gate capping film GP may be disposed on the first active pattern AP1 and the second active pattern AP2. The gate contact CB may be configured to penetrate the gate capping film GP in the second direction D2. The gate capping film GP may be disposed on the second work function film WFM2. In an example embodiment, the gate capping film GP may include an insulating material.

[0119] In an example embodiment, the semiconductor device 10 may include an insulating film ILD1 disposed between layers on a gate capping film GP. A portion of a gate contact CB may be disposed between portions of the insulating film ILD1. The gate contact CB may be configured to penetrate at least a portion of the insulating film ILD1 in a second direction D2. The insulating film ILD1 may include an insulating material. For example, the insulating film ILD1 may include at least one selected from the group consisting of silicon oxide, germanium silicon oxide, germanium oxide, silicon oxynitride, silicon nitride, and low-k materials. The insulating film ILD1 may be formed from a plurality of sequentially deposited layers such that the gate contact CB penetrates through these sequential layers.

[0120] In an example embodiment, the semiconductor device 10 may have a first etch stop film ES1 disposed between the insulating film ILD1 and the gate capping film GP. The first etch stop film ES1 may include at least one selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon carbonitride (SiOC). The gate contact CB may be configured to penetrate the first etch stop film ES1 in a second direction D2.

[0121] In an example embodiment, the semiconductor device 10 may include an insulating film ILD2 disposed between layers on an insulating film ILD1. At least a portion of a wiring WL may be disposed in the insulating film ILD2. The insulating film ILD2 may be formed from a plurality of sequentially deposited layers such that a portion of the wiring WL passes through these sequential layers. The wiring WL may be configured to pass through at least a portion of the insulating film ILD2 in a second direction D2. The insulating film ILD2 may include an insulating material. For example, the insulating film ILD2 may include at least one selected from the group consisting of silicon oxide, germanium silicon oxide, germanium oxide, silicon oxynitride, silicon nitride, and low-k materials.

[0122] In an example embodiment, the semiconductor device 10 may include a second etch stop film ES2 disposed between insulating films ILD2 and ILD1. The second etch stop film ES2 may include at least one selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), and silicon carbonitride (SiOC). Wiring WL may be configured to penetrate the second etch stop film ES2 in a second direction D2.

[0123] In the example embodiment, any known method for manufacturing the semiconductor device 10 can be applied, provided it does not conflict with the method described below. The following will primarily describe the method for ensuring the structural features of the semiconductor device 10 described above.

[0124] Figures 7 to 11 These are methods for illustrating the manufacture of a semiconductor device 10 according to a first and second example embodiment of the present disclosure. Figures 12 to 25 This is used to illustrate some manufacturing methods of a semiconductor device 10 according to a first exemplary embodiment of the present disclosure. Figures 26 to 40 This is to illustrate some methods for manufacturing a semiconductor device 10 according to a second exemplary embodiment of the present disclosure. Hereinafter, an exemplary embodiment of manufacturing a semiconductor device 10 including both a first transistor structure FET1 and a second transistor structure FET2 will be described. However, even if the semiconductor device 10 includes only the first transistor structure FET1 or only the second transistor structure FET2, those skilled in the art to which this disclosure pertains can easily implement the semiconductor device 10 by referring to the following description.

[0125] In this disclosure, although there are no particular limitations on the films or layers, specific films or layers can be formed by deposition in exemplary embodiments. Deposition can be performed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). If other methods besides depositing specific films or layers are available in the art, those methods can be applied. Furthermore, in this disclosure, although there are no particular limitations, in exemplary embodiments, certain films or layers can be removed by etching. For example, etching can be performed by dry etching or wet etching using phosphoric acid.

[0126] Figure 7 A method for manufacturing a semiconductor device 10 according to an example embodiment is shown. The semiconductor device includes a first transistor structure FET1 including a common gate structure and a second transistor structure FET2 including a split gate structure, wherein a dummy gate structure surrounding an active pattern (first active pattern AP1 and second active pattern AP2) is removed.

[0127] Reference Figure 8 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a sacrificial film SCL between upper active patterns (a first upper active pattern AP1_UT and a second upper active pattern AP2_UT) while removing a dummy gate structure surrounding the active patterns (a first active pattern AP1 and a second active pattern AP2). The sacrificial film SCL formed between the upper active patterns (a first upper active pattern AP1_UT and a second upper active pattern AP2_UT) may include lanthanum oxide (LaO), but the sacrificial film SCL is not limited thereto. Here, a gap may exist between the lower active patterns (a first lower active pattern AP1_BT and a second lower active pattern AP2_BT). Although not shown, in order to form the lower active patterns (a first lower active pattern AP1_BT and a second lower active pattern AP2_BT), a sacrificial film is formed between them, and when the sacrificial film is removed, a void space may be formed. In this case, the sacrificial film may include, but is not limited to, aluminum oxide (AlO).

[0128] Reference Figure 9 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a gate dielectric film 130. The gate dielectric film 130 may include an insulating material. The gate dielectric film 130 may be configured to extend along the upper surface of the field insulating film 105 and the upper surface of the fin pattern 101, and may be configured to surround a first active pattern AP1 and a second active pattern AP2.

[0129] Reference Figure 10In an example embodiment, a method for manufacturing a semiconductor device 10 may include: after forming a gate dielectric film 130, forming a sacrificial film SCL between upper active patterns (a first upper active pattern AP1_UT and a second upper active pattern AP2_UT). For further explanation, please refer to the reference [reference needed]. Figure 8 The description.

[0130] In the following text, for ease of explanation, a description of... Figures 11 to 40 The example embodiment is omitted, and the description of the gate dielectric film 130 is omitted, but it will be obvious to those skilled in the art that, referring to Figure 9 and Figure 10 The semiconductor device 10 may include a gate dielectric film 130. (See reference...) Figure 11 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a first work function film WFM1. The first work function film WFM1 is formed by integral deposition and may fill the gap formed between the underlying active patterns (a first underlying active pattern AP1_BT and a second underlying active pattern AP2_BT).

[0131] Reference Figure 12 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: forming a mask MK to leave some space between a first transistor structure FET1 and a second transistor structure FET2; and removing a first work function film WFM1 in a region where the mask MK is not formed.

[0132] Reference Figure 13 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a recess RE by cutting a portion of a first work function film WFM1 disposed between a first transistor structure FET1 and a second transistor structure FET2. For example, the method for manufacturing the semiconductor device 10 may include forming the recess RE by removing the first work function film WFM1 from a region where a mask MK is not formed. In an example embodiment, the method for manufacturing the semiconductor device 10 may include depositing a first layer L1 comprising an insulating material. In some embodiments, the first layer L1 may be formed to have a thickness that does not completely fill the recess RE.

[0133] Reference Figure 14In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing a first layer L1 formed in a second transistor structure FET2. In an example embodiment, a method for manufacturing the semiconductor device 10 may include forming a polymer layer PYL. For example, the polymer layer PYL may include a polymer-based material for a bottom anti-reflective coating (BARC). However, even if the polymer layer PYL is not a polymer, it may include a spin-on hard mask (SOH) material, such as silicon oxide.

[0134] Reference Figure 15 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: removing a portion of a first work function film WFM1 formed on a second transistor structure FET2.

[0135] Reference Figure 16 In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing the polymer layer PYL. In another example embodiment, a method for manufacturing a semiconductor device 10 may include removing a first layer L1 formed in a first transistor structure FET1.

[0136] Reference Figure 17 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: redepositing a first layer L1 comprising an insulating material. In one embodiment, the first layer L1 may be formed with a thickness that does not completely fill a recess RE. In another embodiment, the first layer L1 may be deposited in a recess such that its top surface is lower than the top surface of the first layer L1 immediately adjacent to the recess and outside the recess.

[0137] Reference Figure 18 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a polymer layer PYL. In another example embodiment, a method for manufacturing a semiconductor device 10 may include removing portions of the first layer L1 formed on the first transistor structure FET1 and the second transistor structure FET2.

[0138] Reference Figure 19 In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing the polymer layer PYL. In an example embodiment, a method for manufacturing a semiconductor device 10 may include depositing a second layer L2 comprising an insulating material. In an example embodiment, the second layer L2 may be deposited to fill the recess RE while providing isolation between the upper active pattern (a first upper active pattern AP1_UT and a second upper active pattern AP2_UT) and the lower active pattern (a first lower active pattern AP1_BT and a second lower active pattern AP2_BT).

[0139] Reference Figure 20 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: removing a portion of a second layer L2 formed on a first transistor structure FET1 and a second transistor structure FET2. The second layer L2 formed on the upper portion of the first transistor structure FET1 and the second transistor structure FET2 may be removed. In an example embodiment, a method for manufacturing a semiconductor device 10 may include: removing a portion of a first work function film WFM1 formed on the first transistor structure FET1. Therefore, the first work function film WFM1 formed on the upper side of the first transistor structure FET1 may be removed.

[0140] Reference Figure 21 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: removing a portion of a second layer L2 to expose a first work function film WFM1 from the second layer L2 in a first transistor structure FET1.

[0141] Reference Figure 22 In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing the sacrificial film SCL formed between upper active patterns (a first upper active pattern AP1_UT and a second upper active pattern AP2_UT).

[0142] Reference Figure 23 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a second work function film WFM2 on a second layer L2.

[0143] Reference Figure 24 and Figure 25 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a dicing groove CT_RE by removing a portion of a second work function film WFM2 disposed between a first transistor structure FET1 and a second transistor structure FET2. The dicing groove CT_RE may include removing the second work function film WFM2 along a second direction D2. Here, as the second work function film WFM2 is removed, the length of the dicing groove CT_RE in the first direction D1 may gradually decrease as it approaches the substrate 100. In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a gate dicing film CT by filling the formed dicing groove CT_RE with an insulating material.

[0144] Regarding the following text Figures 26 to 40 If the descriptions are consistent, you can refer to them. Figures 12 to 25 The description.

[0145] Reference Figure 26In an example embodiment, a method for manufacturing a semiconductor device 10 may include: depositing a layer L1' comprising an insulating material. For example, layer L1' may include materials that are bonded to the substrate. Figure 13 The first layer L1 deposited in the description is the same material as the first layer L1.

[0146] Reference Figure 27 In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing layer L1' formed in a second transistor structure FET2. In another example embodiment, a method for manufacturing a semiconductor device 10 may include forming a polymer layer PYL.

[0147] Reference Figure 28 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: removing a portion of a first work function film WFM1 formed on a second transistor structure FET2.

[0148] Reference Figure 29 In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing the polymer layer PYL. In another example embodiment, a method for manufacturing a semiconductor device 10 may include removing layer L1' formed in a first transistor structure FET1.

[0149] Reference Figure 30 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: depositing a first layer L1 comprising a conductive material.

[0150] Reference Figure 31 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: forming a mask MK, leaving a portion between a first transistor structure FET1 and a second transistor structure FET2; and removing a first work function film WFM1 and a first layer L1 in the region where the mask MK is not formed.

[0151] Reference Figure 32 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a recess RE by cutting a portion of a first work function film WFM1 and a first layer L1 disposed between a first transistor structure FET1 and a second transistor structure FET2. In other words, the method for manufacturing the semiconductor device 10 may include forming the recess RE by removing the first work function film WFM1 and the first layer L1 in a region where a mask MK is not formed. In an example embodiment, a method for manufacturing the semiconductor device 10 may include forming a polymer layer PYL.

[0152] Reference Figure 33In an example embodiment, a method for manufacturing a semiconductor device 10 may include: removing a portion of the first layer L1 formed on the first transistor structure FET1 and the second transistor structure FET2.

[0153] Reference Figure 34 In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing the polymer layer PYL. In an example embodiment, a method for manufacturing a semiconductor device 10 may include depositing a second layer L2 comprising an insulating material. In an example embodiment, the second layer L2 may be deposited to fill the recess RE while providing isolation between the upper active pattern (a first upper active pattern AP1_UT and a second upper active pattern AP2_UT) and the lower active pattern (a first lower active pattern AP1_BT and a second lower active pattern AP2_BT).

[0154] Reference Figure 35 In an example embodiment, a method for manufacturing a semiconductor device 10 may include: forming a mask MK while leaving a region of a first transistor structure FET1; and removing a portion of a second layer L2 such that the first layer L1 is exposed from the second layer L2 in the first transistor structure FET1. The second layer L2 formed on the upper side of the first transistor structure FET1 may be removed. In an example embodiment, the method for manufacturing the semiconductor device 10 may include: removing a portion of a first work function film WFM1 formed on the first transistor structure FET1. For example, the first work function film WFM1 formed on the upper side of the first transistor structure FET1 may be removed. Here, since a portion of the first work function film WFM1 is removed, a recessed portion WMF1_G may be formed at the interface between the first work function film WFM1 and the second work function film WFM2 in the first transistor structure FET1.

[0155] Reference Figure 36 In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing a portion of the second layer L2 formed on the second transistor structure FET2 after removing the mask MK. For example, the second layer L2 formed on the upper side of the second transistor structure FET2 may be removed.

[0156] Reference Figure 37 In an example embodiment, a method for manufacturing a semiconductor device 10 may include removing the sacrificial film SCL formed between upper active patterns (a first upper active pattern AP1_UT and a second upper active pattern AP2_UT).

[0157] Reference Figure 38In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a second work function film WFM2 on a second layer L2.

[0158] Reference Figure 39 and Figure 40 In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a dicing groove CT_RE by removing a portion of a second work function film WFM2 disposed between a first transistor structure FET1 and a second transistor structure FET2. The dicing groove CT_RE may include removing the second work function film WFM2 along a second direction D2. Here, as the second work function film WFM2 is removed, the length of the dicing groove CT_RE in the first direction D1 may gradually decrease as it approaches the substrate 100. In an example embodiment, a method for manufacturing a semiconductor device 10 may include forming a gate dicing film CT by filling the formed dicing groove CT_RE with an insulating material.

[0159] According to an example embodiment, a semiconductor device can be provided whose integration density can be increased by reducing its size and whose electrical reliability can be improved.

[0160] The effects of the example embodiments are not limited to those described above, and other effects not described will be clearly understood by those skilled in the art based on the description of the claims.

[0161] Example embodiments of the present disclosure have been described with reference to the accompanying drawings. However, the present disclosure is not limited to the example embodiments, and the semiconductor devices described herein can be manufactured in various other forms. Those skilled in the art to which this disclosure pertains will understand that the disclosed semiconductor devices can be implemented in other specific forms without altering their technical concept or essential characteristics. Therefore, the above example embodiments should be understood in all respects as illustrative rather than restrictive.

Claims

1. A semiconductor device, comprising: Substrate; A plurality of transistor structures are disposed on the substrate and spaced apart from each other in a first direction parallel to the surface of the substrate. Each of the plurality of transistor structures includes a lower active pattern and an upper active pattern spaced apart from the lower active pattern in a second direction intersecting the first direction. A gate dicing film is disposed between two adjacent transistor structures in the plurality of transistor structures; as well as For each lower active pattern, a first layer and a second layer are provided, wherein the first layer at least surrounds a first portion of the lower active pattern, and the second layer is provided on each first layer. Each of the plurality of transistor structures includes a first work function film and a second work function film. The first work function film surrounds a first portion of the lower active pattern, and the second work function film surrounds at least a first portion of the upper active pattern and extends along the first direction. The gate dicing film penetrates the second work function film to form a gap between a first portion of the second work function film and a second portion of the second work function film.

2. The semiconductor device according to claim 1, wherein, The gate dicing film has a length that gradually decreases as it approaches the substrate in the first direction.

3. The semiconductor device according to claim 1, wherein, The first work function film includes a gap formed therebetween at a location between the plurality of transistor structures.

4. The semiconductor device of claim 1, further comprising a separating insulating film disposed in each transistor structure and between the lower active pattern and the upper active pattern. in, The separating insulating membrane is in contact with the second work function membrane.

5. The semiconductor device according to claim 1, wherein, At least one of the plurality of transistor structures includes a region in which the first work function film and the second work function film are in contact with each other.

6. The semiconductor device according to claim 5, wherein: In the common gate transistor structure, The surface area of ​​the entire contact area between the second work function membrane and the second layer is greater than the surface area of ​​the entire contact area between the first work function membrane and the second work function membrane.

7. The semiconductor device according to claim 5, wherein: In the common gate transistor structure, The second work function film includes a bottom surface that is closer to the substrate in the second direction than the uppermost surface of the first work function film.

8. The semiconductor device according to claim 1, wherein, At least one of the plurality of transistor structures includes a region in which the first work function film includes an uppermost surface that is closer to the substrate in the second direction than the bottom surface of the second work function film.

9. The semiconductor device according to claim 8, wherein: In the split-gate transistor structure The length T1 between the uppermost surface of the first work function membrane and the lowermost surface of the second work function membrane in the second direction is less than 5.8 nm.

10. The semiconductor device according to claim 8, wherein, The split-gate transistor structure further includes a separation insulating film disposed between the lower active pattern and the upper active pattern. The ratio T1 / T2 of the length T1 between the uppermost surface of the first work function membrane and the lowermost surface of the second work function membrane to the length T2 of the separating insulating membrane in the second direction is 0.5 or less.

11. The semiconductor device according to claim 1, wherein, The first layer includes a first insulating material, and the second layer includes a second insulating material. A portion of the first layer is disposed continuously between the plurality of transistor structures in the first direction.

12. The semiconductor device according to claim 11, wherein: The first transistor structure in the plurality of transistor structures includes a region in which the first work function film and the second work function film are in contact with each other, and In the first transistor structure, the uppermost surface of the first layer is closer to the substrate than the bottommost surface of the second work function film.

13. The semiconductor device according to claim 11, wherein, The plurality of transistor structures include: a first transistor structure including a region where the first work function film and the second work function film are in contact with each other; and a second transistor structure including the first work function film, the first work function film including an uppermost surface that is closer to the substrate in the second direction than the bottom surface of the second work function film; and Wherein, the maximum thickness of the second work function film of the first transistor structure in the second direction is the same as the maximum thickness of the second work function film of the second transistor structure in the second direction.

14. The semiconductor device according to claim 1, wherein, The first layer comprises a conductive material, and the second layer comprises an insulating material. In this process, gaps are formed in the first layer between the plurality of transistor structures.

15. The semiconductor device according to claim 14, wherein, The plurality of transistor structures include a first transistor structure, the first transistor structure including a region where the first work function film and the second work function film are in contact with each other, and In the first transistor structure, the second work function film includes a bottom surface that is closer to the substrate than the top surface of the first layer.

16. The semiconductor device according to claim 14, wherein, The plurality of transistor structures include: a first transistor structure including a region where the first work function film and the second work function film are in contact with each other; and a second transistor structure including the first work function film, the first work function film including an uppermost surface that is closer to the substrate in the second direction than the bottom surface of the second work function film; and Wherein, the maximum thickness of the second work function film of the first transistor structure in the second direction is greater than the maximum thickness of the second work function film of the second transistor structure in the second direction.

17. The semiconductor device according to claim 16, wherein, The first transistor structure includes a first work function film, which has a recessed portion at its interface with the second work function film.

18. A semiconductor device, comprising: Substrate; A plurality of transistor structures are disposed on the substrate and spaced apart from each other in a first direction parallel to the surface of the substrate. Each transistor structure includes: a lower active pattern including a plurality of thin sheets spaced apart from each other in a second direction intersecting the first direction; an upper active pattern spaced apart from the lower active pattern in the second direction and including a plurality of thin sheets spaced apart from each other in the second direction; and a separating insulating film disposed between the lower active pattern and the upper active pattern. A gate dicing film is disposed between adjacent transistor structures in the plurality of transistor structures; The first layer, encompassing at least a portion of each of the lower active patterns in the lower active pattern; and The second layer is set on top of the first layer. The gate dicing film penetrates the work function film in the second direction to fill the gaps in the work function film.

19. The semiconductor device according to claim 18, wherein, The bottom surface of the gate dicing film is closer to the substrate than the top surface of the separation insulating film.

20. A semiconductor device, comprising: Substrate; A plurality of transistor structures are disposed on the substrate and spaced apart from each other in a first direction parallel to the surface of the substrate. Each transistor structure includes: a lower active pattern including a plurality of thin sheets spaced apart from each other in a second direction intersecting the first direction; an upper active pattern spaced apart from the lower active pattern in the second direction and including a plurality of thin sheets spaced apart from each other in the second direction; and a separating insulating film disposed between the lower active pattern and the upper active pattern. A gate dicing film is disposed between adjacent transistor structures in the plurality of transistor structures; The first layer, encompassing at least a portion of each of the lower active patterns in the lower active pattern; and The second layer is set on top of the first layer. The gate dicing film penetrates the second work function film in the second direction, so that the second work function film has a gap therein relative to the first direction, and the length of the gate dicing film relative to the first direction decreases as the gate dicing film approaches the substrate; The gate dicing film includes a bottom surface that is closer to the substrate than the uppermost surface of the separation insulating film. Wherein, a portion of the first work function film has a gap formed therebetween between the plurality of transistor structures, and The separating insulating membrane is in contact with the second work function membrane.

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