Medium-vanadium oxide laminated structure and dry etching method and application thereof

Abstract

The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a medium-vanadium oxide laminated structure and a dry etching method and application thereof. The etching method comprises the following steps of substrate preparation: loading a laminated substrate with a photoresist mask into a cavity of plasma etching equipment; stabilizing the cavity: introducing etching gas, setting radio frequency power, bias power, cavity pressure, gas flow, substrate temperature and cavity temperature, and starting etching after the parameters of the cavity are stable; single-step main etching: starting plasma etching equipment, and continuously etching the dielectric protection layer and the vanadium oxide layer of the laminated substrate; and end point detection: monitoring an etching end point in real time, and when a vanadium oxide layer etching completion signal is detected, closing the plasma etching equipment, and removing static electricity of the laminated substrate to complete etching. According to the etching method disclosed by the invention, continuous, uniform and morphology-controllable single-step dry etching can be realized on the medium-vanadium oxide laminated structure by utilizing a single gas formula in the same reaction environment.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, specifically relating to a dielectric-vanadium oxide stacked structure and its dry etching method and application. Background Technology

[0002] With the continuous development of infrared detectors (such as uncooled infrared focal plane arrays, IRFPA) and intelligent light-controlled devices, multilayer thin film structures composed of metal oxides, including vanadium oxide, and dielectric materials (such as SiO2 and SiNx) are increasingly widely used in related devices. Vanadium oxide is widely used in the thermistor units of uncooled infrared detectors due to its excellent temperature coefficient of resistance (TCR), while the dielectric material SiNx is usually used as the structural support layer and isolation protection layer of the thermally insulating bridge leg. Together, they constitute the multilayer stacked system of the device core.

[0003] In the patterning process of this stacked structure, traditional methods typically employ a step-by-step etching approach: first, the dielectric layer SiNx is etched using a fluorine-containing gas (such as CF4 or SF6), and after completion, the gas formulation is switched to etch the underlying vanadium oxide layer using a chlorine-containing gas. This process is not only cumbersome but also prone to introducing contamination at the heterogeneous interface, leading to a mismatch in etching rates between different film layers and resulting in poor morphology.

[0004] This two-step etching approach has the following technological drawbacks: The process steps are complicated, and a gas stabilization stage is required for each step switch, resulting in redundant process time and a significant increase in the overall cycle time.

[0005] During the gas switching transition period, residual gases and by-reaction products are easily introduced into the SiNx-vanadium oxide heterostructure interface, causing interface contamination and affecting device performance.

[0006] In two-step etching, the etching rate of different materials is optimized independently, making it difficult to achieve coordinated control of the morphology at the layer interface. This results in discontinuous sidewall contours and inconsistent etching angles, affecting the compatibility of subsequent processes. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a dielectric-vanadium oxide stack structure and its dry etching method and application. This invention introduces a fluorine / chlorine (F / Cl) composite gas system, utilizing the high chemical etching activity of fluorine radicals (F·) on the dielectric layer SiNx, and the characteristic of chlorine radicals (Cl·) reacting with metal elements (V, O, etc.) to generate volatile halides. Through the synergistic effect of plasma physical bombardment and chemical reaction, continuous etching of both SiNx and vanadium oxide materials is achieved in the same process step without the need for intermediate gas switching. This enables continuous, uniform, single-step etching of two materials with vastly different properties under the same reaction environment. The dry etching method of this invention can achieve continuous, uniform, and morphology-controllable single-step dry etching of the dielectric-vanadium oxide stack structure in the same reaction environment using a single gas formulation.

[0008] To achieve the above technical objectives, the technical solution adopted in the embodiments of the present invention is as follows: In a first aspect, embodiments of the present invention provide a dry etching method for a dielectric-vanadium oxide stacked structure, comprising the following steps: Step S1, Substrate preparation: Load the stacked structure substrate with photoresist mask into the chamber of the plasma etching equipment; Step S2, Chamber Stabilization: A mixture of a first gas containing fluorine, a second gas containing chlorine, and an inert gas as the third gas is introduced as the etching gas. The RF power, bias power, chamber pressure, gas flow rate, substrate temperature, and chamber temperature are set. Etching begins after the chamber parameters stabilize. Step S3, Single-step main etching: Start the plasma etching equipment to continuously etch the dielectric protective layer and vanadium oxide layer of the stacked structure substrate; Step S4, Endpoint Detection: Monitor the etching endpoint in real time. When the metal oxide layer etching completion signal is detected, turn off the plasma etching equipment, remove the static electricity from the stacked structure substrate, and complete the etching.

[0009] Furthermore, the stacked structure substrate comprises, from bottom to top, stacked metal oxide layers and dielectric protective layers. The metal oxide layer is vanadium oxide or other metal oxides besides vanadium oxide, and the thickness of the metal oxide layer is 80-120 nm. The dielectric protective layer comprises a SiO2 layer and / or a SiNx layer, and the total thickness of the dielectric protective layer is 30-50 nm.

[0010] Further, in step S2, the first gas includes one or more of CF4, CHF3 and SF6, and the second gas includes one or two of Cl2 and BCl3.

[0011] Furthermore, the volumetric flow rate ratio of the first gas to the second gas is 1:10 to 1:0.3, and the flow rate of the third gas is 10-100 sccm.

[0012] Furthermore, the plasma etching equipment is an inductively coupled plasma etching equipment with a radio frequency power of 300-600 W, a bias power of 50-300 W, and a chamber pressure of 5-20 mTorr.

[0013] Further, the first gas is CF4, the second gas is Cl2, the volumetric flow rate ratio of the first gas to the second gas is 1:10-1:1, the flow rate of the third gas is 10-100 sccm, the radio frequency power of the plasma etching equipment is 300-600 W, the bias power is 50-300 W, and the chamber pressure is 5-20 mTorr.

[0014] Further, the first gas is SF6, the second gas is BCl3, the volumetric flow rate ratio of the first gas to the second gas is 1:10-1:0.3, the flow rate of the third gas is 10-100 sccm, the radio frequency power of the plasma etching equipment is 200-500 W, the bias power is 50-200 W, and the chamber pressure is 5-15 mTorr.

[0015] Furthermore, in step S4, the etching endpoint is detected in real time using optical emission spectroscopy or a laser interferometer.

[0016] Secondly, embodiments of the present invention provide a dielectric-vanadium oxide stacked structure, which is obtained by etching using the etching method described in the first aspect.

[0017] Thirdly, embodiments of the present invention provide the application of the dielectric-vanadium oxide stacked structure described in the second aspect, wherein the stacked structure is used for the patterned fabrication of thermistor units and thermally insulating bridge legs in an uncooled infrared focal plane array detector.

[0018] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows: 1. Significantly improved process efficiency: The dry etching method for the dielectric-vanadium oxide stack structure of this invention can eliminate the gas switching stabilization step between two etching steps, and the single-step etching time is shortened by about 50% compared with the traditional two-step method, which can effectively improve the production line capacity (UPH).

[0019] 2. Significantly improved interface morphology: The dry etching method for the dielectric-vanadium oxide stacked structure of the present invention can improve the continuity of the sidewall morphology at the transition interface between the dielectric protective layer and the metal oxide layer, obtain a smooth and consistent etching profile, avoid step-like defects, and improve the step coverage of subsequent metallization processes.

[0020] 3. The dry etching method for the dielectric-vanadium oxide stacked structure of the present invention achieves equal-rate, controllable etching of two materials with very different properties through a synergistic mechanism of plasma chemistry and physics.

[0021] 4. Reduced risk of interface contamination: The dry etching method for the dielectric-vanadium oxide stacked structure of this invention can simplify the process flow, reduce the risk of heterogeneous interface contamination, eliminate the need to interrupt gas switching, reduce the introduction of heterogeneous interface residues, improve device cleanliness and reliability, thereby improving product yield and batch consistency.

[0022] 5. Wide process window: The F / Cl ratio can be flexibly adjusted to adapt to different film thickness ratios and pattern density requirements, and has strong process adjustability.

[0023] 6. Strong equipment compatibility: It can be implemented directly on existing ICP etching equipment without additional hardware investment. Attached Figure Description

[0024] Figure 1 This is a scanning electron microscope image of the stacked structure obtained after single-step etching in Example 1.

[0025] Figure 2 This is a scanning electron microscope image of the stacked structure obtained after single-step etching in Example 2.

[0026] Figure 3 This is a scanning electron microscope image of the stacked structure obtained after single-step etching in Example 3.

[0027] Figure 4 This is a scanning electron microscope image of the stacked structure obtained after two etching steps in the comparative example.

[0028] Figure 5 This is a schematic diagram of the two-step etching process in the comparative example.

[0029] Figure 6 This is a schematic diagram of the single-step etching process in Example 1. Detailed Implementation

[0030] In the description of this invention, it should be understood that the orientation or positional relationship indicated by directional terms such as "inner" and "outer", "upper" and "lower", "left" and "right" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this invention.

[0031] A dry etching method for a dielectric-vanadium oxide stacked structure includes the following steps: Step S1, Substrate preparation: Load the stacked substrate with photoresist mask into the chamber of the plasma etching equipment; The stacked substrate consists of stacked metal oxide layers and dielectric protective layers from bottom to top. The metal oxide layer is vanadium oxide or other metal oxides besides vanadium oxide. Currently, most metal oxide layers in stacked structures are vanadium oxide layers. The thickness of the metal oxide layer is 80-120 nm, and the thickness can be 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, etc. The dielectric protective layer includes a SiO2 layer and / or a SiNx layer. When the dielectric protective layer is a SiO2 layer or a SiNx layer, the thickness of the SiO2 layer or the SiNx layer is 30-50nm, and can be 30nm, 35nm, 40nm, 45nm, 50nm, etc. When the dielectric protective layer is a SiO2 layer and a SiNx layer, the total thickness of the SiO2 layer and the SiNx layer is 30-50nm, and can be 30nm, 35nm, 40nm, 45nm, 50nm, etc. The thickness ratio of the SiO2 layer to the SiNx layer can be 5:1, 4:1, 3:1, 2:1, 1:1, 1:2, 1:3, 1:4, 1:5, etc.

[0032] Step S2, Chamber Stabilization: A mixture of a first gas containing fluorine, a second gas containing chlorine, and an inert gas as the third gas is introduced as the etching gas. The RF power, bias power, chamber pressure, gas flow rate, substrate temperature, and chamber temperature are set. Etching begins after the chamber parameters stabilize. The first gas includes one or more of CF4, CHF3, and SF6, and the second gas includes one or two of Cl2 and BCl3; the volumetric flow rate ratio of the first gas to the second gas is 1:10-1:0.3, and can take values ​​such as 1:10, 1:9, 1:8, 1:7, 1:6, 1:5, 1:4, 1:3, 1:2, 1:1, 1:0.5, 1:0.3, etc. The flow rate of the third gas is between 10 and 100 sccm, and can be 10 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm, 50 sccm, 55 sccm, 60 sccm, 65 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, etc. The plasma etching equipment is an inductively coupled plasma etching equipment with a radio frequency power of 300-600 W, which can be 300W, 350W, 400W, 450W, 500W, 550W, 600W, etc. The bias power is 50-300 W, and can be 50 W, 100 W, 150 W, 200 W, 250 W, 300 W, etc.; The chamber pressure is 5-20 mTorr, and can be 5 mTorr, 10 mTorr, 15 mTorr, 20 mTorr, etc.

[0033] In one implementation, the first gas is CF4, the second gas is Cl2, the volumetric flow rate ratio of the first gas to the second gas is 1:10-1:1, the flow rate of the third gas is 10-100 sccm, the ICP RF power is 300-600 W, the bias power is 50-300 W, and the chamber pressure is 5-20 mTorr.

[0034] In one implementation, the first gas is SF6, the second gas is BCl3, the volumetric flow rate ratio of the first gas to the second gas is 1:10-1:0.3, the flow rate of the third gas is 10-100 sccm, the ICP RF power is 200-500 W, the bias power is 50-200 W, and the chamber pressure is 5-15 mTorr.

[0035] Step S3, Single-step main etching: Start the plasma etching equipment to continuously etch the dielectric protective layer and vanadium oxide layer of the stacked substrate; Step S4, Endpoint Detection: Monitor the etching endpoint in real time. When the vanadium oxide layer etching completion signal is detected, turn off the plasma etching equipment, remove the static electricity from the stacked substrate, and complete the etching.

[0036] As one implementation method, the etching endpoint is detected in real time using optical emission spectroscopy or a laser interferometer.

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] Example 1 A dry etching method for dielectric-vanadium oxide stacked structures, such as Figure 6 As shown, it includes the following steps: Step S1, Substrate Preparation: Load the stacked substrate uncooled infrared detector wafer with a photoresist mask on its surface into the chamber of the plasma etching equipment. The uncooled infrared detector wafer consists of stacked metal oxide layers and dielectric protective layers from bottom to top. The metal oxide layer is a vanadium oxide layer with a thickness of 80 nm; the dielectric protective layer is a SiNx layer with a thickness of 30 nm. Step S2, Chamber Stabilization: A mixture of the first gas CF4, the second gas Cl2, and the third gas Ar is introduced as the etching gas. The RF power is set to 500 W, the bias power to 100 W, the chamber pressure to 5 mTorr, the flow rate of CF4 to 10 sccm, the flow rate of Cl2 to 40 sccm, the flow rate of Ar to 20 sccm, the substrate temperature to 40℃, and the chamber temperature to 60℃. Etching begins after the chamber parameters stabilize. Step S3, Single-step main etching (ME): Start the plasma etching equipment to continuously etch the dielectric protective layer and vanadium oxide layer of the stacked substrate; Step S4, Endpoint Detection: Monitor the etching endpoint in real time. When the vanadium oxide layer etching completion signal is detected, turn off the plasma etching equipment, remove the static electricity from the stacked substrate, and complete the etching.

[0039] Experimental results: The total time for single-step etching was 56 seconds, saving 50% of the process time compared to the traditional two-step etching (dielectric protection layer etching + chamber stabilization + vanadium oxide layer etching, with a total time exceeding 100 seconds). Figure 1 As shown, the SEM cross-section of the etched stacked structure reveals that the SiNx-vanadium oxide interface sidewall profile is smooth and continuous, which is significantly different from traditional two-step etching (e.g., ...). Figure 4 As shown in the figure, the contour consistency is significantly improved.

[0040] Example 2 A dry etching method for a dielectric-vanadium oxide stacked structure includes the following steps: Step S1, Substrate Preparation: Load the stacked substrate uncooled infrared detector wafer with a photoresist mask on its surface into the chamber of the plasma etching equipment. The uncooled infrared detector wafer consists of stacked metal oxide layers and dielectric protective layers from bottom to top. The metal oxide layer is a vanadium oxide layer with a thickness of 80 nm; the dielectric protective layer is a SiNx layer with a thickness of 30 nm. Step S2, Chamber Stabilization: A mixture of the first gas CF4, the second gas Cl2, and the third gas Ar is introduced as the etching gas. The RF power is set to 500 W, the bias power to 50 W, the chamber pressure to 5 mTorr, the CF4 flow rate to 10 sccm, the Cl2 flow rate to 40 sccm, the Ar flow rate to 20 sccm, the substrate temperature to 40℃, and the chamber temperature to 60℃. Etching begins after the chamber parameters stabilize. Step S3, Single-step main etching (ME): Start the plasma etching equipment to continuously etch the dielectric protective layer and vanadium oxide layer of the stacked substrate; Step S4, Endpoint Detection: Monitor the etching endpoint in real time. When the vanadium oxide layer etching completion signal is detected, turn off the plasma etching equipment, remove the static electricity from the stacked substrate, and complete the etching.

[0041] Experimental results: The total time for single-step ME etching was 77 seconds, as shown below. Figure 2 As shown, the SEM cross-section of the etched stacked structure shows that the SiNx-vanadium oxide interface sidewall profile is smooth and continuous, with an etching angle of 25.67°. Compared with Example 1, the sidewall inclination is increased. This is due to the reduction in bias power, the lower CF4 content in the etching gas, resulting in a low etching rate of the SiNx layer, and insufficient anisotropy in dry etching, which leads to a smaller etching angle.

[0042] Example 3 A dry etching method for a dielectric-vanadium oxide stacked structure includes the following steps: Step S1, Substrate Preparation: Load the stacked substrate uncooled infrared detector wafer with a photoresist mask on its surface into the chamber of the plasma etching equipment. The uncooled infrared detector wafer consists of stacked metal oxide layers and dielectric protective layers from bottom to top. The metal oxide layer is a vanadium oxide layer with a thickness of 80 nm; the dielectric protective layer is a SiNx layer with a thickness of 30 nm. Step S2, Stable Chamber Stabilization: A mixture of the first gas CF4, the second gas Cl2, and the third gas Ar is introduced as the etching gas. The RF power is set to 500 W, the bias power to 100 W, the chamber pressure to 5 mTorr, the flow rate of CF4 to 40 sccm, the flow rate of Cl2 to 40 sccm, the flow rate of Ar to 20 sccm, the substrate temperature to 40℃, and the chamber temperature to 60℃. Etching begins after the chamber parameters stabilize. Step S3, Single-step main etching (ME): Start the plasma etching equipment to continuously etch the dielectric protective layer and vanadium oxide layer of the stacked substrate; Step S4, Endpoint Detection: Monitor the etching endpoint in real time. When the vanadium oxide layer etching completion signal is detected, turn off the plasma etching equipment, remove the static electricity from the stacked substrate, and complete the etching.

[0043] Experimental results: The total time for a single-step etching step was 90 seconds. Figure 3 As shown in the SEM cross-section of the etched stacked structure, vanadium oxide side cutouts appear on the sidewall contour of the SiNx-vanadium oxide interface. Compared with Example 1, the increased F gas content removes the protective byproducts deposited on the vanadium oxide sidewalls during etching, leading to excessive etching of the vanadium oxide by Cl ions. Simultaneously, the increased F gas content also increases the etching rate of SiNx, causing the dielectric protective layer to be etched away prematurely, with more etching time allocated to the etching of the vanadium oxide layer.

[0044] Example 4 A dry etching method for a dielectric-vanadium oxide stacked structure includes the following steps: Step S1, Substrate Preparation: Load the stacked substrate uncooled infrared detector wafer with a photoresist mask on its surface into the chamber of the plasma etching equipment. The uncooled infrared detector wafer consists of stacked metal oxide layers and dielectric protective layers from bottom to top. The metal oxide layer is a vanadium oxide layer with a thickness of 80 nm; the dielectric protective layer is a SiNx layer with a thickness of 30 nm.

[0045] Step S2, Chamber Stabilization: A mixture of the first gas SF6, the second gas BCl3, and the third gas Ar is introduced as the etching gas. The RF power is set to 500 W, the bias power to 100 W, the chamber pressure to 5 mTorr, the flow rate of SF6 to 20 sccm, the flow rate of BCl3 to 100 sccm, the flow rate of Ar to 20 sccm, the substrate temperature to 40℃, and the chamber temperature to 60℃. Etching begins after the chamber parameters stabilize. Step S3, Single-step main etching: Start the plasma etching equipment to continuously etch the dielectric protective layer and vanadium oxide layer of the stacked substrate; Step S4, Endpoint Detection: Monitor the etching endpoint in real time. When the vanadium oxide layer etching completion signal is detected, turn off the plasma etching equipment, remove the static electricity from the stacked substrate, and complete the etching.

[0046] Comparative Example A dry etching method for dielectric-vanadium oxide stacked structures, such as Figure 5 As shown, it includes the following steps: Step S1, Substrate Preparation: Load the stacked substrate uncooled infrared detector wafer with a photoresist mask on its surface into the chamber of the plasma etching equipment. The uncooled infrared detector wafer consists of stacked metal oxide layers and dielectric protective layers from bottom to top. The metal oxide layer is a vanadium oxide layer with a thickness of 80 nm; the dielectric protective layer is a SiNx layer with a thickness of 30 nm. Step S2, Chamber Stabilization: A mixture of the first gas CF4, the second gas CHF3, and the third gas Ar is introduced as the etching gas. The RF power is set to 500 W, the bias power to 100 W, the flow rate of CF4 to 30 sccm, the flow rate of CHF3 to 30 sccm, the flow rate of Ar to 60 sccm, the chamber pressure to 5 mTorr, and the base temperature to 40℃. Etching begins after the chamber parameters stabilize. Step S3, the first main etching in the two-step main etching: start the plasma etching equipment to etch the dielectric protective layer of the stacked substrate, and the etching time is 50s; Step S4, Chamber Stabilization: Introduce a mixture of the first gas Cl2 and the second gas Ar as the etching gas. Set the RF power to 800W, the bias power to 100W, the Cl2 flow rate to 50sccm, the Ar flow rate to 30sccm, the chamber pressure to 5mTorr, and the base temperature to 40℃. After the chamber parameters stabilize, begin etching. Step S5, the second main etching in the two-step main etching: start the plasma etching equipment to etch the vanadium oxide layer of the stacked substrate, and the etching time is 40s; Step S6, Endpoint Detection: Monitor the etching endpoint in real time. When the vanadium oxide layer etching completion signal is detected, turn off the plasma etching equipment, remove the static electricity from the stacked substrate, and complete the etching.

[0047] Experimental results: such as Figure 4 As shown in the figure, SEM cross-section observation after etching reveals a distinct corner in the sidewall profile of the SiNx-vanadium oxide interface.

[0048] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A dry etching method for a dielectric-vanadium oxide stacked structure, characterized in that, Includes the following steps: Step S1, Substrate preparation: Load the stacked structure substrate with photoresist mask into the chamber of the plasma etching equipment; Step S2, Chamber Stabilization: A mixture of a first gas containing fluorine, a second gas containing chlorine, and an inert gas as the third gas is introduced as the etching gas. The RF power, bias power, chamber pressure, gas flow rate, substrate temperature, and chamber temperature are set. Etching begins after the chamber parameters stabilize. Step S3, Single-step main etching: Start the plasma etching equipment to continuously etch the dielectric protective layer and vanadium oxide layer of the stacked structure substrate; Step S4, Endpoint Detection: Monitor the etching endpoint in real time. When the metal oxide layer etching completion signal is detected, turn off the plasma etching equipment, remove the static electricity from the stacked structure substrate, and complete the etching.

2. The dry etching method for the dielectric-vanadium oxide stacked structure according to claim 1, characterized in that, The stacked structure substrate comprises, from bottom to top, stacked metal oxide layers and dielectric protective layers. The metal oxide layer is vanadium oxide or other metal oxides besides vanadium oxide, and the thickness of the metal oxide layer is 80-120 nm. The dielectric protective layer includes a SiO2 layer and / or a SiNx layer, and the total thickness of the dielectric protective layer is 30-50 nm.

3. The dry etching method for the dielectric-vanadium oxide stacked structure according to claim 1, characterized in that, In step S2, the first gas includes one or more of CF4, CHF3 and SF6, and the second gas includes one or two of Cl2 and BCl3.

4. The dry etching method for the dielectric-vanadium oxide stacked structure according to claim 1 or 3, characterized in that, The volumetric flow rate ratio of the first gas to the second gas is 1:10 to 1:0.3, and the flow rate of the third gas is 10-100 sccm.

5. The dry etching method for the dielectric-vanadium oxide stacked structure according to claim 1, characterized in that, The plasma etching equipment is an inductively coupled plasma etching equipment with a radio frequency power of 300-600 W, a bias power of 50-300 W, and a chamber pressure of 5-20 mTorr.

6. The dry etching method for a dielectric-vanadium oxide stacked structure according to any one of claims 1-5, characterized in that, The first gas is CF4, the second gas is Cl2, the volumetric flow rate ratio of the first gas to the second gas is 1:10-1:1, the flow rate of the third gas is 10-100 sccm, the radio frequency power of the plasma etching equipment is 300-600W, the bias power is 50-300W, and the chamber pressure is 5-20 mTorr.

7. The dry etching method for a dielectric-vanadium oxide stacked structure according to any one of claims 1-5, characterized in that, The first gas is SF6, the second gas is BCl3, the volumetric flow rate ratio of the first gas to the second gas is 1:10-1:0.3, the flow rate of the third gas is 10-100 sccm, the radio frequency power of the plasma etching equipment is 200-500 W, the bias power is 50-200 W, and the chamber pressure is 5-15 mTorr.

8. The dry etching method for the dielectric-vanadium oxide stacked structure according to claim 1, characterized in that, Its features are, In step S4, the etching endpoint is detected in real time using optical emission spectroscopy or a laser interferometer.

9. A dielectric-vanadium oxide stacked structure, characterized in that, It is obtained by etching using the etching method described in any one of claims 1-8.

10. The application of the dielectric-vanadium oxide stacked structure according to claim 9, characterized in that, The stacked structure is used for the patterned fabrication of thermistor units and thermally insulating bridge legs in an uncooled infrared focal plane array detector.

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